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1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7/// \file8//===----------------------------------------------------------------------===//9 10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H12 13#include "llvm/MC/MCInstrDesc.h"14 15namespace llvm {16 17// This needs to be kept in sync with the field bits in SIRegisterClass.18enum SIRCFlags : uint8_t {19 RegTupleAlignUnitsWidth = 2,20 HasVGPRBit = RegTupleAlignUnitsWidth,21 HasAGPRBit,22 HasSGPRbit,23 24 HasVGPR = 1 << HasVGPRBit,25 HasAGPR = 1 << HasAGPRBit,26 HasSGPR = 1 << HasSGPRbit,27 28 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1,29 RegKindMask = (HasVGPR | HasAGPR | HasSGPR)30}; // enum SIRCFlagsr31 32namespace SIEncodingFamily {33// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td34// and the columns of the getMCOpcodeGen table.35enum {36 SI = 0,37 VI = 1,38 SDWA = 2,39 SDWA9 = 3,40 GFX80 = 4,41 GFX9 = 5,42 GFX10 = 6,43 SDWA10 = 7,44 GFX90A = 8,45 GFX940 = 9,46 GFX11 = 10,47 GFX12 = 11,48 GFX1250 = 12,49};50}51 52namespace SIInstrFlags {53// This needs to be kept in sync with the field bits in InstSI.54enum : uint64_t {55 // Low bits - basic encoding information.56 SALU = 1 << 0,57 VALU = 1 << 1,58 59 // SALU instruction formats.60 SOP1 = 1 << 2,61 SOP2 = 1 << 3,62 SOPC = 1 << 4,63 SOPK = 1 << 5,64 SOPP = 1 << 6,65 66 // VALU instruction formats.67 VOP1 = 1 << 7,68 VOP2 = 1 << 8,69 VOPC = 1 << 9,70 71 // TODO: Should this be spilt into VOP3 a and b?72 VOP3 = 1 << 10,73 VOP3P = 1 << 12,74 75 VINTRP = 1 << 13,76 SDWA = 1 << 14,77 DPP = 1 << 15,78 TRANS = 1 << 16,79 80 // Memory instruction formats.81 MUBUF = 1 << 17,82 MTBUF = 1 << 18,83 SMRD = 1 << 19,84 MIMG = 1 << 20,85 VIMAGE = 1 << 21,86 VSAMPLE = 1 << 22,87 EXP = 1 << 23,88 FLAT = 1 << 24,89 DS = 1 << 25,90 91 // Combined SGPR/VGPR Spill bit92 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill93 Spill = 1 << 26,94 95 // LDSDIR instruction format.96 LDSDIR = 1 << 28,97 98 // VINTERP instruction format.99 VINTERP = 1 << 29,100 101 VOPD3 = 1 << 30,102 103 // High bits - other information.104 VM_CNT = UINT64_C(1) << 32,105 EXP_CNT = UINT64_C(1) << 33,106 LGKM_CNT = UINT64_C(1) << 34,107 108 WQM = UINT64_C(1) << 35,109 DisableWQM = UINT64_C(1) << 36,110 Gather4 = UINT64_C(1) << 37,111 112 TENSOR_CNT = UINT64_C(1) << 38,113 114 SCALAR_STORE = UINT64_C(1) << 39,115 FIXED_SIZE = UINT64_C(1) << 40,116 117 ASYNC_CNT = UINT64_C(1) << 41,118 119 VOP3_OPSEL = UINT64_C(1) << 42,120 maybeAtomic = UINT64_C(1) << 43,121 renamedInGFX9 = UINT64_C(1) << 44,122 123 // Is a clamp on FP type.124 FPClamp = UINT64_C(1) << 45,125 126 // Is an integer clamp127 IntClamp = UINT64_C(1) << 46,128 129 // Clamps lo component of register.130 ClampLo = UINT64_C(1) << 47,131 132 // Clamps hi component of register.133 // ClampLo and ClampHi set for packed clamp.134 ClampHi = UINT64_C(1) << 48,135 136 // Is a packed VOP3P instruction.137 IsPacked = UINT64_C(1) << 49,138 139 // Is a D16 buffer instruction.140 D16Buf = UINT64_C(1) << 50,141 142 // FLAT instruction accesses FLAT_GLBL segment.143 FlatGlobal = UINT64_C(1) << 51,144 145 // Uses floating point double precision rounding mode146 FPDPRounding = UINT64_C(1) << 52,147 148 // Instruction is FP atomic.149 FPAtomic = UINT64_C(1) << 53,150 151 // Is a MFMA instruction.152 IsMAI = UINT64_C(1) << 54,153 154 // Is a DOT instruction.155 IsDOT = UINT64_C(1) << 55,156 157 // FLAT instruction accesses FLAT_SCRATCH segment.158 FlatScratch = UINT64_C(1) << 56,159 160 // Atomic without return.161 IsAtomicNoRet = UINT64_C(1) << 57,162 163 // Atomic with return.164 IsAtomicRet = UINT64_C(1) << 58,165 166 // Is a WMMA instruction.167 IsWMMA = UINT64_C(1) << 59,168 169 // Whether tied sources will be read.170 TiedSourceNotRead = UINT64_C(1) << 60,171 172 // Is never uniform.173 IsNeverUniform = UINT64_C(1) << 61,174 175 // ds_gws_* instructions.176 GWS = UINT64_C(1) << 62,177 178 // Is a SWMMAC instruction.179 IsSWMMAC = UINT64_C(1) << 63,180};181 182// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.183// The result is true if any of these tests are true.184enum ClassFlags : unsigned {185 S_NAN = 1 << 0, // Signaling NaN186 Q_NAN = 1 << 1, // Quiet NaN187 N_INFINITY = 1 << 2, // Negative infinity188 N_NORMAL = 1 << 3, // Negative normal189 N_SUBNORMAL = 1 << 4, // Negative subnormal190 N_ZERO = 1 << 5, // Negative zero191 P_ZERO = 1 << 6, // Positive zero192 P_SUBNORMAL = 1 << 7, // Positive subnormal193 P_NORMAL = 1 << 8, // Positive normal194 P_INFINITY = 1 << 9 // Positive infinity195};196}197 198namespace AMDGPU {199enum OperandType : unsigned {200 /// Operands with register, 32-bit, or 64-bit immediate201 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,202 OPERAND_REG_IMM_INT64,203 OPERAND_REG_IMM_INT16,204 OPERAND_REG_IMM_FP32,205 OPERAND_REG_IMM_FP64,206 OPERAND_REG_IMM_BF16,207 OPERAND_REG_IMM_FP16,208 OPERAND_REG_IMM_V2BF16,209 OPERAND_REG_IMM_V2FP16,210 OPERAND_REG_IMM_V2INT16,211 OPERAND_REG_IMM_NOINLINE_V2FP16,212 OPERAND_REG_IMM_V2INT32,213 OPERAND_REG_IMM_V2FP32,214 215 /// Operands with register or inline constant216 OPERAND_REG_INLINE_C_INT16,217 OPERAND_REG_INLINE_C_INT32,218 OPERAND_REG_INLINE_C_INT64,219 OPERAND_REG_INLINE_C_BF16,220 OPERAND_REG_INLINE_C_FP16,221 OPERAND_REG_INLINE_C_FP32,222 OPERAND_REG_INLINE_C_FP64,223 OPERAND_REG_INLINE_C_V2INT16,224 OPERAND_REG_INLINE_C_V2BF16,225 OPERAND_REG_INLINE_C_V2FP16,226 227 // Operand for split barrier inline constant228 OPERAND_INLINE_SPLIT_BARRIER_INT32,229 230 /// Operand with 32-bit immediate that uses the constant bus.231 OPERAND_KIMM32,232 OPERAND_KIMM16,233 OPERAND_KIMM64,234 235 /// Operands with an AccVGPR register or inline constant236 OPERAND_REG_INLINE_AC_INT32,237 OPERAND_REG_INLINE_AC_FP32,238 OPERAND_REG_INLINE_AC_FP64,239 240 // Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline241 // constants. Does not accept registers.242 OPERAND_INLINE_C_AV64_PSEUDO,243 244 // Operand for source modifiers for VOP instructions245 OPERAND_INPUT_MODS,246 247 // Operand for SDWA instructions248 OPERAND_SDWA_VOPC_DST,249 250 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,251 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,252 253 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,254 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64,255 256 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32,257 OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO,258 259 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,260 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,261 262 OPERAND_KIMM_FIRST = OPERAND_KIMM32,263 OPERAND_KIMM_LAST = OPERAND_KIMM64264 265};266}267 268// Input operand modifiers bit-masks269// NEG and SEXT share same bit-mask because they can't be set simultaneously.270namespace SISrcMods {271enum : unsigned {272 NONE = 0,273 NEG = 1 << 0, // Floating-point negate modifier274 ABS = 1 << 1, // Floating-point absolute modifier275 SEXT = 1 << 4, // Integer sign-extend modifier276 NEG_HI = ABS, // Floating-point negate high packed component modifier.277 OP_SEL_0 = 1 << 2,278 OP_SEL_1 = 1 << 3,279 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)280};281}282 283namespace SIOutMods {284 enum : unsigned {285 NONE = 0,286 MUL2 = 1,287 MUL4 = 2,288 DIV2 = 3289 };290}291 292namespace AMDGPU {293namespace VGPRIndexMode {294 295enum Id : unsigned { // id of symbolic names296 ID_SRC0 = 0,297 ID_SRC1,298 ID_SRC2,299 ID_DST,300 301 ID_MIN = ID_SRC0,302 ID_MAX = ID_DST303};304 305enum EncBits : unsigned {306 OFF = 0,307 SRC0_ENABLE = 1 << ID_SRC0,308 SRC1_ENABLE = 1 << ID_SRC1,309 SRC2_ENABLE = 1 << ID_SRC2,310 DST_ENABLE = 1 << ID_DST,311 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE,312 UNDEF = 0xFFFF313};314 315} // namespace VGPRIndexMode316} // namespace AMDGPU317 318namespace AMDGPUAsmVariants {319 enum : unsigned {320 DEFAULT = 0,321 VOP3 = 1,322 SDWA = 2,323 SDWA9 = 3,324 DPP = 4,325 VOP3_DPP = 5326 };327} // namespace AMDGPUAsmVariants328 329namespace AMDGPU {330namespace EncValues { // Encoding values of enum9/8/7 operands331 332enum : unsigned {333 SGPR_MIN = 0,334 SGPR_MAX_SI = 101,335 SGPR_MAX_GFX10 = 105,336 TTMP_VI_MIN = 112,337 TTMP_VI_MAX = 123,338 TTMP_GFX9PLUS_MIN = 108,339 TTMP_GFX9PLUS_MAX = 123,340 INLINE_INTEGER_C_MIN = 128,341 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64342 INLINE_INTEGER_C_MAX = 208,343 INLINE_FLOATING_C_MIN = 240,344 INLINE_FLOATING_C_MAX = 248,345 LITERAL64_CONST = 254,346 LITERAL_CONST = 255,347 VGPR_MIN = 256,348 VGPR_MAX = 511,349 IS_VGPR = 256, // Indicates VGPR or AGPR350};351 352} // namespace EncValues353 354// Register codes as defined in the TableGen's HWEncoding field.355namespace HWEncoding {356enum : unsigned {357 REG_IDX_MASK = 0x3ff,358 LO256_REG_IDX_MASK = 0xff,359 IS_VGPR = 1 << 10,360 IS_AGPR = 1 << 11,361 IS_HI16 = 1 << 12,362};363} // namespace HWEncoding364 365namespace CPol {366 367enum CPol {368 GLC = 1,369 SLC = 2,370 DLC = 4,371 SCC = 16,372 SC0 = GLC,373 SC1 = SCC,374 NT = SLC,375 ALL_pregfx12 = GLC | SLC | DLC | SCC,376 SWZ_pregfx12 = 8,377 378 // Below are GFX12+ cache policy bits379 380 // Temporal hint381 TH = 0x7, // All TH bits382 TH_RT = 0, // regular383 TH_NT = 1, // non-temporal384 TH_HT = 2, // high-temporal385 TH_LU = 3, // last use386 TH_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)387 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)388 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)389 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)390 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL)391 TH_BYPASS = 3, // only to be used with scope = 3392 393 TH_RESERVED = 7, // unused value for load insts394 395 // Bits of TH for atomics396 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning397 TH_ATOMIC_NT = SLC, // Non-temporal vs regular398 TH_ATOMIC_CASCADE = 4, // Cascading vs regular399 400 // Scope401 SCOPE_SHIFT = 3,402 SCOPE_MASK = 0x3,403 SCOPE = SCOPE_MASK << SCOPE_SHIFT, // All Scope bits404 SCOPE_CU = 0 << SCOPE_SHIFT,405 SCOPE_SE = 1 << SCOPE_SHIFT,406 SCOPE_DEV = 2 << SCOPE_SHIFT,407 SCOPE_SYS = 3 << SCOPE_SHIFT,408 409 NV = 1 << 5, // Non-volatile bit410 411 SWZ = 1 << 6, // Swizzle bit412 413 SCAL = 1 << 11, // Scale offset bit414 415 ALL = TH | SCOPE | NV,416 417 // Helper bits418 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy419 TH_TYPE_STORE = 1 << 8, // TH_STORE policy420 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy421 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not422 423 // Volatile (used to preserve/signal operation volatility for buffer424 // operations not a real instruction bit)425 VOLATILE = 1 << 31,426 // The set of "cache policy" bits used for compiler features that427 // do not correspond to handware features.428 VIRTUAL_BITS = VOLATILE,429};430 431} // namespace CPol432 433namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.434 435enum Id { // Message ID, width(4) [3:0].436 ID_INTERRUPT = 1,437 438 ID_GS_PreGFX11 = 2, // replaced in GFX11439 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11440 441 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11442 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11443 444 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11445 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12446 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12447 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11448 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10449 ID_GS_ALLOC_REQ = 9, // added in GFX9450 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11451 ID_SAVEWAVE_HAS_TDM = 10, // added in GFX1250452 ID_GET_DDID = 11, // added in GFX10, removed in GFX11453 ID_SYSMSG = 15,454 455 ID_RTN_GET_DOORBELL = 128,456 ID_RTN_GET_DDID = 129,457 ID_RTN_GET_TMA = 130,458 ID_RTN_GET_REALTIME = 131,459 ID_RTN_SAVE_WAVE = 132,460 ID_RTN_GET_TBA = 133,461 ID_RTN_GET_TBA_TO_PC = 134,462 ID_RTN_GET_SE_AID_ID = 135,463 464 ID_RTN_GET_CLUSTER_BARRIER_STATE = 136, // added in GFX1250465 466 ID_MASK_PreGFX11_ = 0xF,467 ID_MASK_GFX11Plus_ = 0xFF468};469 470enum Op { // Both GS and SYS operation IDs.471 OP_SHIFT_ = 4,472 OP_NONE_ = 0,473 // Bits used for operation encoding474 OP_WIDTH_ = 3,475 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),476 // GS operations are encoded in bits 5:4477 OP_GS_NOP = 0,478 OP_GS_CUT = 1,479 OP_GS_EMIT = 2,480 OP_GS_EMIT_CUT = 3,481 OP_GS_FIRST_ = OP_GS_NOP,482 // SYS operations are encoded in bits 6:4483 OP_SYS_ECC_ERR_INTERRUPT = 1,484 OP_SYS_REG_RD = 2,485 OP_SYS_HOST_TRAP_ACK = 3,486 OP_SYS_TTRACE_PC = 4,487 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,488};489 490enum StreamId : unsigned { // Stream ID, (2) [9:8].491 STREAM_ID_NONE_ = 0,492 STREAM_ID_DEFAULT_ = 0,493 STREAM_ID_LAST_ = 4,494 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,495 STREAM_ID_SHIFT_ = 8,496 STREAM_ID_WIDTH_= 2,497 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)498};499 500} // namespace SendMsg501 502namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.503 504enum Id { // HwRegCode, (6) [5:0]505 ID_MODE = 1,506 ID_STATUS = 2,507 ID_TRAPSTS = 3,508 ID_HW_ID = 4,509 ID_GPR_ALLOC = 5,510 ID_LDS_ALLOC = 6,511 ID_IB_STS = 7,512 ID_PERF_SNAPSHOT_DATA_gfx12 = 10,513 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11,514 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12,515 ID_MEM_BASES = 15,516 ID_TBA_LO = 16,517 ID_TBA_HI = 17,518 ID_TMA_LO = 18,519 ID_TMA_HI = 19,520 ID_FLAT_SCR_LO = 20,521 ID_FLAT_SCR_HI = 21,522 ID_XNACK_MASK = 22,523 ID_HW_ID1 = 23,524 ID_HW_ID2 = 24,525 ID_POPS_PACKER = 25,526 ID_SCHED_MODE = 26,527 ID_PERF_SNAPSHOT_DATA_gfx11 = 27,528 ID_IB_STS2 = 28,529 ID_SHADER_CYCLES = 29,530 ID_SHADER_CYCLES_HI = 30,531 ID_DVGPR_ALLOC_LO = 31,532 ID_DVGPR_ALLOC_HI = 32,533 534 // Register numbers reused in GFX11535 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18,536 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19,537 538 // Register numbers reused in GFX12+539 ID_STATE_PRIV = 4,540 ID_PERF_SNAPSHOT_DATA1 = 15,541 ID_PERF_SNAPSHOT_DATA2 = 16,542 ID_EXCP_FLAG_PRIV = 17,543 ID_EXCP_FLAG_USER = 18,544 ID_TRAP_CTRL = 19,545 546 // GFX94* specific registers547 ID_XCC_ID = 20,548 ID_SQ_PERF_SNAPSHOT_DATA = 21,549 ID_SQ_PERF_SNAPSHOT_DATA1 = 22,550 ID_SQ_PERF_SNAPSHOT_PC_LO = 23,551 ID_SQ_PERF_SNAPSHOT_PC_HI = 24,552 553 // GFX1250554 ID_XNACK_STATE_PRIV = 33,555 ID_XNACK_MASK_gfx1250 = 34,556};557 558enum Offset : unsigned { // Offset, (5) [10:6]559 OFFSET_MEM_VIOL = 8,560 OFFSET_ME_ID = 8, // in HW_ID2561};562 563enum ModeRegisterMasks : uint32_t {564 FP_ROUND_MASK = 0xf << 0, // Bits 0..3565 FP_DENORM_MASK = 0xf << 4, // Bits 4..7566 DX10_CLAMP_MASK = 1 << 8,567 IEEE_MODE_MASK = 1 << 9,568 LOD_CLAMP_MASK = 1 << 10,569 DEBUG_MASK = 1 << 11,570 571 // EXCP_EN fields.572 EXCP_EN_INVALID_MASK = 1 << 12,573 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13,574 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14,575 EXCP_EN_OVERFLOW_MASK = 1 << 15,576 EXCP_EN_UNDERFLOW_MASK = 1 << 16,577 EXCP_EN_INEXACT_MASK = 1 << 17,578 EXCP_EN_INT_DIV0_MASK = 1 << 18,579 580 GPR_IDX_EN_MASK = 1 << 27,581 VSKIP_MASK = 1 << 28,582 CSP_MASK = 0x7u << 29, // Bits 29..31583 584 // GFX1250585 DST_VGPR_MSB = 1 << 12,586 SRC0_VGPR_MSB = 1 << 13,587 SRC1_VGPR_MSB = 1 << 14,588 SRC2_VGPR_MSB = 1 << 15,589 VGPR_MSB_MASK = 0xf << 12, // Bits 12..15590 591 REPLAY_MODE = 1 << 25,592 FLAT_SCRATCH_IS_NV = 1 << 26,593};594 595} // namespace Hwreg596 597namespace MTBUFFormat {598 599enum DataFormat : int64_t {600 DFMT_INVALID = 0,601 DFMT_8,602 DFMT_16,603 DFMT_8_8,604 DFMT_32,605 DFMT_16_16,606 DFMT_10_11_11,607 DFMT_11_11_10,608 DFMT_10_10_10_2,609 DFMT_2_10_10_10,610 DFMT_8_8_8_8,611 DFMT_32_32,612 DFMT_16_16_16_16,613 DFMT_32_32_32,614 DFMT_32_32_32_32,615 DFMT_RESERVED_15,616 617 DFMT_MIN = DFMT_INVALID,618 DFMT_MAX = DFMT_RESERVED_15,619 620 DFMT_UNDEF = -1,621 DFMT_DEFAULT = DFMT_8,622 623 DFMT_SHIFT = 0,624 DFMT_MASK = 0xF625};626 627enum NumFormat : int64_t {628 NFMT_UNORM = 0,629 NFMT_SNORM,630 NFMT_USCALED,631 NFMT_SSCALED,632 NFMT_UINT,633 NFMT_SINT,634 NFMT_RESERVED_6, // VI and GFX9635 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only636 NFMT_FLOAT,637 638 NFMT_MIN = NFMT_UNORM,639 NFMT_MAX = NFMT_FLOAT,640 641 NFMT_UNDEF = -1,642 NFMT_DEFAULT = NFMT_UNORM,643 644 NFMT_SHIFT = 4,645 NFMT_MASK = 7646};647 648enum MergedFormat : int64_t {649 DFMT_NFMT_UNDEF = -1,650 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) |651 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT),652 653 654 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT),655 656 DFMT_NFMT_MAX = DFMT_NFMT_MASK657};658 659enum UnifiedFormatCommon : int64_t {660 UFMT_MAX = 127,661 UFMT_UNDEF = -1,662 UFMT_DEFAULT = 1663};664 665} // namespace MTBUFFormat666 667namespace UfmtGFX10 {668enum UnifiedFormat : int64_t {669 UFMT_INVALID = 0,670 671 UFMT_8_UNORM,672 UFMT_8_SNORM,673 UFMT_8_USCALED,674 UFMT_8_SSCALED,675 UFMT_8_UINT,676 UFMT_8_SINT,677 678 UFMT_16_UNORM,679 UFMT_16_SNORM,680 UFMT_16_USCALED,681 UFMT_16_SSCALED,682 UFMT_16_UINT,683 UFMT_16_SINT,684 UFMT_16_FLOAT,685 686 UFMT_8_8_UNORM,687 UFMT_8_8_SNORM,688 UFMT_8_8_USCALED,689 UFMT_8_8_SSCALED,690 UFMT_8_8_UINT,691 UFMT_8_8_SINT,692 693 UFMT_32_UINT,694 UFMT_32_SINT,695 UFMT_32_FLOAT,696 697 UFMT_16_16_UNORM,698 UFMT_16_16_SNORM,699 UFMT_16_16_USCALED,700 UFMT_16_16_SSCALED,701 UFMT_16_16_UINT,702 UFMT_16_16_SINT,703 UFMT_16_16_FLOAT,704 705 UFMT_10_11_11_UNORM,706 UFMT_10_11_11_SNORM,707 UFMT_10_11_11_USCALED,708 UFMT_10_11_11_SSCALED,709 UFMT_10_11_11_UINT,710 UFMT_10_11_11_SINT,711 UFMT_10_11_11_FLOAT,712 713 UFMT_11_11_10_UNORM,714 UFMT_11_11_10_SNORM,715 UFMT_11_11_10_USCALED,716 UFMT_11_11_10_SSCALED,717 UFMT_11_11_10_UINT,718 UFMT_11_11_10_SINT,719 UFMT_11_11_10_FLOAT,720 721 UFMT_10_10_10_2_UNORM,722 UFMT_10_10_10_2_SNORM,723 UFMT_10_10_10_2_USCALED,724 UFMT_10_10_10_2_SSCALED,725 UFMT_10_10_10_2_UINT,726 UFMT_10_10_10_2_SINT,727 728 UFMT_2_10_10_10_UNORM,729 UFMT_2_10_10_10_SNORM,730 UFMT_2_10_10_10_USCALED,731 UFMT_2_10_10_10_SSCALED,732 UFMT_2_10_10_10_UINT,733 UFMT_2_10_10_10_SINT,734 735 UFMT_8_8_8_8_UNORM,736 UFMT_8_8_8_8_SNORM,737 UFMT_8_8_8_8_USCALED,738 UFMT_8_8_8_8_SSCALED,739 UFMT_8_8_8_8_UINT,740 UFMT_8_8_8_8_SINT,741 742 UFMT_32_32_UINT,743 UFMT_32_32_SINT,744 UFMT_32_32_FLOAT,745 746 UFMT_16_16_16_16_UNORM,747 UFMT_16_16_16_16_SNORM,748 UFMT_16_16_16_16_USCALED,749 UFMT_16_16_16_16_SSCALED,750 UFMT_16_16_16_16_UINT,751 UFMT_16_16_16_16_SINT,752 UFMT_16_16_16_16_FLOAT,753 754 UFMT_32_32_32_UINT,755 UFMT_32_32_32_SINT,756 UFMT_32_32_32_FLOAT,757 UFMT_32_32_32_32_UINT,758 UFMT_32_32_32_32_SINT,759 UFMT_32_32_32_32_FLOAT,760 761 UFMT_FIRST = UFMT_INVALID,762 UFMT_LAST = UFMT_32_32_32_32_FLOAT,763};764 765} // namespace UfmtGFX10766 767namespace UfmtGFX11 {768enum UnifiedFormat : int64_t {769 UFMT_INVALID = 0,770 771 UFMT_8_UNORM,772 UFMT_8_SNORM,773 UFMT_8_USCALED,774 UFMT_8_SSCALED,775 UFMT_8_UINT,776 UFMT_8_SINT,777 778 UFMT_16_UNORM,779 UFMT_16_SNORM,780 UFMT_16_USCALED,781 UFMT_16_SSCALED,782 UFMT_16_UINT,783 UFMT_16_SINT,784 UFMT_16_FLOAT,785 786 UFMT_8_8_UNORM,787 UFMT_8_8_SNORM,788 UFMT_8_8_USCALED,789 UFMT_8_8_SSCALED,790 UFMT_8_8_UINT,791 UFMT_8_8_SINT,792 793 UFMT_32_UINT,794 UFMT_32_SINT,795 UFMT_32_FLOAT,796 797 UFMT_16_16_UNORM,798 UFMT_16_16_SNORM,799 UFMT_16_16_USCALED,800 UFMT_16_16_SSCALED,801 UFMT_16_16_UINT,802 UFMT_16_16_SINT,803 UFMT_16_16_FLOAT,804 805 UFMT_10_11_11_FLOAT,806 807 UFMT_11_11_10_FLOAT,808 809 UFMT_10_10_10_2_UNORM,810 UFMT_10_10_10_2_SNORM,811 UFMT_10_10_10_2_UINT,812 UFMT_10_10_10_2_SINT,813 814 UFMT_2_10_10_10_UNORM,815 UFMT_2_10_10_10_SNORM,816 UFMT_2_10_10_10_USCALED,817 UFMT_2_10_10_10_SSCALED,818 UFMT_2_10_10_10_UINT,819 UFMT_2_10_10_10_SINT,820 821 UFMT_8_8_8_8_UNORM,822 UFMT_8_8_8_8_SNORM,823 UFMT_8_8_8_8_USCALED,824 UFMT_8_8_8_8_SSCALED,825 UFMT_8_8_8_8_UINT,826 UFMT_8_8_8_8_SINT,827 828 UFMT_32_32_UINT,829 UFMT_32_32_SINT,830 UFMT_32_32_FLOAT,831 832 UFMT_16_16_16_16_UNORM,833 UFMT_16_16_16_16_SNORM,834 UFMT_16_16_16_16_USCALED,835 UFMT_16_16_16_16_SSCALED,836 UFMT_16_16_16_16_UINT,837 UFMT_16_16_16_16_SINT,838 UFMT_16_16_16_16_FLOAT,839 840 UFMT_32_32_32_UINT,841 UFMT_32_32_32_SINT,842 UFMT_32_32_32_FLOAT,843 UFMT_32_32_32_32_UINT,844 UFMT_32_32_32_32_SINT,845 UFMT_32_32_32_32_FLOAT,846 847 UFMT_FIRST = UFMT_INVALID,848 UFMT_LAST = UFMT_32_32_32_32_FLOAT,849};850 851} // namespace UfmtGFX11852 853namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.854 855enum Id : unsigned { // id of symbolic names856 ID_QUAD_PERM = 0,857 ID_BITMASK_PERM,858 ID_SWAP,859 ID_REVERSE,860 ID_BROADCAST,861 ID_FFT,862 ID_ROTATE863};864 865// clang-format off866enum EncBits : unsigned {867 868 // swizzle mode encodings869 870 QUAD_PERM_ENC = 0x8000,871 QUAD_PERM_ENC_MASK = 0xFF00,872 873 BITMASK_PERM_ENC = 0x0000,874 BITMASK_PERM_ENC_MASK = 0x8000,875 876 FFT_MODE_ENC = 0xE000,877 878 ROTATE_MODE_ENC = 0xC000,879 FFT_ROTATE_MODE_MASK = 0xF000,880 881 ROTATE_MODE_LO = 0xC000,882 FFT_MODE_LO = 0xE000,883 884 // QUAD_PERM encodings885 886 LANE_MASK = 0x3,887 LANE_MAX = LANE_MASK,888 LANE_SHIFT = 2,889 LANE_NUM = 4,890 891 // BITMASK_PERM encodings892 893 BITMASK_MASK = 0x1F,894 BITMASK_MAX = BITMASK_MASK,895 BITMASK_WIDTH = 5,896 897 BITMASK_AND_SHIFT = 0,898 BITMASK_OR_SHIFT = 5,899 BITMASK_XOR_SHIFT = 10,900 901 // FFT encodings902 903 FFT_SWIZZLE_MASK = 0x1F,904 FFT_SWIZZLE_MAX = 0x1F,905 906 // ROTATE encodings907 ROTATE_MAX_SIZE = 0x1F,908 ROTATE_DIR_SHIFT = 10, // bit position of rotate direction909 ROTATE_DIR_MASK = 0x1,910 ROTATE_SIZE_SHIFT = 5, // bit position of rotate size911 ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,912};913// clang-format on914 915} // namespace Swizzle916 917namespace SDWA {918 919enum SdwaSel : unsigned {920 BYTE_0 = 0,921 BYTE_1 = 1,922 BYTE_2 = 2,923 BYTE_3 = 3,924 WORD_0 = 4,925 WORD_1 = 5,926 DWORD = 6,927};928 929enum DstUnused : unsigned {930 UNUSED_PAD = 0,931 UNUSED_SEXT = 1,932 UNUSED_PRESERVE = 2,933};934 935enum SDWA9EncValues : unsigned {936 SRC_SGPR_MASK = 0x100,937 SRC_VGPR_MASK = 0xFF,938 VOPC_DST_VCC_MASK = 0x80,939 VOPC_DST_SGPR_MASK = 0x7F,940 941 SRC_VGPR_MIN = 0,942 SRC_VGPR_MAX = 255,943 SRC_SGPR_MIN = 256,944 SRC_SGPR_MAX_SI = 357,945 SRC_SGPR_MAX_GFX10 = 361,946 SRC_TTMP_MIN = 364,947 SRC_TTMP_MAX = 379,948};949 950} // namespace SDWA951 952namespace DPP {953 954// clang-format off955enum DppCtrl : unsigned {956 QUAD_PERM_FIRST = 0,957 QUAD_PERM_ID = 0xE4, // identity permutation958 QUAD_PERM_LAST = 0xFF,959 DPP_UNUSED1 = 0x100,960 ROW_SHL0 = 0x100,961 ROW_SHL_FIRST = 0x101,962 ROW_SHL_LAST = 0x10F,963 DPP_UNUSED2 = 0x110,964 ROW_SHR0 = 0x110,965 ROW_SHR_FIRST = 0x111,966 ROW_SHR_LAST = 0x11F,967 DPP_UNUSED3 = 0x120,968 ROW_ROR0 = 0x120,969 ROW_ROR_FIRST = 0x121,970 ROW_ROR_LAST = 0x12F,971 WAVE_SHL1 = 0x130,972 DPP_UNUSED4_FIRST = 0x131,973 DPP_UNUSED4_LAST = 0x133,974 WAVE_ROL1 = 0x134,975 DPP_UNUSED5_FIRST = 0x135,976 DPP_UNUSED5_LAST = 0x137,977 WAVE_SHR1 = 0x138,978 DPP_UNUSED6_FIRST = 0x139,979 DPP_UNUSED6_LAST = 0x13B,980 WAVE_ROR1 = 0x13C,981 DPP_UNUSED7_FIRST = 0x13D,982 DPP_UNUSED7_LAST = 0x13F,983 ROW_MIRROR = 0x140,984 ROW_HALF_MIRROR = 0x141,985 BCAST15 = 0x142,986 BCAST31 = 0x143,987 DPP_UNUSED8_FIRST = 0x144,988 DPP_UNUSED8_LAST = 0x14F,989 ROW_NEWBCAST_FIRST= 0x150,990 ROW_NEWBCAST_LAST = 0x15F,991 ROW_SHARE0 = 0x150,992 ROW_SHARE_FIRST = 0x150,993 ROW_SHARE_LAST = 0x15F,994 ROW_XMASK0 = 0x160,995 ROW_XMASK_FIRST = 0x160,996 ROW_XMASK_LAST = 0x16F,997 DPP_LAST = ROW_XMASK_LAST998};999// clang-format on1000 1001enum DppFiMode {1002 DPP_FI_0 = 0,1003 DPP_FI_1 = 1,1004 DPP8_FI_0 = 0xE9,1005 DPP8_FI_1 = 0xEA,1006};1007 1008} // namespace DPP1009 1010namespace Exp {1011 1012enum Target : unsigned {1013 ET_MRT0 = 0,1014 ET_MRT7 = 7,1015 ET_MRTZ = 8,1016 ET_NULL = 9, // Pre-GFX111017 ET_POS0 = 12,1018 ET_POS3 = 15,1019 ET_POS4 = 16, // GFX10+1020 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget1021 ET_PRIM = 20, // GFX10+1022 ET_DUAL_SRC_BLEND0 = 21, // GFX11+1023 ET_DUAL_SRC_BLEND1 = 22, // GFX11+1024 ET_PARAM0 = 32, // Pre-GFX111025 ET_PARAM31 = 63, // Pre-GFX111026 1027 ET_NULL_MAX_IDX = 0,1028 ET_MRTZ_MAX_IDX = 0,1029 ET_PRIM_MAX_IDX = 0,1030 ET_MRT_MAX_IDX = 7,1031 ET_POS_MAX_IDX = 4,1032 ET_DUAL_SRC_BLEND_MAX_IDX = 1,1033 ET_PARAM_MAX_IDX = 31,1034 1035 ET_INVALID = 255,1036};1037 1038} // namespace Exp1039 1040namespace WMMA {1041enum MatrixFMT : unsigned {1042 MATRIX_FMT_FP8 = 0,1043 MATRIX_FMT_BF8 = 1,1044 MATRIX_FMT_FP6 = 2,1045 MATRIX_FMT_BF6 = 3,1046 MATRIX_FMT_FP4 = 41047};1048 1049enum MatrixScale : unsigned {1050 MATRIX_SCALE_ROW0 = 0,1051 MATRIX_SCALE_ROW1 = 1,1052};1053 1054enum MatrixScaleFmt : unsigned {1055 MATRIX_SCALE_FMT_E8 = 0,1056 MATRIX_SCALE_FMT_E5M3 = 1,1057 MATRIX_SCALE_FMT_E4M3 = 21058};1059} // namespace WMMA1060 1061namespace VOP3PEncoding {1062 1063enum OpSel : uint64_t {1064 OP_SEL_HI_0 = UINT64_C(1) << 59,1065 OP_SEL_HI_1 = UINT64_C(1) << 60,1066 OP_SEL_HI_2 = UINT64_C(1) << 14,1067};1068 1069} // namespace VOP3PEncoding1070 1071namespace ImplicitArg {1072// Implicit kernel argument offset for code object version 5.1073enum Offset_COV5 : unsigned {1074 HOSTCALL_PTR_OFFSET = 80,1075 MULTIGRID_SYNC_ARG_OFFSET = 88,1076 HEAP_PTR_OFFSET = 96,1077 1078 DEFAULT_QUEUE_OFFSET = 104,1079 COMPLETION_ACTION_OFFSET = 112,1080 1081 PRIVATE_BASE_OFFSET = 192,1082 SHARED_BASE_OFFSET = 196,1083 QUEUE_PTR_OFFSET = 200,1084};1085 1086} // namespace ImplicitArg1087 1088namespace MFMAScaleFormats {1089// Enum value used in cbsz/blgp for F8F6F4 MFMA operations to select the matrix1090// format.1091enum MFMAScaleFormats {1092 FP8_E4M3 = 0,1093 FP8_E5M2 = 1,1094 FP6_E2M3 = 2,1095 FP6_E3M2 = 3,1096 FP4_E2M1 = 41097};1098} // namespace MFMAScaleFormats1099 1100namespace VirtRegFlag {1101// Virtual register flags used for various target specific handlings during1102// codegen.1103enum Register_Flag : uint8_t {1104 // Register operand in a whole-wave mode operation.1105 WWM_REG = 1 << 0,1106};1107 1108} // namespace VirtRegFlag1109 1110} // namespace AMDGPU1111 1112namespace AMDGPU {1113namespace Barrier {1114 1115enum Type {1116 CLUSTER_TRAP = -4,1117 CLUSTER = -3,1118 TRAP = -2,1119 WORKGROUP = -1,1120 NAMED_BARRIER_FIRST = 1,1121 NAMED_BARRIER_LAST = 16,1122};1123 1124enum {1125 BARRIER_SCOPE_WORKGROUP = 0,1126};1127 1128} // namespace Barrier1129} // namespace AMDGPU1130 1131// clang-format off1132 1133#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B0281134#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)1135#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)1136#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)1137#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)1138#define C_00B028_MEM_ORDERED 0xFDFFFFFF1139 1140#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C1141#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)1142#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B1281143#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)1144#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)1145#define C_00B128_MEM_ORDERED 0xF7FFFFFF1146 1147#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B2281148#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)1149#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)1150#define C_00B228_WGP_MODE 0xF7FFFFFF1151#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)1152#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)1153#define C_00B228_MEM_ORDERED 0xFDFFFFFF1154 1155#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B3281156#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B4281157#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)1158#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)1159#define C_00B428_WGP_MODE 0xFBFFFFFF1160#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)1161#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)1162#define C_00B428_MEM_ORDERED 0xFEFFFFFF1163 1164#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B5281165 1166#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C1167#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)1168#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)1169#define C_00B84C_SCRATCH_EN 0xFFFFFFFE1170#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)1171#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)1172#define C_00B84C_USER_SGPR 0xFFFFFFC11173#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)1174#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)1175#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF1176#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)1177#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)1178#define C_00B84C_TGID_X_EN 0xFFFFFF7F1179#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)1180#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)1181#define C_00B84C_TGID_Y_EN 0xFFFFFEFF1182#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)1183#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)1184#define C_00B84C_TGID_Z_EN 0xFFFFFDFF1185#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)1186#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)1187#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF1188#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)1189#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)1190#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF1191/* CIK */1192#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)1193#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)1194#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF1195/* */1196#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)1197#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)1198#define C_00B84C_LDS_SIZE 0xFF007FFF1199#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)1200#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)1201#define C_00B84C_EXCP_EN 0x80FFFFFF1202 1203#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC1204#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D01205 1206#define R_00B848_COMPUTE_PGM_RSRC1 0x00B8481207#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)1208#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)1209#define C_00B848_VGPRS 0xFFFFFFC01210#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)1211#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)1212#define C_00B848_SGPRS 0xFFFFFC3F1213#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)1214#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)1215#define C_00B848_PRIORITY 0xFFFFF3FF1216#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)1217#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)1218#define C_00B848_FLOAT_MODE 0xFFF00FFF1219#define S_00B848_PRIV(x) (((x) & 0x1) << 20)1220#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)1221#define C_00B848_PRIV 0xFFEFFFFF1222#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)1223#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)1224#define C_00B848_DX10_CLAMP 0xFFDFFFFF1225#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)1226#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)1227#define C_00B848_RR_WG_MODE 0xFFDFFFFF1228#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)1229#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)1230#define C_00B848_DEBUG_MODE 0xFFBFFFFF1231#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)1232#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)1233#define C_00B848_IEEE_MODE 0xFF7FFFFF1234#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)1235#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)1236#define C_00B848_WGP_MODE 0xDFFFFFFF1237#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)1238#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)1239#define C_00B848_MEM_ORDERED 0xBFFFFFFF1240#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)1241#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)1242#define C_00B848_FWD_PROGRESS 0x7FFFFFFF1243 1244// Helpers for setting FLOAT_MODE1245#define FP_ROUND_ROUND_TO_NEAREST 01246#define FP_ROUND_ROUND_TO_INF 11247#define FP_ROUND_ROUND_TO_NEGINF 21248#define FP_ROUND_ROUND_TO_ZERO 31249 1250// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double1251// precision.1252#define FP_ROUND_MODE_SP(x) ((x) & 0x3)1253#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)1254 1255#define FP_DENORM_FLUSH_IN_FLUSH_OUT 01256#define FP_DENORM_FLUSH_OUT 11257#define FP_DENORM_FLUSH_IN 21258#define FP_DENORM_FLUSH_NONE 31259 1260 1261// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double1262// precision.1263#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)1264#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)1265 1266#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B8601267#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)1268#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)1269#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)1270 1271#define R_0286E8_SPI_TMPRING_SIZE 0x0286E81272#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)1273#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)1274#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)1275 1276#define R_028B54_VGT_SHADER_STAGES_EN 0x028B541277#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)1278#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)1279#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)1280#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D81281#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)1282#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B8001283#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)1284 1285#define R_SPILLED_SGPRS 0x41286#define R_SPILLED_VGPRS 0x81287 1288// clang-format on1289 1290} // End namespace llvm1291 1292#endif1293