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1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// SI Instruction format definitions.10//11//===----------------------------------------------------------------------===//12 13class InstSI <dag outs, dag ins, string asm = "",14 list<dag> pattern = []> :15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {16 // Low bits - basic encoding information.17 field bit SALU = 0;18 field bit VALU = 0;19 20 // SALU instruction formats.21 field bit SOP1 = 0;22 field bit SOP2 = 0;23 field bit SOPC = 0;24 field bit SOPK = 0;25 field bit SOPP = 0;26 27 // VALU instruction formats.28 field bit VOP1 = 0;29 field bit VOP2 = 0;30 field bit VOPC = 0;31 field bit VOP3 = 0;32 field bit VOP3P = 0;33 field bit VINTRP = 0;34 field bit SDWA = 0;35 field bit DPP = 0;36 field bit TRANS = 0;37 38 // Memory instruction formats.39 field bit MUBUF = 0;40 field bit MTBUF = 0;41 field bit SMRD = 0;42 field bit MIMG = 0;43 field bit VIMAGE = 0;44 field bit VSAMPLE = 0;45 field bit EXP = 0;46 field bit FLAT = 0;47 field bit DS = 0;48 49 // Combined SGPR/VGPR spill bit50 field bit Spill = 0;51 52 // LDSDIR instruction format.53 field bit LDSDIR = 0;54 55 // VINTERP instruction format.56 field bit VINTERP = 0;57 58 field bit VOPD3 = 0;59 60 // High bits - other information.61 field bit VM_CNT = 0;62 field bit EXP_CNT = 0;63 field bit LGKM_CNT = 0;64 65 // Whether WQM _must_ be enabled for this instruction.66 field bit WQM = 0;67 68 // Whether WQM _must_ be disabled for this instruction.69 field bit DisableWQM = 0;70 71 field bit Gather4 = 0;72 73 // wait count to manage tensor loads/stores.74 field bit TENSOR_CNT = 0;75 76 // This is an s_store_dword* instruction that requires a cache flush77 // on wave termination. It is necessary to distinguish from mayStore78 // SMEM instructions like the cache flush ones.79 field bit ScalarStore = 0;80 81 // Whether the operands can be ignored when computing the82 // instruction size.83 field bit FixedSize = 0;84 85 // wait count to manage asynchronous loads/stores.86 field bit ASYNC_CNT = 0;87 88 // This bit indicates that this is a VOP3 opcode which supports op_sel89 // modifier.90 field bit VOP3_OPSEL = 0;91 92 // Is it possible for this instruction to be atomic?93 field bit maybeAtomic = 1;94 95 // This bit indicates that this has a floating point result type, so96 // the clamp modifier has floating point semantics.97 field bit FPClamp = 0;98 99 // This bit indicates that instruction may support integer clamping100 // which depends on GPU features.101 field bit IntClamp = 0;102 103 // This field indicates that the clamp applies to the low component104 // of a packed output register.105 field bit ClampLo = 0;106 107 // This field indicates that the clamp applies to the high component108 // of a packed output register.109 field bit ClampHi = 0;110 111 // This bit indicates that this is a packed VOP3P instruction112 field bit IsPacked = 0;113 114 // This bit indicates that this is a D16 buffer instruction.115 field bit D16Buf = 0;116 117 // This field indicates that FLAT instruction accesses FLAT_GLBL segment.118 // Must be 0 for non-FLAT instructions.119 field bit FlatGlobal = 0;120 121 // Reads the mode register, usually for FP environment.122 field bit ReadsModeReg = 0;123 124 // This bit indicates that this uses the floating point double precision125 // rounding mode flags126 field bit FPDPRounding = 0;127 128 // Instruction is FP atomic.129 field bit FPAtomic = 0;130 131 // This bit indicates that this is one of MFMA instructions.132 field bit IsMAI = 0;133 134 // This bit indicates that this is one of DOT instructions.135 field bit IsDOT = 0;136 137 // This field indicates that FLAT instruction accesses FLAT_SCRATCH segment.138 // Must be 0 for non-FLAT instructions.139 field bit FlatScratch = 0;140 141 // Atomic without a return.142 field bit IsAtomicNoRet = 0;143 144 // Atomic with return.145 field bit IsAtomicRet = 0;146 147 // This bit indicates that this is one of WMMA instructions.148 field bit IsWMMA = 0;149 150 // This bit indicates that tied source will not be read.151 field bit TiedSourceNotRead = 0;152 153 // This bit indicates that the instruction is never-uniform/divergent154 field bit IsNeverUniform = 0;155 156 // ds_gws_* instructions.157 field bit GWS = 0;158 159 // This bit indicates that this is one of SWMMAC instructions.160 field bit IsSWMMAC = 0;161 162 // These need to be kept in sync with the enum in SIInstrFlags.163 let TSFlags{0} = SALU;164 let TSFlags{1} = VALU;165 166 let TSFlags{2} = SOP1;167 let TSFlags{3} = SOP2;168 let TSFlags{4} = SOPC;169 let TSFlags{5} = SOPK;170 let TSFlags{6} = SOPP;171 172 let TSFlags{7} = VOP1;173 let TSFlags{8} = VOP2;174 let TSFlags{9} = VOPC;175 let TSFlags{10} = VOP3;176 let TSFlags{12} = VOP3P;177 178 let TSFlags{13} = VINTRP;179 let TSFlags{14} = SDWA;180 let TSFlags{15} = DPP;181 let TSFlags{16} = TRANS;182 183 let TSFlags{17} = MUBUF;184 let TSFlags{18} = MTBUF;185 let TSFlags{19} = SMRD;186 let TSFlags{20} = MIMG;187 let TSFlags{21} = VIMAGE;188 let TSFlags{22} = VSAMPLE;189 let TSFlags{23} = EXP;190 let TSFlags{24} = FLAT;191 let TSFlags{25} = DS;192 193 let TSFlags{26} = Spill;194 195 // Reserved, must be 0196 let TSFlags{27} = 0;197 198 let TSFlags{28} = LDSDIR;199 let TSFlags{29} = VINTERP;200 let TSFlags{30} = VOPD3;201 202 let TSFlags{32} = VM_CNT;203 let TSFlags{33} = EXP_CNT;204 let TSFlags{34} = LGKM_CNT;205 206 let TSFlags{35} = WQM;207 let TSFlags{36} = DisableWQM;208 let TSFlags{37} = Gather4;209 210 let TSFlags{38} = TENSOR_CNT;211 212 let TSFlags{39} = ScalarStore;213 let TSFlags{40} = FixedSize;214 215 let TSFlags{41} = ASYNC_CNT;216 217 let TSFlags{42} = VOP3_OPSEL;218 219 let TSFlags{43} = maybeAtomic;220 221 // Reserved, must be 0.222 let TSFlags{44} = 0;223 224 let TSFlags{45} = FPClamp;225 let TSFlags{46} = IntClamp;226 let TSFlags{47} = ClampLo;227 let TSFlags{48} = ClampHi;228 229 let TSFlags{49} = IsPacked;230 231 let TSFlags{50} = D16Buf;232 233 let TSFlags{51} = FlatGlobal;234 235 let TSFlags{52} = FPDPRounding;236 237 let TSFlags{53} = FPAtomic;238 239 let TSFlags{54} = IsMAI;240 241 let TSFlags{55} = IsDOT;242 243 let TSFlags{56} = FlatScratch;244 245 let TSFlags{57} = IsAtomicNoRet;246 247 let TSFlags{58} = IsAtomicRet;248 249 let TSFlags{59} = IsWMMA;250 251 let TSFlags{60} = TiedSourceNotRead;252 253 let TSFlags{61} = IsNeverUniform;254 255 let TSFlags{62} = GWS;256 257 let TSFlags{63} = IsSWMMAC;258 259 let SchedRW = [Write32Bit];260 261 let AsmVariantName = AMDGPUAsmVariants.Default;262 263 // Avoid changing source registers in a way that violates constant bus read limitations.264 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);265}266 267class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">268 : InstSI<outs, ins, asm, pattern> {269 let isPseudo = 1;270 let isCodeGenOnly = 1;271}272 273class SPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">274 : PseudoInstSI<outs, ins, pattern, asm> {275 let SALU = 1;276}277 278class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">279 : PseudoInstSI<outs, ins, pattern, asm> {280 let VALU = 1;281 let Uses = [EXEC];282}283 284class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],285 bit UseExec = 0, bit DefExec = 0> :286 SPseudoInstSI<outs, ins, pattern> {287 288 let Uses = !if(UseExec, [EXEC], []);289 let Defs = !if(DefExec, [EXEC, SCC], [SCC]);290 let mayLoad = 0;291 let mayStore = 0;292 let hasSideEffects = 0;293}294 295class Enc32 {296 field bits<32> Inst;297 int Size = 4;298}299 300class Enc64 {301 field bits<64> Inst;302 int Size = 8;303}304 305class Enc96 {306 field bits<96> Inst;307 int Size = 12;308}309 310class Enc128 {311 field bits<128> Inst;312 int Size = 16;313}314 315def CPolBit {316 int GLC = 0;317 int SLC = 1;318 int DLC = 2;319 int SCC = 4;320 int NV = 5;321 int SCAL = 11;322}323 324class VOPDstOperand<RegisterClassLike rc> : RegisterOperand<rc, "printVOPDst">;325 326def VOPDstOperand_t16 : VOPDstOperand <VGPR_16> {327 let EncoderMethod = "getMachineOpValueT16";328 let DecoderMethod = "DecodeVGPR_16RegisterClass";329}330 331def VOPDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> {332 let EncoderMethod = "getMachineOpValueT16Lo128";333 let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass";334}335 336// Source-encoded destination operand for instructions like v_swap_b16.337def VOPSrcEncodedDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> {338 let EncoderMethod = VSrcT_b16_Lo128.EncoderMethod;339 let DecoderMethod = VSrcT_b16_Lo128.DecoderMethod;340}341 342class VINTRPe <bits<2> op> : Enc32 {343 bits<8> vdst;344 bits<8> vsrc;345 bits<2> attrchan;346 bits<6> attr;347 348 let Inst{7-0} = vsrc;349 let Inst{9-8} = attrchan;350 let Inst{15-10} = attr;351 let Inst{17-16} = op;352 let Inst{25-18} = vdst;353 let Inst{31-26} = 0x32; // encoding354}355 356class MIMGe_gfxpre11 : Enc64 {357 bits<10> vdata;358 bits<4> dmask;359 bits<1> unorm;360 bits<5> cpol;361 bits<1> r128;362 bits<1> tfe;363 bits<1> lwe;364 bit d16;365 bits<7> srsrc;366 bits<7> ssamp;367 368 let Inst{11-8} = dmask;369 let Inst{12} = unorm;370 let Inst{13} = cpol{CPolBit.GLC};371 let Inst{15} = r128;372 let Inst{17} = lwe;373 let Inst{25} = cpol{CPolBit.SLC};374 let Inst{31-26} = 0x3c;375 let Inst{47-40} = vdata{7-0};376 let Inst{52-48} = srsrc{6-2};377 let Inst{57-53} = ssamp{6-2};378 let Inst{63} = d16;379}380 381class MIMGe_gfx6789 <bits<8> op> : MIMGe_gfxpre11 {382 bits<8> vaddr;383 bits<1> da;384 385 let Inst{0} = op{7};386 let Inst{7} = cpol{CPolBit.SCC};387 let Inst{14} = da;388 let Inst{16} = tfe;389 let Inst{24-18} = op{6-0};390 let Inst{39-32} = vaddr;391}392 393class MIMGe_gfx90a <bits<8> op> : MIMGe_gfxpre11 {394 bits<8> vaddr;395 bits<1> da;396 397 let Inst{0} = op{7};398 let Inst{7} = cpol{CPolBit.SCC};399 let Inst{14} = da;400 let Inst{16} = vdata{9}; // ACC bit401 let Inst{24-18} = op{6-0};402 let Inst{39-32} = vaddr;403}404 405class MIMGe_gfx10 <bits<8> op> : MIMGe_gfxpre11 {406 bits<8> vaddr0;407 bits<3> dim;408 bits<2> nsa;409 bits<1> a16;410 411 let Inst{0} = op{7};412 let Inst{2-1} = nsa;413 let Inst{5-3} = dim;414 let Inst{7} = cpol{CPolBit.DLC};415 let Inst{16} = tfe;416 let Inst{24-18} = op{6-0};417 let Inst{39-32} = vaddr0;418 let Inst{62} = a16;419}420 421class MIMGe_gfx11 <bits<8> op> : Enc64 {422 bits<8> vdata;423 bits<4> dmask;424 bits<1> unorm;425 bits<5> cpol;426 bits<1> r128;427 bits<1> tfe;428 bits<1> lwe;429 bits<7> srsrc;430 bits<7> ssamp;431 bit d16;432 bits<1> a16;433 bits<8> vaddr0;434 bits<3> dim;435 bits<1> nsa;436 437 let Inst{0} = nsa;438 let Inst{4-2} = dim;439 let Inst{7} = unorm;440 let Inst{11-8} = dmask;441 let Inst{12} = cpol{CPolBit.SLC};442 let Inst{13} = cpol{CPolBit.DLC};443 let Inst{14} = cpol{CPolBit.GLC};444 let Inst{15} = r128;445 let Inst{16} = a16;446 let Inst{17} = d16;447 let Inst{25-18} = op;448 let Inst{31-26} = 0x3c;449 let Inst{39-32} = vaddr0;450 let Inst{47-40} = vdata;451 let Inst{52-48} = srsrc{6-2};452 let Inst{53} = tfe;453 let Inst{54} = lwe;454 let Inst{62-58} = ssamp{6-2};455}456 457class VIMAGE_VSAMPLE_Common <bits<8> op> : Enc96 {458 bits<3> dim;459 bits<1> tfe;460 bits<1> r128;461 bit d16;462 bits<1> a16;463 bits<4> dmask;464 bits<8> vdata;465 bits<9> rsrc;466 bits<6> cpol;467 bits<8> vaddr0;468 bits<8> vaddr1;469 bits<8> vaddr2;470 bits<8> vaddr3;471 472 let Inst{2-0} = dim;473 let Inst{4} = r128;474 let Inst{5} = d16;475 let Inst{6} = a16;476 let Inst{7} = cpol{5}; // nv477 let Inst{21-14} = op;478 let Inst{25-22} = dmask;479 let Inst{39-32} = vdata;480 let Inst{49-41} = rsrc;481 let Inst{51-50} = cpol{4-3}; // scope482 let Inst{54-52} = cpol{2-0}; // th483 let Inst{71-64} = vaddr0;484 let Inst{79-72} = vaddr1;485 let Inst{87-80} = vaddr2;486 let Inst{95-88} = vaddr3;487}488 489class VSAMPLEe <bits<8> op> : VIMAGE_VSAMPLE_Common<op> {490 bits<1> unorm;491 bits<1> lwe;492 bits<9> samp;493 494 let Inst{3} = tfe;495 let Inst{13} = unorm;496 let Inst{31-26} = 0x39;497 let Inst{40} = lwe;498 let Inst{63-55} = samp;499}500 501class VIMAGEe <bits<8> op> : VIMAGE_VSAMPLE_Common<op> {502 bits<8> vaddr4;503 504 let Inst{31-26} = 0x34;505 let Inst{55} = tfe;506 let Inst{63-56} = vaddr4;507}508 509class EXPe : Enc64 {510 bits<4> en;511 bits<6> tgt;512 bits<1> done;513 bits<8> src0;514 bits<8> src1;515 bits<8> src2;516 bits<8> src3;517 518 let Inst{3-0} = en;519 let Inst{9-4} = tgt;520 let Inst{11} = done;521 let Inst{31-26} = 0x3e;522 let Inst{39-32} = src0;523 let Inst{47-40} = src1;524 let Inst{55-48} = src2;525 let Inst{63-56} = src3;526}527 528// Pre-GFX11 encoding has compr and vm bits.529class EXPe_ComprVM : EXPe {530 bits<1> compr;531 bits<1> vm;532 533 let Inst{10} = compr;534 let Inst{12} = vm;535}536 537// GFX11+ encoding has row bit.538class EXPe_Row : EXPe {539 bits<1> row;540 541 let Inst{13} = row;542}543 544let Uses = [EXEC] in {545 546class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :547 InstSI <outs, ins, asm, pattern> {548 let VINTRP = 1;549 // VINTRP instructions read parameter values from LDS, but these parameter550 // values are stored outside of the LDS memory that is allocated to the551 // shader for general purpose use.552 //553 // While it may be possible for ds_read/ds_write instructions to access554 // the parameter values in LDS, this would essentially be an out-of-bounds555 // memory access which we consider to be undefined behavior.556 //557 // So even though these instructions read memory, this memory is outside the558 // addressable memory space for the shader, and we consider these instructions559 // to be readnone.560 let mayLoad = 0;561 let mayStore = 0;562 let hasSideEffects = 0;563 let VALU = 1;564}565 566} // End Uses = [EXEC]567