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1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Subregister declarations11//===----------------------------------------------------------------------===//12 13let Namespace = "AMDGPU" in {14 15def lo16 : SubRegIndex<16, 0>;16def hi16 : SubRegIndex<16, 16>;17 18foreach Index = 0...31 in {19 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;20}21 22foreach Index = 1...31 in {23 def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>;24 def sub#Index#_hi16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), hi16>;25}26 27foreach Size = {2...6,8,16} in {28 foreach Index = !range(!sub(33, Size)) in {29 def !interleave(!foreach(cur, !range(Size), "sub"#!add(cur, Index)), "_") :30 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {31 let CoveringSubRegIndices =32 !foreach(cur, !range(Size), !cast<SubRegIndex>(sub#!add(cur, Index)));33 }34 }35}36 37}38 39//===----------------------------------------------------------------------===//40// Helpers41//===----------------------------------------------------------------------===//42 43class getSubRegs<int size> {44 list<SubRegIndex> ret =45 !foreach(idx, !range(0, size), !cast<SubRegIndex>(sub#idx));46}47 48// Generates list of sequential register tuple names.49// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ]50class RegSeqNames<int last_reg, int stride, int size, string prefix> {51 defvar numtuples = !div(!sub(!add(last_reg, stride, 1), size), stride);52 defvar range = !range(0, !mul(numtuples, stride), stride);53 list<string> ret = !foreach(n, range, prefix # "[" # n # ":" # !add(n, size, -1) # "]");54}55 56// Generates list of dags for register tuples.57class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size,58 int start = 0> {59 dag trunc_rc = (trunc RC,60 !if(!and(!eq(stride, 1), !eq(start, 0)),61 !sub(!add(last_reg, 2), size),62 !add(last_reg, 1)));63 list<dag> ret =64 !if(!lt(start, size),65 !listconcat([(add (decimate (shl trunc_rc, start), stride))],66 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret),67 []);68}69 70class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC,71 int last_reg, int stride, int size, string prefix> :72 RegisterTuples<Indices,73 RegSeqDags<RC, last_reg, stride, size>.ret,74 RegSeqNames<last_reg, stride, size, prefix>.ret>;75 76//===----------------------------------------------------------------------===//77// Declarations that describe the SI registers78//===----------------------------------------------------------------------===//79class SIReg <string n, bits<10> regIdx = 0, bit isVGPR = 0,80 bit isAGPR = 0, bit isHi16 = 0> : Register<n> {81 let Namespace = "AMDGPU";82 83 // These are generic helper values we use to form actual register84 // codes. They should not be assumed to match any particular register85 // encodings on any particular subtargets.86 let HWEncoding{9-0} = regIdx;87 let HWEncoding{10} = isVGPR;88 let HWEncoding{11} = isAGPR;89 let HWEncoding{12} = isHi16;90 91 int Index = !cast<int>(regIdx);92}93 94class SIRegisterClassLike<int BW = 0, bit V = false,95 bit A = false,96 bit S = false> {97 // Bitwidth of the register98 field int Size = BW;99 100 // For vector register classes.101 field bit HasVGPR = V;102 field bit HasAGPR = A;103 104 // For scalar register classes.105 field bit HasSGPR = S;106}107 108// For register classes that use TSFlags.109class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>110 : RegisterClass <n, rTypes, Align, rList>, SIRegisterClassLike {111 // Alignment of the first register in tuple (in 32-bit units).112 field int RegTupleAlignUnits = 1;113 114 // These need to be kept in sync with the enum SIRCFlags.115 let TSFlags{1-0} = RegTupleAlignUnits;116 let TSFlags{2} = HasVGPR;117 let TSFlags{3} = HasAGPR;118 let TSFlags{4} = HasSGPR;119 120 // RA will use RegisterClass AllocationPriority amongst other info (e.g. ordering in the basic block)121 // to decide which registers to try to assign first. Usually, this RegisterClass priority is given122 // very high priority, if not the highest priority, when considering which VirtReg to allocate next.123 //124 // We have 5 bits to assign AllocationPriorities to RegisterClasses. Generally, it is beneficial to125 // assign more constrained RegisterClasses first. As a result, we prioritize register classes with126 // more 32 bit tuples (e.g. VReg_512) over registers with fewer tuples (e.g. VGPR_32).127 //128 // The interesting case is the vector register case on architectures which have ARegs, VRegs, AVRegs.129 // In this case, we would like to assign ARegs and VRegs before AVRegs, as AVRegs are less constrained130 // and can be assigned to both AGPRs and VGPRs. We use the 5th bit to encode this into the131 // RegisterClass AllocationPriority. BaseClassPriority is used to turn the bit on, and BaseClassScaleFactor132 // is used for scaling of the bit (i.e. 1 << 4).133 field int BaseClassPriority = 1;134 field int BaseClassScaleFactor = 16;135 136}137 138multiclass SIRegLoHi16 <string n, bits<10> regIdx, bit ArtificialHigh = 1,139 bit isVGPR = 0, bit isAGPR = 0,140 list<int> DwarfEncodings = [-1, -1]> {141 def _LO16 : SIReg<n#".l", regIdx, isVGPR, isAGPR>;142 def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx, isVGPR, isAGPR,143 /* isHi16 */ 1> {144 let isArtificial = ArtificialHigh;145 }146 def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"),147 !cast<Register>(NAME#"_HI16")]>,148 DwarfRegNum<DwarfEncodings> {149 let Namespace = "AMDGPU";150 let SubRegIndices = [lo16, hi16];151 let CoveredBySubRegs = !not(ArtificialHigh);152 153 let HWEncoding{9-0} = regIdx;154 let HWEncoding{10} = isVGPR;155 let HWEncoding{11} = isAGPR;156 157 int Index = !cast<int>(regIdx);158 }159}160 161// Special Registers162defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>;163defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>;164 165// Pseudo-registers: Used as placeholders during isel and immediately166// replaced, never seeing the verifier.167def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>;168def FP_REG : SIReg<"fp", 0>;169def SP_REG : SIReg<"sp", 0>;170 171// Pseudo-register to represent the program-counter DWARF register.172def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> {173 // There is no physical register corresponding to a "program counter", but174 // we need to encode the concept in debug information in order to represent175 // things like the return value in unwind information.176 let isArtificial = 1;177}178 179// VCC for 64-bit instructions180def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {181 let Namespace = "AMDGPU";182 let SubRegIndices = [sub0, sub1];183 let HWEncoding = VCC_LO.HWEncoding;184}185 186defm EXEC_LO : SIRegLoHi16<"exec_lo", 126, /*ArtificialHigh=*/1, /*isVGPR=*/0,187 /*isAGPR=*/0, /*DwarfEncodings=*/[1, 1]>;188defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>;189 190def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {191 let Namespace = "AMDGPU";192 let SubRegIndices = [sub0, sub1];193 let HWEncoding = EXEC_LO.HWEncoding;194}195 196// 32-bit real registers, for MC only.197// May be used with both 32-bit and 64-bit operands.198defm SRC_VCCZ : SIRegLoHi16<"src_vccz", 251>;199defm SRC_EXECZ : SIRegLoHi16<"src_execz", 252>;200defm SRC_SCC : SIRegLoHi16<"src_scc", 253>;201 202// 1-bit pseudo register, for codegen only.203// Should never be emitted.204def SCC : SIReg<"scc">;205 206// Encoding changes between subtarget generations.207// See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG.208defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>;209defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>;210defm M0 : SIRegLoHi16 <"m0", 0>;211 212defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>;213defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>;214let isConstant = true in {215defm SGPR_NULL : SIRegLoHi16 <"null", 0>;216defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>;217} // isConstant = true218 219def SGPR_NULL64 :220 RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> {221 let Namespace = "AMDGPU";222 let SubRegIndices = [sub0, sub1];223 let HWEncoding = SGPR_NULL.HWEncoding;224 let isConstant = true;225}226 227// Aperture registers are 64 bit registers with a LO/HI 32 bit.228// HI 32 bit cannot be used, and LO 32 is used by instructions229// with 32 bit sources.230//231// Note that the low 32 bits are essentially useless as they232// don't contain the lower 32 bits of the address - they are in233// the high 32 bits. The lower 32 bits are always zero (for base) or234// -1 (for limit). Since we cannot access the high 32 bits, when we235// need them, we need to do a 64 bit load and extract the bits manually.236multiclass ApertureRegister<string name, bits<10> regIdx> {237 let isConstant = true in {238 defm _LO : SIRegLoHi16 <name, regIdx>;239 def "" : RegisterWithSubRegs<name, [!cast<Register>(NAME#_LO)]> {240 let Namespace = "AMDGPU";241 let SubRegIndices = [sub0];242 let HWEncoding = !cast<Register>(NAME#_LO).HWEncoding;243 let CoveredBySubRegs = 0;244 }245 } // isConstant = true246}247 248defm SRC_SHARED_BASE : ApertureRegister<"src_shared_base", 235>;249defm SRC_SHARED_LIMIT : ApertureRegister<"src_shared_limit", 236>;250defm SRC_PRIVATE_BASE : ApertureRegister<"src_private_base", 237>;251defm SRC_PRIVATE_LIMIT : ApertureRegister<"src_private_limit", 238>;252 253let isConstant = true in {254 defm SRC_FLAT_SCRATCH_BASE_LO : SIRegLoHi16<"src_flat_scratch_base_lo", 230>;255 defm SRC_FLAT_SCRATCH_BASE_HI : SIRegLoHi16<"src_flat_scratch_base_hi", 231>;256 257 // Using src_flat_scratch_base_lo in a 64-bit context gets the full 64-bit258 // hi:lo value.259 def SRC_FLAT_SCRATCH_BASE :260 RegisterWithSubRegs<"src_flat_scratch_base_lo",261 [SRC_FLAT_SCRATCH_BASE_LO,262 SRC_FLAT_SCRATCH_BASE_HI]> {263 let Namespace = "AMDGPU";264 let SubRegIndices = [sub0, sub1];265 let HWEncoding = SRC_FLAT_SCRATCH_BASE_LO.HWEncoding;266 }267}268 269defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>;270 271// Not addressable272def MODE : SIReg <"mode", 0>;273 274// Not addressable, used to model dependencies.275def ASYNCcnt : SIReg <"ASYNCcnt", 0>;276def TENSORcnt : SIReg <"TENSORcnt", 0>;277 278def LDS_DIRECT : SIReg <"src_lds_direct", 254> {279 // There is no physical register corresponding to this. This is an280 // encoding value in a source field, which will ultimately trigger a281 // read from m0.282 let isArtificial = 1;283}284 285defm XNACK_MASK_LO : SIRegLoHi16<"xnack_mask_lo", 104>;286defm XNACK_MASK_HI : SIRegLoHi16<"xnack_mask_hi", 105>;287 288def XNACK_MASK :289 RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> {290 let Namespace = "AMDGPU";291 let SubRegIndices = [sub0, sub1];292 let HWEncoding = XNACK_MASK_LO.HWEncoding;293}294 295// Trap handler registers296defm TBA_LO : SIRegLoHi16<"tba_lo", 108>;297defm TBA_HI : SIRegLoHi16<"tba_hi", 109>;298 299def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> {300 let Namespace = "AMDGPU";301 let SubRegIndices = [sub0, sub1];302 let HWEncoding = TBA_LO.HWEncoding;303}304 305defm TMA_LO : SIRegLoHi16<"tma_lo", 110>;306defm TMA_HI : SIRegLoHi16<"tma_hi", 111>;307 308def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> {309 let Namespace = "AMDGPU";310 let SubRegIndices = [sub0, sub1];311 let HWEncoding = TMA_LO.HWEncoding;312}313 314foreach Index = 0...15 in {315 defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>;316 defm TTMP#Index#_gfx9plus : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>;317 defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>;318}319 320multiclass FLAT_SCR_LOHI_m <string n, bits<10> ci_e, bits<10> vi_e> {321 defm _ci : SIRegLoHi16<n, ci_e>;322 defm _vi : SIRegLoHi16<n, vi_e>;323 defm "" : SIRegLoHi16<n, 0>;324}325 326class FlatReg <Register lo, Register hi, bits<16> encoding> :327 RegisterWithSubRegs<"flat_scratch", [lo, hi]> {328 let Namespace = "AMDGPU";329 let SubRegIndices = [sub0, sub1];330 let HWEncoding = encoding;331}332 333defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes.334defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes.335 336def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>;337def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>;338def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;339 340// SGPR registers341foreach Index = 0...105 in {342 defm SGPR#Index :343 SIRegLoHi16 <"s"#Index, Index, /*ArtificialHigh=*/1,344 /*isVGPR=*/0, /*isAGPR=*/0, /*DwarfEncodings=*/345 [!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),346 !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;347}348 349// VGPR registers350foreach Index = 0...1023 in {351 defm VGPR#Index :352 SIRegLoHi16 <"v"#Index, Index, /*ArtificialHigh=*/ 0,353 /*isVGPR=*/ 1, /*isAGPR=*/ 0, /*DwarfEncodings=*/354 [!if(!le(Index, 511), !add(Index, 2560), -1),355 !if(!le(Index, 511), !add(Index, 1536), !add(Index, !sub(3584, 512)))]>;356}357 358// AccVGPR registers359foreach Index = 0...255 in {360 defm AGPR#Index :361 SIRegLoHi16 <"a"#Index, Index, /*ArtificialHigh=*/ 1,362 /*isVGPR=*/ 0, /*isAGPR=*/ 1, /*DwarfEncodings=*/363 [!add(Index, 3072), !add(Index, 2048)]>;364}365 366//===----------------------------------------------------------------------===//367// Groupings using register classes and tuples368//===----------------------------------------------------------------------===//369 370def SCC_CLASS : SIRegisterClass<"AMDGPU", [i1], 1, (add SCC)> {371 let CopyCost = -1;372 let isAllocatable = 0;373 let HasSGPR = 1;374 let BaseClassOrder = 10000;375}376 377// TODO: Do we need to set DwarfRegAlias on register tuples?378 379def SGPR_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,380 (add (sequence "SGPR%u_LO16", 0, 105))> {381 let AllocationPriority = 0;382 let Size = 16;383 let GeneratePressureSet = 0;384 let HasSGPR = 1;385}386 387def SGPR_HI16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,388 (add (sequence "SGPR%u_HI16", 0, 105))> {389 let isAllocatable = 0;390 let Size = 16;391 let GeneratePressureSet = 0;392 let HasSGPR = 1;393}394 395// SGPR 32-bit registers396def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,397 (add (sequence "SGPR%u", 0, 105))> {398 // Give all SGPR classes higher priority than VGPR classes, because399 // we want to spill SGPRs to VGPRs.400 let AllocationPriority = 0;401 let GeneratePressureSet = 0;402 let HasSGPR = 1;403}404 405// SGPR 64-bit registers406def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">;407 408// SGPR 96-bit registers.409def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 4, 3, "s">;410 411// SGPR 128-bit registers412def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">;413 414// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs.415def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">;416 417// SGPR 192-bit registers. No operations use these, but for symmetry with 192-bit VGPRs.418def SGPR_192Regs : SIRegisterTuples<getSubRegs<6>.ret, SGPR_32, 105, 4, 6, "s">;419 420// SGPR 224-bit registers. No operations use these, but for symmetry with 224-bit VGPRs.421def SGPR_224Regs : SIRegisterTuples<getSubRegs<7>.ret, SGPR_32, 105, 4, 7, "s">;422 423// SGPR 256-bit registers424def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">;425 426// SGPR 288-bit registers. No operations use these, but for symmetry with 288-bit VGPRs.427def SGPR_288Regs : SIRegisterTuples<getSubRegs<9>.ret, SGPR_32, 105, 4, 9, "s">;428 429// SGPR 320-bit registers. No operations use these, but for symmetry with 320-bit VGPRs.430def SGPR_320Regs : SIRegisterTuples<getSubRegs<10>.ret, SGPR_32, 105, 4, 10, "s">;431 432// SGPR 352-bit registers. No operations use these, but for symmetry with 352-bit VGPRs.433def SGPR_352Regs : SIRegisterTuples<getSubRegs<11>.ret, SGPR_32, 105, 4, 11, "s">;434 435// SGPR 384-bit registers. No operations use these, but for symmetry with 384-bit VGPRs.436def SGPR_384Regs : SIRegisterTuples<getSubRegs<12>.ret, SGPR_32, 105, 4, 12, "s">;437 438// SGPR 512-bit registers439def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">;440 441// SGPR 1024-bit registers442def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">;443 444// Trap handler TMP 32-bit registers445def TTMP_32 : SIRegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16, v2bf16], 32,446 (add (sequence "TTMP%u", 0, 15))> {447 let isAllocatable = 0;448 let HasSGPR = 1;449}450 451// Trap handler TMP 16-bit registers452def TTMP_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,453 (add (sequence "TTMP%u_LO16", 0, 15))> {454 let Size = 16;455 let isAllocatable = 0;456 let HasSGPR = 1;457}458 459// Trap handler TMP 64-bit registers460def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">;461 462// Trap handler TMP 96-bit registers463def TTMP_96Regs : SIRegisterTuples<getSubRegs<3>.ret, TTMP_32, 15, 4, 3, "ttmp">;464 465// Trap handler TMP 128-bit registers466def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">;467 468// Trap handler TMP 160-bit registers469def TTMP_160Regs : SIRegisterTuples<getSubRegs<5>.ret, TTMP_32, 15, 4, 5, "ttmp">;470 471// Trap handler TMP 192-bit registers472def TTMP_192Regs : SIRegisterTuples<getSubRegs<6>.ret, TTMP_32, 15, 4, 6, "ttmp">;473 474// Trap handler TMP 224-bit registers475def TTMP_224Regs : SIRegisterTuples<getSubRegs<7>.ret, TTMP_32, 15, 4, 7, "ttmp">;476 477// Trap handler TMP 256-bit registers478def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">;479 480// Trap handler TMP 288-bit registers481def TTMP_288Regs : SIRegisterTuples<getSubRegs<9>.ret, TTMP_32, 15, 4, 9, "ttmp">;482 483// Trap handler TMP 320-bit registers484def TTMP_320Regs : SIRegisterTuples<getSubRegs<10>.ret, TTMP_32, 15, 4, 10, "ttmp">;485 486// Trap handler TMP 352-bit registers487def TTMP_352Regs : SIRegisterTuples<getSubRegs<11>.ret, TTMP_32, 15, 4, 11, "ttmp">;488 489// Trap handler TMP 384-bit registers490def TTMP_384Regs : SIRegisterTuples<getSubRegs<12>.ret, TTMP_32, 15, 4, 12, "ttmp">;491 492// Trap handler TMP 512-bit registers493def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">;494 495class TmpRegTuplesBase<int index, int size,496 list<Register> subRegs,497 list<SubRegIndex> indices = getSubRegs<size>.ret,498 int index1 = !add(index, size, -1),499 string name = "ttmp["#index#":"#index1#"]"> :500 RegisterWithSubRegs<name, subRegs> {501 let HWEncoding = subRegs[0].HWEncoding;502 let SubRegIndices = indices;503}504 505class TmpRegTuples<string tgt,506 int size,507 int index0,508 int index1 = !add(index0, 1),509 int index2 = !add(index0, !if(!eq(size, 2), 1, 2)),510 int index3 = !add(index0, !if(!eq(size, 2), 1, 3)),511 int index4 = !add(index0, !if(!eq(size, 8), 4, 1)),512 int index5 = !add(index0, !if(!eq(size, 8), 5, 1)),513 int index6 = !add(index0, !if(!eq(size, 8), 6, 1)),514 int index7 = !add(index0, !if(!eq(size, 8), 7, 1)),515 Register r0 = !cast<Register>("TTMP"#index0#tgt),516 Register r1 = !cast<Register>("TTMP"#index1#tgt),517 Register r2 = !cast<Register>("TTMP"#index2#tgt),518 Register r3 = !cast<Register>("TTMP"#index3#tgt),519 Register r4 = !cast<Register>("TTMP"#index4#tgt),520 Register r5 = !cast<Register>("TTMP"#index5#tgt),521 Register r6 = !cast<Register>("TTMP"#index6#tgt),522 Register r7 = !cast<Register>("TTMP"#index7#tgt)> :523 TmpRegTuplesBase<index0, size,524 !if(!eq(size, 2), [r0, r1],525 !if(!eq(size, 4), [r0, r1, r2, r3],526 [r0, r1, r2, r3, r4, r5, r6, r7])),527 getSubRegs<size>.ret>;528 529foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in {530 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>;531 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9plus : TmpRegTuples<"_gfx9plus", 2, Index>;532}533 534foreach Index = {0, 4, 8, 12} in {535 def TTMP#Index#_TTMP#!add(Index,1)#536 _TTMP#!add(Index,2)#537 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>;538 def TTMP#Index#_TTMP#!add(Index,1)#539 _TTMP#!add(Index,2)#540 _TTMP#!add(Index,3)#_gfx9plus : TmpRegTuples<"_gfx9plus", 4, Index>;541}542 543foreach Index = {0, 4, 8} in {544 def TTMP#Index#_TTMP#!add(Index,1)#545 _TTMP#!add(Index,2)#546 _TTMP#!add(Index,3)#547 _TTMP#!add(Index,4)#548 _TTMP#!add(Index,5)#549 _TTMP#!add(Index,6)#550 _TTMP#!add(Index,7)#_vi : TmpRegTuples<"_vi", 8, Index>;551 def TTMP#Index#_TTMP#!add(Index,1)#552 _TTMP#!add(Index,2)#553 _TTMP#!add(Index,3)#554 _TTMP#!add(Index,4)#555 _TTMP#!add(Index,5)#556 _TTMP#!add(Index,6)#557 _TTMP#!add(Index,7)#_gfx9plus : TmpRegTuples<"_gfx9plus", 8, Index>;558}559 560def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi :561 TmpRegTuplesBase<0, 16,562 [TTMP0_vi, TTMP1_vi, TTMP2_vi, TTMP3_vi,563 TTMP4_vi, TTMP5_vi, TTMP6_vi, TTMP7_vi,564 TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi,565 TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>;566 567def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus :568 TmpRegTuplesBase<0, 16,569 [TTMP0_gfx9plus, TTMP1_gfx9plus, TTMP2_gfx9plus, TTMP3_gfx9plus,570 TTMP4_gfx9plus, TTMP5_gfx9plus, TTMP6_gfx9plus, TTMP7_gfx9plus,571 TTMP8_gfx9plus, TTMP9_gfx9plus, TTMP10_gfx9plus, TTMP11_gfx9plus,572 TTMP12_gfx9plus, TTMP13_gfx9plus, TTMP14_gfx9plus, TTMP15_gfx9plus]>;573 574class RegisterTypes<list<ValueType> reg_types> {575 list<ValueType> types = reg_types;576}577 578def Reg16Types : RegisterTypes<[i16, f16, bf16]>;579def Reg32DataTypes: RegisterTypes<[i32, f32, v2i16, v2f16, v2bf16]>;580def Reg32PtrTypes: RegisterTypes<[p2, p3, p5, p6]>;581def Reg32Types : RegisterTypes<!listconcat(Reg32DataTypes.types, Reg32PtrTypes.types)>;582def Reg64DataTypes: RegisterTypes<[i64, f64, v2i32, v2f32, v4i16, v4f16, v4bf16]>;583def Reg64PtrTypes: RegisterTypes<[p0, p1, p4]>;584def Reg64Types : RegisterTypes<!listconcat(Reg64DataTypes.types, Reg64PtrTypes.types)>;585def Reg96Types : RegisterTypes<[v3i32, v3f32]>;586def Reg128Types : RegisterTypes<[v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16]>;587def Reg160Types : RegisterTypes<[v5i32, v5f32]>;588def Reg192Types : RegisterTypes<[v6i32, v6f32, v3i64, v3f64]>;589def Reg224Types : RegisterTypes<[v7i32, v7f32]>;590def Reg256Types : RegisterTypes<[v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16]>;591def Reg288Types : RegisterTypes<[v9i32, v9f32]>;592def Reg320Types : RegisterTypes<[v10i32, v10f32]>;593def Reg352Types : RegisterTypes<[v11i32, v11f32]>;594def Reg384Types : RegisterTypes<[v12i32, v12f32]>;595def Reg512Types : RegisterTypes<[v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16]>;596def Reg1024Types : RegisterTypes<[v32i32, v32f32, v16i64, v16f64]>;597 598let HasVGPR = 1 in {599// VOP3 and VINTERP can access 1024 lo and 1024 hi registers.600def VGPR_16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,601 (add (interleave (sequence "VGPR%u_LO16", 0, 1023),602 (sequence "VGPR%u_HI16", 0, 1023)))> {603 let AllocationPriority = !add(2, !mul(BaseClassPriority, BaseClassScaleFactor));604 let Size = 16;605 let GeneratePressureSet = 0;606 607 // This is the base class for VGPR{128..1023}_{LO16,HI16}.608 let BaseClassOrder = 17;609}610 611// VOP1/2/C can access the First 128 lo and 128 hi registers.612// The order of registers in the class determines order of allocation, so it is613// important to interleave lo and hi registers.614def VGPR_16_Lo128 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,615 (add (interleave (sequence "VGPR%u_LO16", 0, 127),616 (sequence "VGPR%u_HI16", 0, 127)))> {617 let Size = 16;618 let GeneratePressureSet = 0;619 let isAllocatable = 0;620 621 // This is the base class for VGPR{0..127}_{LO16,HI16}.622 let BaseClassOrder = 16;623}624 625// VGPR 32-bit registers626// i16/f16 only on VI+627def VGPR_32 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32,628 (add (sequence "VGPR%u", 0, 1023))> {629 let AllocationPriority = !add(0, !mul(BaseClassPriority, BaseClassScaleFactor));630 let Size = 32;631 let Weight = 1;632 let BaseClassOrder = 32;633}634 635// Identical to VGPR_32 except it only contains the low 128 (Lo128) registers.636def VGPR_32_Lo128 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32,637 (add (sequence "VGPR%u", 0, 127))> {638 let AllocationPriority = !add(0, !mul(BaseClassPriority, BaseClassScaleFactor));639 let GeneratePressureSet = 0;640 let Size = 32;641 let Weight = 1;642}643 644// Identical to VGPR_32 except it only contains the low 256 (Lo256) registers.645def VGPR_32_Lo256 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32,646 (add (sequence "VGPR%u", 0, 255))> {647 let AllocationPriority = !add(3, !mul(BaseClassPriority, BaseClassScaleFactor));648 let GeneratePressureSet = 0;649 let Size = 32;650 let Weight = 1;651}652} // End HasVGPR = 1653 654// VGPR 64-bit registers655def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 1023, 1, 2, "v">;656 657// VGPR 96-bit registers658def VGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, VGPR_32, 1023, 1, 3, "v">;659 660// VGPR 128-bit registers661def VGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, VGPR_32, 1023, 1, 4, "v">;662 663// VGPR 160-bit registers664def VGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, VGPR_32, 1023, 1, 5, "v">;665 666// VGPR 192-bit registers667def VGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, VGPR_32, 1023, 1, 6, "v">;668 669// VGPR 224-bit registers670def VGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, VGPR_32, 1023, 1, 7, "v">;671 672// VGPR 256-bit registers673def VGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, VGPR_32, 1023, 1, 8, "v">;674 675// VGPR 288-bit registers676def VGPR_288 : SIRegisterTuples<getSubRegs<9>.ret, VGPR_32, 1023, 1, 9, "v">;677 678// VGPR 320-bit registers679def VGPR_320 : SIRegisterTuples<getSubRegs<10>.ret, VGPR_32, 1023, 1, 10, "v">;680 681// VGPR 352-bit registers682def VGPR_352 : SIRegisterTuples<getSubRegs<11>.ret, VGPR_32, 1023, 1, 11, "v">;683 684// VGPR 384-bit registers685def VGPR_384 : SIRegisterTuples<getSubRegs<12>.ret, VGPR_32, 1023, 1, 12, "v">;686 687// VGPR 512-bit registers688def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 1023, 1, 16, "v">;689 690// VGPR 1024-bit registers691def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 1023, 1, 32, "v">;692 693let HasAGPR = 1 in {694def AGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,695 (add (sequence "AGPR%u_LO16", 0, 255))> {696 let isAllocatable = 0;697 let Size = 16;698 let GeneratePressureSet = 0;699 let BaseClassOrder = 16;700}701 702// AccVGPR 32-bit registers703def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,704 (add (sequence "AGPR%u", 0, 255))> {705 let AllocationPriority = !add(0, !mul(BaseClassPriority, BaseClassScaleFactor));706 let Size = 32;707 let Weight = 1;708 let BaseClassOrder = 32;709}710} // End HasAGPR = 1711 712// AGPR 64-bit registers713def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">;714 715// AGPR 96-bit registers716def AGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, AGPR_32, 255, 1, 3, "a">;717 718// AGPR 128-bit registers719def AGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, AGPR_32, 255, 1, 4, "a">;720 721// AGPR 160-bit registers722def AGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, AGPR_32, 255, 1, 5, "a">;723 724// AGPR 192-bit registers725def AGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, AGPR_32, 255, 1, 6, "a">;726 727// AGPR 224-bit registers728def AGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, AGPR_32, 255, 1, 7, "a">;729 730// AGPR 256-bit registers731def AGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, AGPR_32, 255, 1, 8, "a">;732 733// AGPR 288-bit registers734def AGPR_288 : SIRegisterTuples<getSubRegs<9>.ret, AGPR_32, 255, 1, 9, "a">;735 736// AGPR 320-bit registers737def AGPR_320 : SIRegisterTuples<getSubRegs<10>.ret, AGPR_32, 255, 1, 10, "a">;738 739// AGPR 352-bit registers740def AGPR_352 : SIRegisterTuples<getSubRegs<11>.ret, AGPR_32, 255, 1, 11, "a">;741 742// AGPR 384-bit registers743def AGPR_384 : SIRegisterTuples<getSubRegs<12>.ret, AGPR_32, 255, 1, 12, "a">;744 745// AGPR 512-bit registers746def AGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, AGPR_32, 255, 1, 16, "a">;747 748// AGPR 1024-bit registers749def AGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, AGPR_32, 255, 1, 32, "a">;750 751//===----------------------------------------------------------------------===//752// Register classes used as source and destination753//===----------------------------------------------------------------------===//754 755def Pseudo_SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,756 (add FP_REG, SP_REG)> {757 let isAllocatable = 0;758 let CopyCost = -1;759 let HasSGPR = 1;760 let BaseClassOrder = 10000;761}762 763def Pseudo_SReg_128 : SIRegisterClass<"AMDGPU", Reg128Types.types, 32,764 (add PRIVATE_RSRC_REG)> {765 let isAllocatable = 0;766 let CopyCost = -1;767 let HasSGPR = 1;768 let BaseClassOrder = 10000;769}770 771let GeneratePressureSet = 0, HasSGPR = 1 in {772// Subset of SReg_32 without M0 for SMRD instructions and alike.773// See comments in SIInstructions.td for more info.774def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32,775 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI,776 SGPR_NULL, SGPR_NULL_HI, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE_LO,777 SRC_SHARED_LIMIT_LO, SRC_PRIVATE_BASE_LO, SRC_PRIVATE_LIMIT_LO, SRC_POPS_EXITING_WAVE_ID,778 SRC_VCCZ, SRC_EXECZ, SRC_SCC, SRC_FLAT_SCRATCH_BASE_LO, SRC_FLAT_SCRATCH_BASE_HI)> {779 let AllocationPriority = 0;780}781 782def SReg_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,783 (add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16,784 XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, SGPR_NULL_HI_LO16, TTMP_LO16,785 TMA_LO_LO16, TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO_LO16,786 SRC_SHARED_LIMIT_LO_LO16, SRC_PRIVATE_BASE_LO_LO16, SRC_PRIVATE_LIMIT_LO_LO16,787 SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, SRC_EXECZ_LO16, SRC_SCC_LO16,788 EXEC_LO_LO16, EXEC_HI_LO16, M0_LO16, SRC_FLAT_SCRATCH_BASE_LO_LO16,789 SRC_FLAT_SCRATCH_BASE_HI_LO16)> {790 let Size = 16;791 let isAllocatable = 0;792 let BaseClassOrder = 16;793}794 795def SReg_32_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32,796 (add SReg_32_XM0_XEXEC, M0)> {797 let AllocationPriority = 0;798}799 800def SReg_32_XEXEC_HI : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32,801 (add SReg_32_XEXEC, EXEC_LO)> {802 let AllocationPriority = 0;803}804 805def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32,806 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {807 let AllocationPriority = 0;808}809 810def APERTURE_Class : SIRegisterClass<"AMDGPU", Reg64Types.types, 32,811 (add SRC_SHARED_BASE, SRC_SHARED_LIMIT, SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT)> {812 let isAllocatable = 0;813 let Size = 64;814 let BaseClassOrder = 10000;815}816 817} // End GeneratePressureSet = 0818 819// Register class for all scalar registers (SGPRs + Special Registers)820def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32,821 (add SReg_32_XM0, M0)> {822 let AllocationPriority = 0;823 let HasSGPR = 1;824 let BaseClassOrder = 32;825 let Size = 32;826}827 828def SGPR_NULL128 : SIReg<"null">;829def SGPR_NULL256 : SIReg<"null">;830 831let GeneratePressureSet = 0 in {832def SRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,833 (add SReg_32, LDS_DIRECT)> {834 let isAllocatable = 0;835 let HasSGPR = 1;836 let Size = 32;837}838 839def SGPR_64 : SIRegisterClass<"AMDGPU", Reg64Types.types, 32,840 (add SGPR_64Regs)> {841 let CopyCost = 1;842 let AllocationPriority = 1;843 let HasSGPR = 1;844}845 846// CCR (call clobbered registers) SGPR 64-bit registers847def CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, (add (trunc SGPR_64, 15))> {848 let CopyCost = SGPR_64.CopyCost;849 let AllocationPriority = SGPR_64.AllocationPriority;850 let HasSGPR = 1;851}852 853// Call clobbered 64-bit SGPRs for AMDGPU_Gfx CC854def Gfx_CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32,855 (add (trunc (shl SGPR_64, 18), 14))> { // s[36:37]-s[s62:63]856 let CopyCost = SGPR_64.CopyCost;857 let AllocationPriority = SGPR_64.AllocationPriority;858 let HasSGPR = 1;859}860 861def TTMP_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16, v4bf16], 32,862 (add TTMP_64Regs)> {863 let isAllocatable = 0;864 let HasSGPR = 1;865}866 867def SReg_64_XEXEC_XNULL : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16, v4bf16], 32,868 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA,869 SRC_FLAT_SCRATCH_BASE)> {870 let CopyCost = 1;871 let AllocationPriority = 1;872 let HasSGPR = 1;873}874 875def SReg_64_XEXEC : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16, v4bf16], 32,876 (add SReg_64_XEXEC_XNULL, SGPR_NULL64)> {877 let CopyCost = 1;878 let AllocationPriority = 1;879 let HasSGPR = 1;880}881 882def SReg_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16, v4bf16], 32,883 (add SReg_64_XEXEC, EXEC)> {884 let CopyCost = 1;885 let AllocationPriority = 1;886 let HasSGPR = 1;887 let BaseClassOrder = 64;888 let Size = 64;889}890 891def SReg_64_Encodable : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16, v4bf16], 32,892 (add SReg_64, APERTURE_Class)> {893 let CopyCost = 1;894 let isAllocatable = 0;895 let HasSGPR = 1;896 let Size = 64;897}898 899multiclass SRegClass<int numRegs,900 list<ValueType> regTypes,901 SIRegisterTuples regList,902 SIRegisterTuples ttmpList = regList,903 bit hasNull = 0,904 int copyCost = !sra(!add(numRegs, 1), 1)> {905 defvar hasTTMP = !ne(regList, ttmpList);906 defvar suffix = !cast<string>(!mul(numRegs, 32));907 defvar sgprName = !strconcat("SGPR_", suffix);908 defvar ttmpName = !strconcat("TTMP_", suffix);909 910 let AllocationPriority = !sub(numRegs, 1), CopyCost = copyCost, HasSGPR = 1 in {911 def "" # sgprName : SIRegisterClass<"AMDGPU", regTypes, 32, (add regList)> {912 }913 914 if hasTTMP then {915 def "" # ttmpName : SIRegisterClass<"AMDGPU", regTypes, 32, (add ttmpList)> {916 let isAllocatable = 0;917 }918 }919 920 def SReg_ # suffix # !if(hasNull, "_XNULL", ""):921 SIRegisterClass<"AMDGPU", regTypes, 32,922 !con((add !cast<RegisterClass>(sgprName)),923 !if(hasTTMP,924 (add !cast<RegisterClass>(ttmpName)),925 (add)))> {926 let isAllocatable = 0;927 let BaseClassOrder = !mul(numRegs, 32);928 }929 930 if hasNull then {931 def SReg_ # suffix :932 SIRegisterClass<"AMDGPU", regTypes, 32,933 (add !cast<RegisterClass>("SReg_" # suffix # "_XNULL"), !cast<Register>("SGPR_NULL" # suffix))> {934 let isAllocatable = 0;935 let BaseClassOrder = !mul(numRegs, 32);936 }937 }938 }939}940 941defm "" : SRegClass<3, Reg96Types.types, SGPR_96Regs, TTMP_96Regs>;942defm "" : SRegClass<4, Reg128Types.types, SGPR_128Regs, TTMP_128Regs, /*hasNull*/ true>;943defm "" : SRegClass<5, Reg160Types.types, SGPR_160Regs, TTMP_160Regs>;944defm "" : SRegClass<6, Reg192Types.types, SGPR_192Regs, TTMP_192Regs>;945defm "" : SRegClass<7, Reg224Types.types, SGPR_224Regs, TTMP_224Regs>;946defm "" : SRegClass<8, Reg256Types.types, SGPR_256Regs, TTMP_256Regs, /*hasNull*/ true>;947defm "" : SRegClass<9, Reg288Types.types, SGPR_288Regs, TTMP_288Regs>;948defm "" : SRegClass<10, Reg320Types.types, SGPR_320Regs, TTMP_320Regs>;949defm "" : SRegClass<11, Reg352Types.types, SGPR_352Regs, TTMP_352Regs>;950defm "" : SRegClass<12, Reg384Types.types, SGPR_384Regs, TTMP_384Regs>;951 952let GlobalPriority = true in {953defm "" : SRegClass<16, Reg512Types.types, SGPR_512Regs, TTMP_512Regs>;954defm "" : SRegClass<32, Reg1024Types.types, SGPR_1024Regs>;955}956 957def VRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,958 (add VGPR_32, LDS_DIRECT)> {959 let isAllocatable = 0;960 let HasVGPR = 1;961 let Size = 32;962}963 964// Register class for all vector registers (VGPRs + Interpolation Registers)965class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> :966 SIRegisterClass<"AMDGPU", regTypes, 32, regList> {967 let Size = !mul(numRegs, 32);968 969 // Requires n v_mov_b32 to copy970 let CopyCost = numRegs;971 972 // Since we only have 5 bits for the RegisterClass Allocation Priorty, and since we use the973 // 5th bit for BaseClassPriority, we need to encode the SizePriority into 4 bits. As a result974 // of this encoding, for registers with numRegs 15 or 16, we give SizePriority of 14, and for975 // regsters with numRegs 17+ we give SizePriority of 15. In practice, there is only one976 // RegClass per Vector Register type in each of these groups (i.e. numRegs = 15,16 : {VReg_512},977 // and numRegs = 17+ : {VReg_1024}). Therefore, we have not lost any info by compressing.978 defvar SizePrioriity = !if(!le(numRegs, 14), !sub(numRegs, 1), !if(!le(numRegs, 16), 14, 15));979 980 let AllocationPriority = !add(SizePrioriity, !mul(BaseClassPriority, BaseClassScaleFactor));981 let Weight = numRegs;982}983 984// Define a register tuple class, along with one requiring an even985// aligned base register.986multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> {987 let HasVGPR = 1, BaseClassPriority = 1,988 DecoderMethod = "DecodeVReg_"#!mul(numRegs, 32)#"RegisterClass" in {989 // Define the regular class.990 def "" : VRegClassBase<numRegs, regTypes, regList> {991 let BaseClassOrder = !mul(numRegs, 32);992 }993 994 // Define 2-aligned variant995 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)> {996 // Give aligned class higher priority in base class resolution997 let BaseClassOrder = !sub(!mul(numRegs, 32), 1);998 let RegTupleAlignUnits = 2;999 }1000 1001 // Aligned register tuples starting with low 256 vgprs1002 def _Lo256_Align2 : VRegClassBase<numRegs, regTypes,1003 (trunc (decimate regList, 2), !div(!sub(258, numRegs), 2))> {1004 let RegTupleAlignUnits = 2;1005 }1006 }1007}1008 1009defm VReg_64 : VRegClass<2, Reg64Types.types, (add VGPR_64)>;1010defm VReg_96 : VRegClass<3, Reg96Types.types, (add VGPR_96)>;1011defm VReg_128 : VRegClass<4, Reg128Types.types, (add VGPR_128)>;1012defm VReg_160 : VRegClass<5, Reg160Types.types, (add VGPR_160)>;1013 1014defm VReg_192 : VRegClass<6, Reg192Types.types, (add VGPR_192)>;1015defm VReg_224 : VRegClass<7, Reg224Types.types, (add VGPR_224)>;1016defm VReg_256 : VRegClass<8, Reg256Types.types, (add VGPR_256)>;1017defm VReg_288 : VRegClass<9, Reg288Types.types, (add VGPR_288)>;1018defm VReg_320 : VRegClass<10, Reg320Types.types, (add VGPR_320)>;1019defm VReg_352 : VRegClass<11, Reg352Types.types, (add VGPR_352)>;1020defm VReg_384 : VRegClass<12, Reg384Types.types, (add VGPR_384)>;1021 1022let GlobalPriority = true in {1023defm VReg_512 : VRegClass<16, Reg512Types.types, (add VGPR_512)>;1024defm VReg_1024 : VRegClass<32, Reg1024Types.types, (add VGPR_1024)>;1025}1026 1027multiclass ARegClass<int numRegs, list<ValueType> regTypes, dag regList> {1028 let CopyCost = !add(numRegs, numRegs, 1), HasAGPR = 1, BaseClassPriority = 1,1029 DecoderMethod = "DecodeAReg_"#!mul(numRegs, 32)#"RegisterClass" in {1030 // Define the regular class.1031 def "" : VRegClassBase<numRegs, regTypes, regList> {1032 let BaseClassOrder = !mul(numRegs, 32);1033 }1034 1035 // Define 2-aligned variant1036 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)> {1037 // Give aligned class higher priority in base class resolution1038 let BaseClassOrder = !sub(!mul(numRegs, 32), 1);1039 let RegTupleAlignUnits = 2;1040 }1041 }1042}1043 1044defm AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16],1045 (add AGPR_64)>;1046defm AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>;1047defm AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16], (add AGPR_128)>;1048defm AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>;1049defm AReg_192 : ARegClass<6, [v6i32, v6f32, v3i64, v3f64], (add AGPR_192)>;1050defm AReg_224 : ARegClass<7, [v7i32, v7f32], (add AGPR_224)>;1051defm AReg_256 : ARegClass<8, [v8i32, v8f32, v4i64, v4f64], (add AGPR_256)>;1052defm AReg_288 : ARegClass<9, [v9i32, v9f32], (add AGPR_288)>;1053defm AReg_320 : ARegClass<10, [v10i32, v10f32], (add AGPR_320)>;1054defm AReg_352 : ARegClass<11, [v11i32, v11f32], (add AGPR_352)>;1055defm AReg_384 : ARegClass<12, [v12i32, v12f32], (add AGPR_384)>;1056 1057let GlobalPriority = true in {1058defm AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>;1059defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>;1060}1061 1062} // End GeneratePressureSet = 01063 1064let GeneratePressureSet = 0 in {1065// No register should ever be allocated using VReg_1. This is a hack for1066// SelectionDAG that should always be lowered by SILowerI1Copies. TableGen1067// sorts register classes based on the number of registers in them so this is1068// sorted to the end and not preferred over VGPR_32.1069def VReg_1 : SIRegisterClass<"AMDGPU", [i1], 32, (add)> {1070 let Size = 1;1071 let HasVGPR = 1;1072}1073 1074def VS_16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,1075 (add VGPR_16, SReg_32, LDS_DIRECT)> {1076 let isAllocatable = 0;1077 let HasVGPR = 1;1078 let Size = 16;1079}1080 1081def VS_16_Lo128 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16,1082 (add VGPR_16_Lo128, SReg_32, LDS_DIRECT)> {1083 let isAllocatable = 0;1084 let HasVGPR = 1;1085 let Size = 16;1086}1087 1088def VS_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,1089 (add VGPR_32, SReg_32, LDS_DIRECT)> {1090 let isAllocatable = 0;1091 let HasVGPR = 1;1092 let HasSGPR = 1;1093 let Size = 32;1094}1095 1096def VS_32_Lo128 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,1097 (add VGPR_32_Lo128, SReg_32, LDS_DIRECT)> {1098 let isAllocatable = 0;1099 let HasVGPR = 1;1100 let HasSGPR = 1;1101 let Size = 32;1102}1103 1104def VS_32_Lo256 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,1105 (add VGPR_32_Lo256, SReg_32, LDS_DIRECT)> {1106 let isAllocatable = 0;1107 let HasVGPR = 1;1108 let HasSGPR = 1;1109 let Size = 32;1110}1111 1112def VS_64 : SIRegisterClass<"AMDGPU", VReg_64.RegTypes, 32,1113 (add VReg_64, SReg_64_Encodable)> {1114 let isAllocatable = 0;1115 let HasVGPR = 1;1116 let HasSGPR = 1;1117 let Size = 64;1118}1119 1120def VS_64_Align2 : SIRegisterClass<"AMDGPU", VReg_64.RegTypes, 32,1121 (add VReg_64_Align2, SReg_64_Encodable)> {1122 let isAllocatable = 0;1123 let HasVGPR = 1;1124 let HasSGPR = 1;1125 let Size = 64;1126}1127 1128def AV_32 : SIRegisterClass<"AMDGPU", VGPR_32.RegTypes, 32, (add VGPR_32, AGPR_32)> {1129 let HasVGPR = 1;1130 let HasAGPR = 1;1131 let BaseClassPriority = 0;1132 let Size = 32;1133}1134 1135def VS_64_Lo256 : SIRegisterClass<"AMDGPU", VReg_64.RegTypes, 32,1136 (add VReg_64_Lo256_Align2, SReg_64_Encodable)> {1137 let isAllocatable = 0;1138 let HasVGPR = 1;1139 let HasSGPR = 1;1140 let Size = 64;1141}1142 1143def VS_128 : SIRegisterClass<"AMDGPU", VReg_128.RegTypes, 32,1144 (add VReg_128, SReg_128)> {1145 let isAllocatable = 0;1146 let HasVGPR = 1;1147 let HasSGPR = 1;1148 let Size = 128;1149}1150 1151def VS_128_Align2 : SIRegisterClass<"AMDGPU", VReg_128.RegTypes, 32,1152 (add VReg_128_Align2, SReg_128)> {1153 let isAllocatable = 0;1154 let HasVGPR = 1;1155 let HasSGPR = 1;1156 let Size = 128;1157}1158} // End GeneratePressureSet = 01159 1160// Define a register tuple class, along with one requiring an even1161// aligned base register.1162multiclass AVRegClass<int numRegs, list<ValueType> regTypes,1163 dag vregList, dag aregList> {1164 let HasVGPR = 1, HasAGPR = 1, BaseClassPriority = 0 in {1165 // Define the regular class.1166 def "" : VRegClassBase<numRegs, regTypes, (add vregList, aregList)>;1167 1168 // Define 2-aligned variant1169 def _Align2 : VRegClassBase<numRegs, regTypes,1170 (add (decimate vregList, 2),1171 (decimate aregList, 2))> {1172 let RegTupleAlignUnits = 2;1173 }1174 }1175}1176 1177defm AV_64 : AVRegClass<2, VReg_64.RegTypes, (add VGPR_64), (add AGPR_64)>;1178defm AV_96 : AVRegClass<3, VReg_96.RegTypes, (add VGPR_96), (add AGPR_96)>;1179defm AV_128 : AVRegClass<4, VReg_128.RegTypes, (add VGPR_128), (add AGPR_128)>;1180defm AV_160 : AVRegClass<5, VReg_160.RegTypes, (add VGPR_160), (add AGPR_160)>;1181defm AV_192 : AVRegClass<6, VReg_192.RegTypes, (add VGPR_192), (add AGPR_192)>;1182defm AV_224 : AVRegClass<7, VReg_224.RegTypes, (add VGPR_224), (add AGPR_224)>;1183defm AV_256 : AVRegClass<8, VReg_256.RegTypes, (add VGPR_256), (add AGPR_256)>;1184defm AV_288 : AVRegClass<9, VReg_288.RegTypes, (add VGPR_288), (add AGPR_288)>;1185defm AV_320 : AVRegClass<10, VReg_320.RegTypes, (add VGPR_320), (add AGPR_320)>;1186defm AV_352 : AVRegClass<11, VReg_352.RegTypes, (add VGPR_352), (add AGPR_352)>;1187defm AV_384 : AVRegClass<12, VReg_384.RegTypes, (add VGPR_384), (add AGPR_384)>;1188 1189let GlobalPriority = true in {1190defm AV_512 : AVRegClass<16, VReg_512.RegTypes, (add VGPR_512), (add AGPR_512)>;1191defm AV_1024 : AVRegClass<32, VReg_1024.RegTypes, (add VGPR_1024), (add AGPR_1024)>;1192}1193 1194def SReg_1_XEXEC : SIRegisterClassLike<0, false, false, true>,1195 RegClassByHwMode<1196 [DefaultMode_Wave64,1197 AlignedVGPRNoAGPRMode_Wave64,1198 AVAlign2LoadStoreMode,1199 DefaultMode_Wave32,1200 AlignedVGPRNoAGPRMode_Wave32],1201 [SReg_64_XEXEC,1202 SReg_64_XEXEC,1203 SReg_64_XEXEC,1204 SReg_32_XM0_XEXEC, // FIXME: Why do the wave32 cases exclude m0?1205 SReg_32_XM0_XEXEC]1206>;1207 1208def SReg_1 : SIRegisterClassLike<0, false, false, true>,1209 RegClassByHwMode<1210 [DefaultMode_Wave64,1211 AlignedVGPRNoAGPRMode_Wave64,1212 AVAlign2LoadStoreMode,1213 DefaultMode_Wave32,1214 AlignedVGPRNoAGPRMode_Wave32],1215 [SReg_64,1216 SReg_64,1217 SReg_64,1218 SReg_32,1219 SReg_32]1220>;1221 1222//===----------------------------------------------------------------------===//1223//1224// AlignTarget classes. Artifical classes to swap between1225// even-aligned and any-aligned classes depending on subtarget.1226//1227//===----------------------------------------------------------------------===//1228 1229// We have 3 orthogonal properties to consider. Unfortunately we need1230// to define the cross product of these states, minus unused1231// combinations.1232 1233def AV_LdSt_32_Target : RegClassByHwMode<1234 [DefaultMode_Wave64,1235 DefaultMode_Wave32,1236 AVAlign2LoadStoreMode,1237 AlignedVGPRNoAGPRMode_Wave64,1238 AlignedVGPRNoAGPRMode_Wave32],1239 [VGPR_32,1240 VGPR_32,1241 AV_32,1242 VGPR_32,1243 VGPR_32]>,1244 SIRegisterClassLike<32, true, true> {1245 let DecoderMethod = "decodeAVLdSt";1246}1247 1248foreach RegSize = [ 64, 96, 128, 160, 192, 224, 256, 288, 320, 352, 384, 512, 1024 ] in {1249 def VReg_#RegSize#_AlignTarget : SIRegisterClassLike<RegSize, true>,1250 RegClassByHwMode<1251 [DefaultMode_Wave64,1252 DefaultMode_Wave32,1253 AVAlign2LoadStoreMode,1254 AlignedVGPRNoAGPRMode_Wave64,1255 AlignedVGPRNoAGPRMode_Wave32],1256 [!cast<RegisterClass>("VReg_"#RegSize),1257 !cast<RegisterClass>("VReg_"#RegSize),1258 !cast<RegisterClass>("VReg_"#RegSize#_Align2),1259 !cast<RegisterClass>("VReg_"#RegSize#_Align2),1260 !cast<RegisterClass>("VReg_"#RegSize#_Align2)]> {1261 let DecoderMethod = "DecodeVReg_"#RegSize#"RegisterClass";1262 }1263 1264 def AReg_#RegSize#_AlignTarget : SIRegisterClassLike<RegSize, false, true>,1265 RegClassByHwMode<1266 [DefaultMode_Wave64, /*unused combination*/ AVAlign2LoadStoreMode, /*Unused combination*/ /*Unused combination*/],1267 [!cast<RegisterClass>("AReg_"#RegSize),1268 /*unused combination*/1269 !cast<RegisterClass>("AReg_"#RegSize#_Align2)1270 /*Unused combination*/1271 /*Unused combination*/]> {1272 let DecoderMethod = "DecodeAReg_"#RegSize#"RegisterClass";1273 }1274 1275 def AV_#RegSize#_AlignTarget : SIRegisterClassLike<RegSize, true, true>,1276 RegClassByHwMode<1277 [DefaultMode_Wave32,1278 DefaultMode_Wave64,1279 AVAlign2LoadStoreMode,1280 AlignedVGPRNoAGPRMode_Wave64,1281 AlignedVGPRNoAGPRMode_Wave32],1282 [!cast<RegisterClass>("AV_"#RegSize),1283 !cast<RegisterClass>("AV_"#RegSize),1284 !cast<RegisterClass>("AV_"#RegSize#_Align2),1285 !cast<RegisterClass>("VReg_"#RegSize#_Align2),1286 !cast<RegisterClass>("VReg_"#RegSize#_Align2)]> {1287 let DecoderMethod = "DecodeAV_"#RegSize#"RegisterClass";1288 }1289 1290 def AV_LdSt_#RegSize#_AlignTarget : SIRegisterClassLike<RegSize, true, true>,1291 RegClassByHwMode<1292 [DefaultMode_Wave64, DefaultMode_Wave32, AVAlign2LoadStoreMode, AlignedVGPRNoAGPRMode_Wave64, AlignedVGPRNoAGPRMode_Wave32],1293 [!cast<RegisterClass>("VReg_"#RegSize),1294 !cast<RegisterClass>("VReg_"#RegSize),1295 !cast<RegisterClass>("AV_"#RegSize#_Align2),1296 !cast<RegisterClass>("VReg_"#RegSize#_Align2),1297 !cast<RegisterClass>("VReg_"#RegSize#_Align2)]> {1298 let DecoderMethod = "decodeAVLdSt";1299 }1300 1301 def AV_LdSt_#RegSize#_Align2 : SIRegisterClassLike<RegSize, true, true>,1302 RegClassByHwMode<1303 [DefaultMode_Wave64, DefaultMode_Wave32, AVAlign2LoadStoreMode, AlignedVGPRNoAGPRMode_Wave64, AlignedVGPRNoAGPRMode_Wave32],1304 [!cast<RegisterClass>("VReg_"#RegSize#_Align2),1305 !cast<RegisterClass>("VReg_"#RegSize#_Align2),1306 !cast<RegisterClass>("AV_"#RegSize#_Align2),1307 !cast<RegisterClass>("VReg_"#RegSize#_Align2),1308 !cast<RegisterClass>("VReg_"#RegSize#_Align2)]> {1309 let DecoderMethod = "decodeAVLdSt";1310 }1311 1312 def AV_LdSt_#RegSize#_Align1 : SIRegisterClassLike<RegSize, true, true>,1313 RegClassByHwMode<1314 [DefaultMode_Wave64, DefaultMode_Wave32, AVAlign2LoadStoreMode, AlignedVGPRNoAGPRMode_Wave64, AlignedVGPRNoAGPRMode_Wave32],1315 [!cast<RegisterClass>("VReg_"#RegSize),1316 !cast<RegisterClass>("VReg_"#RegSize),1317 !cast<RegisterClass>("AV_"#RegSize),1318 !cast<RegisterClass>("VReg_"#RegSize),1319 !cast<RegisterClass>("VReg_"#RegSize)]> {1320 let DecoderMethod = "decodeAVLdSt";1321 }1322}1323 1324def VS_64_AlignTarget : SIRegisterClassLike<64, true, false, true>,1325 RegClassByHwMode<1326 [DefaultMode_Wave64, DefaultMode_Wave32, AVAlign2LoadStoreMode, AlignedVGPRNoAGPRMode_Wave64, AlignedVGPRNoAGPRMode_Wave32],1327 [VS_64, VS_64, VS_64_Align2, VS_64_Align2, VS_64_Align2]> {1328 let DecoderMethod = "decodeSrcRegOrImm9";1329}1330 1331 1332// Special case for DS_GWS instructions. The register input is really1333// 32-bit, but it needs to be even aligned on targets with a VGPR1334// alignment requirement.1335def AV_LdSt_32_Align2 : SIRegisterClassLike</*Bitwidth=*/32, /*VGPR=*/true, /*AGPR=*/true>,1336 RegClassByHwMode<1337 [DefaultMode_Wave64, DefaultMode_Wave32, AVAlign2LoadStoreMode, AlignedVGPRNoAGPRMode_Wave64, AlignedVGPRNoAGPRMode_Wave32],1338 [VGPR_32, VGPR_32, AV_64_Align2, VReg_64_Align2, VReg_64_Align2]> {1339 let DecoderMethod = "decodeAVLdSt<32>";1340}1341 1342class RegImmMatcher<string name> : AsmOperandClass {1343 let Name = name;1344 let RenderMethod = "addRegOrImmOperands";1345}1346 1347class RegOrImmOperand <RegisterClassLike RegClass, string OperandTypeName>1348 : RegisterOperand<RegClass> {1349 let OperandNamespace = "AMDGPU";1350 let OperandType = OperandTypeName;1351 let ParserMatchClass = RegImmMatcher<NAME>;1352}1353 1354//===----------------------------------------------------------------------===//1355// Register operands1356//===----------------------------------------------------------------------===//1357 1358//===----------------------------------------------------------------------===//1359// SSrc_* Operands with an SGPR, a 32-bit immediate, or 64-bit immediate1360// if supported by target.1361//===----------------------------------------------------------------------===//1362 1363class SrcRegOrImm9<RegisterClassLike regClass, string operandType>1364 : RegOrImmOperand<regClass, operandType> {1365 string DecoderMethodName = "decodeSrcRegOrImm9";1366 let DecoderMethod = DecoderMethodName # "<" # !cast<SIRegisterClassLike>(regClass).Size # ">";1367}1368 1369class SrcRegOrImm9_t16<string operandType, RegisterClass regClass = VS_16>1370 : SrcRegOrImm9<regClass, operandType> {1371 let DecoderMethodName = "decodeOperand_VSrcT16";1372 let EncoderMethod = "getMachineOpValueT16";1373}1374 1375def SSrc_b16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_INT16">;1376def SSrc_bf16: SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_BF16">;1377def SSrc_f16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_FP16">;1378def SSrc_b32 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_INT32">;1379def SSrc_f32 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_FP32">;1380def SSrc_b64 : SrcRegOrImm9 <SReg_64_Encodable, "OPERAND_REG_IMM_INT64">;1381 1382def SSrcOrLds_b32 : SrcRegOrImm9 <SRegOrLds_32, "OPERAND_REG_IMM_INT32">;1383 1384//===----------------------------------------------------------------------===//1385// SCSrc_* Operands with an SGPR or a inline constant1386//===----------------------------------------------------------------------===//1387 1388def SCSrc_b32 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_INLINE_C_INT32">;1389def SCSrc_b64 : SrcRegOrImm9 <SReg_64, "OPERAND_REG_INLINE_C_INT64">;1390 1391//===----------------------------------------------------------------------===//1392// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate1393//===----------------------------------------------------------------------===//1394 1395// The current and temporary future default used case for VOP3.1396def VSrc_b16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_INT16">;1397def VSrc_bf16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_BF16">;1398def VSrc_f16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_FP16">;1399 1400// True16 VOP3 operands.1401def VSrcT_b16 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_INT16">;1402def VSrcT_bf16 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_BF16">;1403def VSrcT_f16 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_FP16">;1404 1405// True16 VOP1/2/C operands.1406let DecoderMethodName = "decodeOperand_VSrcT16_Lo128", EncoderMethod = "getMachineOpValueT16Lo128" in {1407 def VSrcT_b16_Lo128 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_INT16", VS_16_Lo128>;1408 def VSrcT_bf16_Lo128 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_BF16", VS_16_Lo128>;1409 def VSrcT_f16_Lo128 : SrcRegOrImm9_t16 <"OPERAND_REG_IMM_FP16", VS_16_Lo128>;1410} // End DecoderMethodName = "decodeOperand_VSrcT16_Lo128", EncoderMethod = "getMachineOpValueT16Lo128"1411 1412// The current and temporary future default used case for fake VOP1/2/C.1413// For VOP1,2,C True16 instructions. _Lo128 use first 128 32-bit VGPRs only.1414def VSrcFake16_b16_Lo128 : SrcRegOrImm9 <VS_32_Lo128, "OPERAND_REG_IMM_INT16">;1415def VSrcFake16_bf16_Lo128 : SrcRegOrImm9 <VS_32_Lo128, "OPERAND_REG_IMM_BF16">;1416def VSrcFake16_f16_Lo128 : SrcRegOrImm9 <VS_32_Lo128, "OPERAND_REG_IMM_FP16">;1417 1418def VSrc_b32 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_INT32">;1419def VSrc_f32 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_FP32">;1420def VSrc_v2b16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_V2INT16">;1421def VSrc_v2bf16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_V2BF16">;1422def VSrc_v2f16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_V2FP16">;1423def VSrc_b64 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_INT64">;1424def VSrc_f64 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_FP64"> {1425 let DecoderMethod = "decodeOperand_VSrc_f64";1426}1427def VSrc_v2b32 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_V2INT32">;1428def VSrc_v2f32 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_IMM_V2FP32">;1429 1430def VSrc_NoInline_v2f16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_IMM_NOINLINE_V2FP16">;1431 1432//===----------------------------------------------------------------------===//1433// VRegSrc_* Operands with a VGPR1434//===----------------------------------------------------------------------===//1435 1436// This is for operands with the enum(9), VSrc encoding restriction,1437// but only allows VGPRs.1438class SrcReg9<RegisterClassLike regClass> : RegisterOperand<regClass> {1439 let DecoderMethod = "decodeSrcReg9<" # !cast<SIRegisterClassLike>(regClass).Size # ">";1440}1441 1442def VRegSrc_32 : SrcReg9<VGPR_32>;1443def VRegSrc_64 : SrcReg9<VReg_64_AlignTarget>;1444def VRegSrc_96 : SrcReg9<VReg_96_AlignTarget>;1445def VRegSrc_128 : SrcReg9<VReg_128_AlignTarget>;1446def VRegSrc_192 : SrcReg9<VReg_192_AlignTarget>;1447def VRegSrc_256 : SrcReg9<VReg_256_AlignTarget>;1448def VRegSrc_384 : SrcReg9<VReg_384_AlignTarget>;1449def VRegSrc_512 : SrcReg9<VReg_512_AlignTarget>;1450def VRegSrc_1024 : SrcReg9<VReg_1024_AlignTarget>;1451def VRegOrLdsSrc_32 : SrcReg9<VRegOrLds_32>;1452 1453// True 16 Operands1454def VRegSrc_16 : RegisterOperand<VGPR_16> {1455 let DecoderMethod = "decodeOperand_VGPR_16";1456 let EncoderMethod = "getMachineOpValueT16";1457}1458def VRegSrc_fake16: SrcReg9<VGPR_32> {1459 let EncoderMethod = "getMachineOpValueT16";1460}1461//===----------------------------------------------------------------------===//1462// VGPROp_* An 8-bit RegisterOperand wrapper for a VGPR1463//===----------------------------------------------------------------------===//1464 1465class VGPROp<RegisterClass regClass> : RegisterOperand<regClass> {1466 let DecoderMethod = "Decode" # regClass # "RegisterClass";1467}1468class VGPROp_Align2<RegisterClass regClass> : RegisterOperand<!cast<RegisterClass>(regClass#_Align2)> {1469 let DecoderMethod = "Decode" # regClass # "RegisterClass";1470}1471 1472// TODO: These cases should use default target alignment1473def VGPROp_16 : VGPROp<VGPR_16> {1474 let EncoderMethod = "getMachineOpValueT16";1475}1476 1477def VGPROp_32 : VGPROp<VGPR_32>;1478 1479foreach size = ["64", "96", "128", "160", "192", "224", "256", "288", "320", "352", "384", "512", "1024"] in {1480 // Target default alignment1481 def VGPROp_#size : RegisterOperand<!cast<RegisterClassLike>("VReg_"#size#_AlignTarget)>;1482 1483 // No alignment requirement1484 def VGPROp_#size#_Align1 : RegisterOperand<!cast<RegisterClassLike>("VReg_"#size)>;1485 1486 // Always even alignment requirement1487 def VGPROp_#size#_Align2 : RegisterOperand<!cast<RegisterClassLike>("VReg_"#size#_Align2)>;1488}1489 1490def VGPROp_16_Lo128 : RegisterOperand<VGPR_16_Lo128> {1491 let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass";1492 let EncoderMethod = "getMachineOpValueT16Lo128";1493}1494 1495def VGPROp_32_Lo128 : RegisterOperand<VGPR_32_Lo128> {1496 let DecoderMethod = "DecodeVGPR_32RegisterClass";1497}1498 1499//===----------------------------------------------------------------------===//1500// ASrc_* Operands with an AccVGPR1501//===----------------------------------------------------------------------===//1502 1503class AVOperand<RegisterClassLike regClass, string decoder>1504 : RegisterOperand<regClass> {1505 let DecoderMethod = decoder # "<" # !cast<SIRegisterClassLike>(regClass).Size # ">";1506 let EncoderMethod = "getAVOperandEncoding";1507}1508 1509def ARegSrc_32 : AVOperand<AGPR_32, "decodeSrcA9">;1510 1511//===----------------------------------------------------------------------===//1512// VCSrc_* Operands with an SGPR, VGPR or an inline constant1513//===----------------------------------------------------------------------===//1514 1515def VCSrc_b16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_INT16">;1516def VCSrc_bf16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_BF16">;1517def VCSrc_f16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_FP16">;1518def VCSrc_b32 : SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_INT32">;1519def VCSrc_f32 : SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_FP32">;1520def VCSrc_b64 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_INLINE_C_INT64">;1521def VCSrc_f64 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_INLINE_C_FP64">;1522def VCSrc_v2b16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_V2INT16">;1523def VCSrc_v2bf16: SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_V2BF16">;1524def VCSrc_v2f16 : SrcRegOrImm9 <VS_32, "OPERAND_REG_INLINE_C_V2FP16">;1525def VCSrc_b32_Lo256 : SrcRegOrImm9 <VS_32_Lo256, "OPERAND_REG_INLINE_C_INT32">;1526def VCSrc_v2b32 : SrcRegOrImm9 <VS_64_AlignTarget, "OPERAND_REG_INLINE_C_V2INT32">;1527def VCSrc_b64_Lo256 : SrcRegOrImm9 <VS_64_Lo256, "OPERAND_REG_INLINE_C_INT64">;1528 1529// True 16 Operands1530def VCSrcT_b16 : SrcRegOrImm9_t16 <"OPERAND_REG_INLINE_C_INT16">;1531def VCSrcT_bf16 : SrcRegOrImm9_t16 <"OPERAND_REG_INLINE_C_BF16">;1532def VCSrcT_f16 : SrcRegOrImm9_t16 <"OPERAND_REG_INLINE_C_FP16">;1533//===----------------------------------------------------------------------===//1534// VISrc_* Operands with a VGPR or an inline constant1535//===----------------------------------------------------------------------===//1536 1537def VISrc_64_bf16 : SrcRegOrImm9 <VReg_64_AlignTarget, "OPERAND_REG_INLINE_C_BF16">;1538def VISrc_64_f16 : SrcRegOrImm9 <VReg_64_AlignTarget, "OPERAND_REG_INLINE_C_FP16">;1539def VISrc_64_b32 : SrcRegOrImm9 <VReg_64_AlignTarget, "OPERAND_REG_INLINE_C_INT32">;1540def VISrc_64_f64 : SrcRegOrImm9 <VReg_64_AlignTarget, "OPERAND_REG_INLINE_C_FP64">;1541def VISrc_128_bf16 : SrcRegOrImm9 <VReg_128_AlignTarget, "OPERAND_REG_INLINE_C_BF16">;1542def VISrc_128_f16 : SrcRegOrImm9 <VReg_128_AlignTarget, "OPERAND_REG_INLINE_C_FP16">;1543def VISrc_128_b32 : SrcRegOrImm9 <VReg_128_AlignTarget, "OPERAND_REG_INLINE_C_INT32">;1544def VISrc_128_f32 : SrcRegOrImm9 <VReg_128_AlignTarget, "OPERAND_REG_INLINE_C_FP32">;1545def VISrc_256_b32 : SrcRegOrImm9 <VReg_256_AlignTarget, "OPERAND_REG_INLINE_C_INT32">;1546def VISrc_256_f32 : SrcRegOrImm9 <VReg_256_AlignTarget, "OPERAND_REG_INLINE_C_FP32">;1547def VISrc_256_f64 : SrcRegOrImm9 <VReg_256_AlignTarget, "OPERAND_REG_INLINE_C_FP64">;1548def VISrc_512_b32 : SrcRegOrImm9 <VReg_512_AlignTarget, "OPERAND_REG_INLINE_C_INT32">;1549def VISrc_512_f32 : SrcRegOrImm9 <VReg_512_AlignTarget, "OPERAND_REG_INLINE_C_FP32">;1550def VISrc_512_f64 : SrcRegOrImm9 <VReg_512_AlignTarget, "OPERAND_REG_INLINE_C_FP64">;1551def VISrc_1024_b32 : SrcRegOrImm9 <VReg_1024_AlignTarget, "OPERAND_REG_INLINE_C_INT32">;1552def VISrc_1024_f32 : SrcRegOrImm9 <VReg_1024_AlignTarget, "OPERAND_REG_INLINE_C_FP32">;1553 1554//===----------------------------------------------------------------------===//1555// AVSrc_*, AVDst_*, AVLdSt_* Operands with an AGPR or VGPR1556//===----------------------------------------------------------------------===//1557 1558class AVSrcOperand<RegisterClassLike regClass>1559 : AVOperand<regClass, "decodeSrcAV10">;1560 1561def AVSrc_32 : AVSrcOperand<AV_32>;1562def AVSrc_64 : AVSrcOperand<AV_64_AlignTarget>;1563def AVSrc_128 : AVSrcOperand<AV_128_AlignTarget>;1564def AVSrc_192 : AVSrcOperand<AV_192_AlignTarget>;1565def AVSrc_256 : AVSrcOperand<AV_256_AlignTarget>;1566 1567def AVSrc_64_Align2 : AVSrcOperand<AV_64_Align2>;1568def AVSrc_128_Align2 : AVSrcOperand<AV_128_Align2>;1569def AVSrc_192_Align2 : AVSrcOperand<AV_192_Align2>;1570def AVSrc_256_Align2 : AVSrcOperand<AV_256_Align2>;1571 1572class AVDstOperand<RegisterClassLike regClass>1573 : AVOperand<regClass, "decodeAV10">;1574 1575def AVDst_128 : AVDstOperand<AV_128>;1576def AVDst_256 : AVDstOperand<AV_256>;1577def AVDst_512 : AVDstOperand<AV_512>;1578 1579def AVDst_128_Align2 : AVDstOperand<AV_128_Align2>;1580def AVDst_256_Align2 : AVDstOperand<AV_256_Align2>;1581def AVDst_512_Align2 : AVDstOperand<AV_512_Align2>;1582 1583class AVLdStOperand<RegisterClassLike regClass>1584 : AVOperand<regClass, "decodeAVLdSt">;1585 1586def AVLdSt_32 : AVLdStOperand<AV_LdSt_32_Target>;1587 1588foreach size = ["64", "96", "128", "160", "256", "1024" ] in {1589 def AVLdSt_#size : AVLdStOperand<!cast<RegisterClassLike>("AV_LdSt_"#size#_AlignTarget)>;1590 def AVLdSt_#size#_Align1 : AVLdStOperand<!cast<RegisterClassLike>("AV_LdSt_"#size#_Align1)>;1591 def AVLdSt_#size#_Align2 : AVLdStOperand<!cast<RegisterClassLike>("AV_LdSt_"#size#_Align2)>;1592}1593 1594def AV_LdSt_32_Align2_RegMatcher : AsmOperandClass {1595 let Name = "AV_LdSt_32_Align2_RegOp";1596 let RenderMethod = "addRegOperands";1597}1598 1599def AV_LdSt_32_Align2_RegOp : RegisterOperand<AV_LdSt_32_Align2> {1600 let ParserMatchClass = AV_LdSt_32_Align2_RegMatcher;1601 let PrintMethod = "printAVLdSt32Align2RegOp";1602 let EncoderMethod = "getAVOperandEncoding";1603}1604 1605//===----------------------------------------------------------------------===//1606// ACSrc_* Operands with an AGPR or an inline constant1607//===----------------------------------------------------------------------===//1608 1609class SrcRegOrImmA9<RegisterClassLike regClass, string operandType>1610 : RegOrImmOperand<regClass, operandType> {1611 let DecoderMethod = "decodeSrcRegOrImmA9<" # !cast<SIRegisterClassLike>(regClass).Size # ">";1612}1613 1614def AISrc_64_f64 : SrcRegOrImmA9 <AReg_64_AlignTarget, "OPERAND_REG_INLINE_AC_FP64">;1615def AISrc_128_f32 : SrcRegOrImmA9 <AReg_128_AlignTarget, "OPERAND_REG_INLINE_AC_FP32">;1616def AISrc_128_b32 : SrcRegOrImmA9 <AReg_128_AlignTarget, "OPERAND_REG_INLINE_AC_INT32">;1617def AISrc_256_f64 : SrcRegOrImmA9 <AReg_256_AlignTarget, "OPERAND_REG_INLINE_AC_FP64">;1618def AISrc_512_f32 : SrcRegOrImmA9 <AReg_512_AlignTarget, "OPERAND_REG_INLINE_AC_FP32">;1619def AISrc_512_b32 : SrcRegOrImmA9 <AReg_512_AlignTarget, "OPERAND_REG_INLINE_AC_INT32">;1620def AISrc_1024_f32 : SrcRegOrImmA9 <AReg_1024_AlignTarget, "OPERAND_REG_INLINE_AC_FP32">;1621def AISrc_1024_b32 : SrcRegOrImmA9 <AReg_1024_AlignTarget, "OPERAND_REG_INLINE_AC_INT32">;1622 1623//===----------------------------------------------------------------------===//1624// Tablegen programming utilities1625//===----------------------------------------------------------------------===//1626 1627/// Helper function to extract the register class from an1628/// instruction's operand list, which may be a RegisterOperand or a1629/// direct RegisterClass reference.1630class getRegClassFromOp<DAGOperand Op> {1631 SIRegisterClassLike ret = !if(1632 !isa<RegisterOperand>(Op),1633 !cast<SIRegisterClassLike>(!cast<RegisterOperand>(Op).RegClass),1634 !cast<SIRegisterClassLike>(Op));1635}1636 1637/// Check if the operand will use an AV_* class.1638class OperandIsAV<DAGOperand Op> {1639 defvar reg_class = getRegClassFromOp<Op>.ret;1640 bit ret = !and(reg_class.HasAGPR, reg_class.HasVGPR);1641}1642 1643/// Check if the operand will use an AGPR class.1644class OperandIsAGPR<DAGOperand Op> {1645 defvar reg_class = getRegClassFromOp<Op>.ret;1646 bit ret = !and(reg_class.HasAGPR, !not(reg_class.HasVGPR));1647}1648 1649/// Check if the operand will use a VGPR class.1650class OperandIsVGPR<DAGOperand Op> {1651 defvar reg_class = getRegClassFromOp<Op>.ret;1652 bit ret = !and(reg_class.HasVGPR, !not(reg_class.HasAGPR));1653}1654 1655class VDstOperandIsAV<dag OperandList> {1656 bit ret = OperandIsAV<!getdagarg<DAGOperand>(OperandList, "vdst")>.ret;1657}1658 1659class VDstOperandIsAGPR<dag OperandList> {1660 bit ret = OperandIsAGPR<!getdagarg<DAGOperand>(OperandList, "vdst")>.ret;1661}1662 1663class Data0OperandIsAV<dag OperandList> {1664 bit ret = OperandIsAV<!getdagarg<DAGOperand>(OperandList, "data0")>.ret;1665}1666 1667class Data0OperandIsAGPR<dag OperandList> {1668 bit ret = OperandIsAGPR<!getdagarg<DAGOperand>(OperandList, "data0")>.ret;1669}1670 1671class VDataOperandIsAV<dag OperandList> {1672 bit ret = OperandIsAV<!getdagarg<DAGOperand>(OperandList, "vdata")>.ret;1673}1674 1675class VDataOperandIsAGPR<dag OperandList> {1676 bit ret = OperandIsAGPR<!getdagarg<DAGOperand>(OperandList, "vdata")>.ret;1677}1678