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1//===-- SISchedule.td - SI Scheduling definitions -------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// MachineModel definitions for Southern Islands (SI)10//11//===----------------------------------------------------------------------===//12 13def : PredicateProlog<[{14 const SIInstrInfo *TII =15 static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());16 (void)TII;17}]>;18 19def WriteBranch : SchedWrite;20def WriteExport : SchedWrite;21def WriteLDS : SchedWrite;22def WriteSALU : SchedWrite;23def WriteSMEM : SchedWrite;24def WriteVMEM : SchedWrite;25def WriteBarrier : SchedWrite;26 27def MIVGPRRead : SchedRead;28def MIMFMARead : SchedRead;29 30// Normal 16 or 32 bit VALU instructions31def Write32Bit : SchedWrite;32// Conversion to or from F32 (but not converting F64 to or from F32)33def WriteFloatCvt : SchedWrite;34// F16 or F32 transcendental instructions (these are quarter rate)35def WriteTrans32 : SchedWrite;36// Other quarter rate VALU instructions37def WriteQuarterRate32 : SchedWrite;38 39def WriteFloatFMA : SchedWrite;40 41// Slow quarter rate f64 instruction.42def WriteDouble : SchedWrite;43 44// half rate f64 instruction (same as v_add_f64)45def WriteDoubleAdd : SchedWrite;46 47// Conversion to or from f64 instruction48def WriteDoubleCvt : SchedWrite;49 50// F64 "transcendental" (actually only reciprocal and/or square root)51// instructions52def WriteTrans64 : SchedWrite;53 54// Half rate 64-bit instructions.55def Write64Bit : SchedWrite;56 57// Integer multiplications.58def WriteIntMul : SchedWrite;59 60// mAI multipass instructions.61def Write2PassMAI : SchedWrite;62def Write4PassMAI : SchedWrite;63def Write8PassMAI : SchedWrite;64def Write16PassMAI : SchedWrite;65def Write4PassDGEMM : SchedWrite;66def Write8PassDGEMM : SchedWrite;67def Write16PassDGEMM : SchedWrite;68 69// WMMA/SWMMA instructions70def WriteXDL2PassWMMA : SchedWrite;71def WriteXDL4PassWMMA : SchedWrite;72def Write4PassWMMA : SchedWrite;73def Write8PassWMMA : SchedWrite;74def Write16PassWMMA : SchedWrite;75 76// Scalar float instructions77def WriteSFPU : SchedWrite;78 79// F16 or F32 pseudo scalar transcendental instructions80def WritePseudoScalarTrans : SchedWrite;81 82// FIXME: Should there be a class for instructions which are VALU83// instructions and have VALU rates, but write to the SALU (i.e. VOPC84// instructions)85 86class SISchedMachineModel : SchedMachineModel {87 let CompleteModel = 1;88 // MicroOpBufferSize = 1 means that instructions will always be added89 // the ready queue when they become available. This exposes them90 // to the register pressure analysis.91 let MicroOpBufferSize = 1;92 let IssueWidth = 1;93 let PostRAScheduler = 1;94 95 // FIXME:Approximate 2 * branch cost. Try to hack around bad96 // early-ifcvt heuristics. These need improvement to avoid the OOE97 // heuristics.98 int MispredictPenalty = 20;99}100 101def SIFullSpeedModel : SISchedMachineModel;102def SIQuarterSpeedModel : SISchedMachineModel;103def SIDPFullSpeedModel : SISchedMachineModel;104def SIDPGFX942FullSpeedModel : SISchedMachineModel;105def SIDPGFX950FullSpeedModel : SISchedMachineModel;106def GFX10SpeedModel : SISchedMachineModel;107def GFX11SpeedModel : SISchedMachineModel;108def GFX12SpeedModel : SISchedMachineModel;109def GFX1250SpeedModel : SISchedMachineModel;110 111// XXX: Are the resource counts correct?112def HWBranch : ProcResource<1> {113 let BufferSize = 1;114}115def HWExport : ProcResource<1> {116 let BufferSize = 1;117}118def HWLGKM : ProcResource<1> {119 let BufferSize = 1;120}121def HWSALU : ProcResource<1> {122 let BufferSize = 1;123}124def HWVMEM : ProcResource<1> {125 let BufferSize = 1;126}127def HWVALU : ProcResource<1> {128 let BufferSize = 1;129}130def HWTransVALU : ProcResource<1> { // Transcendental VALU131 let BufferSize = 1;132}133def HWRC : ProcResource<1> { // Register destination cache134 let BufferSize = 1;135}136def HWXDL : ProcResource<1> { // MFMA CU137 let BufferSize = 0;138}139 140class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,141 int latency> : WriteRes<write, resources> {142 let Latency = latency;143}144 145class HWVALUWriteRes<SchedWrite write, int latency> :146 HWWriteRes<write, [HWVALU], latency>;147 148class UnsupportedWriteRes<SchedWrite write> : WriteRes<write, []> {149 let Unsupported = 1;150}151 152def PredMIReadVGPR : SchedPredicate<[{TII->hasVGPRUses(*MI)}]>;153 154def MIReadVGPR : SchedReadVariant<[155 SchedVar<PredMIReadVGPR, [MIVGPRRead]>,156 SchedVar<NoSchedPred, [ReadDefault]>]>;157 158// The latency numbers are taken from AMD Accelerated Parallel Processing159// guide. They may not be accurate.160 161// The latency values are 1 / (operations / cycle) / 4.162multiclass SICommonWriteRes {163 164 let RetireOOO = 1 in { // llvm-mca specific flag165 def : HWWriteRes<WriteBranch, [HWBranch], 8>;166 def : HWWriteRes<WriteExport, [HWExport], 4>;167 def : HWWriteRes<WriteLDS, [HWLGKM], 5>; // Can be between 2 and 64168 def : HWWriteRes<WriteSALU, [HWSALU], 1>;169 def : HWWriteRes<WriteSMEM, [HWLGKM], 5>;170 def : HWWriteRes<WriteVMEM, [HWVMEM], 80>;171 def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???172 173 def : HWVALUWriteRes<Write32Bit, 1>;174 def : HWVALUWriteRes<WriteFloatCvt, 4>;175 def : HWVALUWriteRes<WriteTrans32, 4>;176 def : HWVALUWriteRes<WriteQuarterRate32, 4>;177 178 let ReleaseAtCycles = [4] in179 def : HWVALUWriteRes<Write4PassDGEMM, 4>;180 let ReleaseAtCycles = [8] in181 def : HWVALUWriteRes<Write8PassDGEMM, 8>;182 let ReleaseAtCycles = [16] in183 def : HWVALUWriteRes<Write16PassDGEMM, 16>;184 185 let ReleaseAtCycles = [2] in186 def : HWWriteRes<Write2PassMAI, [HWXDL], 2>;187 let ReleaseAtCycles = [4] in188 def : HWWriteRes<Write4PassMAI, [HWXDL], 4>;189 let ReleaseAtCycles = [8] in190 def : HWWriteRes<Write8PassMAI, [HWXDL], 8>;191 let ReleaseAtCycles = [16] in192 def : HWWriteRes<Write16PassMAI, [HWXDL], 16>;193 194 def : UnsupportedWriteRes<WriteSFPU>;195 def : UnsupportedWriteRes<WritePseudoScalarTrans>;196 } // End RetireOOO = 1197 198 def : ReadAdvance<MIVGPRRead, -2>;199 200 // Technically mfma reads can be from 0 to 4 cycles but that does not make201 // sense to model because its register setup is huge. In particular if we202 // properly model read advance as -2 for a vgpr read it will result in a203 // bad scheduling of acc writes before that mfma. To avoid it we would204 // need to consume 2 or 4 more vgprs to be initialized before the acc205 // write sequence. Just assume worst case here.206 def : ReadAdvance<MIMFMARead, -4>;207}208 209def PredIsVGPR32Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32}]>;210def PredIsVGPR64Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32}]>;211def WriteCopy : SchedWriteVariant<[212 SchedVar<PredIsVGPR32Copy, [Write32Bit]>,213 SchedVar<PredIsVGPR64Copy, [Write64Bit]>,214 SchedVar<NoSchedPred, [WriteSALU]>]>;215 216// Check if any matrix inputs are interpreted as f8 in an f8f6f4 mfma217// instruction.218def PredIsF8_MFMA_SCALE : SchedPredicate<[{219 TII->getNamedOperand(*MI, AMDGPU::OpName::cbsz)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 ||220 TII->getNamedOperand(*MI, AMDGPU::OpName::blgp)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2221}]>;222 223let SchedModel = SIFullSpeedModel in {224 225defm : SICommonWriteRes;226 227let RetireOOO = 1 in { // llvm-mca specific flag228def : HWVALUWriteRes<Write64Bit, 2>;229def : HWVALUWriteRes<WriteIntMul, 4>;230def : HWVALUWriteRes<WriteFloatFMA, 1>;231def : HWVALUWriteRes<WriteDouble, 4>;232def : HWVALUWriteRes<WriteDoubleAdd, 2>;233def : HWVALUWriteRes<WriteDoubleCvt, 4>;234def : HWVALUWriteRes<WriteTrans64, 4>;235} // End RetireOOO = 1236 237def : InstRW<[WriteCopy], (instrs COPY)>;238 239} // End SchedModel = SIFullSpeedModel240 241let SchedModel = SIQuarterSpeedModel in {242 243defm : SICommonWriteRes;244 245let RetireOOO = 1 in { // llvm-mca specific flag246def : HWVALUWriteRes<Write64Bit, 2>;247def : HWVALUWriteRes<WriteIntMul, 4>;248def : HWVALUWriteRes<WriteFloatFMA, 16>;249def : HWVALUWriteRes<WriteDouble, 16>;250def : HWVALUWriteRes<WriteDoubleAdd, 8>;251def : HWVALUWriteRes<WriteDoubleCvt, 4>;252def : HWVALUWriteRes<WriteTrans64, 16>;253} // End RetireOOO = 1254 255def : InstRW<[WriteCopy], (instrs COPY)>;256def : InstRW<[Write64Bit, MIReadVGPR], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;257def : InstRW<[Write2PassMAI, MIMFMARead], (instregex "^V_MFMA_..._4X4X")>;258def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_..._16X16X")>;259def : InstRW<[Write16PassMAI, MIMFMARead], (instregex "^V_MFMA_..._32X32X")>;260 261} // End SchedModel = SIQuarterSpeedModel262 263let SchedModel = SIDPFullSpeedModel in {264 265defm : SICommonWriteRes;266 267let RetireOOO = 1 in { // llvm-mca specific flag268def : HWVALUWriteRes<WriteFloatFMA, 1>;269def : HWVALUWriteRes<WriteDouble, 1>;270def : HWVALUWriteRes<WriteDoubleAdd, 1>;271def : HWVALUWriteRes<WriteDoubleCvt, 1>;272def : HWVALUWriteRes<WriteTrans64, 4>;273def : HWVALUWriteRes<WriteIntMul, 1>;274def : HWVALUWriteRes<Write64Bit, 1>;275} // End RetireOOO = 1276 277def : InstRW<[WriteCopy], (instrs COPY)>;278def : InstRW<[Write64Bit], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;279def : InstRW<[Write2PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_4X4X")>;280def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X")>;281def : InstRW<[Write16PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X")>;282def : InstRW<[Write4PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_4X4X")>;283def : InstRW<[Write8PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_16X16X")>;284 285} // End SchedModel = SIDPFullSpeedModel286 287let SchedModel = SIDPGFX942FullSpeedModel in {288 289defm : SICommonWriteRes;290 291def : HWVALUWriteRes<WriteFloatFMA, 1>;292def : HWVALUWriteRes<WriteDouble, 1>;293def : HWVALUWriteRes<WriteDoubleAdd, 1>;294def : HWVALUWriteRes<WriteDoubleCvt, 1>;295def : HWVALUWriteRes<WriteTrans64, 4>;296def : HWVALUWriteRes<WriteIntMul, 1>;297def : HWVALUWriteRes<Write64Bit, 1>;298 299def : InstRW<[WriteCopy], (instrs COPY)>;300def : InstRW<[Write64Bit], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;301def : InstRW<[Write2PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_4X4X")>;302 303def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X8X")>;304def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X16")>;305def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X32")>;306def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X[14][FBI]")>;307 308def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X4XF")>;309def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X8")>;310def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X16")>;311def : InstRW<[Write16PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X[124][FBI]")>;312 313def : InstRW<[Write4PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_4X4X")>;314def : InstRW<[Write8PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_16X16X")>;315 316def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_SMFMAC_.32_16X16X")>;317def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_SMFMAC_.32_32X32X")>;318 319} // End SchedModel = SIDPGFX942FullSpeedModel320 321 322let SchedModel = SIDPGFX950FullSpeedModel in {323defm : SICommonWriteRes;324 325def : HWVALUWriteRes<WriteFloatFMA, 1>;326def : HWVALUWriteRes<WriteDouble, 1>;327def : HWVALUWriteRes<WriteDoubleAdd, 1>;328def : HWVALUWriteRes<WriteDoubleCvt, 1>;329def : HWVALUWriteRes<WriteTrans64, 4>;330def : HWVALUWriteRes<WriteIntMul, 1>;331def : HWVALUWriteRes<Write64Bit, 1>;332 333def : InstRW<[WriteCopy], (instrs COPY)>;334def : InstRW<[Write64Bit], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;335def : InstRW<[Write2PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_4X4X")>;336 337def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X8X")>;338def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X16")>;339def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X32")>;340def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X64")>;341def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X[14][FBI]")>;342 343def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X4XF")>;344def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X8")>;345def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X16")>;346def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X32_")>;347def : InstRW<[Write16PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X[124][FBI]")>;348 349def : InstRW<[Write4PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_4X4X")>;350def : InstRW<[Write16PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_16X16X")>;351 352def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_SMFMAC_.32_16X16X")>;353def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_SMFMAC_.32_32X32X")>;354 355 356// If either matrix format is f8, the instruction takes 2x as many357// cycles. TODO: This isn't reflected in MCA.358def WriteMFMAScale_16X16X128_F8F6F4 : SchedWriteVariant<[359 SchedVar<PredIsF8_MFMA_SCALE, [Write8PassMAI]>,360 SchedVar<NoSchedPred, [Write4PassMAI]>]>;361def WriteMFMAScale_32X32X64_F8F6F4 : SchedWriteVariant<[362 SchedVar<PredIsF8_MFMA_SCALE, [Write16PassMAI]>,363 SchedVar<NoSchedPred, [Write8PassMAI]>]>;364 365def : InstRW<[WriteMFMAScale_16X16X128_F8F6F4, MIMFMARead],366 (instregex "^V_MFMA(_SCALE)?_.32_16X16X128_F8F6F4")>;367def : InstRW<[WriteMFMAScale_32X32X64_F8F6F4, MIMFMARead],368 (instregex "^V_MFMA(_SCALE)?_.32_32X32X64_F8F6F4")>;369 370} // End SchedModel = SIDPGFX950FullSpeedModel371 372 373let SchedModel = GFX10SpeedModel in {374 375// The latency values are 1 / (operations / cycle).376// Add 1 stall cycle for VGPR read.377let RetireOOO = 1 in { // llvm-mca specific flag378def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>;379def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>;380def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 6>;381def : HWWriteRes<WriteTrans32, [HWTransVALU, HWRC], 10>;382def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 8>;383def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>;384def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 22>;385def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 22>;386def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 22>;387def : HWWriteRes<WriteIntMul, [HWVALU, HWRC], 8>;388def : HWWriteRes<WriteTrans64, [HWVALU, HWTransVALU, HWRC], 24>;389 390def : HWWriteRes<WriteBranch, [HWBranch], 32>;391def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>;392def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>;393def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>;394def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>;395def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>;396def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;397 398def : UnsupportedWriteRes<WriteSFPU>;399def : UnsupportedWriteRes<WritePseudoScalarTrans>;400} // End RetireOOO = 1401 402def : InstRW<[WriteCopy], (instrs COPY)>;403 404} // End SchedModel = GFX10SpeedModel405 406let SchedModel = GFX11SpeedModel in {407 408// The latency values are 1 / (operations / cycle).409// Add 1 stall cycle for VGPR read.410let RetireOOO = 1 in { // llvm-mca specific flag411def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>;412def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>;413def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 6>;414def : HWWriteRes<WriteTrans32, [HWTransVALU, HWRC], 10>;415def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 8>;416def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>;417def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 38>;418def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 38>;419def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 38>;420def : HWWriteRes<WriteIntMul, [HWVALU, HWRC], 8>;421def : HWWriteRes<WriteTrans64, [HWVALU, HWTransVALU, HWRC], 40>;422 423def : HWWriteRes<WriteBranch, [HWBranch], 32>;424def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>;425def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>;426def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>;427def : HWWriteRes<WriteSFPU, [HWSALU, HWRC], 4>;428def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>;429def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>;430def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;431} // End RetireOOO = 1432 433def : UnsupportedWriteRes<WritePseudoScalarTrans>;434 435def : InstRW<[WriteCopy], (instrs COPY)>;436 437} // End SchedModel = GFX11SpeedModel438 439let SchedModel = GFX12SpeedModel in {440 441def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>;442def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>;443def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 6>;444def : HWWriteRes<WriteTrans32, [HWVALU, HWRC], 10>;445def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 8>;446def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>;447def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 38>;448def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 38>;449def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 38>;450def : HWWriteRes<WriteIntMul, [HWVALU, HWRC], 8>;451def : HWWriteRes<WriteTrans64, [HWVALU, HWRC], 40>;452def : HWWriteRes<WritePseudoScalarTrans, [HWVALU, HWRC], 7>;453 454def : HWWriteRes<WriteBranch, [HWBranch], 32>;455def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>;456def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>;457def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>;458def : HWWriteRes<WriteSFPU, [HWSALU, HWRC], 4>;459def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>;460def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>;461def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;462 463def : InstRW<[WriteCopy], (instrs COPY)>;464 465} // End SchedModel = GFX12SpeedModel466 467// Check if any matrix inputs are interpreted as f8 in an f8f6f4468// wmma instruction.469def PredIsF8_WMMA_SCALE : SchedPredicate<[{470 TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_a_fmt)->getImm() <= AMDGPU::WMMA::MATRIX_FMT_BF8 ||471 TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_b_fmt)->getImm() <= AMDGPU::WMMA::MATRIX_FMT_BF8472}]>;473 474// If either matrix format is f8, the instruction takes 2x as many475// cycles. TODO: This isn't reflected in MCA.476def WriteWMMAScale_16X16X128_F8F6F4 : SchedWriteVariant<[477 SchedVar<PredIsF8_WMMA_SCALE, [WriteXDL4PassWMMA]>,478 SchedVar<NoSchedPred, [WriteXDL2PassWMMA]>479]>;480 481multiclass GFX125xCommonWriteRes {482 483let ReleaseAtCycles = [8] in484def : HWWriteRes<WriteXDL2PassWMMA, [HWXDL], 8>;485let ReleaseAtCycles = [16] in486def : HWWriteRes<WriteXDL4PassWMMA, [HWXDL], 16>;487 488def : HWWriteRes<Write4PassWMMA, [HWVALU], 16>;489def : HWWriteRes<Write8PassWMMA, [HWVALU], 32>;490def : HWWriteRes<Write16PassWMMA, [HWVALU], 64>;491 492def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>;493def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>;494def : HWWriteRes<WriteTrans32, [HWTransVALU, HWRC], 7>;495def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 6>;496def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>;497def : HWWriteRes<WritePseudoScalarTrans, [HWVALU, HWRC], 8>;498 499def : HWWriteRes<WriteBranch, [HWBranch], 32>;500def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>;501def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>;502def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>;503def : HWWriteRes<WriteSFPU, [HWSALU, HWRC], 4>;504def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>;505def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>;506def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;507 508def : InstRW<[WriteCopy], (instrs COPY)>;509 510def : InstRW<[WriteXDL2PassWMMA], (instregex "^V_[S]*WMMA[C]*_.*_(FP8|BF8|BF16|F16)_w32")>;511def : InstRW<[WriteXDL4PassWMMA], (instregex "^V_[S]*WMMA[C]*_.*_(IU8|IU4)_w32")>;512def : InstRW<[WriteWMMAScale_16X16X128_F8F6F4], (instregex "^V_WMMA_.*_16X16X128_F8F6F4.*_w32")>;513def : InstRW<[Write4PassWMMA], (instregex "^V_WMMA_F32_16X16X4_F32_w32")>;514def : InstRW<[WriteXDL2PassWMMA], (instregex "^V_WMMA.*_F32_32X16X128_F4")>;515} // End GFX125xCommonWriteRes516 517let SchedModel = GFX1250SpeedModel in {518defm : GFX125xCommonWriteRes;519 520def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 7>;521def : HWWriteRes<WriteIntMul, [HWVALU, HWRC], 11>;522def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 32>;523def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 32>;524def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 32>;525def : HWWriteRes<WriteTrans64, [HWVALU, HWTransVALU, HWRC], 38>;526} // SchedModel = GFX1250SpeedModel527