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1//===-- SOPInstructions.td - SOP Instruction Definitions ------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9def GPRIdxMode : CustomOperand<i32>;10 11class SOP_Pseudo<string opName, dag outs, dag ins, string asmOps,12 list<dag> pattern=[]> :13 InstSI<outs, ins, "", pattern>,14 SIMCInstr<opName, SIEncodingFamily.NONE> {15 16 let isPseudo = 1;17 let isCodeGenOnly = 1;18 let Size = 4;19 20 string Mnemonic = opName;21 string AsmOperands = asmOps;22 23 bits<1> has_sdst = 0;24}25 26//===----------------------------------------------------------------------===//27// SOP1 Instructions28//===----------------------------------------------------------------------===//29 30class SOP1_Pseudo <string opName, dag outs, dag ins,31 string asmOps, list<dag> pattern=[]> :32 SOP_Pseudo<opName, outs, ins, " " # asmOps, pattern> {33 34 let mayLoad = 0;35 let mayStore = 0;36 let hasSideEffects = 0;37 let SALU = 1;38 let SOP1 = 1;39 let SchedRW = [WriteSALU];40 let UseNamedOperandTable = 1;41 42 bits<1> has_src0 = 1;43 let has_sdst = 1;44}45 46class SOP1_Real<bits<8> op, SOP1_Pseudo ps, string real_name = ps.Mnemonic> :47 InstSI <ps.OutOperandList, ps.InOperandList,48 real_name # ps.AsmOperands>,49 Enc32 {50 51 let SALU = 1;52 let SOP1 = 1;53 let isPseudo = 0;54 let isCodeGenOnly = 0;55 let Size = 4;56 57 // copy relevant pseudo op flags58 let SubtargetPredicate = ps.SubtargetPredicate;59 let AsmMatchConverter = ps.AsmMatchConverter;60 let SchedRW = ps.SchedRW;61 let mayLoad = ps.mayLoad;62 let mayStore = ps.mayStore;63 let isTerminator = ps.isTerminator;64 let isReturn = ps.isReturn;65 let isCall = ps.isCall;66 let isBranch = ps.isBranch;67 let isBarrier = ps.isBarrier;68 let Uses = ps.Uses;69 let Defs = ps.Defs;70 let isConvergent = ps.isConvergent;71 72 // encoding73 bits<7> sdst;74 bits<8> src0;75 76 let Inst{7-0} = !if(ps.has_src0, src0, ?);77 let Inst{15-8} = op;78 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);79 let Inst{31-23} = 0x17d; //encoding;80}81 82class SOP1_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseudo <83 opName, (outs SReg_32:$sdst),84 !if(tied_in, (ins SSrc_b32:$src0, SReg_32:$sdst_in),85 (ins SSrc_b32:$src0)),86 "$sdst, $src0", pattern> {87 let Constraints = !if(tied_in, "$sdst = $sdst_in", "");88}89 90// Only register input allowed.91class SOP1_32R <string opName, list<dag> pattern=[]> : SOP1_Pseudo <92 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),93 "$sdst, $src0", pattern>;94 95// 32-bit input, no output.96class SOP1_0_32 <string opName, list<dag> pattern = []> : SOP1_Pseudo <97 opName, (outs), (ins SSrc_b32:$src0),98 "$src0", pattern> {99 let has_sdst = 0;100}101 102// Special case for movreld where sdst is treated as a use operand.103class SOP1_32_movreld <string opName, list<dag> pattern=[]> : SOP1_Pseudo <104 opName, (outs), (ins SReg_32:$sdst, SSrc_b32:$src0),105 "$sdst, $src0", pattern>;106 107// Special case for movreld where sdst is treated as a use operand.108class SOP1_64_movreld <string opName, list<dag> pattern=[]> : SOP1_Pseudo <109 opName, (outs), (ins SReg_64:$sdst, SSrc_b64:$src0),110 "$sdst, $src0", pattern111>;112 113class SOP1_0_32R <string opName, list<dag> pattern = []> : SOP1_Pseudo <114 opName, (outs), (ins SReg_32:$src0),115 "$src0", pattern> {116 let has_sdst = 0;117}118 119class SOP1_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <120 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),121 "$sdst, $src0", pattern122>;123 124// Only register input allowed.125class SOP1_64R <string opName, list<dag> pattern=[]> : SOP1_Pseudo <126 opName, (outs SReg_64:$sdst), (ins SReg_64:$src0),127 "$sdst, $src0", pattern128>;129 130// 64-bit input, 32-bit output.131class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <132 opName, (outs SReg_32:$sdst), (ins SSrc_b64:$src0),133 "$sdst, $src0", pattern134>;135 136// 32-bit input, 64-bit output.137class SOP1_64_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseudo <138 opName, (outs SReg_64:$sdst),139 !if(tied_in, (ins SSrc_b32:$src0, SReg_64:$sdst_in),140 (ins SSrc_b32:$src0)),141 "$sdst, $src0", pattern> {142 let Constraints = !if(tied_in, "$sdst = $sdst_in", "");143}144 145// no input, 64-bit output.146class SOP1_64_0 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <147 opName, (outs SReg_64:$sdst), (ins), "$sdst", pattern> {148 let has_src0 = 0;149}150 151// 64-bit input, no output152class SOP1_1 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <153 opName, (outs), (ins SReg_64:$src0), "$src0", pattern> {154 let has_sdst = 0;155}156 157class SOP1_1_REGIMM64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <158 opName, (outs), (ins SSrc_b64:$src0), "$src0", pattern> {159 let has_sdst = 0;160}161 162class UniformUnaryFrag<SDPatternOperator Op> : PatFrag <163 (ops node:$src0),164 (Op $src0),165 [{ return !N->isDivergent(); }]> {166 // This check is unnecessary as it's captured by the result register167 // bank constraint.168 //169 // FIXME: Should add a way for the emitter to recognize this is a170 // trivially true predicate to eliminate the check.171 let GISelPredicateCode = [{return true;}];172}173 174class UniformBinFrag<SDPatternOperator Op> : PatFrag <175 (ops node:$src0, node:$src1),176 (Op $src0, $src1),177 [{ return !N->isDivergent(); }]> {178 // This check is unnecessary as it's captured by the result register179 // bank constraint.180 //181 // FIXME: Should add a way for the emitter to recognize this is a182 // trivially true predicate to eliminate the check.183 let GISelPredicateCode = [{return true;}];184}185 186class UniformTernaryFrag<SDPatternOperator Op> : PatFrag <187 (ops node:$src0, node:$src1, node:$src2),188 (Op $src0, $src1, $src2),189 [{ return !N->isDivergent(); }]> {190 // This check is unnecessary as it's captured by the result register191 // bank constraint.192 //193 // FIXME: Should add a way for the emitter to recognize this is a194 // trivially true predicate to eliminate the check.195 let GISelPredicateCode = [{return true;}];196}197 198class DivergentBinFrag<SDPatternOperator Op> : PatFrag <199 (ops node:$src0, node:$src1),200 (Op $src0, $src1),201 [{ return N->isDivergent(); }]> {202 // This check is unnecessary as it's captured by the result register203 // bank constraint.204 //205 // FIXME: Should add a way for the emitter to recognize this is a206 // trivially true predicate to eliminate the check.207 let GISelPredicateCode = [{return true;}];208}209 210 211let isMoveImm = 1 in {212 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {213 def S_MOV_B32 : SOP1_32 <"s_mov_b32">;214 def S_MOV_B64 : SOP1_64 <"s_mov_b64">;215 } // End isReMaterializable = 1216 217 let Uses = [SCC] in {218 def S_CMOV_B32 : SOP1_32 <"s_cmov_b32">;219 def S_CMOV_B64 : SOP1_64 <"s_cmov_b64">;220 } // End Uses = [SCC]221} // End isMoveImm = 1222 223// Variant of S_MOV_B32 used for reading from volatile registers like224// SRC_POPS_EXITING_WAVE_ID.225let hasSideEffects = 1 in226def S_MOV_B32_sideeffects : SOP1_32 <"s_mov_b32">;227 228let Defs = [SCC] in {229 def S_NOT_B32 : SOP1_32 <"s_not_b32",230 [(set i32:$sdst, (UniformUnaryFrag<not> i32:$src0))]231 >;232 233 def S_NOT_B64 : SOP1_64 <"s_not_b64",234 [(set i64:$sdst, (UniformUnaryFrag<not> i64:$src0))]235 >;236 def S_WQM_B32 : SOP1_32 <"s_wqm_b32",237 [(set i32:$sdst, (int_amdgcn_s_wqm i32:$src0))]>;238 def S_WQM_B64 : SOP1_64 <"s_wqm_b64",239 [(set i64:$sdst, (int_amdgcn_s_wqm i64:$src0))]>;240} // End Defs = [SCC]241 242 243let WaveSizePredicate = isWave32 in {244def : GCNPat <245 (int_amdgcn_wqm_vote i1:$src0),246 (S_WQM_B32 SSrc_b32:$src0)247>;248}249 250let WaveSizePredicate = isWave64 in {251def : GCNPat <252 (int_amdgcn_wqm_vote i1:$src0),253 (S_WQM_B64 SSrc_b64:$src0)254>;255}256 257let isReMaterializable = 1, isAsCheapAsAMove = 1 in {258def S_BREV_B32 : SOP1_32 <"s_brev_b32",259 [(set i32:$sdst, (UniformUnaryFrag<bitreverse> i32:$src0))]260>;261def S_BREV_B64 : SOP1_64 <"s_brev_b64",262 [(set i64:$sdst, (UniformUnaryFrag<bitreverse> i64:$src0))]263>;264} // End isReMaterializable = 1, isAsCheapAsAMove = 1265 266let Defs = [SCC] in {267def S_BCNT0_I32_B32 : SOP1_32 <"s_bcnt0_i32_b32">;268def S_BCNT0_I32_B64 : SOP1_32_64 <"s_bcnt0_i32_b64">;269def S_BCNT1_I32_B32 : SOP1_32 <"s_bcnt1_i32_b32",270 [(set i32:$sdst, (UniformUnaryFrag<ctpop> i32:$src0))]271>;272def S_BCNT1_I32_B64 : SOP1_32_64 <"s_bcnt1_i32_b64",273 [(set i32:$sdst, (UniformUnaryFrag<ctpop> i64:$src0))]274>;275} // End Defs = [SCC]276 277let isReMaterializable = 1 in {278def S_FF0_I32_B32 : SOP1_32 <"s_ff0_i32_b32">;279def S_FF0_I32_B64 : SOP1_32_64 <"s_ff0_i32_b64">;280def S_FF1_I32_B64 : SOP1_32_64 <"s_ff1_i32_b64",281 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbl_b32> i64:$src0))]282>;283 284def S_FF1_I32_B32 : SOP1_32 <"s_ff1_i32_b32",285 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbl_b32> i32:$src0))]286>;287 288def S_FLBIT_I32_B32 : SOP1_32 <"s_flbit_i32_b32",289 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbh_u32> i32:$src0))]290>;291 292def S_FLBIT_I32_B64 : SOP1_32_64 <"s_flbit_i32_b64",293 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbh_u32> i64:$src0))]294>;295def S_FLBIT_I32 : SOP1_32 <"s_flbit_i32",296 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbh_i32> i32:$src0))]297>;298def S_FLBIT_I32_I64 : SOP1_32_64 <"s_flbit_i32_i64">;299def S_SEXT_I32_I8 : SOP1_32 <"s_sext_i32_i8",300 [(set i32:$sdst, (UniformSextInreg<i8> i32:$src0))]301>;302def S_SEXT_I32_I16 : SOP1_32 <"s_sext_i32_i16",303 [(set i32:$sdst, (UniformSextInreg<i16> i32:$src0))]304>;305} // End isReMaterializable = 1306 307def S_BITSET0_B32 : SOP1_32 <"s_bitset0_b32", [], 1>;308def S_BITSET0_B64 : SOP1_64_32 <"s_bitset0_b64", [], 1>;309def S_BITSET1_B32 : SOP1_32 <"s_bitset1_b32", [], 1>;310def S_BITSET1_B64 : SOP1_64_32 <"s_bitset1_b64", [], 1>;311 312def S_GETPC_B64 : SOP1_64_0 <"s_getpc_b64">;313// PSEUDO includes a workaround for a hardware anomaly where some ASICs314// zero-extend the result from 48 bits instead of sign-extending.315let isReMaterializable = 1 in316def S_GETPC_B64_pseudo : SOP1_64_0 <"s_getpc_b64",317 [(set i64:$sdst, (int_amdgcn_s_getpc))]318>;319 320let isTerminator = 1, isBarrier = 1, SchedRW = [WriteBranch] in {321 322let isBranch = 1, isIndirectBranch = 1 in {323def S_SETPC_B64 : SOP1_1 <"s_setpc_b64">;324 325let SubtargetPredicate = HasAddPC64Inst in326def S_ADD_PC_I64 : SOP1_1_REGIMM64 <"s_add_pc_i64">;327} // End isBranch = 1, isIndirectBranch = 1328 329let isReturn = 1 in {330// Define variant marked as return rather than branch.331def S_SETPC_B64_return : SOP1_1<"">;332}333} // End isTerminator = 1, isBarrier = 1334 335let isCall = 1 in {336def S_SWAPPC_B64 : SOP1_64 <"s_swappc_b64"337>;338}339 340def S_RFE_B64 : SOP1_1 <"s_rfe_b64">;341 342let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {343 344def S_AND_SAVEEXEC_B64 : SOP1_64 <"s_and_saveexec_b64">;345def S_OR_SAVEEXEC_B64 : SOP1_64 <"s_or_saveexec_b64">;346def S_XOR_SAVEEXEC_B64 : SOP1_64 <"s_xor_saveexec_b64">;347def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <"s_andn2_saveexec_b64">;348def S_ORN2_SAVEEXEC_B64 : SOP1_64 <"s_orn2_saveexec_b64">;349def S_NAND_SAVEEXEC_B64 : SOP1_64 <"s_nand_saveexec_b64">;350def S_NOR_SAVEEXEC_B64 : SOP1_64 <"s_nor_saveexec_b64">;351def S_XNOR_SAVEEXEC_B64 : SOP1_64 <"s_xnor_saveexec_b64">;352 353} // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC]354 355let Defs = [SCC] in {356def S_QUADMASK_B32 : SOP1_32 <"s_quadmask_b32",357 [(set i32:$sdst, (int_amdgcn_s_quadmask i32:$src0))]>;358def S_QUADMASK_B64 : SOP1_64 <"s_quadmask_b64",359 [(set i64:$sdst, (int_amdgcn_s_quadmask i64:$src0))]>;360}361 362let Uses = [M0] in {363def S_MOVRELS_B32 : SOP1_32R <"s_movrels_b32">;364def S_MOVRELS_B64 : SOP1_64R <"s_movrels_b64">;365def S_MOVRELD_B32 : SOP1_32_movreld <"s_movreld_b32">;366def S_MOVRELD_B64 : SOP1_64_movreld <"s_movreld_b64">;367} // End Uses = [M0]368 369let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in {370def S_CBRANCH_JOIN : SOP1_0_32R <"s_cbranch_join">;371} // End SubtargetPredicate = isGFX6GFX7GFX8GFX9372 373let Defs = [SCC] in {374def S_ABS_I32 : SOP1_32 <"s_abs_i32",375 [(set i32:$sdst, (UniformUnaryFrag<abs> i32:$src0))]376 >;377} // End Defs = [SCC]378 379let SubtargetPredicate = HasVGPRIndexMode in {380def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> {381 let Uses = [M0, MODE];382 let Defs = [M0, MODE];383}384}385 386let SubtargetPredicate = isGFX9Plus in {387 let hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] in {388 def S_ANDN1_SAVEEXEC_B64 : SOP1_64<"s_andn1_saveexec_b64">;389 def S_ORN1_SAVEEXEC_B64 : SOP1_64<"s_orn1_saveexec_b64">;390 def S_ANDN1_WREXEC_B64 : SOP1_64<"s_andn1_wrexec_b64">;391 def S_ANDN2_WREXEC_B64 : SOP1_64<"s_andn2_wrexec_b64">;392 } // End hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC]393 394 let isReMaterializable = 1 in395 def S_BITREPLICATE_B64_B32 : SOP1_64_32<"s_bitreplicate_b64_b32",396 [(set i64:$sdst, (int_amdgcn_s_bitreplicate i32:$src0))]>;397} // End SubtargetPredicate = isGFX9Plus398 399let SubtargetPredicate = isGFX10Plus in {400 let hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC] in {401 def S_AND_SAVEEXEC_B32 : SOP1_32<"s_and_saveexec_b32">;402 def S_OR_SAVEEXEC_B32 : SOP1_32<"s_or_saveexec_b32">;403 def S_XOR_SAVEEXEC_B32 : SOP1_32<"s_xor_saveexec_b32">;404 def S_ANDN2_SAVEEXEC_B32 : SOP1_32<"s_andn2_saveexec_b32">;405 def S_ORN2_SAVEEXEC_B32 : SOP1_32<"s_orn2_saveexec_b32">;406 def S_NAND_SAVEEXEC_B32 : SOP1_32<"s_nand_saveexec_b32">;407 def S_NOR_SAVEEXEC_B32 : SOP1_32<"s_nor_saveexec_b32">;408 def S_XNOR_SAVEEXEC_B32 : SOP1_32<"s_xnor_saveexec_b32">;409 def S_ANDN1_SAVEEXEC_B32 : SOP1_32<"s_andn1_saveexec_b32">;410 def S_ORN1_SAVEEXEC_B32 : SOP1_32<"s_orn1_saveexec_b32">;411 def S_ANDN1_WREXEC_B32 : SOP1_32<"s_andn1_wrexec_b32">;412 def S_ANDN2_WREXEC_B32 : SOP1_32<"s_andn2_wrexec_b32">;413 } // End hasSideEffects = 1, Defs = [EXEC, SCC], Uses = [EXEC]414 415 let Uses = [M0] in {416 def S_MOVRELSD_2_B32 : SOP1_32<"s_movrelsd_2_b32">;417 } // End Uses = [M0]418} // End SubtargetPredicate = isGFX10Plus419 420let SubtargetPredicate = isGFX11Plus in {421 let hasSideEffects = 1 in {422 // For s_sendmsg_rtn_* the src0 field encodes the message type directly; it423 // is not an SGPR number.424 def S_SENDMSG_RTN_B32 : SOP1_Pseudo<425 "s_sendmsg_rtn_b32", (outs SReg_32:$sdst), (ins SendMsg:$src0),426 "$sdst, $src0", [(set i32:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))]427 >;428 def S_SENDMSG_RTN_B64 : SOP1_Pseudo<429 "s_sendmsg_rtn_b64", (outs SReg_64:$sdst), (ins SendMsg:$src0),430 "$sdst, $src0", [(set i64:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))]431 >;432 }433} // End SubtargetPredicate = isGFX11Plus434 435let SubtargetPredicate = isGFX12Plus in {436 let hasSideEffects = 1, Defs = [SCC] in {437 def S_ALLOC_VGPR : SOP1_0_32 <"s_alloc_vgpr">;438 }439} // End SubtargetPredicate = isGFX12Plus440 441class SOP1_F32_Inst<string opName, SDPatternOperator Op, ValueType vt0=f32,442 ValueType vt1=vt0> :443 SOP1_32<opName, [(set vt0:$sdst, (UniformUnaryFrag<Op> vt1:$src0))]>;444 445let SubtargetPredicate = HasSALUFloatInsts, Uses = [MODE],446 SchedRW = [WriteSFPU], isReMaterializable = 1 in {447 def S_CVT_F32_I32 : SOP1_F32_Inst<"s_cvt_f32_i32", sint_to_fp, f32, i32>;448 def S_CVT_F32_U32 : SOP1_F32_Inst<"s_cvt_f32_u32", uint_to_fp, f32, i32>;449 450 let mayRaiseFPException = 1 in {451 def S_CVT_I32_F32 : SOP1_F32_Inst<"s_cvt_i32_f32", fp_to_sint, i32, f32>;452 def S_CVT_U32_F32 : SOP1_F32_Inst<"s_cvt_u32_f32", fp_to_uint, i32, f32>;453 def S_CVT_F32_F16 : SOP1_F32_Inst<"s_cvt_f32_f16", fpextend, f32, f16>;454 def S_CVT_HI_F32_F16 : SOP1_32<"s_cvt_hi_f32_f16">;455 456 def S_CEIL_F32 : SOP1_F32_Inst<"s_ceil_f32", fceil>;457 def S_FLOOR_F32 : SOP1_F32_Inst<"s_floor_f32", ffloor>;458 def S_TRUNC_F32 : SOP1_F32_Inst<"s_trunc_f32", ftrunc>;459 def S_RNDNE_F32 : SOP1_F32_Inst<"s_rndne_f32", froundeven>;460 461 let FPDPRounding = 1 in462 def S_CVT_F16_F32 : SOP1_F32_Inst<"s_cvt_f16_f32", fpround, f16, f32>;463 464 def S_CEIL_F16 : SOP1_F32_Inst<"s_ceil_f16", fceil, f16>;465 def S_FLOOR_F16 : SOP1_F32_Inst<"s_floor_f16", ffloor, f16>;466 def S_TRUNC_F16 : SOP1_F32_Inst<"s_trunc_f16", ftrunc, f16>;467 def S_RNDNE_F16 : SOP1_F32_Inst<"s_rndne_f16", froundeven, f16>;468 } // End mayRaiseFPException = 1469} // End SubtargetPredicate = HasSALUFloatInsts, Uses = [MODE]470 // SchedRW = [WriteSFPU], isReMaterializable = 1471 472let hasSideEffects = 1 in {473let has_sdst = 0 in {474let Uses = [M0] in {475def S_BARRIER_SIGNAL_M0 : SOP1_Pseudo <"s_barrier_signal m0", (outs), (ins),476 "", []>{477 let SchedRW = [WriteBarrier];478 let isConvergent = 1;479}480 481def S_BARRIER_SIGNAL_ISFIRST_M0 : SOP1_Pseudo <"s_barrier_signal_isfirst m0", (outs), (ins),482 "", []>{483 let Defs = [SCC];484 let Uses = [M0, SCC];485 let SchedRW = [WriteBarrier];486 let isConvergent = 1;487}488 489def S_BARRIER_INIT_M0 : SOP1_Pseudo <"s_barrier_init m0", (outs), (ins),490 "", []>{491 let SchedRW = [WriteBarrier];492 let isConvergent = 1;493}494 495def S_BARRIER_INIT_IMM : SOP1_Pseudo <"s_barrier_init", (outs),496 (ins SplitBarrier:$src0), "$src0", []>{497 let SchedRW = [WriteBarrier];498 let isConvergent = 1;499}500 501def S_BARRIER_JOIN_M0 : SOP1_Pseudo <"s_barrier_join m0", (outs), (ins),502 "", []>{503 let SchedRW = [WriteBarrier];504 let isConvergent = 1;505}506 507} // End Uses = [M0]508 509def S_BARRIER_SIGNAL_IMM : SOP1_Pseudo <"s_barrier_signal", (outs),510 (ins SplitBarrier:$src0), "$src0", [(int_amdgcn_s_barrier_signal timm:$src0)]>{511 let SchedRW = [WriteBarrier];512 let isConvergent = 1;513}514 515def S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_Pseudo <"s_barrier_signal_isfirst", (outs),516 (ins SplitBarrier:$src0), "$src0", [(set SCC, (int_amdgcn_s_barrier_signal_isfirst timm:$src0))]>{517 let Defs = [SCC];518 let Uses = [SCC];519 let usesCustomInserter = 1;520 let SchedRW = [WriteBarrier];521 let isConvergent = 1;522}523 524def S_BARRIER_JOIN_IMM : SOP1_Pseudo <"s_barrier_join", (outs),525 (ins SplitBarrier:$src0), "$src0", []>{526 let SchedRW = [WriteBarrier];527 let isConvergent = 1;528}529 530} // End has_sdst = 0531 532def S_GET_BARRIER_STATE_IMM : SOP1_Pseudo <"s_get_barrier_state", (outs SSrc_b32:$sdst),533 (ins SplitBarrier:$src0), "$sdst, $src0", []>{534 let SchedRW = [WriteBarrier];535 let isConvergent = 1;536}537 538def S_GET_BARRIER_STATE_M0 : SOP1_Pseudo <"s_get_barrier_state $sdst, m0", (outs SSrc_b32:$sdst),539 (ins), "", []>{540 let Uses = [M0];541 let SchedRW = [WriteBarrier];542 let isConvergent = 1;543}544} // End hasSideEffects = 1545 546//===----------------------------------------------------------------------===//547// SOP2 Instructions548//===----------------------------------------------------------------------===//549 550class SOP2_Pseudo<string opName, dag outs, dag ins,551 string asmOps, list<dag> pattern=[]> :552 SOP_Pseudo<opName, outs, ins, " " # asmOps, pattern> {553 554 let mayLoad = 0;555 let mayStore = 0;556 let hasSideEffects = 0;557 let SALU = 1;558 let SOP2 = 1;559 let SchedRW = [WriteSALU];560 let UseNamedOperandTable = 1;561 562 let has_sdst = 1;563 564 // Pseudo instructions have no encodings, but adding this field here allows565 // us to do:566 // let sdst = xxx in {567 // for multiclasses that include both real and pseudo instructions.568 // field bits<7> sdst = 0;569}570 571class SOP2_Real<SOP_Pseudo ps, string name = ps.Mnemonic> :572 InstSI <ps.OutOperandList, ps.InOperandList,573 name # ps.AsmOperands> {574 let SALU = 1;575 let SOP2 = 1;576 let isPseudo = 0;577 let isCodeGenOnly = 0;578 579 // copy relevant pseudo op flags580 let SubtargetPredicate = ps.SubtargetPredicate;581 let AsmMatchConverter = ps.AsmMatchConverter;582 let UseNamedOperandTable = ps.UseNamedOperandTable;583 let TSFlags = ps.TSFlags;584 let SchedRW = ps.SchedRW;585 let mayLoad = ps.mayLoad;586 let mayStore = ps.mayStore;587 let Constraints = ps.Constraints;588 let Uses = ps.Uses;589 let Defs = ps.Defs;590 let isConvergent = ps.isConvergent;591 592 // encoding593 bits<7> sdst;594 bits<8> src0;595 bits<8> src1;596 bits<32> imm;597}598 599class SOP2_Real32<bits<7> op, SOP_Pseudo ps, string name = ps.Mnemonic> :600 SOP2_Real<ps, name>, Enc32 {601 let Inst{7-0} = src0;602 let Inst{15-8} = src1;603 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);604 let Inst{29-23} = op;605 let Inst{31-30} = 0x2; // encoding606}607 608class SOP2_Real64<bits<7> op, SOP_Pseudo ps, string name = ps.Mnemonic> :609 SOP2_Real<ps, name>, Enc64 {610 let Inst{7-0} = src0;611 let Inst{15-8} = src1;612 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);613 let Inst{29-23} = op;614 let Inst{31-30} = 0x2; // encoding615 let Inst{63-32} = imm;616}617 618class SOP2_F16 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <619 opName, (outs SReg_32:$sdst), (ins SSrc_f16:$src0, SSrc_f16:$src1),620 "$sdst, $src0, $src1", pattern621>;622 623class SOP2_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <624 opName, (outs SReg_32:$sdst), (ins SSrc_b32:$src0, SSrc_b32:$src1),625 "$sdst, $src0, $src1", pattern626>;627 628class SOP2_F32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <629 opName, (outs SReg_32:$sdst), (ins SSrc_f32:$src0, SSrc_f32:$src1),630 "$sdst, $src0, $src1", pattern631>;632 633class SOP2_64 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <634 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),635 "$sdst, $src0, $src1", pattern636>;637 638class SOP2_64_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <639 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b32:$src1),640 "$sdst, $src0, $src1", pattern641>;642 643class SOP2_64_32_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <644 opName, (outs SReg_64:$sdst), (ins SSrc_b32:$src0, SSrc_b32:$src1),645 "$sdst, $src0, $src1", pattern646>;647 648 649let Defs = [SCC] in { // Carry out goes to SCC650let isCommutable = 1, isAdd = 1 in {651def S_ADD_U32 : SOP2_32 <"s_add_u32">;652def S_ADD_I32 : SOP2_32 <"s_add_i32",653 [(set i32:$sdst, (UniformBinFrag<add> SSrc_b32:$src0, SSrc_b32:$src1))]654>;655} // End isCommutable = 1, isAdd = 1656 657def S_SUB_U32 : SOP2_32 <"s_sub_u32">;658def S_SUB_I32 : SOP2_32 <"s_sub_i32",659 [(set i32:$sdst, (UniformBinFrag<sub> SSrc_b32:$src0, SSrc_b32:$src1))]660>;661 662let Uses = [SCC] in { // Carry in comes from SCC663let isCommutable = 1 in {664def S_ADDC_U32 : SOP2_32 <"s_addc_u32",665 [(set i32:$sdst, (UniformBinFrag<adde> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]>;666} // End isCommutable = 1667 668def S_SUBB_U32 : SOP2_32 <"s_subb_u32",669 [(set i32:$sdst, (UniformBinFrag<sube> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]>;670} // End Uses = [SCC]671 672let isCommutable = 1 in {673def S_MIN_I32 : SOP2_32 <"s_min_i32",674 [(set i32:$sdst, (UniformBinFrag<smin> i32:$src0, i32:$src1))]675>;676def S_MIN_U32 : SOP2_32 <"s_min_u32",677 [(set i32:$sdst, (UniformBinFrag<umin> i32:$src0, i32:$src1))]678>;679def S_MAX_I32 : SOP2_32 <"s_max_i32",680 [(set i32:$sdst, (UniformBinFrag<smax> i32:$src0, i32:$src1))]681>;682def S_MAX_U32 : SOP2_32 <"s_max_u32",683 [(set i32:$sdst, (UniformBinFrag<umax> i32:$src0, i32:$src1))]684>;685} // End isCommutable = 1686} // End Defs = [SCC]687 688let SubtargetPredicate = isGFX12Plus in {689 def S_ADD_U64 : SOP2_64<"s_add_u64">{690 let isCommutable = 1;691 }692 693 def S_SUB_U64 : SOP2_64<"s_sub_u64">;694 695 def S_MUL_U64 : SOP2_64 <"s_mul_u64",696 [(set i64:$sdst, (UniformBinFrag<mul> i64:$src0, i64:$src1))]> {697 let isCommutable = 1;698 }699 700 // The higher 32-bits of the inputs contain the sign extension bits.701 let hasSideEffects = 0 in {702 def S_MUL_I64_I32_PSEUDO : SPseudoInstSI <703 (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)704 >;705 706 // The higher 32-bits of the inputs are zero.707 def S_MUL_U64_U32_PSEUDO : SPseudoInstSI <708 (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)709 >;710 }711 712} // End SubtargetPredicate = isGFX12Plus713 714let Uses = [SCC] in {715 def S_CSELECT_B32 : SOP2_32 <"s_cselect_b32">;716 def S_CSELECT_B64 : SOP2_64 <"s_cselect_b64">;717} // End Uses = [SCC]718 719let Defs = [SCC] in {720let isCommutable = 1 in {721def S_AND_B32 : SOP2_32 <"s_and_b32",722 [(set i32:$sdst, (UniformBinFrag<and> i32:$src0, i32:$src1))]723>;724 725def S_AND_B64 : SOP2_64 <"s_and_b64",726 [(set i64:$sdst, (UniformBinFrag<and> i64:$src0, i64:$src1))]727>;728 729def S_OR_B32 : SOP2_32 <"s_or_b32",730 [(set i32:$sdst, (UniformBinFrag<or> i32:$src0, i32:$src1))]731>;732 733def S_OR_B64 : SOP2_64 <"s_or_b64",734 [(set i64:$sdst, (UniformBinFrag<or> i64:$src0, i64:$src1))]735>;736 737def S_XOR_B32 : SOP2_32 <"s_xor_b32",738 [(set i32:$sdst, (UniformBinFrag<xor> i32:$src0, i32:$src1))]739>;740 741def S_XOR_B64 : SOP2_64 <"s_xor_b64",742 [(set i64:$sdst, (UniformBinFrag<xor> i64:$src0, i64:$src1))]743>;744 745def S_XNOR_B32 : SOP2_32 <"s_xnor_b32",746 [(set i32:$sdst, (UniformUnaryFrag<not> (xor_oneuse i32:$src0, i32:$src1)))]747>;748 749def S_XNOR_B64 : SOP2_64 <"s_xnor_b64",750 [(set i64:$sdst, (UniformUnaryFrag<not> (xor_oneuse i64:$src0, i64:$src1)))]751>;752 753def S_NAND_B32 : SOP2_32 <"s_nand_b32",754 [(set i32:$sdst, (UniformUnaryFrag<not> (and_oneuse i32:$src0, i32:$src1)))]755>;756 757def S_NAND_B64 : SOP2_64 <"s_nand_b64",758 [(set i64:$sdst, (UniformUnaryFrag<not> (and_oneuse i64:$src0, i64:$src1)))]759>;760 761def S_NOR_B32 : SOP2_32 <"s_nor_b32",762 [(set i32:$sdst, (UniformUnaryFrag<not> (or_oneuse i32:$src0, i32:$src1)))]763>;764 765def S_NOR_B64 : SOP2_64 <"s_nor_b64",766 [(set i64:$sdst, (UniformUnaryFrag<not> (or_oneuse i64:$src0, i64:$src1)))]767>;768} // End isCommutable = 1769 770// There are also separate patterns for types other than i32771def S_ANDN2_B32 : SOP2_32 <"s_andn2_b32",772 [(set i32:$sdst, (UniformBinFrag<and> i32:$src0, (not i32:$src1)))]773>;774 775def S_ANDN2_B64 : SOP2_64 <"s_andn2_b64",776 [(set i64:$sdst, (UniformBinFrag<and> i64:$src0, (not i64:$src1)))]777>;778 779def S_ORN2_B32 : SOP2_32 <"s_orn2_b32",780 [(set i32:$sdst, (UniformBinFrag<or> i32:$src0, (not i32:$src1)))]781>;782 783def S_ORN2_B64 : SOP2_64 <"s_orn2_b64",784 [(set i64:$sdst, (UniformBinFrag<or> i64:$src0, (not i64:$src1)))]785>;786} // End Defs = [SCC]787 788// Use added complexity so these patterns are preferred to the VALU patterns.789let AddedComplexity = 1 in {790 791let Defs = [SCC] in {792// TODO: b64 versions require VOP3 change since v_lshlrev_b64 is VOP3793def S_LSHL_B32 : SOP2_32 <"s_lshl_b32",794 [(set SReg_32:$sdst, (UniformBinFrag<cshl_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]795>;796def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64",797 [(set SReg_64:$sdst, (UniformBinFrag<cshl_64> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]798>;799def S_LSHR_B32 : SOP2_32 <"s_lshr_b32",800 [(set SReg_32:$sdst, (UniformBinFrag<csrl_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]801>;802def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64",803 [(set SReg_64:$sdst, (UniformBinFrag<csrl_64> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]804>;805def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",806 [(set SReg_32:$sdst, (UniformBinFrag<csra_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]807>;808def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64",809 [(set SReg_64:$sdst, (UniformBinFrag<csra_64> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]810>;811} // End Defs = [SCC]812 813let isReMaterializable = 1 in {814def S_BFM_B32 : SOP2_32 <"s_bfm_b32",815 [(set i32:$sdst, (UniformBinFrag<AMDGPUbfm> i32:$src0, i32:$src1))]>;816def S_BFM_B64 : SOP2_64_32_32 <"s_bfm_b64">;817 818def S_MUL_I32 : SOP2_32 <"s_mul_i32",819 [(set i32:$sdst, (UniformBinFrag<mul> i32:$src0, i32:$src1))]> {820 let isCommutable = 1;821}822} // End isReMaterializable = 1823} // End AddedComplexity = 1824 825let Defs = [SCC] in {826def S_BFE_U32 : SOP2_32 <"s_bfe_u32">;827def S_BFE_I32 : SOP2_32 <"s_bfe_i32">;828def S_BFE_U64 : SOP2_64_32 <"s_bfe_u64">;829def S_BFE_I64 : SOP2_64_32 <"s_bfe_i64">;830} // End Defs = [SCC]831 832def S_CBRANCH_G_FORK : SOP2_Pseudo <833 "s_cbranch_g_fork", (outs),834 (ins SCSrc_b64:$src0, SCSrc_b64:$src1),835 "$src0, $src1"836> {837 let has_sdst = 0;838 let SubtargetPredicate = isGFX6GFX7GFX8GFX9;839}840 841let isCommutable = 1, Defs = [SCC] in842def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32",843 [(set i32:$sdst, (UniformUnaryFrag<abs> (sub_oneuse i32:$src0, i32:$src1)))]844>;845 846let SubtargetPredicate = isGFX8GFX9 in {847 def S_RFE_RESTORE_B64 : SOP2_Pseudo <848 "s_rfe_restore_b64", (outs),849 (ins SSrc_b64:$src0, SSrc_b32:$src1),850 "$src0, $src1"851 > {852 let hasSideEffects = 1;853 let has_sdst = 0;854 }855}856 857let SubtargetPredicate = isGFX9Plus in {858 let isReMaterializable = 1 in {859 def S_PACK_LL_B32_B16 : SOP2_32<"s_pack_ll_b32_b16">;860 def S_PACK_LH_B32_B16 : SOP2_32<"s_pack_lh_b32_b16">;861 def S_PACK_HH_B32_B16 : SOP2_32<"s_pack_hh_b32_b16">;862 } // End isReMaterializable = 1863 864 let Defs = [SCC] in {865 def S_LSHL1_ADD_U32 : SOP2_32<"s_lshl1_add_u32",866 [(set i32:$sdst, (shl1_add SSrc_b32:$src0, SSrc_b32:$src1))]867 >;868 def S_LSHL2_ADD_U32 : SOP2_32<"s_lshl2_add_u32",869 [(set i32:$sdst, (shl2_add SSrc_b32:$src0, SSrc_b32:$src1))]870 >;871 def S_LSHL3_ADD_U32 : SOP2_32<"s_lshl3_add_u32",872 [(set i32:$sdst, (shl3_add SSrc_b32:$src0, SSrc_b32:$src1))]873 >;874 def S_LSHL4_ADD_U32 : SOP2_32<"s_lshl4_add_u32",875 [(set i32:$sdst, (shl4_add SSrc_b32:$src0, SSrc_b32:$src1))]876 >;877 } // End Defs = [SCC]878 879 let isCommutable = 1, isReMaterializable = 1 in {880 def S_MUL_HI_U32 : SOP2_32<"s_mul_hi_u32",881 [(set i32:$sdst, (UniformBinFrag<mulhu> SSrc_b32:$src0, SSrc_b32:$src1))]>;882 def S_MUL_HI_I32 : SOP2_32<"s_mul_hi_i32",883 [(set i32:$sdst, (UniformBinFrag<mulhs> SSrc_b32:$src0, SSrc_b32:$src1))]>;884 } // End isCommutable = 1, isReMaterializable = 1885} // End SubtargetPredicate = isGFX9Plus886 887let SubtargetPredicate = isGFX11Plus in {888 def S_PACK_HL_B32_B16 : SOP2_32<"s_pack_hl_b32_b16">;889} // End SubtargetPredicate = isGFX11Plus890 891class SOP2_F32_Inst<string opName, SDPatternOperator Op, ValueType dstVt=f32> :892 SOP2_F32<opName,893 [(set dstVt:$sdst, (UniformBinFrag<Op> SSrc_f32:$src0, SSrc_f32:$src1))]>;894 895class SOP2_F16_Inst<string opName, SDPatternOperator Op> :896 SOP2_F16<opName,897 [(set f16:$sdst, (UniformBinFrag<Op> SSrc_f16:$src0, SSrc_f16:$src1))]>;898 899let SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,900 Uses = [MODE], SchedRW = [WriteSFPU] in {901 let isReMaterializable = 1 in {902 let isCommutable = 1 in {903 def S_ADD_F32 : SOP2_F32_Inst<"s_add_f32", any_fadd>;904 def S_MIN_F32 : SOP2_F32_Inst<"s_min_f32", fminnum_like>;905 def S_MAX_F32 : SOP2_F32_Inst<"s_max_f32", fmaxnum_like>;906 def S_MUL_F32 : SOP2_F32_Inst<"s_mul_f32", any_fmul>;907 908 let FixedSize = 1 in909 def S_FMAAK_F32 : SOP2_Pseudo<910 "s_fmaak_f32", (outs SReg_32:$sdst),911 (ins SSrc_f32:$src0, SSrc_f32:$src1, KImmFP32:$imm),912 "$sdst, $src0, $src1, $imm"913 >;914 915 let FPDPRounding = 1 in {916 def S_ADD_F16 : SOP2_F16_Inst<"s_add_f16", any_fadd>;917 def S_MUL_F16 : SOP2_F16_Inst<"s_mul_f16", any_fmul>;918 } // End FPDPRounding919 920 def S_MIN_F16 : SOP2_F16_Inst<"s_min_f16", fminnum_like>;921 def S_MAX_F16 : SOP2_F16_Inst<"s_max_f16", fmaxnum_like>;922 } // End isCommutable = 1923 924 let FPDPRounding = 1 in925 def S_SUB_F16 : SOP2_F16_Inst<"s_sub_f16", any_fsub>;926 927 def S_SUB_F32 : SOP2_F32_Inst<"s_sub_f32", any_fsub>;928 def S_CVT_PK_RTZ_F16_F32 : SOP2_F32_Inst<"s_cvt_pk_rtz_f16_f32",929 AMDGPUpkrtz_f16_f32, v2f16>;930 931 let FixedSize = 1 in932 def S_FMAMK_F32 : SOP2_Pseudo<933 "s_fmamk_f32", (outs SReg_32:$sdst),934 (ins SSrc_f32:$src0, KImmFP32:$imm, SSrc_f32:$src1),935 "$sdst, $src0, $imm, $src1"936 >;937 } // End isReMaterializable = 1938 939 let Constraints = "$sdst = $src2",940 isCommutable = 1, AddedComplexity = 20 in {941 def S_FMAC_F32 : SOP2_Pseudo<942 "s_fmac_f32", (outs SReg_32:$sdst),943 (ins SSrc_f32:$src0, SSrc_f32:$src1, SReg_32:$src2),944 "$sdst, $src0, $src1",945 [(set f32:$sdst, (UniformTernaryFrag<any_fma> SSrc_f32:$src0, SSrc_f32:$src1, SReg_32:$src2))]946 >;947 948 def S_FMAC_F16 : SOP2_Pseudo<949 "s_fmac_f16", (outs SReg_32:$sdst),950 (ins SSrc_f16:$src0, SSrc_f16:$src1, SReg_32:$src2),951 "$sdst, $src0, $src1",952 [(set f16:$sdst, (UniformTernaryFrag<any_fma> SSrc_f16:$src0, SSrc_f16:$src1, SReg_32:$src2))]953 >;954 } // End Constraints = "$sdst = $src2",955 // isCommutable = 1, AddedComplexity = 20956} // End SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,957 // Uses = [MODE], SchedRW = [WriteSFPU]958 959// On GFX12 MIN/MAX instructions do not read MODE register.960let SubtargetPredicate = isGFX12Plus, mayRaiseFPException = 1, isCommutable = 1,961 isReMaterializable = 1, SchedRW = [WriteSFPU], AddedComplexity = 25 in {962 def S_MINIMUM_F32 : SOP2_F32_Inst<"s_minimum_f32", UniformBinFrag<fminimum>>;963 def S_MAXIMUM_F32 : SOP2_F32_Inst<"s_maximum_f32", UniformBinFrag<fmaximum>>;964 def S_MINIMUM_F16 : SOP2_F16_Inst<"s_minimum_f16", UniformBinFrag<fminimum>>;965 def S_MAXIMUM_F16 : SOP2_F16_Inst<"s_maximum_f16", UniformBinFrag<fmaximum>>;966}967 968//===----------------------------------------------------------------------===//969// SOPK Instructions970//===----------------------------------------------------------------------===//971 972class SOPK_Pseudo <string opName, dag outs, dag ins,973 string asmOps, list<dag> pattern=[]> :974 SOP_Pseudo<opName, outs, ins, " " # asmOps, pattern> {975 let mayLoad = 0;976 let mayStore = 0;977 let hasSideEffects = 0;978 let SALU = 1;979 let SOPK = 1;980 let FixedSize = 1;981 let SchedRW = [WriteSALU];982 let UseNamedOperandTable = 1;983 984 let has_sdst = 1;985}986 987class SOPK_Real<SOPK_Pseudo ps, string name = ps.Mnemonic> :988 InstSI <ps.OutOperandList, ps.InOperandList,989 name # ps.AsmOperands> {990 let SALU = 1;991 let SOPK = 1;992 let isPseudo = 0;993 let isCodeGenOnly = 0;994 let UseNamedOperandTable = 1;995 996 // copy relevant pseudo op flags997 let SubtargetPredicate = ps.SubtargetPredicate;998 let AsmMatchConverter = ps.AsmMatchConverter;999 let Constraints = ps.Constraints;1000 let SchedRW = ps.SchedRW;1001 let mayLoad = ps.mayLoad;1002 let mayStore = ps.mayStore;1003 let isBranch = ps.isBranch;1004 let isCall = ps.isCall;1005 let isTerminator = ps.isTerminator;1006 let isReturn = ps.isReturn;1007 let isBarrier = ps.isBarrier;1008 let Uses = ps.Uses;1009 let Defs = ps.Defs;1010 let isConvergent = ps.isConvergent;1011 1012 // encoding1013 bits<7> sdst;1014 bits<16> simm16;1015 bits<32> imm;1016}1017 1018class SOPK_Real32<bits<5> op, SOPK_Pseudo ps, string name = ps.Mnemonic> :1019 SOPK_Real <ps, name>,1020 Enc32 {1021 let Inst{15-0} = simm16;1022 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);1023 let Inst{27-23} = op;1024 let Inst{31-28} = 0xb; //encoding1025}1026 1027class SOPK_Real64<bits<5> op, SOPK_Pseudo ps> :1028 SOPK_Real<ps>,1029 Enc64 {1030 let Inst{15-0} = simm16;1031 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);1032 let Inst{27-23} = op;1033 let Inst{31-28} = 0xb; //encoding1034 let Inst{63-32} = imm;1035}1036 1037class SOPKInstTable <bit is_sopk, string cmpOp = ""> {1038 bit IsSOPK = is_sopk;1039 string BaseCmpOp = cmpOp;1040}1041 1042class SOPK_32 <string opName, list<dag> pattern=[]> : SOPK_Pseudo <1043 opName,1044 (outs SReg_32:$sdst),1045 (ins s16imm:$simm16),1046 "$sdst, $simm16",1047 pattern>;1048 1049class SOPK_32_BR <string opName, list<dag> pattern=[]> : SOPK_Pseudo <1050 opName,1051 (outs),1052 (ins SOPPBrTarget:$simm16, SReg_32:$sdst),1053 "$sdst, $simm16",1054 pattern> {1055 let Defs = [EXEC];1056 let Uses = [EXEC];1057 let isBranch = 1;1058 let isTerminator = 1;1059 let SchedRW = [WriteBranch];1060}1061 1062class SOPK_SCC <string opName, string base_op, bit isSignExt> : SOPK_Pseudo <1063 opName,1064 (outs),1065 !if(isSignExt,1066 (ins SReg_32:$sdst, s16imm:$simm16),1067 (ins SReg_32:$sdst, u16imm:$simm16)),1068 "$sdst, $simm16">,1069 SOPKInstTable<1, base_op>{1070 let Defs = [SCC];1071}1072 1073class SOPK_32TIE <string opName, list<dag> pattern=[]> : SOPK_Pseudo <1074 opName,1075 (outs SReg_32:$sdst),1076 (ins SReg_32:$src0, s16imm:$simm16),1077 "$sdst, $simm16",1078 pattern1079>;1080 1081let isReMaterializable = 1, isMoveImm = 1 in {1082def S_MOVK_I32 : SOPK_32 <"s_movk_i32">;1083} // End isReMaterializable = 11084let Uses = [SCC] in {1085def S_CMOVK_I32 : SOPK_32 <"s_cmovk_i32">;1086}1087 1088let isCompare = 1 in {1089 1090// This instruction is disabled for now until we can figure out how to teach1091// the instruction selector to correctly use the S_CMP* vs V_CMP*1092// instructions.1093//1094// When this instruction is enabled the code generator sometimes produces this1095// invalid sequence:1096//1097// SCC = S_CMPK_EQ_I32 SGPR0, imm1098// VCC = COPY SCC1099// VGPR0 = V_CNDMASK VCC, VGPR0, VGPR11100//1101// def S_CMPK_EQ_I32 : SOPK_SCC <"s_cmpk_eq_i32",1102// [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]1103// >;1104 1105def S_CMPK_EQ_I32 : SOPK_SCC <"s_cmpk_eq_i32", "s_cmp_eq_i32", 1>;1106def S_CMPK_LG_I32 : SOPK_SCC <"s_cmpk_lg_i32", "s_cmp_lg_i32", 1>;1107def S_CMPK_GT_I32 : SOPK_SCC <"s_cmpk_gt_i32", "s_cmp_gt_i32", 1>;1108def S_CMPK_GE_I32 : SOPK_SCC <"s_cmpk_ge_i32", "s_cmp_ge_i32", 1>;1109def S_CMPK_LT_I32 : SOPK_SCC <"s_cmpk_lt_i32", "s_cmp_lt_i32", 1>;1110def S_CMPK_LE_I32 : SOPK_SCC <"s_cmpk_le_i32", "s_cmp_le_i32", 1>;1111 1112def S_CMPK_EQ_U32 : SOPK_SCC <"s_cmpk_eq_u32", "s_cmp_eq_u32", 0>;1113def S_CMPK_LG_U32 : SOPK_SCC <"s_cmpk_lg_u32", "s_cmp_lg_u32", 0>;1114def S_CMPK_GT_U32 : SOPK_SCC <"s_cmpk_gt_u32", "s_cmp_gt_u32", 0>;1115def S_CMPK_GE_U32 : SOPK_SCC <"s_cmpk_ge_u32", "s_cmp_ge_u32", 0>;1116def S_CMPK_LT_U32 : SOPK_SCC <"s_cmpk_lt_u32", "s_cmp_lt_u32", 0>;1117def S_CMPK_LE_U32 : SOPK_SCC <"s_cmpk_le_u32", "s_cmp_le_u32", 0>;1118} // End isCompare = 11119 1120let isCommutable = 1, Constraints = "$sdst = $src0" in {1121 let Defs = [SCC] in1122 def S_ADDK_I32 : SOPK_32TIE <"s_addk_i32">;1123 def S_MULK_I32 : SOPK_32TIE <"s_mulk_i32">;1124}1125 1126let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in1127def S_CBRANCH_I_FORK : SOPK_Pseudo <1128 "s_cbranch_i_fork",1129 (outs), (ins SReg_64:$sdst, SOPPBrTarget:$simm16),1130 "$sdst, $simm16"1131>;1132 1133// FIXME: Need to truncate immediate to 16-bits.1134class S_GETREG_B32_Pseudo<list<dag> pattern=[]> : SOPK_Pseudo <1135 "s_getreg_b32",1136 (outs SReg_32:$sdst), (ins hwreg:$simm16),1137 "$sdst, $simm16", pattern>;1138 1139// This is hasSideEffects to allow its use in readcyclecounter selection.1140// FIXME: Should have separate pseudos for known may read MODE and1141// only read MODE.1142def S_GETREG_B32 : S_GETREG_B32_Pseudo<1143 [(set i32:$sdst, (int_amdgcn_s_getreg (i32 timm:$simm16)))]> {1144 let hasSideEffects = 1;1145 let Uses = [MODE];1146}1147 1148// A version of the pseudo for reading hardware register fields that are1149// known to remain the same during the course of the run. Has no side1150// effects and doesn't read MODE.1151def S_GETREG_B32_const : S_GETREG_B32_Pseudo;1152 1153let Defs = [MODE], Uses = [MODE] in {1154 1155// FIXME: Need to truncate immediate to 16-bits.1156class S_SETREG_B32_Pseudo <list<dag> pattern=[]> : SOPK_Pseudo <1157 "s_setreg_b32",1158 (outs), (ins SReg_32:$sdst, hwreg:$simm16),1159 "$simm16, $sdst",1160 pattern>;1161 1162def S_SETREG_B32 : S_SETREG_B32_Pseudo <1163 [(int_amdgcn_s_setreg (i32 SIMM16bit:$simm16), i32:$sdst)]> {1164 // Use custom inserter to optimize some cases to1165 // S_DENORM_MODE/S_ROUND_MODE/S_SETREG_B32_mode.1166 let usesCustomInserter = 1;1167 let hasSideEffects = 1;1168}1169 1170// Variant of SETREG that is guaranteed to only touch FP bits in the MODE1171// register, so doesn't have unmodeled side effects.1172def S_SETREG_B32_mode : S_SETREG_B32_Pseudo {1173 let hasSideEffects = 0;1174}1175 1176// FIXME: Not on SI?1177//def S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32">;1178 1179class S_SETREG_IMM32_B32_Pseudo : SOPK_Pseudo <1180 "s_setreg_imm32_b32",1181 (outs), (ins i32imm:$imm, hwreg:$simm16),1182 "$simm16, $imm"> {1183 let Size = 8; // Unlike every other SOPK instruction.1184 let has_sdst = 0;1185}1186 1187def S_SETREG_IMM32_B32 : S_SETREG_IMM32_B32_Pseudo {1188 let hasSideEffects = 1;1189}1190 1191// Variant of SETREG_IMM32 that is guaranteed to only touch FP bits in the MODE1192// register, so doesn't have unmodeled side effects.1193def S_SETREG_IMM32_B32_mode : S_SETREG_IMM32_B32_Pseudo {1194 let hasSideEffects = 0;1195}1196 1197} // End Defs = [MODE], Uses = [MODE]1198 1199class SOPK_WAITCNT<string opName, list<dag> pat=[]> :1200 SOPK_Pseudo<1201 opName,1202 (outs),1203 (ins SReg_32:$sdst, s16imm:$simm16),1204 "$sdst, $simm16",1205 pat> {1206 let hasSideEffects = 1;1207 let mayLoad = 1;1208 let mayStore = 1;1209 let has_sdst = 1; // First source takes place of sdst in encoding1210}1211 1212let SubtargetPredicate = isGFX9Plus in {1213 def S_CALL_B64 : SOPK_Pseudo<1214 "s_call_b64",1215 (outs SReg_64:$sdst),1216 (ins SOPPBrTarget:$simm16),1217 "$sdst, $simm16"> {1218 let isCall = 1;1219 }1220} // End SubtargetPredicate = isGFX9Plus1221 1222def VersionImm : S16ImmOperand {1223 let DecoderMethod = "decodeVersionImm";1224}1225 1226let SubtargetPredicate = isGFX10Plus in {1227 def S_VERSION : SOPK_Pseudo<1228 "s_version",1229 (outs),1230 (ins VersionImm:$simm16),1231 "$simm16"> {1232 let has_sdst = 0;1233 }1234} // End SubtargetPredicate = isGFX10Plus1235 1236let SubtargetPredicate = isGFX10GFX11 in {1237 def S_SUBVECTOR_LOOP_BEGIN : SOPK_32_BR<"s_subvector_loop_begin">;1238 def S_SUBVECTOR_LOOP_END : SOPK_32_BR<"s_subvector_loop_end">;1239 1240 def S_WAITCNT_VSCNT : SOPK_WAITCNT<"s_waitcnt_vscnt">;1241 def S_WAITCNT_VMCNT : SOPK_WAITCNT<"s_waitcnt_vmcnt">;1242 def S_WAITCNT_EXPCNT : SOPK_WAITCNT<"s_waitcnt_expcnt">;1243 def S_WAITCNT_LGKMCNT : SOPK_WAITCNT<"s_waitcnt_lgkmcnt">;1244} // End SubtargetPredicate = isGFX10GFX111245 1246//===----------------------------------------------------------------------===//1247// SOPC Instructions1248//===----------------------------------------------------------------------===//1249 1250class SOPC_Pseudo<string opName, dag outs, dag ins,1251 string asmOps, list<dag> pattern=[]> :1252 SOP_Pseudo<opName, outs, ins, " " # asmOps, pattern> {1253 let mayLoad = 0;1254 let mayStore = 0;1255 let hasSideEffects = 0;1256 let SALU = 1;1257 let SOPC = 1;1258 let Defs = [SCC];1259 let SchedRW = [WriteSALU];1260 let UseNamedOperandTable = 1;1261}1262 1263class SOPC_Real<bits<7> op, SOPC_Pseudo ps> :1264 InstSI <ps.OutOperandList, ps.InOperandList,1265 ps.Mnemonic # ps.AsmOperands>,1266 Enc32 {1267 let SALU = 1;1268 let SOPC = 1;1269 let isPseudo = 0;1270 let isCodeGenOnly = 0;1271 1272 // copy relevant pseudo op flags1273 let SubtargetPredicate = ps.SubtargetPredicate;1274 let OtherPredicates = ps.OtherPredicates;1275 let AsmMatchConverter = ps.AsmMatchConverter;1276 let UseNamedOperandTable = ps.UseNamedOperandTable;1277 let TSFlags = ps.TSFlags;1278 let SchedRW = ps.SchedRW;1279 let mayLoad = ps.mayLoad;1280 let mayStore = ps.mayStore;1281 let Uses = ps.Uses;1282 let Defs = ps.Defs;1283 let isConvergent = ps.isConvergent;1284 1285 // encoding1286 bits<8> src0;1287 bits<8> src1;1288 1289 let Inst{7-0} = src0;1290 let Inst{15-8} = src1;1291 let Inst{22-16} = op;1292 let Inst{31-23} = 0x17e;1293}1294 1295class SOPC_Base <RegisterOperand rc0, RegisterOperand rc1,1296 string opName, list<dag> pattern = []> : SOPC_Pseudo <1297 opName, (outs), (ins rc0:$src0, rc1:$src1),1298 "$src0, $src1", pattern > {1299}1300 1301class SOPC_Helper <RegisterOperand rc, ValueType vt,1302 string opName, SDPatternOperator cond> : SOPC_Base <1303 rc, rc, opName,1304 [(set SCC, (UniformTernaryFrag<setcc> vt:$src0, vt:$src1, cond))] > {1305}1306 1307class SOPC_CMP_32<string opName,1308 SDPatternOperator cond = COND_NULL, string revOp = opName>1309 : SOPC_Helper<SSrc_b32, i32, opName, cond>,1310 Commutable_REV<revOp, !eq(revOp, opName)>,1311 SOPKInstTable<0, opName> {1312 let isCompare = 1;1313 let isCommutable = 1;1314}1315 1316class SOPC_CMP_F32<string opName,1317 SDPatternOperator cond = COND_NULL, string revOp = opName>1318 : SOPC_Helper<SSrc_b32, f32, opName, cond>,1319 Commutable_REV<revOp, !eq(revOp, opName)>,1320 SOPKInstTable<0, opName> {1321 let isCompare = 1;1322 let isCommutable = 1;1323 let mayRaiseFPException = 1;1324 let Uses = [MODE];1325 let SchedRW = [WriteSFPU];1326}1327 1328class SOPC_CMP_F16<string opName,1329 SDPatternOperator cond = COND_NULL, string revOp = opName>1330 : SOPC_Helper<SSrc_b16, f16, opName, cond>,1331 Commutable_REV<revOp, !eq(revOp, opName)>,1332 SOPKInstTable<0, opName> {1333 let isCompare = 1;1334 let isCommutable = 1;1335 let mayRaiseFPException = 1;1336 let Uses = [MODE];1337 let SchedRW = [WriteSFPU];1338}1339 1340class SOPC_CMP_64<string opName,1341 SDPatternOperator cond = COND_NULL, string revOp = opName>1342 : SOPC_Helper<SSrc_b64, i64, opName, cond>,1343 Commutable_REV<revOp, !eq(revOp, opName)> {1344 let isCompare = 1;1345 let isCommutable = 1;1346}1347 1348class SOPC_32<string opName, list<dag> pattern = []>1349 : SOPC_Base<SSrc_b32, SSrc_b32, opName, pattern>;1350 1351class SOPC_64_32<string opName, list<dag> pattern = []>1352 : SOPC_Base<SSrc_b64, SSrc_b32, opName, pattern>;1353 1354def S_CMP_EQ_I32 : SOPC_CMP_32 <"s_cmp_eq_i32">;1355def S_CMP_LG_I32 : SOPC_CMP_32 <"s_cmp_lg_i32">;1356def S_CMP_GT_I32 : SOPC_CMP_32 <"s_cmp_gt_i32", COND_SGT>;1357def S_CMP_GE_I32 : SOPC_CMP_32 <"s_cmp_ge_i32", COND_SGE>;1358def S_CMP_LT_I32 : SOPC_CMP_32 <"s_cmp_lt_i32", COND_SLT, "s_cmp_gt_i32">;1359def S_CMP_LE_I32 : SOPC_CMP_32 <"s_cmp_le_i32", COND_SLE, "s_cmp_ge_i32">;1360def S_CMP_EQ_U32 : SOPC_CMP_32 <"s_cmp_eq_u32", COND_EQ>;1361def S_CMP_LG_U32 : SOPC_CMP_32 <"s_cmp_lg_u32", COND_NE>;1362def S_CMP_GT_U32 : SOPC_CMP_32 <"s_cmp_gt_u32", COND_UGT>;1363def S_CMP_GE_U32 : SOPC_CMP_32 <"s_cmp_ge_u32", COND_UGE>;1364def S_CMP_LT_U32 : SOPC_CMP_32 <"s_cmp_lt_u32", COND_ULT, "s_cmp_gt_u32">;1365def S_CMP_LE_U32 : SOPC_CMP_32 <"s_cmp_le_u32", COND_ULE, "s_cmp_ge_u32">;1366 1367def S_BITCMP0_B32 : SOPC_32 <"s_bitcmp0_b32">;1368def S_BITCMP1_B32 : SOPC_32 <"s_bitcmp1_b32">;1369def S_BITCMP0_B64 : SOPC_64_32 <"s_bitcmp0_b64">;1370def S_BITCMP1_B64 : SOPC_64_32 <"s_bitcmp1_b64">;1371let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in1372def S_SETVSKIP : SOPC_32 <"s_setvskip">;1373 1374let SubtargetPredicate = isGFX8Plus in {1375def S_CMP_EQ_U64 : SOPC_CMP_64 <"s_cmp_eq_u64", COND_EQ>;1376def S_CMP_LG_U64 : SOPC_CMP_64 <"s_cmp_lg_u64", COND_NE>;1377} // End SubtargetPredicate = isGFX8Plus1378 1379let SubtargetPredicate = HasVGPRIndexMode in {1380// Setting the GPR index mode is really writing the fields in the mode1381// register. We don't want to add mode register uses to every1382// instruction, and it's too complicated to deal with anyway. This is1383// modeled just as a side effect.1384def S_SET_GPR_IDX_ON : SOPC_Pseudo <1385 "s_set_gpr_idx_on" ,1386 (outs),1387 (ins SSrc_b32:$src0, GPRIdxMode:$src1),1388 "$src0, $src1"> {1389 let Defs = [M0, MODE]; // No scc def1390 let Uses = [M0, MODE]; // Other bits of mode, m0 unmodified.1391 let hasSideEffects = 1; // Sets mode.gpr_idx_en1392 let FixedSize = 1;1393}1394}1395 1396let SubtargetPredicate = HasSALUFloatInsts in {1397 1398def S_CMP_LT_F32 : SOPC_CMP_F32<"s_cmp_lt_f32", COND_OLT, "s_cmp_gt_f32">;1399def S_CMP_EQ_F32 : SOPC_CMP_F32<"s_cmp_eq_f32", COND_OEQ>;1400def S_CMP_LE_F32 : SOPC_CMP_F32<"s_cmp_le_f32", COND_OLE, "s_cmp_ge_f32">;1401def S_CMP_GT_F32 : SOPC_CMP_F32<"s_cmp_gt_f32", COND_OGT>;1402def S_CMP_LG_F32 : SOPC_CMP_F32<"s_cmp_lg_f32", COND_ONE>;1403def S_CMP_GE_F32 : SOPC_CMP_F32<"s_cmp_ge_f32", COND_OGE>;1404def S_CMP_O_F32 : SOPC_CMP_F32<"s_cmp_o_f32", COND_O>;1405def S_CMP_U_F32 : SOPC_CMP_F32<"s_cmp_u_f32", COND_UO>;1406def S_CMP_NGE_F32 : SOPC_CMP_F32<"s_cmp_nge_f32", COND_ULT, "s_cmp_nle_f32">;1407def S_CMP_NLG_F32 : SOPC_CMP_F32<"s_cmp_nlg_f32", COND_UEQ>;1408def S_CMP_NGT_F32 : SOPC_CMP_F32<"s_cmp_ngt_f32", COND_ULE, "s_cmp_nlt_f32">;1409def S_CMP_NLE_F32 : SOPC_CMP_F32<"s_cmp_nle_f32", COND_UGT>;1410def S_CMP_NEQ_F32 : SOPC_CMP_F32<"s_cmp_neq_f32", COND_UNE>;1411def S_CMP_NLT_F32 : SOPC_CMP_F32<"s_cmp_nlt_f32", COND_UGE>;1412 1413def S_CMP_LT_F16 : SOPC_CMP_F16<"s_cmp_lt_f16", COND_OLT, "s_cmp_gt_f16">;1414def S_CMP_EQ_F16 : SOPC_CMP_F16<"s_cmp_eq_f16", COND_OEQ>;1415def S_CMP_LE_F16 : SOPC_CMP_F16<"s_cmp_le_f16", COND_OLE, "s_cmp_ge_f16">;1416def S_CMP_GT_F16 : SOPC_CMP_F16<"s_cmp_gt_f16", COND_OGT>;1417def S_CMP_LG_F16 : SOPC_CMP_F16<"s_cmp_lg_f16", COND_ONE>;1418def S_CMP_GE_F16 : SOPC_CMP_F16<"s_cmp_ge_f16", COND_OGE>;1419def S_CMP_O_F16 : SOPC_CMP_F16<"s_cmp_o_f16", COND_O>;1420def S_CMP_U_F16 : SOPC_CMP_F16<"s_cmp_u_f16", COND_UO>;1421def S_CMP_NGE_F16 : SOPC_CMP_F16<"s_cmp_nge_f16", COND_ULT, "s_cmp_nle_f16">;1422def S_CMP_NLG_F16 : SOPC_CMP_F16<"s_cmp_nlg_f16", COND_UEQ>;1423def S_CMP_NGT_F16 : SOPC_CMP_F16<"s_cmp_ngt_f16", COND_ULE, "s_cmp_nlt_f16">;1424def S_CMP_NLE_F16 : SOPC_CMP_F16<"s_cmp_nle_f16", COND_UGT>;1425def S_CMP_NEQ_F16 : SOPC_CMP_F16<"s_cmp_neq_f16", COND_UNE>;1426def S_CMP_NLT_F16 : SOPC_CMP_F16<"s_cmp_nlt_f16", COND_UGE>;1427 1428} // End SubtargetPredicate = HasSALUFloatInsts1429 1430//===----------------------------------------------------------------------===//1431// SOPP Instructions1432//===----------------------------------------------------------------------===//1433 1434class SOPP_Pseudo<string opName, dag ins,1435 string asmOps = "", list<dag> pattern=[],1436 string sep = !if(!empty(asmOps), "", " "),1437 string keyName = opName> :1438 SOP_Pseudo<opName, (outs), ins, sep # asmOps, pattern> {1439 let mayLoad = 0;1440 let mayStore = 0;1441 let hasSideEffects = 0;1442 let SALU = 1;1443 let SOPP = 1;1444 let FixedSize = 1;1445 let SchedRW = [WriteSALU];1446 let UseNamedOperandTable = 1;1447 bits <16> simm16;1448 bits <1> fixed_imm = 0;1449 string KeyName = keyName;1450}1451 1452class SOPPRelaxTable <bit isRelaxed, string keyName, string gfxip> {1453 bit IsRelaxed = isRelaxed;1454 string KeyName = keyName # gfxip;1455}1456 1457class SOPP_Real<SOPP_Pseudo ps, string name = ps.Mnemonic> :1458 InstSI <ps.OutOperandList, ps.InOperandList,1459 name # ps.AsmOperands> {1460 let SALU = 1;1461 let SOPP = 1;1462 let isPseudo = 0;1463 let isCodeGenOnly = 0;1464 1465 // copy relevant pseudo op flags1466 let SubtargetPredicate = ps.SubtargetPredicate;1467 let OtherPredicates = ps.OtherPredicates;1468 let AsmMatchConverter = ps.AsmMatchConverter;1469 let UseNamedOperandTable = ps.UseNamedOperandTable;1470 let TSFlags = ps.TSFlags;1471 let SchedRW = ps.SchedRW;1472 let mayLoad = ps.mayLoad;1473 let mayStore = ps.mayStore;1474 let isTerminator = ps.isTerminator;1475 let isReturn = ps.isReturn;1476 let isCall = ps.isCall;1477 let isBranch = ps.isBranch;1478 let isBarrier = ps.isBarrier;1479 let Uses = ps.Uses;1480 let Defs = ps.Defs;1481 let isConvergent = ps.isConvergent;1482 bits <16> simm16;1483}1484 1485class SOPP_Real_32 <bits<7> op, SOPP_Pseudo ps, string name = ps.Mnemonic> : SOPP_Real<ps, name>,1486Enc32 {1487 let Inst{15-0} = !if(ps.fixed_imm, ps.simm16, simm16);1488 let Inst{22-16} = op;1489 let Inst{31-23} = 0x17f;1490}1491 1492class SOPP_Real_64 <bits<7> op, SOPP_Pseudo ps, string name = ps.Mnemonic> : SOPP_Real<ps, name>,1493Enc64 {1494 // encoding1495 let Inst{15-0} = !if(ps.fixed_imm, ps.simm16, simm16);1496 let Inst{22-16} = op;1497 let Inst{31-23} = 0x17f;1498 //effectively a nop1499 let Inst{47-32} = 0x0;1500 let Inst{54-48} = 0x0;1501 let Inst{63-55} = 0x17f;1502}1503 1504multiclass SOPP_With_Relaxation <string opName, dag ins,1505 string asmOps, list<dag> pattern=[]> {1506 def "" : SOPP_Pseudo <opName, ins, asmOps, pattern>;1507 def _pad_s_nop : SOPP_Pseudo <opName # "_pad_s_nop", ins, asmOps, pattern, " ", opName>;1508}1509 1510def S_NOP : SOPP_Pseudo<"s_nop" , (ins i16imm:$simm16), "$simm16",1511 [(int_amdgcn_s_nop timm:$simm16)]> {1512 let hasSideEffects = 1;1513}1514 1515let isTerminator = 1 in {1516def S_ENDPGM : SOPP_Pseudo<"s_endpgm", (ins Endpgm:$simm16), "$simm16", [], ""> {1517 let isBarrier = 1;1518 let isReturn = 1;1519 let hasSideEffects = 1;1520}1521 1522def S_ENDPGM_SAVED : SOPP_Pseudo<"s_endpgm_saved", (ins)> {1523 let SubtargetPredicate = isGFX8Plus;1524 let simm16 = 0;1525 let fixed_imm = 1;1526 let isBarrier = 1;1527 let isReturn = 1;1528}1529 1530let SubtargetPredicate = isGFX9GFX10GFX11 in {1531 let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {1532 def S_ENDPGM_ORDERED_PS_DONE :1533 SOPP_Pseudo<"s_endpgm_ordered_ps_done", (ins)>;1534 } // End isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 11535} // End SubtargetPredicate = isGFX9GFX10GFX111536 1537let SubtargetPredicate = isGFX10Plus in {1538 let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {1539 def S_CODE_END :1540 SOPP_Pseudo<"s_code_end", (ins)>;1541 } // End isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 11542} // End SubtargetPredicate = isGFX10Plus1543 1544let isBranch = 1, SchedRW = [WriteBranch] in {1545let isBarrier = 1 in {1546defm S_BRANCH : SOPP_With_Relaxation<1547 "s_branch" , (ins SOPPBrTarget:$simm16), "$simm16",1548 [(br bb:$simm16)]>;1549}1550 1551let Uses = [SCC] in {1552defm S_CBRANCH_SCC0 : SOPP_With_Relaxation<1553 "s_cbranch_scc0" , (ins SOPPBrTarget:$simm16),1554 "$simm16"1555>;1556defm S_CBRANCH_SCC1 : SOPP_With_Relaxation <1557 "s_cbranch_scc1" , (ins SOPPBrTarget:$simm16),1558 "$simm16"1559>;1560} // End Uses = [SCC]1561 1562let Uses = [VCC] in {1563defm S_CBRANCH_VCCZ : SOPP_With_Relaxation <1564 "s_cbranch_vccz" , (ins SOPPBrTarget:$simm16),1565 "$simm16"1566>;1567defm S_CBRANCH_VCCNZ : SOPP_With_Relaxation <1568 "s_cbranch_vccnz" , (ins SOPPBrTarget:$simm16),1569 "$simm16"1570>;1571} // End Uses = [VCC]1572 1573let Uses = [EXEC] in {1574defm S_CBRANCH_EXECZ : SOPP_With_Relaxation <1575 "s_cbranch_execz" , (ins SOPPBrTarget:$simm16),1576 "$simm16"1577>;1578defm S_CBRANCH_EXECNZ : SOPP_With_Relaxation <1579 "s_cbranch_execnz" , (ins SOPPBrTarget:$simm16),1580 "$simm16"1581>;1582} // End Uses = [EXEC]1583 1584defm S_CBRANCH_CDBGSYS : SOPP_With_Relaxation <1585 "s_cbranch_cdbgsys" , (ins SOPPBrTarget:$simm16),1586 "$simm16"1587>;1588 1589defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_With_Relaxation <1590 "s_cbranch_cdbgsys_and_user" , (ins SOPPBrTarget:$simm16),1591 "$simm16"1592>;1593 1594defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_With_Relaxation <1595 "s_cbranch_cdbgsys_or_user" , (ins SOPPBrTarget:$simm16),1596 "$simm16"1597>;1598 1599defm S_CBRANCH_CDBGUSER : SOPP_With_Relaxation <1600 "s_cbranch_cdbguser" , (ins SOPPBrTarget:$simm16),1601 "$simm16"1602>;1603 1604} // End isBranch = 11605} // End isTerminator = 11606 1607let hasSideEffects = 1 in {1608def S_BARRIER : SOPP_Pseudo <"s_barrier", (ins), "",1609 [(int_amdgcn_s_barrier)]> {1610 let SchedRW = [WriteBarrier];1611 let simm16 = 0;1612 let fixed_imm = 1;1613 let isConvergent = 1;1614}1615 1616def S_BARRIER_WAIT : SOPP_Pseudo <"s_barrier_wait", (ins i16imm:$simm16), "$simm16",1617 [(int_amdgcn_s_barrier_wait timm:$simm16)]> {1618 let SchedRW = [WriteBarrier];1619 let isConvergent = 1;1620}1621 1622 def S_BARRIER_LEAVE : SOPP_Pseudo <"s_barrier_leave",1623 (ins), "", [(int_amdgcn_s_barrier_leave (i16 srcvalue))] > {1624 let SchedRW = [WriteBarrier];1625 let simm16 = 0;1626 let fixed_imm = 1;1627 let isConvergent = 1;1628 let Defs = [SCC];1629}1630 1631def S_WAKEUP : SOPP_Pseudo <"s_wakeup", (ins) > {1632 let SubtargetPredicate = isGFX8Plus;1633 let simm16 = 0;1634 let fixed_imm = 1;1635 let mayLoad = 1;1636 let mayStore = 1;1637}1638 1639let SubtargetPredicate = isNotGFX1250Plus in {1640def S_WAITCNT : SOPP_Pseudo <"s_waitcnt" , (ins SWaitCnt:$simm16), "$simm16",1641 [(int_amdgcn_s_waitcnt timm:$simm16)]>;1642}1643 1644// "_soft" waitcnts are waitcnts that are either relaxed into their non-soft1645// counterpart, or completely removed.1646//1647// These are inserted by SIMemoryLegalizer to resolve memory dependencies1648// and later optimized by SIInsertWaitcnts1649// For example, a S_WAITCNT_soft 0 can be completely removed in a function1650// that doesn't access memory.1651def S_WAITCNT_soft : SOPP_Pseudo <"s_soft_waitcnt" , (ins SWaitCnt:$simm16), "$simm16">;1652def S_WAITCNT_VSCNT_soft : SOPK_WAITCNT<"s_soft_waitcnt_vscnt">;1653let SubtargetPredicate = isGFX12Plus in {1654 def S_WAIT_LOADCNT_soft : SOPP_Pseudo <"s_soft_wait_loadcnt", (ins s16imm:$simm16), "$simm16">;1655 def S_WAIT_STORECNT_soft : SOPP_Pseudo <"s_soft_wait_storecnt", (ins s16imm:$simm16), "$simm16">;1656let OtherPredicates = [HasImageInsts] in {1657 def S_WAIT_SAMPLECNT_soft : SOPP_Pseudo <"s_soft_wait_samplecnt", (ins s16imm:$simm16), "$simm16">;1658 def S_WAIT_BVHCNT_soft : SOPP_Pseudo <"s_soft_wait_bvhcnt", (ins s16imm:$simm16), "$simm16">;1659} // End OtherPredicates = [HasImageInsts].1660 def S_WAIT_DSCNT_soft : SOPP_Pseudo <"s_soft_wait_dscnt", (ins s16imm:$simm16), "$simm16">;1661 def S_WAIT_KMCNT_soft : SOPP_Pseudo <"s_soft_wait_kmcnt", (ins s16imm:$simm16), "$simm16">;1662}1663 1664 1665let SubtargetPredicate = HasWaitXcnt in {1666 def S_WAIT_XCNT_soft : SOPP_Pseudo<"", (ins s16imm:$simm16), "$simm16">;1667}1668 1669// Represents the point at which a wave must wait for all outstanding direct loads to LDS.1670// Typically inserted by the memory legalizer and consumed by SIInsertWaitcnts.1671 1672def S_WAITCNT_lds_direct : SPseudoInstSI<(outs), (ins)> {1673 let hasSideEffects = 0;1674}1675 1676def S_SETHALT : SOPP_Pseudo <"s_sethalt" , (ins i32imm:$simm16), "$simm16",1677 [(int_amdgcn_s_sethalt timm:$simm16)]>;1678def S_SETKILL : SOPP_Pseudo <"s_setkill" , (ins i16imm:$simm16), "$simm16"> {1679 let SubtargetPredicate = isNotGFX1250Plus;1680}1681 1682// On SI the documentation says sleep for approximately 64 * low 21683// bits, consistent with the reported maximum of 448. On VI the1684// maximum reported is 960 cycles, so 960 / 64 = 15 max, so is the1685// maximum really 15 on VI?1686def S_SLEEP : SOPP_Pseudo <"s_sleep", (ins i32imm:$simm16),1687 "$simm16", [(int_amdgcn_s_sleep timm:$simm16)]> {1688}1689 1690def S_SLEEP_VAR : SOP1_0_32 <"s_sleep_var", [(int_amdgcn_s_sleep_var SSrc_b32:$src0)]> {1691 let hasSideEffects = 1;1692}1693 1694def S_SETPRIO : SOPP_Pseudo <"s_setprio", (ins i16imm:$simm16), "$simm16",1695 [(int_amdgcn_s_setprio timm:$simm16)]> {1696}1697 1698def S_SETPRIO_INC_WG : SOPP_Pseudo <"s_setprio_inc_wg", (ins i16imm:$simm16), "$simm16",1699 [(int_amdgcn_s_setprio_inc_wg timm:$simm16)]> {1700 let SubtargetPredicate = HasSetPrioIncWgInst;1701}1702 1703def S_GET_SHADER_CYCLES_U64 : SOP1_64_0 <"s_get_shader_cycles_u64",1704 [(set i64:$sdst, (readcyclecounter))]> {1705 let SubtargetPredicate = HasSGetShaderCyclesInst;1706 let hasSideEffects = 1;1707}1708 1709let Uses = [EXEC, M0] in {1710def S_SENDMSG : SOPP_Pseudo <"s_sendmsg" , (ins SendMsg:$simm16), "$simm16",1711 [(int_amdgcn_s_sendmsg (i32 timm:$simm16), M0)]> {1712}1713 1714def S_SENDMSGHALT : SOPP_Pseudo <"s_sendmsghalt" , (ins SendMsg:$simm16), "$simm16",1715 [(int_amdgcn_s_sendmsghalt (i32 timm:$simm16), M0)]> {1716}1717 1718} // End Uses = [EXEC, M0]1719 1720def S_TRAP : SOPP_Pseudo <"s_trap" , (ins i16imm:$simm16), "$simm16"> {1721 let isTrap = 1;1722}1723 1724def S_ICACHE_INV : SOPP_Pseudo <"s_icache_inv", (ins)> {1725 let simm16 = 0;1726 let fixed_imm = 1;1727}1728def S_INCPERFLEVEL : SOPP_Pseudo <"s_incperflevel", (ins i32imm:$simm16), "$simm16",1729 [(int_amdgcn_s_incperflevel timm:$simm16)]> {1730}1731def S_DECPERFLEVEL : SOPP_Pseudo <"s_decperflevel", (ins i32imm:$simm16), "$simm16",1732 [(int_amdgcn_s_decperflevel timm:$simm16)]> {1733}1734 1735let Uses = [M0] in1736def S_TTRACEDATA : SOPP_Pseudo <"s_ttracedata", (ins), "",1737 [(int_amdgcn_s_ttracedata M0)]> {1738 let simm16 = 0;1739 let fixed_imm = 1;1740}1741 1742let SubtargetPredicate = HasVGPRIndexMode in {1743def S_SET_GPR_IDX_OFF : SOPP_Pseudo<"s_set_gpr_idx_off", (ins) > {1744 let simm16 = 0;1745 let fixed_imm = 1;1746 let Defs = [MODE];1747 let Uses = [MODE];1748}1749}1750 1751def S_MONITOR_SLEEP : SOPP_Pseudo <"s_monitor_sleep", (ins i16imm:$simm16), "$simm16",1752 [(int_amdgcn_s_monitor_sleep timm:$simm16)]> {1753 let SubtargetPredicate = isGFX1250Plus;1754}1755 1756} // End hasSideEffects1757 1758let SubtargetPredicate = HasVGPRIndexMode in {1759def S_SET_GPR_IDX_MODE : SOPP_Pseudo<"s_set_gpr_idx_mode", (ins GPRIdxMode:$simm16),1760 "$simm16"> {1761 let Defs = [M0, MODE];1762 let Uses = [MODE];1763}1764}1765 1766let SubtargetPredicate = isGFX10Plus in {1767 def S_INST_PREFETCH :1768 SOPP_Pseudo<"s_inst_prefetch", (ins s16imm:$simm16), "$simm16">;1769 def S_CLAUSE :1770 SOPP_Pseudo<"s_clause", (ins s16imm:$simm16), "$simm16">;1771 def S_WAIT_IDLE :1772 SOPP_Pseudo <"s_wait_idle", (ins)> {1773 let simm16 = 0;1774 let fixed_imm = 1;1775 }1776 def S_WAITCNT_DEPCTR :1777 SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtr:$simm16), "$simm16">;1778 1779 let hasSideEffects = 0, Uses = [MODE], Defs = [MODE] in {1780 def S_ROUND_MODE :1781 SOPP_Pseudo<"s_round_mode", (ins s16imm:$simm16), "$simm16">;1782 def S_DENORM_MODE :1783 SOPP_Pseudo<"s_denorm_mode", (ins i32imm:$simm16), "$simm16",1784 [(SIdenorm_mode (i32 timm:$simm16))]>;1785 }1786 1787 let hasSideEffects = 1 in1788 def S_TTRACEDATA_IMM :1789 SOPP_Pseudo<"s_ttracedata_imm", (ins s16imm:$simm16), "$simm16",1790 [(int_amdgcn_s_ttracedata_imm timm:$simm16)]>;1791} // End SubtargetPredicate = isGFX10Plus1792 1793let SubtargetPredicate = isGFX11Plus in {1794let OtherPredicates = [HasExportInsts] in1795 def S_WAIT_EVENT : SOPP_Pseudo<"s_wait_event", (ins s16imm:$simm16),1796 "$simm16"> {1797 let hasSideEffects = 1;1798 }1799 def S_DELAY_ALU : SOPP_Pseudo<"s_delay_alu", (ins SDelayALU:$simm16),1800 "$simm16">;1801} // End SubtargetPredicate = isGFX11Plus1802 1803let SubtargetPredicate = isGFX12Plus, hasSideEffects = 1 in {1804 def S_WAIT_LOADCNT :1805 SOPP_Pseudo<"s_wait_loadcnt", (ins s16imm:$simm16), "$simm16",1806 [(int_amdgcn_s_wait_loadcnt timm:$simm16)]>;1807 def S_WAIT_LOADCNT_DSCNT :1808 SOPP_Pseudo<"s_wait_loadcnt_dscnt", (ins s16imm:$simm16), "$simm16">;1809 def S_WAIT_STORECNT :1810 SOPP_Pseudo<"s_wait_storecnt", (ins s16imm:$simm16), "$simm16",1811 [(int_amdgcn_s_wait_storecnt timm:$simm16)]>;1812 def S_WAIT_STORECNT_DSCNT :1813 SOPP_Pseudo<"s_wait_storecnt_dscnt", (ins s16imm:$simm16), "$simm16">;1814let OtherPredicates = [HasImageInsts] in {1815 def S_WAIT_SAMPLECNT :1816 SOPP_Pseudo<"s_wait_samplecnt", (ins s16imm:$simm16), "$simm16",1817 [(int_amdgcn_s_wait_samplecnt timm:$simm16)]>;1818 def S_WAIT_BVHCNT :1819 SOPP_Pseudo<"s_wait_bvhcnt", (ins s16imm:$simm16), "$simm16",1820 [(int_amdgcn_s_wait_bvhcnt timm:$simm16)]>;1821} // End OtherPredicates = [HasImageInsts].1822let OtherPredicates = [HasExportInsts] in1823 def S_WAIT_EXPCNT :1824 SOPP_Pseudo<"s_wait_expcnt", (ins s16imm:$simm16), "$simm16",1825 [(int_amdgcn_s_wait_expcnt timm:$simm16)]>;1826 def S_WAIT_DSCNT :1827 SOPP_Pseudo<"s_wait_dscnt", (ins s16imm:$simm16), "$simm16",1828 [(int_amdgcn_s_wait_dscnt timm:$simm16)]>;1829 def S_WAIT_KMCNT :1830 SOPP_Pseudo<"s_wait_kmcnt", (ins s16imm:$simm16), "$simm16",1831 [(int_amdgcn_s_wait_kmcnt timm:$simm16)]>;1832} // End SubtargetPredicate = isGFX12Plus, hasSideEffects = 11833 1834let SubtargetPredicate = isGFX1250Plus, hasSideEffects = 1 in {1835 def S_WAIT_ASYNCCNT :1836 SOPP_Pseudo<"s_wait_asynccnt", (ins s16imm:$simm16), "$simm16",1837 [(int_amdgcn_s_wait_asynccnt timm:$simm16)]> {1838 let mayLoad = 1;1839 let mayStore = 1;1840 let maybeAtomic = 0;1841 let Uses = [ASYNCcnt];1842 let Defs = [ASYNCcnt];1843 }1844 def S_WAIT_TENSORCNT :1845 SOPP_Pseudo<"s_wait_tensorcnt", (ins s16imm:$simm16), "$simm16",1846 [(int_amdgcn_s_wait_tensorcnt timm:$simm16)]> {1847 let mayLoad = 1;1848 let mayStore = 1;1849 let maybeAtomic = 0;1850 let Uses = [TENSORcnt];1851 let Defs = [TENSORcnt];1852 }1853} // End SubtargetPredicate = isGFX1250Plus, hasSideEffects = 11854 1855let SubtargetPredicate = HasWaitXcnt, hasSideEffects = 1 in {1856 def S_WAIT_XCNT :1857 SOPP_Pseudo<"s_wait_xcnt", (ins s16imm:$simm16), "$simm16">;1858} // End SubtargetPredicate = hasWaitXcnt, hasSideEffects = 11859 1860let SubtargetPredicate = Has1024AddressableVGPRs in {1861 def S_SET_VGPR_MSB : SOPP_Pseudo<"s_set_vgpr_msb" , (ins i16imm:$simm16), "$simm16"> {1862 let hasSideEffects = 1;1863 let Defs = [MODE];1864 }1865}1866 1867//===----------------------------------------------------------------------===//1868// SOP1 Patterns1869//===----------------------------------------------------------------------===//1870 1871def : GCNPat <1872 (AMDGPUendpgm),1873 (S_ENDPGM (i16 0))1874>;1875 1876def : GCNPat <1877 (int_amdgcn_endpgm),1878 (S_ENDPGM (i16 0))1879>;1880 1881def : GCNPat <1882 (i64 (UniformUnaryFrag<ctpop> i64:$src)),1883 (i64 (REG_SEQUENCE SReg_64,1884 (i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0,1885 (S_MOV_B32 (i32 0)), sub1))1886>;1887 1888def : GCNPat <1889 (i32 (UniformBinFrag<smax> i32:$x, (i32 (ineg i32:$x)))),1890 (S_ABS_I32 SReg_32:$x)1891>;1892 1893def : GCNPat <1894 (i16 imm:$imm),1895 (S_MOV_B32 imm:$imm)1896>;1897 1898def : GCNPat <1899 (v2i32 (UniformBinFrag<and> v2i32:$x, v2i32:$y)),1900 (S_AND_B64 SReg_64:$x, SReg_64:$y)1901>;1902 1903def : GCNPat <1904 (v2i32 (UniformBinFrag<or> v2i32:$x, v2i32:$y)),1905 (S_OR_B64 SReg_64:$x, SReg_64:$y)1906>;1907 1908def : GCNPat <1909 (v2i32 (UniformBinFrag<xor> v2i32:$x, v2i32:$y)),1910 (S_XOR_B64 SReg_64:$x, SReg_64:$y)1911>;1912 1913// Same as a 32-bit inreg1914def : GCNPat<1915 (i32 (UniformUnaryFrag<sext> i16:$src)),1916 (S_SEXT_I32_I16 $src)1917>;1918 1919let SubtargetPredicate = isNotGFX12Plus in1920 def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 0))>;1921let SubtargetPredicate = isGFX12Plus in1922 def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 2))>;1923 1924// The first 10 bits of the mode register are the core FP mode on all1925// subtargets.1926//1927// The high bits include additional fields, intermixed with some1928// non-floating point environment information. We extract the full1929// register and clear non-relevant bits.1930//1931// EXCP_EN covers floating point exceptions, but also some other1932// non-FP exceptions.1933//1934// Bits 12-18 cover the relevant exception mask on all subtargets.1935//1936// FIXME: Bit 18 is int_div0, should this be in the FP environment? I1937// think the only source is v_rcp_iflag_i32.1938//1939// On GFX9+:1940// Bit 23 is the additional FP16_OVFL mode.1941//1942// Bits 19, 20, and 21 cover non-FP exceptions and differ between1943// gfx9/10/11, so we ignore them here.1944 1945// TODO: Would it be cheaper to emit multiple s_getreg_b32 calls for1946// the ranges and combine the results?1947 1948defvar fp_round_mask = !add(!shl(1, 4), -1);1949defvar fp_denorm_mask = !shl(!add(!shl(1, 4), -1), 4);1950defvar dx10_clamp_mask = !shl(1, 8);1951defvar ieee_mode_mask = !shl(1, 9);1952 1953// Covers fp_round, fp_denorm, dx10_clamp, and IEEE bit.1954defvar fpmode_mask =1955 !or(fp_round_mask, fp_denorm_mask, dx10_clamp_mask, ieee_mode_mask);1956 1957defvar fp_excp_en_mask = !shl(!add(!shl(1, 7), -1), 12);1958defvar fp16_ovfl = !shl(1, 23);1959defvar fpmode_mask_gfx6plus = !or(fpmode_mask, fp_excp_en_mask);1960defvar fpmode_mask_gfx9plus = !or(fpmode_mask_gfx6plus, fp16_ovfl);1961 1962class GetFPModePat<int fpmode_mask> : GCNPat<1963 (i32 get_fpmode),1964 (S_AND_B32 (i32 fpmode_mask),1965 (S_GETREG_B32 getHwRegImm<1966 HWREG.MODE, 0,1967 !add(!logtwo(fpmode_mask), 1)>.ret))1968>;1969 1970// TODO: Might be worth moving to custom lowering so the and is1971// exposed to demanded bits optimizations. Most users probably only1972// care about the rounding or denorm mode bits. We also can reduce the1973// demanded read from the getreg immediate.1974let SubtargetPredicate = isGFX9Plus in {1975// Last bit = FP16_OVFL1976def : GetFPModePat<fpmode_mask_gfx9plus>;1977}1978 1979// Last bit = EXCP_EN.int_div01980let SubtargetPredicate = isNotGFX9Plus in {1981def : GetFPModePat<fpmode_mask_gfx6plus>;1982}1983 1984let SubtargetPredicate = isGFX9GFX10 in1985def : GCNPat<1986 (int_amdgcn_pops_exiting_wave_id),1987 (S_MOV_B32_sideeffects (i32 SRC_POPS_EXITING_WAVE_ID))1988>;1989 1990//===----------------------------------------------------------------------===//1991// SOP2 Patterns1992//===----------------------------------------------------------------------===//1993 1994def UniformSelect : PatFrag<1995 (ops node:$src0, node:$src1),1996 (select SCC, $src0, $src1),1997 [{ return !N->isDivergent(); }]1998>;1999 2000let AddedComplexity = 20 in {2001 def : GCNPat<2002 (i32 (UniformSelect i32:$src0, i32:$src1)),2003 (S_CSELECT_B32 SSrc_b32:$src0, SSrc_b32:$src1)2004 >;2005 2006 // TODO: The predicate should not be necessary, but enabling this pattern for2007 // all subtargets generates worse code in some cases.2008 let OtherPredicates = [HasPseudoScalarTrans] in2009 def : GCNPat<2010 (f32 (UniformSelect f32:$src0, f32:$src1)),2011 (S_CSELECT_B32 SSrc_b32:$src0, SSrc_b32:$src1)2012 >;2013}2014 2015// V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector2016// case, the sgpr-copies pass will fix this to use the vector version.2017def : GCNPat <2018 (i32 (addc i32:$src0, i32:$src1)),2019 (S_ADD_U32 $src0, $src1)2020>;2021 2022// FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that2023// REG_SEQUENCE patterns don't support instructions with multiple2024// outputs.2025def : GCNPat<2026 (i64 (UniformUnaryFrag<zext> i16:$src)),2027 (REG_SEQUENCE SReg_64,2028 (i32 (COPY_TO_REGCLASS (S_AND_B32 $src, (S_MOV_B32 (i32 0xffff))), SGPR_32)), sub0,2029 (S_MOV_B32 (i32 0)), sub1)2030>;2031 2032def : GCNPat <2033 (i64 (UniformUnaryFrag<sext> i16:$src)),2034 (REG_SEQUENCE SReg_64, (i32 (S_SEXT_I32_I16 $src)), sub0,2035 (i32 (COPY_TO_REGCLASS (S_ASHR_I32 (i32 (S_SEXT_I32_I16 $src)), (S_MOV_B32 (i32 31))), SGPR_32)), sub1)2036>;2037 2038def : GCNPat<2039 (i32 (UniformUnaryFrag<zext> i16:$src)),2040 (S_AND_B32 (S_MOV_B32 (i32 0xffff)), $src)2041>;2042 2043class ScalarNot2Pat<Instruction inst, SDPatternOperator op, ValueType vt,2044 SDPatternOperator notnode = !if(vt.isVector, vnot, not)> : GCNPat<2045 (UniformBinFrag<op> vt:$src0, (notnode vt:$src1)),2046 (inst getSOPSrcForVT<vt>.ret:$src0, getSOPSrcForVT<vt>.ret:$src1)2047>;2048 2049// Match these for some more types2050// TODO: i12051def : ScalarNot2Pat<S_ANDN2_B32, and, i16>;2052def : ScalarNot2Pat<S_ANDN2_B32, and, v2i16>;2053def : ScalarNot2Pat<S_ANDN2_B64, and, v4i16>;2054def : ScalarNot2Pat<S_ANDN2_B64, and, v2i32>;2055 2056def : ScalarNot2Pat<S_ORN2_B32, or, i16>;2057def : ScalarNot2Pat<S_ORN2_B32, or, v2i16>;2058def : ScalarNot2Pat<S_ORN2_B64, or, v4i16>;2059def : ScalarNot2Pat<S_ORN2_B64, or, v2i32>;2060 2061let WaveSizePredicate = isWave32 in {2062def : GCNPat<2063 (i1 (not (or_oneuse i1:$src0, i1:$src1))),2064 (S_NOR_B32 i1:$src0, i1:$src1)2065>;2066}2067 2068let WaveSizePredicate = isWave64 in {2069def : GCNPat<2070 (i1 (not (or_oneuse i1:$src0, i1:$src1))),2071 (S_NOR_B64 i1:$src0, i1:$src1)2072>;2073}2074 2075//===----------------------------------------------------------------------===//2076// Target-specific instruction encodings.2077//===----------------------------------------------------------------------===//2078 2079class Select<GFXGen Gen, string opName> : SIMCInstr<opName, Gen.Subtarget> {2080 Predicate AssemblerPredicate = Gen.AssemblerPredicate;2081 string DecoderNamespace = Gen.DecoderNamespace;2082}2083 2084class Select_vi<string opName> : SIMCInstr<opName, SIEncodingFamily.VI> {2085 Predicate AssemblerPredicate = isGFX8GFX9;2086 string DecoderNamespace = "GFX8";2087}2088 2089class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> {2090 Predicate AssemblerPredicate = isGFX6GFX7;2091 string DecoderNamespace = "GFX6GFX7";2092}2093 2094//===----------------------------------------------------------------------===//2095// SOP1 - GFX11, GFX122096//===----------------------------------------------------------------------===//2097 2098multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {2099 defvar ps = !cast<SOP1_Pseudo>(NAME);2100 def _gfx11 : SOP1_Real<op, ps, name>,2101 Select<GFX11Gen, ps.PseudoInstr>;2102 if !ne(ps.Mnemonic, name) then2103 def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {2104 let AssemblerPredicate = isGFX11Only;2105 }2106}2107 2108multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {2109 defvar ps = !cast<SOP1_Pseudo>(NAME);2110 def _gfx12 : SOP1_Real<op, ps, name>,2111 Select<GFX12Gen, ps.PseudoInstr>;2112 if !ne(ps.Mnemonic, name) then2113 def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {2114 let AssemblerPredicate = isGFX12Plus;2115 }2116}2117 2118multiclass SOP1_M0_Real_gfx12<bits<8> op> {2119 def _gfx12 : SOP1_Real<op, !cast<SOP1_Pseudo>(NAME)>,2120 Select<GFX12Gen, !cast<SOP1_Pseudo>(NAME).PseudoInstr> {2121 let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M02122 }2123}2124 2125multiclass SOP1_IMM_Real_gfx12<bits<8> op> {2126 defvar ps = !cast<SOP1_Pseudo>(NAME);2127 def _gfx12 : SOP1_Real<op, ps>,2128 Select<GFX12Gen, ps.PseudoInstr>;2129}2130 2131multiclass SOP1_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)> :2132 SOP1_Real_gfx11<op, name>, SOP1_Real_gfx12<op, name>;2133 2134multiclass SOP1_Real_gfx1250<bits<8> op, string name = !tolower(NAME)> {2135 defvar ps = !cast<SOP1_Pseudo>(NAME);2136 def _gfx1250 : SOP1_Real<op, ps, name>,2137 Select<GFX1250Gen, ps.PseudoInstr>;2138 if !ne(ps.Mnemonic, name) then2139 let AssemblerPredicate = isGFX1250Plus in2140 def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;2141}2142 2143defm S_MOV_B32 : SOP1_Real_gfx11_gfx12<0x000>;2144defm S_MOV_B64 : SOP1_Real_gfx11_gfx12<0x001>;2145defm S_CMOV_B32 : SOP1_Real_gfx11_gfx12<0x002>;2146defm S_CMOV_B64 : SOP1_Real_gfx11_gfx12<0x003>;2147defm S_BREV_B32 : SOP1_Real_gfx11_gfx12<0x004>;2148defm S_BREV_B64 : SOP1_Real_gfx11_gfx12<0x005>;2149defm S_FF1_I32_B32 : SOP1_Real_gfx11_gfx12<0x008, "s_ctz_i32_b32">;2150defm S_FF1_I32_B64 : SOP1_Real_gfx11_gfx12<0x009, "s_ctz_i32_b64">;2151defm S_FLBIT_I32_B32 : SOP1_Real_gfx11_gfx12<0x00a, "s_clz_i32_u32">;2152defm S_FLBIT_I32_B64 : SOP1_Real_gfx11_gfx12<0x00b, "s_clz_i32_u64">;2153defm S_FLBIT_I32 : SOP1_Real_gfx11_gfx12<0x00c, "s_cls_i32">;2154defm S_FLBIT_I32_I64 : SOP1_Real_gfx11_gfx12<0x00d, "s_cls_i32_i64">;2155defm S_SEXT_I32_I8 : SOP1_Real_gfx11_gfx12<0x00e>;2156defm S_SEXT_I32_I16 : SOP1_Real_gfx11_gfx12<0x00f>;2157defm S_BITSET0_B32 : SOP1_Real_gfx11_gfx12<0x010>;2158defm S_BITSET0_B64 : SOP1_Real_gfx11_gfx12<0x011>;2159defm S_BITSET1_B32 : SOP1_Real_gfx11_gfx12<0x012>;2160defm S_BITSET1_B64 : SOP1_Real_gfx11_gfx12<0x013>;2161defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx11_gfx12<0x014>;2162defm S_ABS_I32 : SOP1_Real_gfx11_gfx12<0x015>;2163defm S_BCNT0_I32_B32 : SOP1_Real_gfx11_gfx12<0x016>;2164defm S_BCNT0_I32_B64 : SOP1_Real_gfx11_gfx12<0x017>;2165defm S_BCNT1_I32_B32 : SOP1_Real_gfx11_gfx12<0x018>;2166defm S_BCNT1_I32_B64 : SOP1_Real_gfx11_gfx12<0x019>;2167defm S_QUADMASK_B32 : SOP1_Real_gfx11_gfx12<0x01a>;2168defm S_QUADMASK_B64 : SOP1_Real_gfx11_gfx12<0x01b>;2169defm S_WQM_B32 : SOP1_Real_gfx11_gfx12<0x01c>;2170defm S_WQM_B64 : SOP1_Real_gfx11_gfx12<0x01d>;2171defm S_NOT_B32 : SOP1_Real_gfx11_gfx12<0x01e>;2172defm S_NOT_B64 : SOP1_Real_gfx11_gfx12<0x01f>;2173defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x020>;2174defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x021>;2175defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x022>;2176defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x023>;2177defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x024>;2178defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x025>;2179defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x026>;2180defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x027>;2181defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x028>;2182defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x029>;2183defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02a>;2184defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02c, "s_and_not0_saveexec_b32">;2185defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02d, "s_and_not0_saveexec_b64">;2186defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02e, "s_or_not0_saveexec_b32">;2187defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02f, "s_or_not0_saveexec_b64">;2188defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x030, "s_and_not1_saveexec_b32">;2189defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x031, "s_and_not1_saveexec_b64">;2190defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x032, "s_or_not1_saveexec_b32">;2191defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x033, "s_or_not1_saveexec_b64">;2192defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx11_gfx12<0x034, "s_and_not0_wrexec_b32">;2193defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx11_gfx12<0x035, "s_and_not0_wrexec_b64">;2194defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx11_gfx12<0x036, "s_and_not1_wrexec_b32">;2195defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx11_gfx12<0x037, "s_and_not1_wrexec_b64">;2196defm S_MOVRELS_B32 : SOP1_Real_gfx11_gfx12<0x040>;2197defm S_MOVRELS_B64 : SOP1_Real_gfx11_gfx12<0x041>;2198defm S_MOVRELD_B32 : SOP1_Real_gfx11_gfx12<0x042>;2199defm S_MOVRELD_B64 : SOP1_Real_gfx11_gfx12<0x043>;2200defm S_MOVRELSD_2_B32 : SOP1_Real_gfx11_gfx12<0x044>;2201let OtherPredicates = [isNotGFX1250Plus] in {2202defm S_GETPC_B64 : SOP1_Real_gfx11_gfx12<0x047>;2203defm S_SETPC_B64 : SOP1_Real_gfx11_gfx12<0x048>;2204defm S_SWAPPC_B64 : SOP1_Real_gfx11_gfx12<0x049>;2205defm S_RFE_B64 : SOP1_Real_gfx11_gfx12<0x04a>;2206}2207defm S_GETPC_B64 : SOP1_Real_gfx1250<0x047, "s_get_pc_i64">;2208defm S_SETPC_B64 : SOP1_Real_gfx1250<0x048, "s_set_pc_i64">;2209defm S_SWAPPC_B64 : SOP1_Real_gfx1250<0x049, "s_swap_pc_i64">;2210defm S_RFE_B64 : SOP1_Real_gfx1250<0x04a, "s_rfe_i64">;2211defm S_SENDMSG_RTN_B32 : SOP1_Real_gfx11_gfx12<0x04c>;2212defm S_SENDMSG_RTN_B64 : SOP1_Real_gfx11_gfx12<0x04d>;2213defm S_BARRIER_SIGNAL_M0 : SOP1_M0_Real_gfx12<0x04e>;2214defm S_BARRIER_SIGNAL_ISFIRST_M0 : SOP1_M0_Real_gfx12<0x04f>;2215defm S_GET_BARRIER_STATE_M0 : SOP1_M0_Real_gfx12<0x050>;2216defm S_BARRIER_INIT_M0 : SOP1_M0_Real_gfx12<0x051>;2217defm S_BARRIER_JOIN_M0 : SOP1_M0_Real_gfx12<0x052>;2218defm S_BARRIER_SIGNAL_IMM : SOP1_IMM_Real_gfx12<0x04e>;2219defm S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_IMM_Real_gfx12<0x04f>;2220defm S_GET_BARRIER_STATE_IMM : SOP1_IMM_Real_gfx12<0x050>;2221defm S_BARRIER_INIT_IMM : SOP1_IMM_Real_gfx12<0x051>;2222defm S_BARRIER_JOIN_IMM : SOP1_IMM_Real_gfx12<0x052>;2223defm S_ALLOC_VGPR : SOP1_Real_gfx12<0x053>;2224defm S_SLEEP_VAR : SOP1_IMM_Real_gfx12<0x058>;2225 2226// GFX12502227defm S_GET_SHADER_CYCLES_U64 : SOP1_Real_gfx12<0x06>;2228defm S_ADD_PC_I64 : SOP1_Real_gfx12<0x04b>;2229 2230//===----------------------------------------------------------------------===//2231// SOP1 - GFX1150, GFX122232//===----------------------------------------------------------------------===//2233 2234defm S_CEIL_F32 : SOP1_Real_gfx11_gfx12<0x060>;2235defm S_FLOOR_F32 : SOP1_Real_gfx11_gfx12<0x061>;2236defm S_TRUNC_F32 : SOP1_Real_gfx11_gfx12<0x062>;2237defm S_RNDNE_F32 : SOP1_Real_gfx11_gfx12<0x063>;2238defm S_CVT_F32_I32 : SOP1_Real_gfx11_gfx12<0x064>;2239defm S_CVT_F32_U32 : SOP1_Real_gfx11_gfx12<0x065>;2240defm S_CVT_I32_F32 : SOP1_Real_gfx11_gfx12<0x066>;2241defm S_CVT_U32_F32 : SOP1_Real_gfx11_gfx12<0x067>;2242defm S_CVT_F16_F32 : SOP1_Real_gfx11_gfx12<0x068>;2243defm S_CVT_F32_F16 : SOP1_Real_gfx11_gfx12<0x069>;2244defm S_CVT_HI_F32_F16 : SOP1_Real_gfx11_gfx12<0x06a>;2245defm S_CEIL_F16 : SOP1_Real_gfx11_gfx12<0x06b>;2246defm S_FLOOR_F16 : SOP1_Real_gfx11_gfx12<0x06c>;2247defm S_TRUNC_F16 : SOP1_Real_gfx11_gfx12<0x06d>;2248defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12<0x06e>;2249 2250//===----------------------------------------------------------------------===//2251// SOP1 - GFX10.2252//===----------------------------------------------------------------------===//2253 2254multiclass SOP1_Real_gfx10<bits<8> op> {2255 defvar ps = !cast<SOP1_Pseudo>(NAME);2256 def _gfx10 : SOP1_Real<op, ps>,2257 Select<GFX10Gen, ps.PseudoInstr>;2258}2259 2260multiclass SOP1_Real_gfx10_gfx11_gfx12<bits<8> op> :2261 SOP1_Real_gfx10<op>, SOP1_Real_gfx11_gfx12<op>;2262 2263defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x037>;2264defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x038>;2265defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx10<0x039>;2266defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx10<0x03a>;2267defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx10<0x03b>;2268defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03c>;2269defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03d>;2270defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03e>;2271defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03f>;2272defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x040>;2273defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x041>;2274defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x042>;2275defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x043>;2276defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x044>;2277defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x045>;2278defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx10<0x046>;2279defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx10<0x047>;2280defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>;2281 2282//===----------------------------------------------------------------------===//2283// SOP1 - GFX6, GFX7, GFX10, GFX11.2284//===----------------------------------------------------------------------===//2285 2286 2287multiclass SOP1_Real_gfx6_gfx7<bits<8> op> {2288 defvar ps = !cast<SOP1_Pseudo>(NAME);2289 def _gfx6_gfx7 : SOP1_Real<op, ps>,2290 Select_gfx6_gfx7<ps.PseudoInstr>;2291}2292 2293multiclass SOP1_Real_gfx6_gfx7_gfx10<bits<8> op> :2294 SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10<op>;2295 2296multiclass SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op> :2297 SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10_gfx11_gfx12<op>;2298 2299defm S_CBRANCH_JOIN : SOP1_Real_gfx6_gfx7<0x032>;2300 2301defm S_MOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x003>;2302defm S_MOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x004>;2303defm S_CMOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x005>;2304defm S_CMOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x006>;2305defm S_NOT_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x007>;2306defm S_NOT_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x008>;2307defm S_WQM_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x009>;2308defm S_WQM_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00a>;2309defm S_BREV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00b>;2310defm S_BREV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00c>;2311defm S_BCNT0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00d>;2312defm S_BCNT0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00e>;2313defm S_BCNT1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00f>;2314defm S_BCNT1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x010>;2315defm S_FF0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x011>;2316defm S_FF0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x012>;2317defm S_FF1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x013>;2318defm S_FF1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x014>;2319defm S_FLBIT_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x015>;2320defm S_FLBIT_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x016>;2321defm S_FLBIT_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x017>;2322defm S_FLBIT_I32_I64 : SOP1_Real_gfx6_gfx7_gfx10<0x018>;2323defm S_SEXT_I32_I8 : SOP1_Real_gfx6_gfx7_gfx10<0x019>;2324defm S_SEXT_I32_I16 : SOP1_Real_gfx6_gfx7_gfx10<0x01a>;2325defm S_BITSET0_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01b>;2326defm S_BITSET0_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01c>;2327defm S_BITSET1_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01d>;2328defm S_BITSET1_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01e>;2329defm S_GETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01f>;2330defm S_SETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x020>;2331defm S_SWAPPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x021>;2332defm S_RFE_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x022>;2333defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x024>;2334defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x025>;2335defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x026>;2336defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x027>;2337defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x028>;2338defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x029>;2339defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02a>;2340defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02b>;2341defm S_QUADMASK_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02c>;2342defm S_QUADMASK_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02d>;2343defm S_MOVRELS_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02e>;2344defm S_MOVRELS_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02f>;2345defm S_MOVRELD_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x030>;2346defm S_MOVRELD_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x031>;2347defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>;2348 2349//===----------------------------------------------------------------------===//2350// SOP2 - GFX122351//===----------------------------------------------------------------------===//2352 2353multiclass SOP2_Real_gfx12<bits<7> op, string name = !tolower(NAME)> {2354 defvar ps = !cast<SOP2_Pseudo>(NAME);2355 def _gfx12 : SOP2_Real32<op, ps, name>,2356 Select<GFX12Gen, ps.PseudoInstr>;2357 if !ne(ps.Mnemonic, name) then2358 def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {2359 let AssemblerPredicate = isGFX12Plus;2360 }2361}2362 2363defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>;2364defm S_MAXIMUM_F32 : SOP2_Real_gfx12<0x050>;2365defm S_MINIMUM_F16 : SOP2_Real_gfx12<0x051>;2366defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>;2367 2368//===----------------------------------------------------------------------===//2369// SOP2 - GFX11, GFX12.2370//===----------------------------------------------------------------------===//2371 2372multiclass SOP2_Real_gfx11<bits<7> op, string name = !tolower(NAME)> {2373 defvar ps = !cast<SOP2_Pseudo>(NAME);2374 def _gfx11 : SOP2_Real32<op, ps, name>,2375 Select<GFX11Gen, ps.PseudoInstr>;2376 if !ne(ps.Mnemonic, name) then2377 def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {2378 let AssemblerPredicate = isGFX11Only;2379 }2380}2381 2382multiclass SOP2_Real_gfx11_gfx12<bits<7> op, string name = !tolower(NAME)> :2383 SOP2_Real_gfx11<op, name>, SOP2_Real_gfx12<op, name>;2384 2385defm S_ABSDIFF_I32 : SOP2_Real_gfx11_gfx12<0x006>;2386defm S_LSHL_B32 : SOP2_Real_gfx11_gfx12<0x008>;2387defm S_LSHL_B64 : SOP2_Real_gfx11_gfx12<0x009>;2388defm S_LSHR_B32 : SOP2_Real_gfx11_gfx12<0x00a>;2389defm S_LSHR_B64 : SOP2_Real_gfx11_gfx12<0x00b>;2390defm S_ASHR_I32 : SOP2_Real_gfx11_gfx12<0x00c>;2391defm S_ASHR_I64 : SOP2_Real_gfx11_gfx12<0x00d>;2392defm S_LSHL1_ADD_U32 : SOP2_Real_gfx11_gfx12<0x00e>;2393defm S_LSHL2_ADD_U32 : SOP2_Real_gfx11_gfx12<0x00f>;2394defm S_LSHL3_ADD_U32 : SOP2_Real_gfx11_gfx12<0x010>;2395defm S_LSHL4_ADD_U32 : SOP2_Real_gfx11_gfx12<0x011>;2396defm S_MIN_I32 : SOP2_Real_gfx11_gfx12<0x012>;2397defm S_MIN_U32 : SOP2_Real_gfx11_gfx12<0x013>;2398defm S_MAX_I32 : SOP2_Real_gfx11_gfx12<0x014>;2399defm S_MAX_U32 : SOP2_Real_gfx11_gfx12<0x015>;2400defm S_AND_B32 : SOP2_Real_gfx11_gfx12<0x016>;2401defm S_AND_B64 : SOP2_Real_gfx11_gfx12<0x017>;2402defm S_OR_B32 : SOP2_Real_gfx11_gfx12<0x018>;2403defm S_OR_B64 : SOP2_Real_gfx11_gfx12<0x019>;2404defm S_XOR_B32 : SOP2_Real_gfx11_gfx12<0x01a>;2405defm S_XOR_B64 : SOP2_Real_gfx11_gfx12<0x01b>;2406defm S_NAND_B32 : SOP2_Real_gfx11_gfx12<0x01c>;2407defm S_NAND_B64 : SOP2_Real_gfx11_gfx12<0x01d>;2408defm S_NOR_B32 : SOP2_Real_gfx11_gfx12<0x01e>;2409defm S_NOR_B64 : SOP2_Real_gfx11_gfx12<0x01f>;2410defm S_XNOR_B32 : SOP2_Real_gfx11_gfx12<0x020>;2411defm S_XNOR_B64 : SOP2_Real_gfx11_gfx12<0x021>;2412defm S_ANDN2_B32 : SOP2_Real_gfx11_gfx12<0x022, "s_and_not1_b32">;2413defm S_ANDN2_B64 : SOP2_Real_gfx11_gfx12<0x023, "s_and_not1_b64">;2414defm S_ORN2_B32 : SOP2_Real_gfx11_gfx12<0x024, "s_or_not1_b32">;2415defm S_ORN2_B64 : SOP2_Real_gfx11_gfx12<0x025, "s_or_not1_b64">;2416defm S_BFE_U32 : SOP2_Real_gfx11_gfx12<0x026>;2417defm S_BFE_I32 : SOP2_Real_gfx11_gfx12<0x027>;2418defm S_BFE_U64 : SOP2_Real_gfx11_gfx12<0x028>;2419defm S_BFE_I64 : SOP2_Real_gfx11_gfx12<0x029>;2420defm S_BFM_B32 : SOP2_Real_gfx11_gfx12<0x02a>;2421defm S_BFM_B64 : SOP2_Real_gfx11_gfx12<0x02b>;2422defm S_MUL_I32 : SOP2_Real_gfx11_gfx12<0x02c>;2423defm S_MUL_HI_U32 : SOP2_Real_gfx11_gfx12<0x02d>;2424defm S_MUL_HI_I32 : SOP2_Real_gfx11_gfx12<0x02e>;2425defm S_CSELECT_B32 : SOP2_Real_gfx11_gfx12<0x030>;2426defm S_CSELECT_B64 : SOP2_Real_gfx11_gfx12<0x031>;2427defm S_PACK_HL_B32_B16 : SOP2_Real_gfx11_gfx12<0x035>;2428defm S_ADD_U64 : SOP2_Real_gfx12<0x053, "s_add_nc_u64">;2429defm S_SUB_U64 : SOP2_Real_gfx12<0x054, "s_sub_nc_u64">;2430defm S_MUL_U64 : SOP2_Real_gfx12<0x055>;2431 2432//===----------------------------------------------------------------------===//2433// SOP2 - GFX1150, GFX122434//===----------------------------------------------------------------------===//2435 2436multiclass SOP2_Real_FMAK_gfx12<bits<7> op> {2437 def _gfx12 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,2438 Select<GFX12Gen, !cast<SOP2_Pseudo>(NAME).PseudoInstr>;2439}2440 2441multiclass SOP2_Real_FMAK_gfx11<bits<7> op> {2442 def _gfx11 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,2443 Select<GFX11Gen, !cast<SOP2_Pseudo>(NAME).PseudoInstr>;2444}2445 2446multiclass SOP2_Real_FMAK_gfx11_gfx12<bits<7> op> :2447 SOP2_Real_FMAK_gfx11<op>, SOP2_Real_FMAK_gfx12<op>;2448 2449defm S_ADD_F32 : SOP2_Real_gfx11_gfx12<0x040>;2450defm S_SUB_F32 : SOP2_Real_gfx11_gfx12<0x041>;2451defm S_MUL_F32 : SOP2_Real_gfx11_gfx12<0x044>;2452defm S_FMAAK_F32 : SOP2_Real_FMAK_gfx11_gfx12<0x045>;2453defm S_FMAMK_F32 : SOP2_Real_FMAK_gfx11_gfx12<0x046>;2454defm S_FMAC_F32 : SOP2_Real_gfx11_gfx12<0x047>;2455defm S_CVT_PK_RTZ_F16_F32 : SOP2_Real_gfx11_gfx12<0x048>;2456defm S_ADD_F16 : SOP2_Real_gfx11_gfx12<0x049>;2457defm S_SUB_F16 : SOP2_Real_gfx11_gfx12<0x04a>;2458defm S_MUL_F16 : SOP2_Real_gfx11_gfx12<0x04d>;2459defm S_FMAC_F16 : SOP2_Real_gfx11_gfx12<0x04e>;2460 2461//===----------------------------------------------------------------------===//2462// SOP2 - GFX11502463//===----------------------------------------------------------------------===//2464 2465multiclass SOP2_Real_gfx11_Renamed_gfx12<bits<7> op, string gfx12_name> :2466 SOP2_Real_gfx11<op>, SOP2_Real_gfx12<op, gfx12_name>;2467 2468defm S_MIN_F32 : SOP2_Real_gfx11_Renamed_gfx12<0x042, "s_min_num_f32">;2469defm S_MAX_F32 : SOP2_Real_gfx11_Renamed_gfx12<0x043, "s_max_num_f32">;2470defm S_MIN_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04b, "s_min_num_f16">;2471defm S_MAX_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04c, "s_max_num_f16">;2472 2473//===----------------------------------------------------------------------===//2474// SOP2 - GFX10.2475//===----------------------------------------------------------------------===//2476 2477multiclass SOP2_Real_gfx10<bits<7> op> {2478 defvar ps = !cast<SOP2_Pseudo>(NAME);2479 def _gfx10 : SOP2_Real32<op, ps>,2480 Select<GFX10Gen, ps.PseudoInstr>;2481}2482 2483multiclass SOP2_Real_gfx10_gfx11_gfx12<bits<7> op> :2484 SOP2_Real_gfx10<op>, SOP2_Real_gfx11_gfx12<op>;2485 2486defm S_LSHL1_ADD_U32 : SOP2_Real_gfx10<0x02e>;2487defm S_LSHL2_ADD_U32 : SOP2_Real_gfx10<0x02f>;2488defm S_LSHL3_ADD_U32 : SOP2_Real_gfx10<0x030>;2489defm S_LSHL4_ADD_U32 : SOP2_Real_gfx10<0x031>;2490defm S_PACK_LL_B32_B16 : SOP2_Real_gfx10_gfx11_gfx12<0x032>;2491defm S_PACK_LH_B32_B16 : SOP2_Real_gfx10_gfx11_gfx12<0x033>;2492defm S_PACK_HH_B32_B16 : SOP2_Real_gfx10_gfx11_gfx12<0x034>;2493defm S_MUL_HI_U32 : SOP2_Real_gfx10<0x035>;2494defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>;2495 2496//===----------------------------------------------------------------------===//2497// SOP2 - GFX6, GFX7.2498//===----------------------------------------------------------------------===//2499 2500multiclass SOP2_Real_gfx6_gfx7<bits<7> op> {2501 defvar ps = !cast<SOP2_Pseudo>(NAME);2502 def _gfx6_gfx7 : SOP2_Real32<op, ps>,2503 Select_gfx6_gfx7<ps.PseudoInstr>;2504}2505 2506multiclass SOP2_Real_gfx6_gfx7_gfx10<bits<7> op> :2507 SOP2_Real_gfx6_gfx7<op>, SOP2_Real_gfx10<op>;2508 2509multiclass SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<bits<7> op, string gfx12_name> :2510 SOP2_Real_gfx6_gfx7<op>, SOP2_Real_gfx10<op>, SOP2_Real_gfx11<op>,2511 SOP2_Real_gfx12<op, gfx12_name>;2512 2513defm S_CBRANCH_G_FORK : SOP2_Real_gfx6_gfx7<0x02b>;2514 2515defm S_ADD_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x000, "s_add_co_u32">;2516defm S_SUB_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x001, "s_sub_co_u32">;2517defm S_ADD_I32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x002, "s_add_co_i32">;2518defm S_SUB_I32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x003, "s_sub_co_i32">;2519defm S_ADDC_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x004, "s_add_co_ci_u32">;2520defm S_SUBB_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x005, "s_sub_co_ci_u32">;2521defm S_MIN_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x006>;2522defm S_MIN_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x007>;2523defm S_MAX_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x008>;2524defm S_MAX_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x009>;2525defm S_CSELECT_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00a>;2526defm S_CSELECT_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00b>;2527defm S_AND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00e>;2528defm S_AND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00f>;2529defm S_OR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x010>;2530defm S_OR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x011>;2531defm S_XOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x012>;2532defm S_XOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x013>;2533defm S_ANDN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x014>;2534defm S_ANDN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x015>;2535defm S_ORN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x016>;2536defm S_ORN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x017>;2537defm S_NAND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x018>;2538defm S_NAND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x019>;2539defm S_NOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01a>;2540defm S_NOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01b>;2541defm S_XNOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01c>;2542defm S_XNOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01d>;2543defm S_LSHL_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01e>;2544defm S_LSHL_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01f>;2545defm S_LSHR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x020>;2546defm S_LSHR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x021>;2547defm S_ASHR_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x022>;2548defm S_ASHR_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x023>;2549defm S_BFM_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x024>;2550defm S_BFM_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x025>;2551defm S_MUL_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x026>;2552defm S_BFE_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x027>;2553defm S_BFE_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x028>;2554defm S_BFE_U64 : SOP2_Real_gfx6_gfx7_gfx10<0x029>;2555defm S_BFE_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x02a>;2556defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>;2557 2558//===----------------------------------------------------------------------===//2559// SOPK - GFX11, GFX12.2560//===----------------------------------------------------------------------===//2561 2562multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> {2563 defvar ps = !cast<SOPK_Pseudo>(NAME);2564 def _gfx12 : SOPK_Real32<op, ps, name>,2565 Select<GFX12Gen, ps.PseudoInstr>;2566 if !ne(ps.Mnemonic, name) then2567 def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {2568 let AssemblerPredicate = isGFX12Plus;2569 }2570}2571 2572multiclass SOPK_Real32_gfx11<bits<5> op> {2573 def _gfx11 : SOPK_Real32<op, !cast<SOPK_Pseudo>(NAME)>,2574 Select<GFX11Gen, !cast<SOPK_Pseudo>(NAME).PseudoInstr>;2575}2576 2577multiclass SOPK_Real64_gfx12<bits<5> op> {2578 def _gfx12 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,2579 Select<GFX12Gen, !cast<SOPK_Pseudo>(NAME).PseudoInstr>;2580}2581 2582multiclass SOPK_Real64_gfx11<bits<5> op> {2583 def _gfx11 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,2584 Select<GFX11Gen, !cast<SOPK_Pseudo>(NAME).PseudoInstr>;2585}2586 2587multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> :2588 SOPK_Real32_gfx11<op>, SOPK_Real32_gfx12<op>;2589 2590multiclass SOPK_Real64_gfx11_gfx12<bits<5> op> :2591 SOPK_Real64_gfx11<op>, SOPK_Real64_gfx12<op>;2592 2593multiclass SOPK_Real32_gfx1250<bits<5> op, string name = !tolower(NAME)> {2594 defvar ps = !cast<SOPK_Pseudo>(NAME);2595 def _gfx1250 : SOPK_Real32<op, ps, name>,2596 Select<GFX1250Gen, ps.PseudoInstr>;2597 if !ne(ps.Mnemonic, name) then2598 let AssemblerPredicate = isGFX1250Plus in2599 def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;2600}2601 2602defm S_GETREG_B32 : SOPK_Real32_gfx11_gfx12<0x011>;2603defm S_SETREG_B32 : SOPK_Real32_gfx11_gfx12<0x012>;2604defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11_gfx12<0x013>;2605let OtherPredicates = [isNotGFX1250Plus] in2606defm S_CALL_B64 : SOPK_Real32_gfx11_gfx12<0x014>;2607defm S_CALL_B64 : SOPK_Real32_gfx1250<0x014, "s_call_i64">;2608defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx11<0x016>;2609defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx11<0x017>;2610defm S_WAITCNT_VSCNT : SOPK_Real32_gfx11<0x018>;2611defm S_WAITCNT_VMCNT : SOPK_Real32_gfx11<0x019>;2612defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx11<0x01a>;2613defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>;2614 2615//===----------------------------------------------------------------------===//2616// SOPK - GFX10.2617//===----------------------------------------------------------------------===//2618 2619multiclass SOPK_Real32_gfx10<bits<5> op> {2620 defvar ps = !cast<SOPK_Pseudo>(NAME);2621 def _gfx10 : SOPK_Real32<op, ps>,2622 Select<GFX10Gen, ps.PseudoInstr>;2623}2624 2625multiclass SOPK_Real64_gfx10<bits<5> op> {2626 defvar ps = !cast<SOPK_Pseudo>(NAME);2627 def _gfx10 : SOPK_Real64<op, ps>,2628 Select<GFX10Gen, ps.PseudoInstr>;2629}2630 2631multiclass SOPK_Real32_gfx10_gfx11<bits<5> op> :2632 SOPK_Real32_gfx10<op>, SOPK_Real32_gfx11<op>;2633 2634multiclass SOPK_Real32_gfx10_gfx11_gfx12<bits<5> op> :2635 SOPK_Real32_gfx10<op>, SOPK_Real32_gfx11_gfx12<op>;2636 2637defm S_VERSION : SOPK_Real32_gfx10_gfx11_gfx12<0x001>;2638defm S_CALL_B64 : SOPK_Real32_gfx10<0x016>;2639defm S_WAITCNT_VSCNT : SOPK_Real32_gfx10<0x017>;2640defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>;2641defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx10<0x019>;2642defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx10<0x01a>;2643defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx10<0x01b>;2644defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>;2645 2646//===----------------------------------------------------------------------===//2647// SOPK - GFX6, GFX7.2648//===----------------------------------------------------------------------===//2649 2650multiclass SOPK_Real32_gfx6_gfx7<bits<5> op> {2651 defvar ps = !cast<SOPK_Pseudo>(NAME);2652 def _gfx6_gfx7 : SOPK_Real32<op, ps>,2653 Select_gfx6_gfx7<ps.PseudoInstr>;2654}2655 2656multiclass SOPK_Real64_gfx6_gfx7<bits<5> op> {2657 defvar ps = !cast<SOPK_Pseudo>(NAME);2658 def _gfx6_gfx7 : SOPK_Real64<op, ps>,2659 Select_gfx6_gfx7<ps.PseudoInstr>;2660}2661 2662multiclass SOPK_Real32_gfx6_gfx7_gfx10<bits<5> op> :2663 SOPK_Real32_gfx6_gfx7<op>, SOPK_Real32_gfx10<op>;2664 2665multiclass SOPK_Real64_gfx6_gfx7_gfx10<bits<5> op> :2666 SOPK_Real64_gfx6_gfx7<op>, SOPK_Real64_gfx10<op>;2667 2668multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11<bits<5> op> :2669 SOPK_Real32_gfx6_gfx7<op>, SOPK_Real32_gfx10_gfx11<op>;2670 2671multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<bits<5> op> :2672 SOPK_Real32_gfx6_gfx7<op>, SOPK_Real32_gfx10_gfx11_gfx12<op>;2673 2674multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<bits<5> op, string gfx12_name> :2675 SOPK_Real32_gfx6_gfx7<op>, SOPK_Real32_gfx10<op>, SOPK_Real32_gfx11<op>,2676 SOPK_Real32_gfx12<op, gfx12_name>;2677 2678defm S_CBRANCH_I_FORK : SOPK_Real32_gfx6_gfx7<0x011>;2679 2680defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x000>;2681defm S_CMOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x002>;2682defm S_CMPK_EQ_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x003>;2683defm S_CMPK_LG_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x004>;2684defm S_CMPK_GT_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x005>;2685defm S_CMPK_GE_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x006>;2686defm S_CMPK_LT_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x007>;2687defm S_CMPK_LE_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x008>;2688defm S_CMPK_EQ_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x009>;2689defm S_CMPK_LG_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00a>;2690defm S_CMPK_GT_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00b>;2691defm S_CMPK_GE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00c>;2692defm S_CMPK_LT_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00d>;2693defm S_CMPK_LE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00e>;2694defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x00f, "s_addk_co_i32">;2695defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x010>;2696defm S_GETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x012>;2697defm S_SETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x013>;2698defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>;2699 2700//===----------------------------------------------------------------------===//2701// SOPP - GFX12 only.2702//===----------------------------------------------------------------------===//2703 2704multiclass SOPP_Real_32_gfx12<bits<7> op, string name = !tolower(NAME)> {2705 defvar ps = !cast<SOPP_Pseudo>(NAME);2706 def _gfx12 : SOPP_Real_32<op, ps, name>,2707 Select<GFX12Gen, ps.PseudoInstr>;2708 if !ne(ps.Mnemonic, name) then2709 def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {2710 let AssemblerPredicate = isGFX12Plus;2711 }2712}2713 2714defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>;2715defm S_BARRIER_LEAVE : SOPP_Real_32_gfx12<0x015>;2716defm S_WAIT_LOADCNT : SOPP_Real_32_gfx12<0x040>;2717defm S_WAIT_STORECNT : SOPP_Real_32_gfx12<0x041>;2718defm S_WAIT_SAMPLECNT : SOPP_Real_32_gfx12<0x042>;2719defm S_WAIT_BVHCNT : SOPP_Real_32_gfx12<0x043>;2720defm S_WAIT_EXPCNT : SOPP_Real_32_gfx12<0x044>;2721defm S_WAIT_DSCNT : SOPP_Real_32_gfx12<0x046>;2722defm S_WAIT_KMCNT : SOPP_Real_32_gfx12<0x047>;2723defm S_WAIT_LOADCNT_DSCNT : SOPP_Real_32_gfx12<0x048>;2724defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>;2725 2726//===----------------------------------------------------------------------===//2727// SOPP - GFX1250 only.2728//===----------------------------------------------------------------------===//2729defm S_SET_VGPR_MSB : SOPP_Real_32_gfx12<0x006>;2730defm S_SETPRIO_INC_WG : SOPP_Real_32_gfx12<0x03e>;2731defm S_WAIT_XCNT : SOPP_Real_32_gfx12<0x045>;2732defm S_WAIT_ASYNCCNT : SOPP_Real_32_gfx12<0x04a>;2733defm S_WAIT_TENSORCNT : SOPP_Real_32_gfx12<0x04b>;2734 2735//===----------------------------------------------------------------------===//2736// SOPP - GFX11, GFX12.2737//===----------------------------------------------------------------------===//2738 2739 2740multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> {2741 defvar ps = !cast<SOPP_Pseudo>(NAME);2742 def _gfx11 : SOPP_Real_32<op, ps, name>,2743 Select<GFX11Gen, ps.PseudoInstr>,2744 SOPPRelaxTable<0, ps.KeyName, "_gfx11">;2745 if !ne(ps.Mnemonic, name) then2746 def : AMDGPUMnemonicAlias<ps.Mnemonic, name> {2747 let AssemblerPredicate = isGFX11Only;2748 }2749}2750 2751multiclass SOPP_Real_64_gfx12<bits<7> op> {2752 def _gfx12 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,2753 Select<GFX12Gen, !cast<SOPP_Pseudo>(NAME).PseudoInstr>,2754 SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx12">;2755}2756 2757multiclass SOPP_Real_64_gfx11<bits<7> op> {2758 def _gfx11 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,2759 Select<GFX11Gen, !cast<SOPP_Pseudo>(NAME).PseudoInstr>,2760 SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx11">;2761}2762 2763multiclass SOPP_Real_32_gfx11_gfx12<bits<7> op> :2764 SOPP_Real_32_gfx11<op>, SOPP_Real_32_gfx12<op>;2765 2766multiclass SOPP_Real_32_gfx11_Renamed_gfx12<bits<7> op, string gfx12_name> :2767 SOPP_Real_32_gfx11<op>, SOPP_Real_32_gfx12<op, gfx12_name>;2768 2769multiclass SOPP_Real_With_Relaxation_gfx12<bits<7> op> {2770 defm "" : SOPP_Real_32_gfx12<op>;2771 let isCodeGenOnly = 1 in2772 defm _pad_s_nop : SOPP_Real_64_gfx12<op>;2773}2774 2775multiclass SOPP_Real_With_Relaxation_gfx11<bits<7> op> {2776 defm "" : SOPP_Real_32_gfx11<op>;2777 let isCodeGenOnly = 1 in2778 defm _pad_s_nop : SOPP_Real_64_gfx11<op>;2779}2780 2781multiclass SOPP_Real_With_Relaxation_gfx11_gfx12<bits<7>op> :2782 SOPP_Real_With_Relaxation_gfx11<op>, SOPP_Real_With_Relaxation_gfx12<op>;2783 2784defm S_SETKILL : SOPP_Real_32_gfx11_gfx12<0x001>;2785defm S_SETHALT : SOPP_Real_32_gfx11_gfx12<0x002>;2786defm S_SLEEP : SOPP_Real_32_gfx11_gfx12<0x003>;2787defm S_INST_PREFETCH : SOPP_Real_32_gfx11<0x004, "s_set_inst_prefetch_distance">;2788defm S_CLAUSE : SOPP_Real_32_gfx11_gfx12<0x005>;2789defm S_DELAY_ALU : SOPP_Real_32_gfx11_gfx12<0x007>;2790defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11_Renamed_gfx12<0x008, "s_wait_alu">;2791defm S_WAITCNT : SOPP_Real_32_gfx11_gfx12<0x009>;2792defm S_WAIT_IDLE : SOPP_Real_32_gfx11_gfx12<0x00a>;2793defm S_WAIT_EVENT : SOPP_Real_32_gfx11_gfx12<0x00b>;2794defm S_TRAP : SOPP_Real_32_gfx11_gfx12<0x010>;2795defm S_ROUND_MODE : SOPP_Real_32_gfx11_gfx12<0x011>;2796defm S_DENORM_MODE : SOPP_Real_32_gfx11_gfx12<0x012>;2797defm S_BRANCH : SOPP_Real_With_Relaxation_gfx11_gfx12<0x020>;2798defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x021>;2799defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x022>;2800defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x023>;2801defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x024>;2802defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x025>;2803defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x026>;2804defm S_CBRANCH_CDBGSYS : SOPP_Real_With_Relaxation_gfx11<0x027>;2805defm S_CBRANCH_CDBGUSER : SOPP_Real_With_Relaxation_gfx11<0x028>;2806defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx11<0x029>;2807defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx11<0x02a>;2808defm S_ENDPGM : SOPP_Real_32_gfx11_gfx12<0x030>;2809defm S_ENDPGM_SAVED : SOPP_Real_32_gfx11_gfx12<0x031>;2810defm S_ENDPGM_ORDERED_PS_DONE : SOPP_Real_32_gfx11<0x032>;2811defm S_WAKEUP : SOPP_Real_32_gfx11_gfx12<0x034>;2812defm S_SETPRIO : SOPP_Real_32_gfx11_gfx12<0x035>;2813defm S_SENDMSG : SOPP_Real_32_gfx11_gfx12<0x036>;2814defm S_SENDMSGHALT : SOPP_Real_32_gfx11_gfx12<0x037>;2815defm S_INCPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x038>;2816defm S_DECPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x039>;2817defm S_TTRACEDATA : SOPP_Real_32_gfx11_gfx12<0x03a>;2818defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx11_gfx12<0x03b>;2819defm S_ICACHE_INV : SOPP_Real_32_gfx11_gfx12<0x03c>;2820 2821defm S_BARRIER : SOPP_Real_32_gfx11<0x03d>;2822 2823//===----------------------------------------------------------------------===//2824// SOPP - GFX1250.2825//===----------------------------------------------------------------------===//2826 2827defm S_MONITOR_SLEEP : SOPP_Real_32_gfx12<0x004>;2828 2829//===----------------------------------------------------------------------===//2830// SOPP - GFX6, GFX7, GFX8, GFX9, GFX102831//===----------------------------------------------------------------------===//2832 2833multiclass SOPP_Real_32_gfx6_gfx7<bits<7> op> {2834 defvar ps = !cast<SOPP_Pseudo>(NAME);2835 def _gfx6_gfx7 : SOPP_Real_32<op, ps, !cast<SOPP_Pseudo>(NAME).Mnemonic>,2836 Select_gfx6_gfx7<ps.PseudoInstr>,2837 SOPPRelaxTable<0, ps.KeyName, "_gfx6_gfx7">;2838}2839 2840multiclass SOPP_Real_32_gfx8_gfx9<bits<7> op> {2841 defvar ps = !cast<SOPP_Pseudo>(NAME);2842 def _vi : SOPP_Real_32<op, ps>,2843 Select_vi<ps.PseudoInstr>,2844 SOPPRelaxTable<0, ps.KeyName, "_vi">;2845}2846 2847multiclass SOPP_Real_32_gfx10<bits<7> op> {2848 defvar ps = !cast<SOPP_Pseudo>(NAME);2849 def _gfx10 : SOPP_Real_32<op, ps>,2850 Select<GFX10Gen, ps.PseudoInstr>,2851 SOPPRelaxTable<0, ps.KeyName, "_gfx10">;2852}2853 2854multiclass SOPP_Real_32_gfx8_gfx9_gfx10<bits<7> op> :2855 SOPP_Real_32_gfx8_gfx9<op>, SOPP_Real_32_gfx10<op>;2856 2857multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9<bits<7> op> :2858 SOPP_Real_32_gfx6_gfx7<op>, SOPP_Real_32_gfx8_gfx9<op>;2859 2860multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> :2861 SOPP_Real_32_gfx6_gfx7_gfx8_gfx9<op>, SOPP_Real_32_gfx10<op>;2862 2863multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<bits<7> op> :2864 SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<op>, SOPP_Real_32_gfx11_gfx12<op>;2865 2866multiclass SOPP_Real_32_gfx10_gfx11_gfx12<bits<7> op> :2867 SOPP_Real_32_gfx10<op>, SOPP_Real_32_gfx11_gfx12<op>;2868 2869//64 bit encodings, for Relaxation2870multiclass SOPP_Real_64_gfx6_gfx7<bits<7> op> {2871 defvar ps = !cast<SOPP_Pseudo>(NAME);2872 def _gfx6_gfx7 : SOPP_Real_64<op, ps>,2873 Select_gfx6_gfx7<ps.PseudoInstr>,2874 SOPPRelaxTable<1, ps.KeyName, "_gfx6_gfx7">;2875}2876 2877multiclass SOPP_Real_64_gfx8_gfx9<bits<7> op> {2878 defvar ps = !cast<SOPP_Pseudo>(NAME);2879 def _vi : SOPP_Real_64<op, ps>,2880 Select_vi<ps.PseudoInstr>,2881 SOPPRelaxTable<1, ps.KeyName, "_vi">;2882}2883 2884multiclass SOPP_Real_64_gfx10<bits<7> op> {2885 defvar ps = !cast<SOPP_Pseudo>(NAME);2886 def _gfx10 : SOPP_Real_64<op, ps>,2887 Select<GFX10Gen, ps.PseudoInstr>,2888 SOPPRelaxTable<1, ps.KeyName, "_gfx10">;2889}2890 2891multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9<bits<7> op> :2892 SOPP_Real_64_gfx6_gfx7<op>, SOPP_Real_64_gfx8_gfx9<op>;2893 2894multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> :2895 SOPP_Real_64_gfx6_gfx7_gfx8_gfx9<op>, SOPP_Real_64_gfx10<op>;2896 2897//relaxation for insts with no operands not implemented2898multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> {2899 defm "" : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<op>;2900 let isCodeGenOnly = 1 in2901 defm _pad_s_nop : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<op>;2902}2903 2904defm S_NOP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x000>;2905defm S_ENDPGM : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x001>;2906defm S_WAKEUP : SOPP_Real_32_gfx8_gfx9_gfx10<0x003>;2907defm S_BARRIER : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00a>;2908defm S_WAITCNT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00c>;2909defm S_SETHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00d>;2910defm S_SETKILL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00b>;2911defm S_SLEEP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00e>;2912defm S_SETPRIO : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00f>;2913defm S_SENDMSG : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x010>;2914defm S_SENDMSGHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x011>;2915defm S_TRAP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x012>;2916defm S_ICACHE_INV : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x013>;2917defm S_INCPERFLEVEL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x014>;2918defm S_DECPERFLEVEL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x015>;2919defm S_TTRACEDATA : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x016>;2920defm S_ENDPGM_SAVED : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x01B>;2921defm S_SET_GPR_IDX_OFF : SOPP_Real_32_gfx8_gfx9<0x01c>;2922defm S_SET_GPR_IDX_MODE : SOPP_Real_32_gfx8_gfx9<0x01d>;2923defm S_ENDPGM_ORDERED_PS_DONE : SOPP_Real_32_gfx8_gfx9_gfx10<0x01e>;2924defm S_CODE_END : SOPP_Real_32_gfx10_gfx11_gfx12<0x01f>;2925defm S_INST_PREFETCH : SOPP_Real_32_gfx10<0x020>;2926defm S_CLAUSE : SOPP_Real_32_gfx10<0x021>;2927defm S_WAIT_IDLE : SOPP_Real_32_gfx10<0x022>;2928defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx10<0x023>;2929defm S_ROUND_MODE : SOPP_Real_32_gfx10<0x024>;2930defm S_DENORM_MODE : SOPP_Real_32_gfx10<0x025>;2931defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx10<0x028>;2932 2933let isBranch = 1 in {2934defm S_BRANCH : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x002>;2935defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x004>;2936defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x005>;2937defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x006>;2938defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x007>;2939defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x008>;2940defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x009>;2941defm S_CBRANCH_CDBGSYS : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x017>;2942defm S_CBRANCH_CDBGUSER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x018>;2943defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x019>;2944defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x01A>;2945}2946 2947//===----------------------------------------------------------------------===//2948// SOPC - GFX11, GFX12.2949//===----------------------------------------------------------------------===//2950 2951multiclass SOPC_Real_gfx12<bits<7> op> {2952 def _gfx12 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,2953 Select<GFX12Gen, !cast<SOPC_Pseudo>(NAME).PseudoInstr>;2954}2955 2956multiclass SOPC_Real_gfx11<bits<7> op> {2957 def _gfx11 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,2958 Select<GFX11Gen, !cast<SOPC_Pseudo>(NAME).PseudoInstr>;2959}2960 2961multiclass SOPC_Real_gfx11_gfx12<bits<7> op> :2962 SOPC_Real_gfx11<op>, SOPC_Real_gfx12<op>;2963 2964defm S_CMP_EQ_U64 : SOPC_Real_gfx11_gfx12<0x10>;2965defm S_CMP_LG_U64 : SOPC_Real_gfx11_gfx12<0x11>;2966 2967//===----------------------------------------------------------------------===//2968// SOPC - GFX1150, GFX122969//===----------------------------------------------------------------------===//2970 2971defm S_CMP_LT_F32 : SOPC_Real_gfx11_gfx12<0x41>;2972defm S_CMP_EQ_F32 : SOPC_Real_gfx11_gfx12<0x42>;2973defm S_CMP_LE_F32 : SOPC_Real_gfx11_gfx12<0x43>;2974defm S_CMP_GT_F32 : SOPC_Real_gfx11_gfx12<0x44>;2975defm S_CMP_LG_F32 : SOPC_Real_gfx11_gfx12<0x45>;2976defm S_CMP_GE_F32 : SOPC_Real_gfx11_gfx12<0x46>;2977defm S_CMP_O_F32 : SOPC_Real_gfx11_gfx12<0x47>;2978defm S_CMP_U_F32 : SOPC_Real_gfx11_gfx12<0x48>;2979defm S_CMP_NGE_F32 : SOPC_Real_gfx11_gfx12<0x49>;2980defm S_CMP_NLG_F32 : SOPC_Real_gfx11_gfx12<0x4a>;2981defm S_CMP_NGT_F32 : SOPC_Real_gfx11_gfx12<0x4b>;2982defm S_CMP_NLE_F32 : SOPC_Real_gfx11_gfx12<0x4c>;2983defm S_CMP_NEQ_F32 : SOPC_Real_gfx11_gfx12<0x4d>;2984defm S_CMP_NLT_F32 : SOPC_Real_gfx11_gfx12<0x4e>;2985 2986defm S_CMP_LT_F16 : SOPC_Real_gfx11_gfx12<0x51>;2987defm S_CMP_EQ_F16 : SOPC_Real_gfx11_gfx12<0x52>;2988defm S_CMP_LE_F16 : SOPC_Real_gfx11_gfx12<0x53>;2989defm S_CMP_GT_F16 : SOPC_Real_gfx11_gfx12<0x54>;2990defm S_CMP_LG_F16 : SOPC_Real_gfx11_gfx12<0x55>;2991defm S_CMP_GE_F16 : SOPC_Real_gfx11_gfx12<0x56>;2992defm S_CMP_O_F16 : SOPC_Real_gfx11_gfx12<0x57>;2993defm S_CMP_U_F16 : SOPC_Real_gfx11_gfx12<0x58>;2994defm S_CMP_NGE_F16 : SOPC_Real_gfx11_gfx12<0x59>;2995defm S_CMP_NLG_F16 : SOPC_Real_gfx11_gfx12<0x5a>;2996defm S_CMP_NGT_F16 : SOPC_Real_gfx11_gfx12<0x5b>;2997defm S_CMP_NLE_F16 : SOPC_Real_gfx11_gfx12<0x5c>;2998defm S_CMP_NEQ_F16 : SOPC_Real_gfx11_gfx12<0x5d>;2999defm S_CMP_NLT_F16 : SOPC_Real_gfx11_gfx12<0x5e>;3000 3001//===----------------------------------------------------------------------===//3002// SOPC - GFX6, GFX7, GFX8, GFX9, GFX103003//===----------------------------------------------------------------------===//3004 3005multiclass SOPC_Real_gfx6_gfx7<bits<7> op> {3006 defvar ps = !cast<SOPC_Pseudo>(NAME);3007 def _gfx6_gfx7 : SOPC_Real<op, ps>,3008 Select_gfx6_gfx7<ps.PseudoInstr>;3009}3010 3011multiclass SOPC_Real_gfx8_gfx9<bits<7> op> {3012 defvar ps = !cast<SOPC_Pseudo>(NAME);3013 def _vi : SOPC_Real<op, ps>,3014 Select_vi<ps.PseudoInstr>;3015}3016 3017multiclass SOPC_Real_gfx10<bits<7> op> {3018 defvar ps = !cast<SOPC_Pseudo>(NAME);3019 def _gfx10 : SOPC_Real<op, ps>,3020 Select<GFX10Gen, ps.PseudoInstr>;3021}3022 3023multiclass SOPC_Real_gfx8_gfx9_gfx10<bits<7> op> :3024 SOPC_Real_gfx8_gfx9<op>, SOPC_Real_gfx10<op>;3025 3026multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9<bits<7> op> :3027 SOPC_Real_gfx6_gfx7<op>, SOPC_Real_gfx8_gfx9<op>;3028 3029multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<bits<7> op> :3030 SOPC_Real_gfx6_gfx7_gfx8_gfx9<op>, SOPC_Real_gfx10<op>, SOPC_Real_gfx11<op>,3031 SOPC_Real_gfx12<op>;3032 3033defm S_CMP_EQ_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x00>;3034defm S_CMP_LG_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x01>;3035defm S_CMP_GT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x02>;3036defm S_CMP_GE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x03>;3037defm S_CMP_LT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x04>;3038defm S_CMP_LE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x05>;3039defm S_CMP_EQ_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x06>;3040defm S_CMP_LG_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x07>;3041defm S_CMP_GT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x08>;3042defm S_CMP_GE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x09>;3043defm S_CMP_LT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0a>;3044defm S_CMP_LE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0b>;3045defm S_BITCMP0_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0c>;3046defm S_BITCMP1_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0d>;3047defm S_BITCMP0_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0e>;3048defm S_BITCMP1_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0f>;3049defm S_SETVSKIP : SOPC_Real_gfx6_gfx7_gfx8_gfx9<0x10>;3050defm S_SET_GPR_IDX_ON : SOPC_Real_gfx8_gfx9<0x11>;3051defm S_CMP_EQ_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x12>;3052defm S_CMP_LG_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x13>;3053 3054//===----------------------------------------------------------------------===//3055// GFX8 (VI), GFX9.3056//===----------------------------------------------------------------------===//3057 3058class SOP1_Real_vi<bits<8> op, SOP1_Pseudo ps> :3059 SOP1_Real<op, ps>,3060 Select_vi<ps.PseudoInstr>;3061 3062class SOP2_Real_vi<bits<7> op, SOP2_Pseudo ps> :3063 SOP2_Real32<op, ps>,3064 Select_vi<ps.PseudoInstr>;3065 3066class SOPK_Real_vi<bits<5> op, SOPK_Pseudo ps> :3067 SOPK_Real32<op, ps>,3068 Select_vi<ps.PseudoInstr>;3069 3070def S_MOV_B32_vi : SOP1_Real_vi <0x00, S_MOV_B32>;3071def S_MOV_B64_vi : SOP1_Real_vi <0x01, S_MOV_B64>;3072def S_CMOV_B32_vi : SOP1_Real_vi <0x02, S_CMOV_B32>;3073def S_CMOV_B64_vi : SOP1_Real_vi <0x03, S_CMOV_B64>;3074def S_NOT_B32_vi : SOP1_Real_vi <0x04, S_NOT_B32>;3075def S_NOT_B64_vi : SOP1_Real_vi <0x05, S_NOT_B64>;3076def S_WQM_B32_vi : SOP1_Real_vi <0x06, S_WQM_B32>;3077def S_WQM_B64_vi : SOP1_Real_vi <0x07, S_WQM_B64>;3078def S_BREV_B32_vi : SOP1_Real_vi <0x08, S_BREV_B32>;3079def S_BREV_B64_vi : SOP1_Real_vi <0x09, S_BREV_B64>;3080def S_BCNT0_I32_B32_vi : SOP1_Real_vi <0x0a, S_BCNT0_I32_B32>;3081def S_BCNT0_I32_B64_vi : SOP1_Real_vi <0x0b, S_BCNT0_I32_B64>;3082def S_BCNT1_I32_B32_vi : SOP1_Real_vi <0x0c, S_BCNT1_I32_B32>;3083def S_BCNT1_I32_B64_vi : SOP1_Real_vi <0x0d, S_BCNT1_I32_B64>;3084def S_FF0_I32_B32_vi : SOP1_Real_vi <0x0e, S_FF0_I32_B32>;3085def S_FF0_I32_B64_vi : SOP1_Real_vi <0x0f, S_FF0_I32_B64>;3086def S_FF1_I32_B32_vi : SOP1_Real_vi <0x10, S_FF1_I32_B32>;3087def S_FF1_I32_B64_vi : SOP1_Real_vi <0x11, S_FF1_I32_B64>;3088def S_FLBIT_I32_B32_vi : SOP1_Real_vi <0x12, S_FLBIT_I32_B32>;3089def S_FLBIT_I32_B64_vi : SOP1_Real_vi <0x13, S_FLBIT_I32_B64>;3090def S_FLBIT_I32_vi : SOP1_Real_vi <0x14, S_FLBIT_I32>;3091def S_FLBIT_I32_I64_vi : SOP1_Real_vi <0x15, S_FLBIT_I32_I64>;3092def S_SEXT_I32_I8_vi : SOP1_Real_vi <0x16, S_SEXT_I32_I8>;3093def S_SEXT_I32_I16_vi : SOP1_Real_vi <0x17, S_SEXT_I32_I16>;3094def S_BITSET0_B32_vi : SOP1_Real_vi <0x18, S_BITSET0_B32>;3095def S_BITSET0_B64_vi : SOP1_Real_vi <0x19, S_BITSET0_B64>;3096def S_BITSET1_B32_vi : SOP1_Real_vi <0x1a, S_BITSET1_B32>;3097def S_BITSET1_B64_vi : SOP1_Real_vi <0x1b, S_BITSET1_B64>;3098def S_GETPC_B64_vi : SOP1_Real_vi <0x1c, S_GETPC_B64>;3099def S_SETPC_B64_vi : SOP1_Real_vi <0x1d, S_SETPC_B64>;3100def S_SWAPPC_B64_vi : SOP1_Real_vi <0x1e, S_SWAPPC_B64>;3101def S_RFE_B64_vi : SOP1_Real_vi <0x1f, S_RFE_B64>;3102def S_AND_SAVEEXEC_B64_vi : SOP1_Real_vi <0x20, S_AND_SAVEEXEC_B64>;3103def S_OR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x21, S_OR_SAVEEXEC_B64>;3104def S_XOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x22, S_XOR_SAVEEXEC_B64>;3105def S_ANDN2_SAVEEXEC_B64_vi: SOP1_Real_vi <0x23, S_ANDN2_SAVEEXEC_B64>;3106def S_ORN2_SAVEEXEC_B64_vi : SOP1_Real_vi <0x24, S_ORN2_SAVEEXEC_B64>;3107def S_NAND_SAVEEXEC_B64_vi : SOP1_Real_vi <0x25, S_NAND_SAVEEXEC_B64>;3108def S_NOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x26, S_NOR_SAVEEXEC_B64>;3109def S_XNOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x27, S_XNOR_SAVEEXEC_B64>;3110def S_QUADMASK_B32_vi : SOP1_Real_vi <0x28, S_QUADMASK_B32>;3111def S_QUADMASK_B64_vi : SOP1_Real_vi <0x29, S_QUADMASK_B64>;3112def S_MOVRELS_B32_vi : SOP1_Real_vi <0x2a, S_MOVRELS_B32>;3113def S_MOVRELS_B64_vi : SOP1_Real_vi <0x2b, S_MOVRELS_B64>;3114def S_MOVRELD_B32_vi : SOP1_Real_vi <0x2c, S_MOVRELD_B32>;3115def S_MOVRELD_B64_vi : SOP1_Real_vi <0x2d, S_MOVRELD_B64>;3116def S_CBRANCH_JOIN_vi : SOP1_Real_vi <0x2e, S_CBRANCH_JOIN>;3117def S_ABS_I32_vi : SOP1_Real_vi <0x30, S_ABS_I32>;3118def S_SET_GPR_IDX_IDX_vi : SOP1_Real_vi <0x32, S_SET_GPR_IDX_IDX>;3119 3120def S_ADD_U32_vi : SOP2_Real_vi <0x00, S_ADD_U32>;3121def S_ADD_I32_vi : SOP2_Real_vi <0x02, S_ADD_I32>;3122def S_SUB_U32_vi : SOP2_Real_vi <0x01, S_SUB_U32>;3123def S_SUB_I32_vi : SOP2_Real_vi <0x03, S_SUB_I32>;3124def S_ADDC_U32_vi : SOP2_Real_vi <0x04, S_ADDC_U32>;3125def S_SUBB_U32_vi : SOP2_Real_vi <0x05, S_SUBB_U32>;3126def S_MIN_I32_vi : SOP2_Real_vi <0x06, S_MIN_I32>;3127def S_MIN_U32_vi : SOP2_Real_vi <0x07, S_MIN_U32>;3128def S_MAX_I32_vi : SOP2_Real_vi <0x08, S_MAX_I32>;3129def S_MAX_U32_vi : SOP2_Real_vi <0x09, S_MAX_U32>;3130def S_CSELECT_B32_vi : SOP2_Real_vi <0x0a, S_CSELECT_B32>;3131def S_CSELECT_B64_vi : SOP2_Real_vi <0x0b, S_CSELECT_B64>;3132def S_AND_B32_vi : SOP2_Real_vi <0x0c, S_AND_B32>;3133def S_AND_B64_vi : SOP2_Real_vi <0x0d, S_AND_B64>;3134def S_OR_B32_vi : SOP2_Real_vi <0x0e, S_OR_B32>;3135def S_OR_B64_vi : SOP2_Real_vi <0x0f, S_OR_B64>;3136def S_XOR_B32_vi : SOP2_Real_vi <0x10, S_XOR_B32>;3137def S_XOR_B64_vi : SOP2_Real_vi <0x11, S_XOR_B64>;3138def S_ANDN2_B32_vi : SOP2_Real_vi <0x12, S_ANDN2_B32>;3139def S_ANDN2_B64_vi : SOP2_Real_vi <0x13, S_ANDN2_B64>;3140def S_ORN2_B32_vi : SOP2_Real_vi <0x14, S_ORN2_B32>;3141def S_ORN2_B64_vi : SOP2_Real_vi <0x15, S_ORN2_B64>;3142def S_NAND_B32_vi : SOP2_Real_vi <0x16, S_NAND_B32>;3143def S_NAND_B64_vi : SOP2_Real_vi <0x17, S_NAND_B64>;3144def S_NOR_B32_vi : SOP2_Real_vi <0x18, S_NOR_B32>;3145def S_NOR_B64_vi : SOP2_Real_vi <0x19, S_NOR_B64>;3146def S_XNOR_B32_vi : SOP2_Real_vi <0x1a, S_XNOR_B32>;3147def S_XNOR_B64_vi : SOP2_Real_vi <0x1b, S_XNOR_B64>;3148def S_LSHL_B32_vi : SOP2_Real_vi <0x1c, S_LSHL_B32>;3149def S_LSHL_B64_vi : SOP2_Real_vi <0x1d, S_LSHL_B64>;3150def S_LSHR_B32_vi : SOP2_Real_vi <0x1e, S_LSHR_B32>;3151def S_LSHR_B64_vi : SOP2_Real_vi <0x1f, S_LSHR_B64>;3152def S_ASHR_I32_vi : SOP2_Real_vi <0x20, S_ASHR_I32>;3153def S_ASHR_I64_vi : SOP2_Real_vi <0x21, S_ASHR_I64>;3154def S_BFM_B32_vi : SOP2_Real_vi <0x22, S_BFM_B32>;3155def S_BFM_B64_vi : SOP2_Real_vi <0x23, S_BFM_B64>;3156def S_MUL_I32_vi : SOP2_Real_vi <0x24, S_MUL_I32>;3157def S_BFE_U32_vi : SOP2_Real_vi <0x25, S_BFE_U32>;3158def S_BFE_I32_vi : SOP2_Real_vi <0x26, S_BFE_I32>;3159def S_BFE_U64_vi : SOP2_Real_vi <0x27, S_BFE_U64>;3160def S_BFE_I64_vi : SOP2_Real_vi <0x28, S_BFE_I64>;3161def S_CBRANCH_G_FORK_vi : SOP2_Real_vi <0x29, S_CBRANCH_G_FORK>;3162def S_ABSDIFF_I32_vi : SOP2_Real_vi <0x2a, S_ABSDIFF_I32>;3163def S_PACK_LL_B32_B16_vi : SOP2_Real_vi <0x32, S_PACK_LL_B32_B16>;3164def S_PACK_LH_B32_B16_vi : SOP2_Real_vi <0x33, S_PACK_LH_B32_B16>;3165def S_PACK_HH_B32_B16_vi : SOP2_Real_vi <0x34, S_PACK_HH_B32_B16>;3166def S_RFE_RESTORE_B64_vi : SOP2_Real_vi <0x2b, S_RFE_RESTORE_B64>;3167 3168def S_MOVK_I32_vi : SOPK_Real_vi <0x00, S_MOVK_I32>;3169def S_CMOVK_I32_vi : SOPK_Real_vi <0x01, S_CMOVK_I32>;3170def S_CMPK_EQ_I32_vi : SOPK_Real_vi <0x02, S_CMPK_EQ_I32>;3171def S_CMPK_LG_I32_vi : SOPK_Real_vi <0x03, S_CMPK_LG_I32>;3172def S_CMPK_GT_I32_vi : SOPK_Real_vi <0x04, S_CMPK_GT_I32>;3173def S_CMPK_GE_I32_vi : SOPK_Real_vi <0x05, S_CMPK_GE_I32>;3174def S_CMPK_LT_I32_vi : SOPK_Real_vi <0x06, S_CMPK_LT_I32>;3175def S_CMPK_LE_I32_vi : SOPK_Real_vi <0x07, S_CMPK_LE_I32>;3176def S_CMPK_EQ_U32_vi : SOPK_Real_vi <0x08, S_CMPK_EQ_U32>;3177def S_CMPK_LG_U32_vi : SOPK_Real_vi <0x09, S_CMPK_LG_U32>;3178def S_CMPK_GT_U32_vi : SOPK_Real_vi <0x0A, S_CMPK_GT_U32>;3179def S_CMPK_GE_U32_vi : SOPK_Real_vi <0x0B, S_CMPK_GE_U32>;3180def S_CMPK_LT_U32_vi : SOPK_Real_vi <0x0C, S_CMPK_LT_U32>;3181def S_CMPK_LE_U32_vi : SOPK_Real_vi <0x0D, S_CMPK_LE_U32>;3182def S_ADDK_I32_vi : SOPK_Real_vi <0x0E, S_ADDK_I32>;3183def S_MULK_I32_vi : SOPK_Real_vi <0x0F, S_MULK_I32>;3184def S_CBRANCH_I_FORK_vi : SOPK_Real_vi <0x10, S_CBRANCH_I_FORK>;3185def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>;3186def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>;3187//def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments3188def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,3189 Select_vi<S_SETREG_IMM32_B32.PseudoInstr>;3190 3191def S_CALL_B64_vi : SOPK_Real_vi <0x15, S_CALL_B64>;3192 3193//===----------------------------------------------------------------------===//3194// SOP1 - GFX9.3195//===----------------------------------------------------------------------===//3196 3197def S_ANDN1_SAVEEXEC_B64_vi : SOP1_Real_vi<0x33, S_ANDN1_SAVEEXEC_B64>;3198def S_ORN1_SAVEEXEC_B64_vi : SOP1_Real_vi<0x34, S_ORN1_SAVEEXEC_B64>;3199def S_ANDN1_WREXEC_B64_vi : SOP1_Real_vi<0x35, S_ANDN1_WREXEC_B64>;3200def S_ANDN2_WREXEC_B64_vi : SOP1_Real_vi<0x36, S_ANDN2_WREXEC_B64>;3201def S_BITREPLICATE_B64_B32_vi : SOP1_Real_vi<0x37, S_BITREPLICATE_B64_B32>;3202 3203//===----------------------------------------------------------------------===//3204// SOP2 - GFX9.3205//===----------------------------------------------------------------------===//3206 3207def S_LSHL1_ADD_U32_vi : SOP2_Real_vi<0x2e, S_LSHL1_ADD_U32>;3208def S_LSHL2_ADD_U32_vi : SOP2_Real_vi<0x2f, S_LSHL2_ADD_U32>;3209def S_LSHL3_ADD_U32_vi : SOP2_Real_vi<0x30, S_LSHL3_ADD_U32>;3210def S_LSHL4_ADD_U32_vi : SOP2_Real_vi<0x31, S_LSHL4_ADD_U32>;3211def S_MUL_HI_U32_vi : SOP2_Real_vi<0x2c, S_MUL_HI_U32>;3212def S_MUL_HI_I32_vi : SOP2_Real_vi<0x2d, S_MUL_HI_I32>;3213