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1//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H11 12#include "AMDGPUSubtarget.h"13#include "SIDefines.h"14#include "llvm/IR/CallingConv.h"15#include "llvm/IR/InstrTypes.h"16#include "llvm/IR/Module.h"17#include "llvm/Support/Alignment.h"18#include <array>19#include <functional>20#include <utility>21 22// Pull in OpName enum definition and getNamedOperandIdx() declaration.23#define GET_INSTRINFO_OPERAND_ENUM24#include "AMDGPUGenInstrInfo.inc"25 26struct amd_kernel_code_t;27 28namespace llvm {29 30struct Align;31class Argument;32class Function;33class GlobalValue;34class MCInstrInfo;35class MCRegisterClass;36class MCRegisterInfo;37class MCSubtargetInfo;38class MDNode;39class StringRef;40class Triple;41class raw_ostream;42 43namespace AMDGPU {44 45struct AMDGPUMCKernelCodeT;46struct IsaVersion;47 48/// Generic target versions emitted by this version of LLVM.49///50/// These numbers are incremented every time a codegen breaking change occurs51/// within a generic family.52namespace GenericVersion {53static constexpr unsigned GFX9 = 1;54static constexpr unsigned GFX9_4 = 1;55static constexpr unsigned GFX10_1 = 1;56static constexpr unsigned GFX10_3 = 1;57static constexpr unsigned GFX11 = 1;58static constexpr unsigned GFX12 = 1;59} // namespace GenericVersion60 61enum { AMDHSA_COV4 = 4, AMDHSA_COV5 = 5, AMDHSA_COV6 = 6 };62 63enum class FPType { None, FP4, FP8 };64 65/// \returns True if \p STI is AMDHSA.66bool isHsaAbi(const MCSubtargetInfo &STI);67 68/// \returns Code object version from the IR module flag.69unsigned getAMDHSACodeObjectVersion(const Module &M);70 71/// \returns Code object version from ELF's e_ident[EI_ABIVERSION].72unsigned getAMDHSACodeObjectVersion(unsigned ABIVersion);73 74/// \returns The default HSA code object version. This should only be used when75/// we lack a more accurate CodeObjectVersion value (e.g. from the IR module76/// flag or a .amdhsa_code_object_version directive)77unsigned getDefaultAMDHSACodeObjectVersion();78 79/// \returns ABIVersion suitable for use in ELF's e_ident[EI_ABIVERSION]. \param80/// CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion().81uint8_t getELFABIVersion(const Triple &OS, unsigned CodeObjectVersion);82 83/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr84unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);85 86/// \returns The offset of the hostcall pointer argument from implicitarg_ptr87unsigned getHostcallImplicitArgPosition(unsigned COV);88 89unsigned getDefaultQueueImplicitArgPosition(unsigned COV);90unsigned getCompletionActionImplicitArgPosition(unsigned COV);91 92struct GcnBufferFormatInfo {93 unsigned Format;94 unsigned BitsPerComp;95 unsigned NumComponents;96 unsigned NumFormat;97 unsigned DataFormat;98};99 100struct MAIInstInfo {101 uint16_t Opcode;102 bool is_dgemm;103 bool is_gfx940_xdl;104};105 106struct MFMA_F8F6F4_Info {107 unsigned Opcode;108 unsigned F8F8Opcode;109 uint8_t NumRegsSrcA;110 uint8_t NumRegsSrcB;111};112 113struct CvtScaleF32_F32F16ToF8F4_Info {114 unsigned Opcode;115};116 117struct True16D16Info {118 unsigned T16Op;119 unsigned HiOp;120 unsigned LoOp;121};122 123struct WMMAInstInfo {124 uint16_t Opcode;125 bool is_wmma_xdl;126};127 128#define GET_MIMGBaseOpcode_DECL129#define GET_MIMGDim_DECL130#define GET_MIMGEncoding_DECL131#define GET_MIMGLZMapping_DECL132#define GET_MIMGMIPMapping_DECL133#define GET_MIMGBiASMapping_DECL134#define GET_MAIInstInfoTable_DECL135#define GET_isMFMA_F8F6F4Table_DECL136#define GET_isCvtScaleF32_F32F16ToF8F4Table_DECL137#define GET_True16D16Table_DECL138#define GET_WMMAInstInfoTable_DECL139#include "AMDGPUGenSearchableTables.inc"140 141namespace IsaInfo {142 143enum {144 // The closed Vulkan driver sets 96, which limits the wave count to 8 but145 // doesn't spill SGPRs as much as when 80 is set.146 FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,147 TRAP_NUM_SGPRS = 16148};149 150enum class TargetIDSetting { Unsupported, Any, Off, On };151 152class AMDGPUTargetID {153private:154 const MCSubtargetInfo &STI;155 TargetIDSetting XnackSetting;156 TargetIDSetting SramEccSetting;157 158public:159 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);160 ~AMDGPUTargetID() = default;161 162 /// \return True if the current xnack setting is not "Unsupported".163 bool isXnackSupported() const {164 return XnackSetting != TargetIDSetting::Unsupported;165 }166 167 /// \returns True if the current xnack setting is "On" or "Any".168 bool isXnackOnOrAny() const {169 return XnackSetting == TargetIDSetting::On ||170 XnackSetting == TargetIDSetting::Any;171 }172 173 /// \returns True if current xnack setting is "On" or "Off",174 /// false otherwise.175 bool isXnackOnOrOff() const {176 return getXnackSetting() == TargetIDSetting::On ||177 getXnackSetting() == TargetIDSetting::Off;178 }179 180 /// \returns The current xnack TargetIDSetting, possible options are181 /// "Unsupported", "Any", "Off", and "On".182 TargetIDSetting getXnackSetting() const { return XnackSetting; }183 184 /// Sets xnack setting to \p NewXnackSetting.185 void setXnackSetting(TargetIDSetting NewXnackSetting) {186 XnackSetting = NewXnackSetting;187 }188 189 /// \return True if the current sramecc setting is not "Unsupported".190 bool isSramEccSupported() const {191 return SramEccSetting != TargetIDSetting::Unsupported;192 }193 194 /// \returns True if the current sramecc setting is "On" or "Any".195 bool isSramEccOnOrAny() const {196 return SramEccSetting == TargetIDSetting::On ||197 SramEccSetting == TargetIDSetting::Any;198 }199 200 /// \returns True if current sramecc setting is "On" or "Off",201 /// false otherwise.202 bool isSramEccOnOrOff() const {203 return getSramEccSetting() == TargetIDSetting::On ||204 getSramEccSetting() == TargetIDSetting::Off;205 }206 207 /// \returns The current sramecc TargetIDSetting, possible options are208 /// "Unsupported", "Any", "Off", and "On".209 TargetIDSetting getSramEccSetting() const { return SramEccSetting; }210 211 /// Sets sramecc setting to \p NewSramEccSetting.212 void setSramEccSetting(TargetIDSetting NewSramEccSetting) {213 SramEccSetting = NewSramEccSetting;214 }215 216 void setTargetIDFromFeaturesString(StringRef FS);217 void setTargetIDFromTargetIDStream(StringRef TargetID);218 219 /// \returns String representation of an object.220 std::string toString() const;221};222 223/// \returns Wavefront size for given subtarget \p STI.224unsigned getWavefrontSize(const MCSubtargetInfo *STI);225 226/// \returns Local memory size in bytes for given subtarget \p STI.227unsigned getLocalMemorySize(const MCSubtargetInfo *STI);228 229/// \returns Maximum addressable local memory size in bytes for given subtarget230/// \p STI.231unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI);232 233/// \returns Number of execution units per compute unit for given subtarget \p234/// STI.235unsigned getEUsPerCU(const MCSubtargetInfo *STI);236 237/// \returns Maximum number of work groups per compute unit for given subtarget238/// \p STI and limited by given \p FlatWorkGroupSize.239unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,240 unsigned FlatWorkGroupSize);241 242/// \returns Minimum number of waves per execution unit for given subtarget \p243/// STI.244unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);245 246/// \returns Maximum number of waves per execution unit for given subtarget \p247/// STI without any kind of limitation.248unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);249 250/// \returns Number of waves per execution unit required to support the given \p251/// FlatWorkGroupSize.252unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,253 unsigned FlatWorkGroupSize);254 255/// \returns Minimum flat work group size for given subtarget \p STI.256unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);257 258/// \returns Maximum flat work group size for given subtarget \p STI.259unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);260 261/// \returns Number of waves per work group for given subtarget \p STI and262/// \p FlatWorkGroupSize.263unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,264 unsigned FlatWorkGroupSize);265 266/// \returns SGPR allocation granularity for given subtarget \p STI.267unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);268 269/// \returns SGPR encoding granularity for given subtarget \p STI.270unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);271 272/// \returns Total number of SGPRs for given subtarget \p STI.273unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);274 275/// \returns Addressable number of SGPRs for given subtarget \p STI.276unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);277 278/// \returns Minimum number of SGPRs that meets the given number of waves per279/// execution unit requirement for given subtarget \p STI.280unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);281 282/// \returns Maximum number of SGPRs that meets the given number of waves per283/// execution unit requirement for given subtarget \p STI.284unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,285 bool Addressable);286 287/// \returns Number of extra SGPRs implicitly required by given subtarget \p288/// STI when the given special registers are used.289unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,290 bool FlatScrUsed, bool XNACKUsed);291 292/// \returns Number of extra SGPRs implicitly required by given subtarget \p293/// STI when the given special registers are used. XNACK is inferred from294/// \p STI.295unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,296 bool FlatScrUsed);297 298/// \returns Number of SGPR blocks needed for given subtarget \p STI when299/// \p NumSGPRs are used. \p NumSGPRs should already include any special300/// register counts.301unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);302 303/// \returns VGPR allocation granularity for given subtarget \p STI.304///305/// For subtargets which support it, \p EnableWavefrontSize32 should match306/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.307unsigned308getVGPRAllocGranule(const MCSubtargetInfo *STI, unsigned DynamicVGPRBlockSize,309 std::optional<bool> EnableWavefrontSize32 = std::nullopt);310 311/// \returns VGPR encoding granularity for given subtarget \p STI.312///313/// For subtargets which support it, \p EnableWavefrontSize32 should match314/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.315unsigned getVGPREncodingGranule(316 const MCSubtargetInfo *STI,317 std::optional<bool> EnableWavefrontSize32 = std::nullopt);318 319/// For subtargets with a unified VGPR file and mixed ArchVGPR/AGPR usage,320/// returns the allocation granule for ArchVGPRs.321unsigned getArchVGPRAllocGranule();322 323/// \returns Total number of VGPRs for given subtarget \p STI.324unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);325 326/// \returns Addressable number of architectural VGPRs for a given subtarget \p327/// STI.328unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI);329 330/// \returns Addressable number of VGPRs for given subtarget \p STI.331unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI,332 unsigned DynamicVGPRBlockSize);333 334/// \returns Minimum number of VGPRs that meets given number of waves per335/// execution unit requirement for given subtarget \p STI.336unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,337 unsigned DynamicVGPRBlockSize);338 339/// \returns Maximum number of VGPRs that meets given number of waves per340/// execution unit requirement for given subtarget \p STI.341unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,342 unsigned DynamicVGPRBlockSize);343 344/// \returns Number of waves reachable for a given \p NumVGPRs usage for given345/// subtarget \p STI.346unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI,347 unsigned NumVGPRs,348 unsigned DynamicVGPRBlockSize);349 350/// \returns Number of waves reachable for a given \p NumVGPRs usage, \p Granule351/// size, \p MaxWaves possible, and \p TotalNumVGPRs available.352unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,353 unsigned MaxWaves,354 unsigned TotalNumVGPRs);355 356/// \returns Occupancy for a given \p SGPRs usage, \p MaxWaves possible, and \p357/// Gen.358unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,359 AMDGPUSubtarget::Generation Gen);360 361/// \returns Number of VGPR blocks needed for given subtarget \p STI when362/// \p NumVGPRs are used. We actually return the number of blocks -1, since363/// that's what we encode.364///365/// For subtargets which support it, \p EnableWavefrontSize32 should match the366/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.367unsigned getEncodedNumVGPRBlocks(368 const MCSubtargetInfo *STI, unsigned NumVGPRs,369 std::optional<bool> EnableWavefrontSize32 = std::nullopt);370 371/// \returns Number of VGPR blocks that need to be allocated for the given372/// subtarget \p STI when \p NumVGPRs are used.373unsigned getAllocatedNumVGPRBlocks(374 const MCSubtargetInfo *STI, unsigned NumVGPRs,375 unsigned DynamicVGPRBlockSize,376 std::optional<bool> EnableWavefrontSize32 = std::nullopt);377 378} // end namespace IsaInfo379 380// Represents a field in an encoded value.381template <unsigned HighBit, unsigned LowBit, unsigned D = 0>382struct EncodingField {383 static_assert(HighBit >= LowBit, "Invalid bit range!");384 static constexpr unsigned Offset = LowBit;385 static constexpr unsigned Width = HighBit - LowBit + 1;386 387 using ValueType = unsigned;388 static constexpr ValueType Default = D;389 390 ValueType Value;391 constexpr EncodingField(ValueType Value) : Value(Value) {}392 393 constexpr uint64_t encode() const { return Value; }394 static ValueType decode(uint64_t Encoded) { return Encoded; }395};396 397// Represents a single bit in an encoded value.398template <unsigned Bit, unsigned D = 0>399using EncodingBit = EncodingField<Bit, Bit, D>;400 401// A helper for encoding and decoding multiple fields.402template <typename... Fields> struct EncodingFields {403 static constexpr uint64_t encode(Fields... Values) {404 return ((Values.encode() << Values.Offset) | ...);405 }406 407 static std::tuple<typename Fields::ValueType...> decode(uint64_t Encoded) {408 return {Fields::decode((Encoded >> Fields::Offset) &409 maxUIntN(Fields::Width))...};410 }411};412 413LLVM_READONLY414inline bool hasNamedOperand(uint64_t Opcode, OpName NamedIdx) {415 return getNamedOperandIdx(Opcode, NamedIdx) != -1;416}417 418LLVM_READONLY419int getSOPPWithRelaxation(uint16_t Opcode);420 421struct MIMGBaseOpcodeInfo {422 MIMGBaseOpcode BaseOpcode;423 bool Store;424 bool Atomic;425 bool AtomicX2;426 bool Sampler;427 bool Gather4;428 429 uint8_t NumExtraArgs;430 bool Gradients;431 bool G16;432 bool Coordinates;433 bool LodOrClampOrMip;434 bool HasD16;435 bool MSAA;436 bool BVH;437 bool A16;438 bool NoReturn;439 bool PointSampleAccel;440};441 442LLVM_READONLY443const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);444 445LLVM_READONLY446const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);447 448struct MIMGDimInfo {449 MIMGDim Dim;450 uint8_t NumCoords;451 uint8_t NumGradients;452 bool MSAA;453 bool DA;454 uint8_t Encoding;455 const char *AsmSuffix;456};457 458LLVM_READONLY459const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);460 461LLVM_READONLY462const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);463 464LLVM_READONLY465const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);466 467struct MIMGLZMappingInfo {468 MIMGBaseOpcode L;469 MIMGBaseOpcode LZ;470};471 472struct MIMGMIPMappingInfo {473 MIMGBaseOpcode MIP;474 MIMGBaseOpcode NONMIP;475};476 477struct MIMGBiasMappingInfo {478 MIMGBaseOpcode Bias;479 MIMGBaseOpcode NoBias;480};481 482struct MIMGOffsetMappingInfo {483 MIMGBaseOpcode Offset;484 MIMGBaseOpcode NoOffset;485};486 487struct MIMGG16MappingInfo {488 MIMGBaseOpcode G;489 MIMGBaseOpcode G16;490};491 492LLVM_READONLY493const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);494 495struct WMMAOpcodeMappingInfo {496 unsigned Opcode2Addr;497 unsigned Opcode3Addr;498};499 500LLVM_READONLY501const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);502 503LLVM_READONLY504const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);505 506LLVM_READONLY507const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);508 509LLVM_READONLY510const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);511 512LLVM_READONLY513int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,514 unsigned VDataDwords, unsigned VAddrDwords);515 516LLVM_READONLY517int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);518 519LLVM_READONLY520unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,521 const MIMGDimInfo *Dim, bool IsA16,522 bool IsG16Supported);523 524struct MIMGInfo {525 uint16_t Opcode;526 uint16_t BaseOpcode;527 uint8_t MIMGEncoding;528 uint8_t VDataDwords;529 uint8_t VAddrDwords;530 uint8_t VAddrOperands;531};532 533LLVM_READONLY534const MIMGInfo *getMIMGInfo(unsigned Opc);535 536LLVM_READONLY537int getMTBUFBaseOpcode(unsigned Opc);538 539LLVM_READONLY540int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);541 542LLVM_READONLY543int getMTBUFElements(unsigned Opc);544 545LLVM_READONLY546bool getMTBUFHasVAddr(unsigned Opc);547 548LLVM_READONLY549bool getMTBUFHasSrsrc(unsigned Opc);550 551LLVM_READONLY552bool getMTBUFHasSoffset(unsigned Opc);553 554LLVM_READONLY555int getMUBUFBaseOpcode(unsigned Opc);556 557LLVM_READONLY558int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);559 560LLVM_READONLY561int getMUBUFElements(unsigned Opc);562 563LLVM_READONLY564bool getMUBUFHasVAddr(unsigned Opc);565 566LLVM_READONLY567bool getMUBUFHasSrsrc(unsigned Opc);568 569LLVM_READONLY570bool getMUBUFHasSoffset(unsigned Opc);571 572LLVM_READONLY573bool getMUBUFIsBufferInv(unsigned Opc);574 575LLVM_READONLY576bool getMUBUFTfe(unsigned Opc);577 578LLVM_READONLY579bool getSMEMIsBuffer(unsigned Opc);580 581LLVM_READONLY582bool getVOP1IsSingle(unsigned Opc);583 584LLVM_READONLY585bool getVOP2IsSingle(unsigned Opc);586 587LLVM_READONLY588bool getVOP3IsSingle(unsigned Opc);589 590LLVM_READONLY591bool isVOPC64DPP(unsigned Opc);592 593LLVM_READONLY594bool isVOPCAsmOnly(unsigned Opc);595 596/// Returns true if MAI operation is a double precision GEMM.597LLVM_READONLY598bool getMAIIsDGEMM(unsigned Opc);599 600LLVM_READONLY601bool getMAIIsGFX940XDL(unsigned Opc);602 603LLVM_READONLY604bool getWMMAIsXDL(unsigned Opc);605 606// Get an equivalent BitOp3 for a binary logical \p Opc.607// \returns BitOp3 modifier for the logical operation or zero.608// Used in VOPD3 conversion.609unsigned getBitOp2(unsigned Opc);610 611struct CanBeVOPD {612 bool X;613 bool Y;614};615 616/// \returns SIEncodingFamily used for VOPD encoding on a \p ST.617LLVM_READONLY618unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST);619 620LLVM_READONLY621CanBeVOPD getCanBeVOPD(unsigned Opc, unsigned EncodingFamily, bool VOPD3);622 623LLVM_READNONE624uint8_t mfmaScaleF8F6F4FormatToNumRegs(unsigned EncodingVal);625 626LLVM_READONLY627const MFMA_F8F6F4_Info *getMFMA_F8F6F4_WithFormatArgs(unsigned CBSZ,628 unsigned BLGP,629 unsigned F8F8Opcode);630 631LLVM_READNONE632uint8_t wmmaScaleF8F6F4FormatToNumRegs(unsigned Fmt);633 634LLVM_READONLY635const MFMA_F8F6F4_Info *getWMMA_F8F6F4_WithFormatArgs(unsigned FmtA,636 unsigned FmtB,637 unsigned F8F8Opcode);638 639LLVM_READONLY640const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,641 uint8_t NumComponents,642 uint8_t NumFormat,643 const MCSubtargetInfo &STI);644LLVM_READONLY645const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,646 const MCSubtargetInfo &STI);647 648LLVM_READONLY649int getMCOpcode(uint16_t Opcode, unsigned Gen);650 651LLVM_READONLY652unsigned getVOPDOpcode(unsigned Opc, bool VOPD3);653 654LLVM_READONLY655int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily,656 bool VOPD3);657 658LLVM_READONLY659bool isVOPD(unsigned Opc);660 661LLVM_READNONE662bool isMAC(unsigned Opc);663 664LLVM_READNONE665bool isPermlane16(unsigned Opc);666 667LLVM_READNONE668bool isGenericAtomic(unsigned Opc);669 670LLVM_READNONE671bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc);672 673namespace VOPD {674 675enum Component : unsigned {676 DST = 0,677 SRC0,678 SRC1,679 SRC2,680 681 DST_NUM = 1,682 MAX_SRC_NUM = 3,683 MAX_OPR_NUM = DST_NUM + MAX_SRC_NUM684};685 686// LSB mask for VGPR banks per VOPD component operand.687// 4 banks result in a mask 3, setting 2 lower bits.688constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};689constexpr unsigned VOPD3_VGPR_BANK_MASKS[] = {1, 3, 3, 3};690 691enum ComponentIndex : unsigned { X = 0, Y = 1 };692constexpr unsigned COMPONENTS[] = {ComponentIndex::X, ComponentIndex::Y};693constexpr unsigned COMPONENTS_NUM = 2;694 695// Properties of VOPD components.696class ComponentProps {697private:698 unsigned SrcOperandsNum = 0;699 unsigned MandatoryLiteralIdx = ~0u;700 bool HasSrc2Acc = false;701 unsigned NumVOPD3Mods = 0;702 unsigned Opcode = 0;703 bool IsVOP3 = false;704 705public:706 ComponentProps() = default;707 ComponentProps(const MCInstrDesc &OpDesc, bool VOP3Layout = false);708 709 // Return the total number of src operands this component has.710 unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }711 712 // Return the number of src operands of this component visible to the parser.713 unsigned getCompParsedSrcOperandsNum() const {714 return SrcOperandsNum - HasSrc2Acc;715 }716 717 // Return true iif this component has a mandatory literal.718 bool hasMandatoryLiteral() const { return MandatoryLiteralIdx != ~0u; }719 720 // If this component has a mandatory literal, return component operand721 // index of this literal (i.e. either Component::SRC1 or Component::SRC2).722 unsigned getMandatoryLiteralCompOperandIndex() const {723 assert(hasMandatoryLiteral());724 return MandatoryLiteralIdx;725 }726 727 // Return true iif this component has operand728 // with component index CompSrcIdx and this operand may be a register.729 bool hasRegSrcOperand(unsigned CompSrcIdx) const {730 assert(CompSrcIdx < Component::MAX_SRC_NUM);731 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);732 }733 734 // Return true iif this component has tied src2.735 bool hasSrc2Acc() const { return HasSrc2Acc; }736 737 // Return a number of source modifiers if instruction is used in VOPD3.738 unsigned getCompVOPD3ModsNum() const { return NumVOPD3Mods; }739 740 // Return opcode of the component.741 unsigned getOpcode() const { return Opcode; }742 743 // Returns if component opcode is in VOP3 encoding.744 unsigned isVOP3() const { return IsVOP3; }745 746 // Return index of BitOp3 operand or -1.747 int getBitOp3OperandIdx() const;748 749private:750 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {751 assert(CompSrcIdx < Component::MAX_SRC_NUM);752 return MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;753 }754};755 756enum ComponentKind : unsigned {757 SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.758 COMPONENT_X, // A VOPD instruction, X component.759 COMPONENT_Y, // A VOPD instruction, Y component.760 MAX = COMPONENT_Y761};762 763// Interface functions of this class map VOPD component operand indices764// to indices of operands in MachineInstr/MCInst or parsed operands array.765//766// Note that this class operates with 3 kinds of indices:767// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);768// - MC operand indices (they refer operands in a MachineInstr/MCInst);769// - parsed operand indices (they refer operands in parsed operands array).770//771// For SINGLE components mapping between these indices is trivial.772// But things get more complicated for COMPONENT_X and773// COMPONENT_Y because these components share the same774// MachineInstr/MCInst and the same parsed operands array.775// Below is an example of component operand to parsed operand776// mapping for the following instruction:777//778// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1779//780// PARSED COMPONENT PARSED781// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX782// -------------------------------------------------------------------783// "v_dual_add_f32" 0784// v_dual_add_f32 v255 0 (DST) --> 1785// v4 1 (SRC0) --> 2786// v5 2 (SRC1) --> 3787// "::" 4788// "v_dual_mov_b32" 5789// v_dual_mov_b32 v6 0 (DST) --> 6790// v1 1 (SRC0) --> 7791// -------------------------------------------------------------------792//793class ComponentLayout {794private:795 // Regular MachineInstr/MCInst operands are ordered as follows:796 // dst, src0 [, other src operands]797 // VOPD MachineInstr/MCInst operands are ordered as follows:798 // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]799 // Each ComponentKind has operand indices defined below.800 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};801 802 // VOPD3 instructions may have 2 or 3 source modifiers, src2 modifier is not803 // used if there is tied accumulator. Indexing of this array:804 // MC_SRC_IDX[VOPD3ModsNum][SrcNo]. This returns an index for a SINGLE805 // instruction layout, add 1 for COMPONENT_X or COMPONENT_Y. For the second806 // component add OpX.MCSrcNum + OpX.VOPD3ModsNum.807 // For VOPD1/VOPD2 use column with zero modifiers.808 static constexpr unsigned SINGLE_MC_SRC_IDX[4][3] = {809 {1, 2, 3}, {2, 3, 4}, {2, 4, 5}, {2, 4, 6}};810 811 // Parsed operands of regular instructions are ordered as follows:812 // Mnemo dst src0 [vsrc1 ...]813 // Parsed VOPD operands are ordered as follows:814 // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'815 // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]816 // Each ComponentKind has operand indices defined below.817 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,818 4 /* + OpX.ParsedSrcNum */};819 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {820 2, 2, 5 /* + OpX.ParsedSrcNum */};821 822private:823 const ComponentKind Kind;824 const ComponentProps PrevComp;825 const unsigned VOPD3ModsNum;826 const int BitOp3Idx; // Index of bitop3 operand or -1827 828public:829 // Create layout for COMPONENT_X or SINGLE component.830 ComponentLayout(ComponentKind Kind, unsigned VOPD3ModsNum, int BitOp3Idx)831 : Kind(Kind), VOPD3ModsNum(VOPD3ModsNum), BitOp3Idx(BitOp3Idx) {832 assert(Kind == ComponentKind::SINGLE || Kind == ComponentKind::COMPONENT_X);833 }834 835 // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.836 ComponentLayout(const ComponentProps &OpXProps, unsigned VOPD3ModsNum,837 int BitOp3Idx)838 : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps),839 VOPD3ModsNum(VOPD3ModsNum), BitOp3Idx(BitOp3Idx) {}840 841public:842 // Return the index of dst operand in MCInst operands.843 unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }844 845 // Return the index of the specified src operand in MCInst operands.846 unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx, bool VOPD3) const {847 assert(CompSrcIdx < Component::MAX_SRC_NUM);848 849 if (Kind == SINGLE && CompSrcIdx == 2 && BitOp3Idx != -1)850 return BitOp3Idx;851 852 if (VOPD3) {853 return SINGLE_MC_SRC_IDX[VOPD3ModsNum][CompSrcIdx] + getPrevCompSrcNum() +854 getPrevCompVOPD3ModsNum() + (Kind != SINGLE ? 1 : 0);855 }856 857 return SINGLE_MC_SRC_IDX[0][CompSrcIdx] + getPrevCompSrcNum() +858 (Kind != SINGLE ? 1 : 0);859 }860 861 // Return the index of dst operand in the parsed operands array.862 unsigned getIndexOfDstInParsedOperands() const {863 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();864 }865 866 // Return the index of the specified src operand in the parsed operands array.867 unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {868 assert(CompSrcIdx < Component::MAX_SRC_NUM);869 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;870 }871 872private:873 unsigned getPrevCompSrcNum() const {874 return PrevComp.getCompSrcOperandsNum();875 }876 unsigned getPrevCompParsedSrcNum() const {877 return PrevComp.getCompParsedSrcOperandsNum();878 }879 unsigned getPrevCompVOPD3ModsNum() const {880 return PrevComp.getCompVOPD3ModsNum();881 }882};883 884// Layout and properties of VOPD components.885class ComponentInfo : public ComponentProps, public ComponentLayout {886public:887 // Create ComponentInfo for COMPONENT_X or SINGLE component.888 ComponentInfo(const MCInstrDesc &OpDesc,889 ComponentKind Kind = ComponentKind::SINGLE,890 bool VOP3Layout = false)891 : ComponentProps(OpDesc, VOP3Layout),892 ComponentLayout(Kind, getCompVOPD3ModsNum(), getBitOp3OperandIdx()) {}893 894 // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.895 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps,896 bool VOP3Layout = false)897 : ComponentProps(OpDesc, VOP3Layout),898 ComponentLayout(OpXProps, getCompVOPD3ModsNum(),899 getBitOp3OperandIdx()) {}900 901 // Map component operand index to parsed operand index.902 // Return 0 if the specified operand does not exist.903 unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;904};905 906// Properties of VOPD instructions.907class InstInfo {908private:909 const ComponentInfo CompInfo[COMPONENTS_NUM];910 911public:912 using RegIndices = std::array<MCRegister, Component::MAX_OPR_NUM>;913 914 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)915 : CompInfo{OpX, OpY} {}916 917 InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)918 : CompInfo{OprInfoX, OprInfoY} {}919 920 const ComponentInfo &operator[](size_t ComponentIdx) const {921 assert(ComponentIdx < COMPONENTS_NUM);922 return CompInfo[ComponentIdx];923 }924 925 // Check VOPD operands constraints.926 // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index927 // for the specified component and MC operand. The callback must return 0928 // if the operand is not a register or not a VGPR.929 // If \p SkipSrc is set to true then constraints for source operands are not930 // checked.931 // If \p AllowSameVGPR is set then same VGPRs are allowed for X and Y sources932 // even though it violates requirement to be from different banks.933 // If \p VOPD3 is set to true both dst registers allowed to be either odd934 // or even and instruction may have real src2 as opposed to tied accumulator.935 bool936 hasInvalidOperand(std::function<MCRegister(unsigned, unsigned)> GetRegIdx,937 const MCRegisterInfo &MRI, bool SkipSrc = false,938 bool AllowSameVGPR = false, bool VOPD3 = false) const {939 return getInvalidCompOperandIndex(GetRegIdx, MRI, SkipSrc, AllowSameVGPR,940 VOPD3)941 .has_value();942 }943 944 // Check VOPD operands constraints.945 // Return the index of an invalid component operand, if any.946 // If \p SkipSrc is set to true then constraints for source operands are not947 // checked except for being from the same halves of VGPR file on gfx1250.948 // If \p AllowSameVGPR is set then same VGPRs are allowed for X and Y sources949 // even though it violates requirement to be from different banks.950 // If \p VOPD3 is set to true both dst registers allowed to be either odd951 // or even and instruction may have real src2 as opposed to tied accumulator.952 std::optional<unsigned> getInvalidCompOperandIndex(953 std::function<MCRegister(unsigned, unsigned)> GetRegIdx,954 const MCRegisterInfo &MRI, bool SkipSrc = false,955 bool AllowSameVGPR = false, bool VOPD3 = false) const;956 957private:958 RegIndices959 getRegIndices(unsigned ComponentIdx,960 std::function<MCRegister(unsigned, unsigned)> GetRegIdx,961 bool VOPD3) const;962};963 964} // namespace VOPD965 966LLVM_READONLY967std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);968 969LLVM_READONLY970// Get properties of 2 single VOP1/VOP2 instructions971// used as components to create a VOPD instruction.972VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);973 974LLVM_READONLY975// Get properties of VOPD X and Y components.976VOPD::InstInfo getVOPDInstInfo(unsigned VOPDOpcode,977 const MCInstrInfo *InstrInfo);978 979LLVM_READONLY980bool isAsyncStore(unsigned Opc);981LLVM_READONLY982bool isTensorStore(unsigned Opc);983LLVM_READONLY984unsigned getTemporalHintType(const MCInstrDesc TID);985 986LLVM_READONLY987bool isTrue16Inst(unsigned Opc);988 989LLVM_READONLY990FPType getFPDstSelType(unsigned Opc);991 992LLVM_READONLY993bool isInvalidSingleUseConsumerInst(unsigned Opc);994 995LLVM_READONLY996bool isInvalidSingleUseProducerInst(unsigned Opc);997 998bool isDPMACCInstruction(unsigned Opc);999 1000LLVM_READONLY1001unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);1002 1003LLVM_READONLY1004unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);1005 1006void initDefaultAMDKernelCodeT(AMDGPUMCKernelCodeT &Header,1007 const MCSubtargetInfo *STI);1008 1009bool isGroupSegment(const GlobalValue *GV);1010bool isGlobalSegment(const GlobalValue *GV);1011bool isReadOnlySegment(const GlobalValue *GV);1012 1013/// \returns True if constants should be emitted to .text section for given1014/// target triple \p TT, false otherwise.1015bool shouldEmitConstantsToTextSection(const Triple &TT);1016 1017/// Returns a valid charcode or 0 in the first entry if this is a valid physical1018/// register name. Followed by the start register number, and the register1019/// width. Does not validate the number of registers exists in the class. Unlike1020/// parseAsmConstraintPhysReg, this does not expect the name to be wrapped in1021/// "{}".1022std::tuple<char, unsigned, unsigned> parseAsmPhysRegName(StringRef TupleString);1023 1024/// Returns a valid charcode or 0 in the first entry if this is a valid physical1025/// register constraint. Followed by the start register number, and the register1026/// width. Does not validate the number of registers exists in the class.1027std::tuple<char, unsigned, unsigned>1028parseAsmConstraintPhysReg(StringRef Constraint);1029 1030/// \returns Integer value requested using \p F's \p Name attribute.1031///1032/// \returns \p Default if attribute is not present.1033///1034/// \returns \p Default and emits error if requested value cannot be converted1035/// to integer.1036int getIntegerAttribute(const Function &F, StringRef Name, int Default);1037 1038/// \returns A pair of integer values requested using \p F's \p Name attribute1039/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired1040/// is false).1041///1042/// \returns \p Default if attribute is not present.1043///1044/// \returns \p Default and emits error if one of the requested values cannot be1045/// converted to integer, or \p OnlyFirstRequired is false and "second" value is1046/// not present.1047std::pair<unsigned, unsigned>1048getIntegerPairAttribute(const Function &F, StringRef Name,1049 std::pair<unsigned, unsigned> Default,1050 bool OnlyFirstRequired = false);1051 1052/// \returns A pair of integer values requested using \p F's \p Name attribute1053/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired1054/// is false).1055///1056/// \returns \p std::nullopt if attribute is not present.1057///1058/// \returns \p std::nullopt and emits error if one of the requested values1059/// cannot be converted to integer, or \p OnlyFirstRequired is false and1060/// "second" value is not present.1061std::optional<std::pair<unsigned, std::optional<unsigned>>>1062getIntegerPairAttribute(const Function &F, StringRef Name,1063 bool OnlyFirstRequired = false);1064 1065/// \returns Generate a vector of integer values requested using \p F's \p Name1066/// attribute.1067/// \returns A vector of size \p Size, with all elements set to \p DefaultVal,1068/// if any error occurs. The corresponding error will also be emitted.1069SmallVector<unsigned> getIntegerVecAttribute(const Function &F, StringRef Name,1070 unsigned Size,1071 unsigned DefaultVal);1072/// Similar to the function above, but returns std::nullopt if any error occurs.1073std::optional<SmallVector<unsigned>>1074getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size);1075 1076/// Checks if \p Val is inside \p MD, a !range-like metadata.1077bool hasValueInRangeLikeMetadata(const MDNode &MD, int64_t Val);1078 1079/// Represents the counter values to wait for in an s_waitcnt instruction.1080///1081/// Large values (including the maximum possible integer) can be used to1082/// represent "don't care" waits.1083struct Waitcnt {1084 unsigned LoadCnt = ~0u; // Corresponds to Vmcnt prior to gfx12.1085 unsigned ExpCnt = ~0u;1086 unsigned DsCnt = ~0u; // Corresponds to LGKMcnt prior to gfx12.1087 unsigned StoreCnt = ~0u; // Corresponds to VScnt on gfx10/gfx11.1088 unsigned SampleCnt = ~0u; // gfx12+ only.1089 unsigned BvhCnt = ~0u; // gfx12+ only.1090 unsigned KmCnt = ~0u; // gfx12+ only.1091 unsigned XCnt = ~0u; // gfx1250.1092 1093 Waitcnt() = default;1094 // Pre-gfx12 constructor.1095 Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)1096 : LoadCnt(VmCnt), ExpCnt(ExpCnt), DsCnt(LgkmCnt), StoreCnt(VsCnt) {}1097 1098 // gfx12+ constructor.1099 Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt,1100 unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt, unsigned XCnt)1101 : LoadCnt(LoadCnt), ExpCnt(ExpCnt), DsCnt(DsCnt), StoreCnt(StoreCnt),1102 SampleCnt(SampleCnt), BvhCnt(BvhCnt), KmCnt(KmCnt), XCnt(XCnt) {}1103 1104 bool hasWait() const { return StoreCnt != ~0u || hasWaitExceptStoreCnt(); }1105 1106 bool hasWaitExceptStoreCnt() const {1107 return LoadCnt != ~0u || ExpCnt != ~0u || DsCnt != ~0u ||1108 SampleCnt != ~0u || BvhCnt != ~0u || KmCnt != ~0u || XCnt != ~0u;1109 }1110 1111 bool hasWaitStoreCnt() const { return StoreCnt != ~0u; }1112 1113 Waitcnt combined(const Waitcnt &Other) const {1114 // Does the right thing provided self and Other are either both pre-gfx121115 // or both gfx12+.1116 return Waitcnt(1117 std::min(LoadCnt, Other.LoadCnt), std::min(ExpCnt, Other.ExpCnt),1118 std::min(DsCnt, Other.DsCnt), std::min(StoreCnt, Other.StoreCnt),1119 std::min(SampleCnt, Other.SampleCnt), std::min(BvhCnt, Other.BvhCnt),1120 std::min(KmCnt, Other.KmCnt), std::min(XCnt, Other.XCnt));1121 }1122};1123 1124// The following methods are only meaningful on targets that support1125// S_WAITCNT.1126 1127/// \returns Vmcnt bit mask for given isa \p Version.1128unsigned getVmcntBitMask(const IsaVersion &Version);1129 1130/// \returns Expcnt bit mask for given isa \p Version.1131unsigned getExpcntBitMask(const IsaVersion &Version);1132 1133/// \returns Lgkmcnt bit mask for given isa \p Version.1134unsigned getLgkmcntBitMask(const IsaVersion &Version);1135 1136/// \returns Waitcnt bit mask for given isa \p Version.1137unsigned getWaitcntBitMask(const IsaVersion &Version);1138 1139/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.1140unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);1141 1142/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.1143unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);1144 1145/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.1146unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);1147 1148/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa1149/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and1150/// \p Lgkmcnt respectively. Should not be used on gfx12+, the instruction1151/// which needs it is deprecated1152///1153/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:1154/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)1155/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)1156/// \p Vmcnt = \p Waitcnt[15:10] (gfx11)1157/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)1158/// \p Expcnt = \p Waitcnt[2:0] (gfx11)1159/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)1160/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)1161/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11)1162///1163void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt,1164 unsigned &Expcnt, unsigned &Lgkmcnt);1165 1166Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);1167 1168/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.1169unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,1170 unsigned Vmcnt);1171 1172/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.1173unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,1174 unsigned Expcnt);1175 1176/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.1177unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,1178 unsigned Lgkmcnt);1179 1180/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa1181/// \p Version. Should not be used on gfx12+, the instruction which needs1182/// it is deprecated1183///1184/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:1185/// Waitcnt[2:0] = \p Expcnt (gfx11+)1186/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)1187/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)1188/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)1189/// Waitcnt[9:4] = \p Lgkmcnt (gfx11)1190/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)1191/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)1192/// Waitcnt[15:10] = \p Vmcnt (gfx11)1193/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)1194///1195/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given1196/// isa \p Version.1197///1198unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt,1199 unsigned Expcnt, unsigned Lgkmcnt);1200 1201unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);1202 1203// The following methods are only meaningful on targets that support1204// S_WAIT_*CNT, introduced with gfx12.1205 1206/// \returns Loadcnt bit mask for given isa \p Version.1207/// Returns 0 for versions that do not support LOADcnt1208unsigned getLoadcntBitMask(const IsaVersion &Version);1209 1210/// \returns Samplecnt bit mask for given isa \p Version.1211/// Returns 0 for versions that do not support SAMPLEcnt1212unsigned getSamplecntBitMask(const IsaVersion &Version);1213 1214/// \returns Bvhcnt bit mask for given isa \p Version.1215/// Returns 0 for versions that do not support BVHcnt1216unsigned getBvhcntBitMask(const IsaVersion &Version);1217 1218/// \returns Dscnt bit mask for given isa \p Version.1219/// Returns 0 for versions that do not support DScnt1220unsigned getDscntBitMask(const IsaVersion &Version);1221 1222/// \returns Dscnt bit mask for given isa \p Version.1223/// Returns 0 for versions that do not support KMcnt1224unsigned getKmcntBitMask(const IsaVersion &Version);1225 1226/// \returns Xcnt bit mask for given isa \p Version.1227/// Returns 0 for versions that do not support Xcnt.1228unsigned getXcntBitMask(const IsaVersion &Version);1229 1230/// \return STOREcnt or VScnt bit mask for given isa \p Version.1231/// returns 0 for versions that do not support STOREcnt or VScnt.1232/// STOREcnt and VScnt are the same counter, the name used1233/// depends on the ISA version.1234unsigned getStorecntBitMask(const IsaVersion &Version);1235 1236// The following are only meaningful on targets that support1237// S_WAIT_LOADCNT_DSCNT and S_WAIT_STORECNT_DSCNT.1238 1239/// \returns Decoded Waitcnt structure from given \p LoadcntDscnt for given1240/// isa \p Version.1241Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt);1242 1243/// \returns Decoded Waitcnt structure from given \p StorecntDscnt for given1244/// isa \p Version.1245Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt);1246 1247/// \returns \p Loadcnt and \p Dscnt components of \p Decoded encoded as an1248/// immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa1249/// \p Version.1250unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);1251 1252/// \returns \p Storecnt and \p Dscnt components of \p Decoded encoded as an1253/// immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa1254/// \p Version.1255unsigned encodeStorecntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);1256 1257namespace Hwreg {1258 1259using HwregId = EncodingField<5, 0>;1260using HwregOffset = EncodingField<10, 6>;1261 1262struct HwregSize : EncodingField<15, 11, 32> {1263 using EncodingField::EncodingField;1264 constexpr uint64_t encode() const { return Value - 1; }1265 static ValueType decode(uint64_t Encoded) { return Encoded + 1; }1266};1267 1268using HwregEncoding = EncodingFields<HwregId, HwregOffset, HwregSize>;1269 1270} // namespace Hwreg1271 1272namespace DepCtr {1273 1274int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);1275int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,1276 const MCSubtargetInfo &STI);1277bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,1278 const MCSubtargetInfo &STI);1279bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,1280 bool &IsDefault, const MCSubtargetInfo &STI);1281 1282/// \returns Decoded VaVdst from given immediate \p Encoded.1283unsigned decodeFieldVaVdst(unsigned Encoded);1284 1285/// \returns Decoded VmVsrc from given immediate \p Encoded.1286unsigned decodeFieldVmVsrc(unsigned Encoded);1287 1288/// \returns Decoded SaSdst from given immediate \p Encoded.1289unsigned decodeFieldSaSdst(unsigned Encoded);1290 1291/// \returns Decoded VaSdst from given immediate \p Encoded.1292unsigned decodeFieldVaSdst(unsigned Encoded);1293 1294/// \returns Decoded VaVcc from given immediate \p Encoded.1295unsigned decodeFieldVaVcc(unsigned Encoded);1296 1297/// \returns Decoded SaSrc from given immediate \p Encoded.1298unsigned decodeFieldVaSsrc(unsigned Encoded);1299 1300/// \returns Decoded HoldCnt from given immediate \p Encoded.1301unsigned decodeFieldHoldCnt(unsigned Encoded);1302 1303/// \returns \p VmVsrc as an encoded Depctr immediate.1304unsigned encodeFieldVmVsrc(unsigned VmVsrc, const MCSubtargetInfo &STI);1305 1306/// \returns \p Encoded combined with encoded \p VmVsrc.1307unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);1308 1309/// \returns \p VaVdst as an encoded Depctr immediate.1310unsigned encodeFieldVaVdst(unsigned VaVdst, const MCSubtargetInfo &STI);1311 1312/// \returns \p Encoded combined with encoded \p VaVdst.1313unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);1314 1315/// \returns \p SaSdst as an encoded Depctr immediate.1316unsigned encodeFieldSaSdst(unsigned SaSdst, const MCSubtargetInfo &STI);1317 1318/// \returns \p Encoded combined with encoded \p SaSdst.1319unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);1320 1321/// \returns \p VaSdst as an encoded Depctr immediate.1322unsigned encodeFieldVaSdst(unsigned VaSdst, const MCSubtargetInfo &STI);1323 1324/// \returns \p Encoded combined with encoded \p VaSdst.1325unsigned encodeFieldVaSdst(unsigned Encoded, unsigned VaSdst);1326 1327/// \returns \p VaVcc as an encoded Depctr immediate.1328unsigned encodeFieldVaVcc(unsigned VaVcc, const MCSubtargetInfo &STI);1329 1330/// \returns \p Encoded combined with encoded \p VaVcc.1331unsigned encodeFieldVaVcc(unsigned Encoded, unsigned VaVcc);1332 1333/// \returns \p HoldCnt as an encoded Depctr immediate.1334unsigned encodeFieldHoldCnt(unsigned HoldCnt, const MCSubtargetInfo &STI);1335 1336/// \returns \p Encoded combined with encoded \p HoldCnt.1337unsigned encodeFieldHoldCnt(unsigned Encoded, unsigned HoldCnt);1338 1339/// \returns \p VaSsrc as an encoded Depctr immediate.1340unsigned encodeFieldVaSsrc(unsigned VaSsrc, const MCSubtargetInfo &STI);1341 1342/// \returns \p Encoded combined with encoded \p VaSsrc.1343unsigned encodeFieldVaSsrc(unsigned Encoded, unsigned VaSsrc);1344 1345} // namespace DepCtr1346 1347namespace Exp {1348 1349bool getTgtName(unsigned Id, StringRef &Name, int &Index);1350 1351LLVM_READONLY1352unsigned getTgtId(const StringRef Name);1353 1354LLVM_READNONE1355bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);1356 1357} // namespace Exp1358 1359namespace MTBUFFormat {1360 1361LLVM_READNONE1362int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);1363 1364void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);1365 1366int64_t getDfmt(const StringRef Name);1367 1368StringRef getDfmtName(unsigned Id);1369 1370int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);1371 1372StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);1373 1374bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);1375 1376bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);1377 1378int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);1379 1380StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);1381 1382bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);1383 1384int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,1385 const MCSubtargetInfo &STI);1386 1387bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);1388 1389unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);1390 1391} // namespace MTBUFFormat1392 1393namespace SendMsg {1394 1395LLVM_READNONE1396bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);1397 1398LLVM_READNONE1399bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,1400 bool Strict = true);1401 1402LLVM_READNONE1403bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,1404 const MCSubtargetInfo &STI, bool Strict = true);1405 1406LLVM_READNONE1407bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);1408 1409LLVM_READNONE1410bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);1411 1412void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,1413 uint16_t &StreamId, const MCSubtargetInfo &STI);1414 1415LLVM_READNONE1416uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId);1417 1418} // namespace SendMsg1419 1420unsigned getInitialPSInputAddr(const Function &F);1421 1422bool getHasColorExport(const Function &F);1423 1424bool getHasDepthExport(const Function &F);1425 1426bool hasDynamicVGPR(const Function &F);1427 1428// Returns the value of the "amdgpu-dynamic-vgpr-block-size" attribute, or 0 if1429// the attribute is missing or its value is invalid.1430unsigned getDynamicVGPRBlockSize(const Function &F);1431 1432LLVM_READNONE1433constexpr bool isShader(CallingConv::ID CC) {1434 switch (CC) {1435 case CallingConv::AMDGPU_VS:1436 case CallingConv::AMDGPU_LS:1437 case CallingConv::AMDGPU_HS:1438 case CallingConv::AMDGPU_ES:1439 case CallingConv::AMDGPU_GS:1440 case CallingConv::AMDGPU_PS:1441 case CallingConv::AMDGPU_CS_Chain:1442 case CallingConv::AMDGPU_CS_ChainPreserve:1443 case CallingConv::AMDGPU_CS:1444 return true;1445 default:1446 return false;1447 }1448}1449 1450LLVM_READNONE1451constexpr bool isGraphics(CallingConv::ID CC) {1452 return isShader(CC) || CC == CallingConv::AMDGPU_Gfx ||1453 CC == CallingConv::AMDGPU_Gfx_WholeWave;1454}1455 1456LLVM_READNONE1457constexpr bool isCompute(CallingConv::ID CC) {1458 return !isGraphics(CC) || CC == CallingConv::AMDGPU_CS;1459}1460 1461LLVM_READNONE1462constexpr bool isEntryFunctionCC(CallingConv::ID CC) {1463 switch (CC) {1464 case CallingConv::AMDGPU_KERNEL:1465 case CallingConv::SPIR_KERNEL:1466 case CallingConv::AMDGPU_VS:1467 case CallingConv::AMDGPU_GS:1468 case CallingConv::AMDGPU_PS:1469 case CallingConv::AMDGPU_CS:1470 case CallingConv::AMDGPU_ES:1471 case CallingConv::AMDGPU_HS:1472 case CallingConv::AMDGPU_LS:1473 return true;1474 default:1475 return false;1476 }1477}1478 1479LLVM_READNONE1480constexpr bool isChainCC(CallingConv::ID CC) {1481 switch (CC) {1482 case CallingConv::AMDGPU_CS_Chain:1483 case CallingConv::AMDGPU_CS_ChainPreserve:1484 return true;1485 default:1486 return false;1487 }1488}1489 1490// These functions are considered entrypoints into the current module, i.e. they1491// are allowed to be called from outside the current module. This is different1492// from isEntryFunctionCC, which is only true for functions that are entered by1493// the hardware. Module entry points include all entry functions but also1494// include functions that can be called from other functions inside or outside1495// the current module. Module entry functions are allowed to allocate LDS.1496LLVM_READNONE1497constexpr bool isModuleEntryFunctionCC(CallingConv::ID CC) {1498 switch (CC) {1499 case CallingConv::AMDGPU_Gfx:1500 return true;1501 default:1502 return isEntryFunctionCC(CC) || isChainCC(CC);1503 }1504}1505 1506LLVM_READNONE1507constexpr inline bool isKernel(CallingConv::ID CC) {1508 switch (CC) {1509 case CallingConv::AMDGPU_KERNEL:1510 case CallingConv::SPIR_KERNEL:1511 return true;1512 default:1513 return false;1514 }1515}1516 1517inline bool isKernel(const Function &F) { return isKernel(F.getCallingConv()); }1518 1519LLVM_READNONE1520constexpr bool canGuaranteeTCO(CallingConv::ID CC) {1521 return CC == CallingConv::Fast;1522}1523 1524/// Return true if we might ever do TCO for calls with this calling convention.1525LLVM_READNONE1526constexpr bool mayTailCallThisCC(CallingConv::ID CC) {1527 switch (CC) {1528 case CallingConv::C:1529 case CallingConv::AMDGPU_Gfx:1530 case CallingConv::AMDGPU_Gfx_WholeWave:1531 return true;1532 default:1533 return canGuaranteeTCO(CC);1534 }1535}1536 1537bool hasXNACK(const MCSubtargetInfo &STI);1538bool hasSRAMECC(const MCSubtargetInfo &STI);1539bool hasMIMG_R128(const MCSubtargetInfo &STI);1540bool hasA16(const MCSubtargetInfo &STI);1541bool hasG16(const MCSubtargetInfo &STI);1542bool hasPackedD16(const MCSubtargetInfo &STI);1543bool hasGDS(const MCSubtargetInfo &STI);1544unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler = false);1545unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI);1546 1547bool isSI(const MCSubtargetInfo &STI);1548bool isCI(const MCSubtargetInfo &STI);1549bool isVI(const MCSubtargetInfo &STI);1550bool isGFX9(const MCSubtargetInfo &STI);1551bool isGFX9_GFX10(const MCSubtargetInfo &STI);1552bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI);1553bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);1554bool isGFX8Plus(const MCSubtargetInfo &STI);1555bool isGFX9Plus(const MCSubtargetInfo &STI);1556bool isNotGFX9Plus(const MCSubtargetInfo &STI);1557bool isGFX10(const MCSubtargetInfo &STI);1558bool isGFX10_GFX11(const MCSubtargetInfo &STI);1559bool isGFX10Plus(const MCSubtargetInfo &STI);1560bool isNotGFX10Plus(const MCSubtargetInfo &STI);1561bool isGFX10Before1030(const MCSubtargetInfo &STI);1562bool isGFX11(const MCSubtargetInfo &STI);1563bool isGFX11Plus(const MCSubtargetInfo &STI);1564bool isGFX12(const MCSubtargetInfo &STI);1565bool isGFX12Plus(const MCSubtargetInfo &STI);1566bool isGFX1250(const MCSubtargetInfo &STI);1567bool supportsWGP(const MCSubtargetInfo &STI);1568bool isNotGFX12Plus(const MCSubtargetInfo &STI);1569bool isNotGFX11Plus(const MCSubtargetInfo &STI);1570bool isGCN3Encoding(const MCSubtargetInfo &STI);1571bool isGFX10_AEncoding(const MCSubtargetInfo &STI);1572bool isGFX10_BEncoding(const MCSubtargetInfo &STI);1573bool hasGFX10_3Insts(const MCSubtargetInfo &STI);1574bool isGFX10_3_GFX11(const MCSubtargetInfo &STI);1575bool isGFX90A(const MCSubtargetInfo &STI);1576bool isGFX940(const MCSubtargetInfo &STI);1577bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);1578bool hasMAIInsts(const MCSubtargetInfo &STI);1579bool hasVOPD(const MCSubtargetInfo &STI);1580bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI);1581 1582inline bool supportsWave32(const MCSubtargetInfo &STI) {1583 return AMDGPU::isGFX10Plus(STI) && !AMDGPU::isGFX1250(STI);1584}1585 1586int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);1587unsigned hasKernargPreload(const MCSubtargetInfo &STI);1588bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST);1589 1590/// Is Reg - scalar register1591bool isSGPR(MCRegister Reg, const MCRegisterInfo *TRI);1592 1593/// \returns if \p Reg occupies the high 16-bits of a 32-bit register.1594bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI);1595 1596/// If \p Reg is a pseudo reg, return the correct hardware register given1597/// \p STI otherwise return \p Reg.1598MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI);1599 1600/// Convert hardware register \p Reg to a pseudo register1601LLVM_READNONE1602MCRegister mc2PseudoReg(MCRegister Reg);1603 1604LLVM_READNONE1605bool isInlineValue(MCRegister Reg);1606 1607/// Is this an AMDGPU specific source operand? These include registers,1608/// inline constants, literals and mandatory literals (KImm).1609constexpr bool isSISrcOperand(const MCOperandInfo &OpInfo) {1610 return OpInfo.OperandType >= AMDGPU::OPERAND_SRC_FIRST &&1611 OpInfo.OperandType <= AMDGPU::OPERAND_SRC_LAST;1612}1613 1614inline bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {1615 return isSISrcOperand(Desc.operands()[OpNo]);1616}1617 1618/// Is this a KImm operand?1619bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);1620 1621/// Is this floating-point operand?1622bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);1623 1624/// Does this operand support only inlinable literals?1625bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);1626 1627/// Get the size in bits of a register from the register class \p RC.1628unsigned getRegBitWidth(unsigned RCID);1629 1630/// Get the size in bits of a register from the register class \p RC.1631unsigned getRegBitWidth(const MCRegisterClass &RC);1632 1633LLVM_READNONE1634inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {1635 switch (OpInfo.OperandType) {1636 case AMDGPU::OPERAND_REG_IMM_INT32:1637 case AMDGPU::OPERAND_REG_IMM_FP32:1638 case AMDGPU::OPERAND_REG_INLINE_C_INT32:1639 case AMDGPU::OPERAND_REG_INLINE_C_FP32:1640 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:1641 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:1642 case AMDGPU::OPERAND_REG_IMM_V2INT32:1643 case AMDGPU::OPERAND_REG_IMM_V2FP32:1644 case AMDGPU::OPERAND_KIMM32:1645 case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 41646 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:1647 return 4;1648 1649 case AMDGPU::OPERAND_REG_IMM_INT64:1650 case AMDGPU::OPERAND_REG_IMM_FP64:1651 case AMDGPU::OPERAND_REG_INLINE_C_INT64:1652 case AMDGPU::OPERAND_REG_INLINE_C_FP64:1653 case AMDGPU::OPERAND_REG_INLINE_AC_FP64:1654 case AMDGPU::OPERAND_KIMM64:1655 return 8;1656 1657 case AMDGPU::OPERAND_REG_IMM_INT16:1658 case AMDGPU::OPERAND_REG_IMM_BF16:1659 case AMDGPU::OPERAND_REG_IMM_FP16:1660 case AMDGPU::OPERAND_REG_INLINE_C_INT16:1661 case AMDGPU::OPERAND_REG_INLINE_C_BF16:1662 case AMDGPU::OPERAND_REG_INLINE_C_FP16:1663 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:1664 case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:1665 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:1666 case AMDGPU::OPERAND_REG_IMM_V2INT16:1667 case AMDGPU::OPERAND_REG_IMM_V2BF16:1668 case AMDGPU::OPERAND_REG_IMM_V2FP16:1669 case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:1670 return 2;1671 1672 default:1673 llvm_unreachable("unhandled operand type");1674 }1675}1676 1677LLVM_READNONE1678inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {1679 return getOperandSize(Desc.operands()[OpNo]);1680}1681 1682/// Is this literal inlinable, and not one of the values intended for floating1683/// point values.1684LLVM_READNONE1685inline bool isInlinableIntLiteral(int64_t Literal) {1686 return Literal >= -16 && Literal <= 64;1687}1688 1689/// Is this literal inlinable1690LLVM_READNONE1691bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);1692 1693LLVM_READNONE1694bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);1695 1696LLVM_READNONE1697bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi);1698 1699LLVM_READNONE1700bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi);1701 1702LLVM_READNONE1703bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi);1704 1705LLVM_READNONE1706std::optional<unsigned> getInlineEncodingV2I16(uint32_t Literal);1707 1708LLVM_READNONE1709std::optional<unsigned> getInlineEncodingV2BF16(uint32_t Literal);1710 1711LLVM_READNONE1712std::optional<unsigned> getInlineEncodingV2F16(uint32_t Literal);1713 1714LLVM_READNONE1715bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType);1716 1717LLVM_READNONE1718bool isInlinableLiteralV2I16(uint32_t Literal);1719 1720LLVM_READNONE1721bool isInlinableLiteralV2BF16(uint32_t Literal);1722 1723LLVM_READNONE1724bool isInlinableLiteralV2F16(uint32_t Literal);1725 1726LLVM_READNONE1727bool isValid32BitLiteral(uint64_t Val, bool IsFP64);1728 1729LLVM_READNONE1730int64_t encode32BitLiteral(int64_t Imm, OperandType Type, bool IsLit);1731 1732bool isArgPassedInSGPR(const Argument *Arg);1733 1734bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);1735 1736LLVM_READONLY bool isPackedFP32Inst(unsigned Opc);1737 1738LLVM_READONLY1739bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,1740 int64_t EncodedOffset);1741 1742LLVM_READONLY1743bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,1744 int64_t EncodedOffset, bool IsBuffer);1745 1746/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate1747/// offsets.1748uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);1749 1750/// \returns The encoding that will be used for \p ByteOffset in the1751/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX101752/// S_LOAD instructions have a signed offset, on other subtargets it is1753/// unsigned. S_BUFFER has an unsigned offset for all subtargets.1754std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,1755 int64_t ByteOffset, bool IsBuffer,1756 bool HasSOffset = false);1757 1758/// \return The encoding that can be used for a 32-bit literal offset in an SMRD1759/// instruction. This is only useful on CI.s1760std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,1761 int64_t ByteOffset);1762 1763/// For pre-GFX12 FLAT instructions the offset must be positive;1764/// MSB is ignored and forced to zero.1765///1766/// \return The number of bits available for the signed offset field in flat1767/// instructions. Note that some forms of the instruction disallow negative1768/// offsets.1769unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);1770 1771/// \returns true if this offset is small enough to fit in the SMRD1772/// offset field. \p ByteOffset should be the offset in bytes and1773/// not the encoded offset.1774bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);1775 1776LLVM_READNONE1777inline bool isLegalDPALU_DPPControl(const MCSubtargetInfo &ST, unsigned DC) {1778 if (isGFX12(ST))1779 return DC >= DPP::ROW_SHARE_FIRST && DC <= DPP::ROW_SHARE_LAST;1780 if (isGFX90A(ST))1781 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;1782 return false;1783}1784 1785/// \returns true if an instruction may have a 64-bit VGPR operand.1786bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc,1787 const MCSubtargetInfo &ST);1788 1789/// \returns true if an instruction is a DP ALU DPP without any 64-bit operands.1790bool isDPALU_DPP32BitOpc(unsigned Opc);1791 1792/// \returns true if an instruction is a DP ALU DPP.1793bool isDPALU_DPP(const MCInstrDesc &OpDesc, const MCInstrInfo &MII,1794 const MCSubtargetInfo &ST);1795 1796/// \returns true if the intrinsic is divergent1797bool isIntrinsicSourceOfDivergence(unsigned IntrID);1798 1799/// \returns true if the intrinsic is uniform1800bool isIntrinsicAlwaysUniform(unsigned IntrID);1801 1802/// \returns a register class for the physical register \p Reg if it is a VGPR1803/// or nullptr otherwise.1804const MCRegisterClass *getVGPRPhysRegClass(MCRegister Reg,1805 const MCRegisterInfo &MRI);1806 1807/// \returns the MODE bits which have to be set by the S_SET_VGPR_MSB for the1808/// physical register \p Reg.1809unsigned getVGPREncodingMSBs(MCRegister Reg, const MCRegisterInfo &MRI);1810 1811/// If \p Reg is a low VGPR return a corresponding high VGPR with \p MSBs set.1812MCRegister getVGPRWithMSBs(MCRegister Reg, unsigned MSBs,1813 const MCRegisterInfo &MRI);1814 1815// Returns a table for the opcode with a given \p Desc to map the VGPR MSB1816// set by the S_SET_VGPR_MSB to one of 4 sources. In case of VOPD returns 21817// maps, one for X and one for Y component.1818std::pair<const AMDGPU::OpName *, const AMDGPU::OpName *>1819getVGPRLoweringOperandTables(const MCInstrDesc &Desc);1820 1821/// \returns true if a memory instruction supports scale_offset modifier.1822bool supportsScaleOffset(const MCInstrInfo &MII, unsigned Opcode);1823 1824/// \returns lds block size in terms of dwords. \p1825/// This is used to calculate the lds size encoded for PAL metadata 3.0+ which1826/// must be defined in terms of bytes.1827unsigned getLdsDwGranularity(const MCSubtargetInfo &ST);1828 1829class ClusterDimsAttr {1830public:1831 enum class Kind { Unknown, NoCluster, VariableDims, FixedDims };1832 1833 ClusterDimsAttr() = default;1834 1835 Kind getKind() const { return AttrKind; }1836 1837 bool isUnknown() const { return getKind() == Kind::Unknown; }1838 1839 bool isNoCluster() const { return getKind() == Kind::NoCluster; }1840 1841 bool isFixedDims() const { return getKind() == Kind::FixedDims; }1842 1843 bool isVariableDims() const { return getKind() == Kind::VariableDims; }1844 1845 void setUnknown() { *this = ClusterDimsAttr(Kind::Unknown); }1846 1847 void setNoCluster() { *this = ClusterDimsAttr(Kind::NoCluster); }1848 1849 void setVariableDims() { *this = ClusterDimsAttr(Kind::VariableDims); }1850 1851 /// \returns the dims stored. Note that this function can only be called if1852 /// the kind is \p Fixed.1853 const std::array<unsigned, 3> &getDims() const;1854 1855 bool operator==(const ClusterDimsAttr &RHS) const {1856 return AttrKind == RHS.AttrKind && Dims == RHS.Dims;1857 }1858 1859 std::string to_string() const;1860 1861 static ClusterDimsAttr get(const Function &F);1862 1863private:1864 enum Encoding { EncoNoCluster = 0, EncoVariableDims = 1024 };1865 1866 ClusterDimsAttr(Kind AttrKind) : AttrKind(AttrKind) {}1867 1868 std::array<unsigned, 3> Dims = {0, 0, 0};1869 1870 Kind AttrKind = Kind::Unknown;1871};1872 1873} // end namespace AMDGPU1874 1875raw_ostream &operator<<(raw_ostream &OS,1876 const AMDGPU::IsaInfo::TargetIDSetting S);1877 1878} // end namespace llvm1879 1880#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H1881