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1 2//===-- VOP1Instructions.td - Vector Instruction Definitions --------------===//3//4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.5// See https://llvm.org/LICENSE.txt for license information.6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception7//8//===----------------------------------------------------------------------===//9 10//===----------------------------------------------------------------------===//11// VOP1 Classes12//===----------------------------------------------------------------------===//13 14class VOP1e <bits<8> op, VOPProfile P> : Enc32 {15 bits<8> vdst;16 bits<9> src0;17 18 let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, ?);19 let Inst{16-9} = op;20 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);21 let Inst{31-25} = 0x3f; //encoding22}23 24class VOP1_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {25 bits<8> vdst;26 27 let Inst{8-0} = 0xf9; // sdwa28 let Inst{16-9} = op;29 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);30 let Inst{31-25} = 0x3f; // encoding31}32 33class VOP1_SDWA9Ae <bits<8> op, VOPProfile P> : VOP_SDWA9Ae <P> {34 bits<8> vdst;35 36 let Inst{8-0} = 0xf9; // sdwa37 let Inst{16-9} = op;38 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);39 let Inst{31-25} = 0x3f; // encoding40}41 42class VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP1Only = 0> :43 VOP_Pseudo <opName, !if(VOP1Only, "", "_e32"), P, P.Outs32, P.Ins32, "", pattern> {44 45 let AsmOperands = P.Asm32;46 47 let Size = 4;48 let mayLoad = 0;49 let mayStore = 0;50 let hasSideEffects = 0;51 52 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);53 54 let mayRaiseFPException = ReadsModeReg;55 56 let VOP1 = 1;57 let VALU = 1;58 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);59 60 let AsmVariantName = AMDGPUAsmVariants.Default;61}62 63class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemonic > :64 VOP_Real <ps>,65 InstSI <ps.OutOperandList, ps.InOperandList, real_name # ps.AsmOperands, []>,66 SIMCInstr <ps.PseudoInstr, EncodingFamily> {67 68 let VALU = 1;69 let VOP1 = 1;70 let isPseudo = 0;71 let isCodeGenOnly = 0;72 73 let Constraints = ps.Constraints;74 75 // copy relevant pseudo op flags76 let SubtargetPredicate = ps.SubtargetPredicate;77 let OtherPredicates = ps.OtherPredicates;78 let True16Predicate = ps.True16Predicate;79 let AsmMatchConverter = ps.AsmMatchConverter;80 let AsmVariantName = ps.AsmVariantName;81 let Constraints = ps.Constraints;82 let TSFlags = ps.TSFlags;83 let UseNamedOperandTable = ps.UseNamedOperandTable;84 let Uses = ps.Uses;85 let Defs = ps.Defs;86 let SchedRW = ps.SchedRW;87 let mayLoad = ps.mayLoad;88 let mayStore = ps.mayStore;89 let TRANS = ps.TRANS;90 let isConvergent = ps.isConvergent;91}92 93class VOP1_Real_Gen <VOP1_Pseudo ps, GFXGen Gen, string real_name = ps.Mnemonic> :94 VOP1_Real <ps, Gen.Subtarget, real_name> {95 let AssemblerPredicate = Gen.AssemblerPredicate;96 let DecoderNamespace = Gen.DecoderNamespace;97}98 99class VOP1_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :100 VOP_SDWA_Pseudo <OpName, P, pattern> {101 let AsmMatchConverter = "cvtSdwaVOP1";102}103 104class VOP1_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :105 VOP_DPP_Pseudo <OpName, P, pattern> {106}107 108multiclass VOP1Inst <string opName, VOPProfile P,109 SDPatternOperator node = null_frag, int VOPDOp = -1> {110 // We only want to set this on the basic, non-SDWA or DPP forms.111 defvar should_mov_imm = !or(!eq(opName, "v_mov_b32"),112 !eq(opName, "v_mov_b64"));113 114 let isMoveImm = should_mov_imm in {115 if !eq(VOPDOp, -1) then116 def _e32 : VOP1_Pseudo <opName, P>;117 else118 // Only for V_MOV_B32119 def _e32 : VOP1_Pseudo <opName, P>, VOPD_Component<VOPDOp, opName>;120 def _e64 : VOP3InstBase <opName, P, node>;121 }122 123 if P.HasExtSDWA then124 def _sdwa : VOP1_SDWA_Pseudo <opName, P>;125 126 if P.HasExtDPP then127 def _dpp : VOP1_DPP_Pseudo <opName, P>;128 129 if P.HasExtVOP3DPP then130 def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {131 let SubtargetPredicate = isGFX11Plus;132 }133 else if P.HasExt64BitDPP then134 def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {135 let OtherPredicates = [HasDPALU_DPP];136 }137 138 def : LetDummies, AMDGPUMnemonicAlias<opName#"_e32", opName>;139 def : LetDummies, AMDGPUMnemonicAlias<opName#"_e64", opName>;140 141 if P.HasExtSDWA then142 def : LetDummies, AMDGPUMnemonicAlias<opName#"_sdwa", opName>;143 144 if P.HasExtDPP then145 def : LetDummies, AMDGPUMnemonicAlias<opName#"_dpp", opName, AMDGPUAsmVariants.DPP>;146}147 148multiclass VOP1Inst_t16_with_profiles<string opName,149 VOPProfile P,150 VOPProfile P_t16,151 VOPProfile P_fake16,152 SDPatternOperator node = null_frag> {153 let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts] in {154 defm NAME : VOP1Inst<opName, P, node>;155 }156 let OtherPredicates = [UseRealTrue16Insts] in {157 defm _t16 : VOP1Inst<opName#"_t16", P_t16, node>;158 }159 let OtherPredicates = [UseFakeTrue16Insts] in {160 defm _fake16 : VOP1Inst<opName#"_fake16", P_fake16, node>;161 }162}163 164multiclass VOP1Inst_t16<string opName, VOPProfile P,165 SDPatternOperator node = null_frag> :166 VOP1Inst_t16_with_profiles<opName, P, VOPProfile_True16<P>, VOPProfile_Fake16<P>, node>;167 168// Special profile for instructions which have clamp169// and output modifiers (but have no input modifiers)170class VOPProfileI2F<ValueType dstVt, ValueType srcVt> :171 VOPProfile<[dstVt, srcVt, untyped, untyped]> {172 173 let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);174 let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);175 let AsmVOP3Base = "$vdst, $src0$clamp$omod";176 177 let HasModifiers = 0;178 let HasClamp = 1;179}180 181def VOP1_F64_I32 : VOPProfileI2F <f64, i32>;182def VOP1_F32_I32 : VOPProfileI2F <f32, i32>;183def VOP1_F16_I16 : VOPProfileI2F <f16, i16>;184def VOP1_F16_I16_t16 : VOPProfile_True16 <VOP_F16_I16> {185 let HasClamp = 1;186}187def VOP1_F16_I16_fake16 : VOPProfile_Fake16<VOP_F16_I16> {188 let HasModifiers = 0;189 let HasOMod = 1;190 let HasClamp = 1;191}192 193def VOP_NOP_PROFILE : VOPProfile <[untyped, untyped, untyped, untyped]>{194 let HasExtVOP3DPP = 0;195}196 197// OMod clears exceptions when set. OMod was always an operand, but its198// now explicitly set.199class VOP_SPECIAL_OMOD_PROF<ValueType dstVt, ValueType srcVt> :200 VOPProfile<[dstVt, srcVt, untyped, untyped]> {201 202 let HasOMod = 1;203}204def VOP_I32_F32_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f32>;205def VOP_I32_F64_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f64>;206def VOP_I16_F16_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i16, f16>;207def VOP_I16_F16_SPECIAL_OMOD_t16 : VOPProfile_True16<VOP_I16_F16> {208 let HasOMod = 1;209}210def VOP_I16_F16_SPECIAL_OMOD_fake16 : VOPProfile_Fake16<VOP_I16_F16> {211 let HasOMod = 1;212}213 214 215def VOP_F64_F64_NO_DPP : VOPProfile <[f64, f64, untyped, untyped]> {216 let HasExtVOP3DPP = 0;217 let HasExt64BitDPP = 0;218}219 220//===----------------------------------------------------------------------===//221// VOP1 Instructions222//===----------------------------------------------------------------------===//223 224defm V_NOP : VOP1Inst <"v_nop", VOP_NOP_PROFILE>;225 226def VOPProfile_MOV : VOPProfile <[i32, i32, untyped, untyped]> {227 let InsVOPDX = (ins Src0RC32:$src0X);228 let InsVOPDY = (ins Src0RC32:$src0Y);229}230 231let isReMaterializable = 1, isAsCheapAsAMove = 1 in {232defm V_MOV_B32 : VOP1Inst <"v_mov_b32", VOPProfile_MOV, null_frag, 0x8>;233 234let SubtargetPredicate = isGFX940orGFX1250, SchedRW = [Write64Bit] in235defm V_MOV_B64 : VOP1Inst <"v_mov_b64", VOP_I64_I64>;236} // End isMoveImm = 1237 238def VOP_READFIRSTLANE : VOPProfile <[i32, i32, untyped, untyped]> {239 let DstRC = RegisterOperand<SReg_32_XM0>;240 let Src0RC32 = VRegOrLdsSrc_32;241 let Asm32 = " $vdst, $src0";242}243 244// FIXME: Specify SchedRW for READFIRSTLANE_B32245// TODO: There is VOP3 encoding also246def V_READFIRSTLANE_B32 : VOP1_Pseudo <"v_readfirstlane_b32", VOP_READFIRSTLANE,247 [], 1> {248 let isConvergent = 1;249}250 251foreach vt = Reg32Types.types in {252 def : GCNPat<(vt (int_amdgcn_readfirstlane (vt VRegOrLdsSrc_32:$src0))),253 (V_READFIRSTLANE_B32 (vt VRegOrLdsSrc_32:$src0))254 >;255}256 257let HasOMod = 0, HasClamp = 0 in {258 def VOPProfile_CVT_F32_BF16_gfx1250_t16 : VOPProfile_True16 <VOP_F32_BF16>;259 let HasOpSel = 1, EmitDstSel = 0 in260 def VOPProfile_CVT_F32_BF16_gfx1250_fake16 : VOPProfile_Fake16 <VOP_F32_BF16>;261} // End HasOMod = 0, HasClamp = 0262 263let isReMaterializable = 1 in {264let SchedRW = [WriteDoubleCvt] in {265// OMod clears exceptions when set in this instruction266defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64_SPECIAL_OMOD, fp_to_sint>;267 268let mayRaiseFPException = 0 in {269defm V_CVT_F64_I32 : VOP1Inst <"v_cvt_f64_i32", VOP1_F64_I32, sint_to_fp>;270}271 272defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64, fpround>;273defm V_CVT_F64_F32 : VOP1Inst <"v_cvt_f64_f32", VOP_F64_F32, any_fpextend>;274// OMod clears exceptions when set in this instruction275defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64_SPECIAL_OMOD, fp_to_uint>;276 277let mayRaiseFPException = 0 in {278defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP1_F64_I32, uint_to_fp>;279}280 281} // End SchedRW = [WriteDoubleCvt]282 283let SchedRW = [WriteFloatCvt] in {284 285// XXX: Does this really not raise exceptions? The manual claims the286// 16-bit ones can.287let mayRaiseFPException = 0 in {288defm V_CVT_F32_I32 : VOP1Inst <"v_cvt_f32_i32", VOP1_F32_I32, sint_to_fp>;289defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP1_F32_I32, uint_to_fp>;290}291 292// OMod clears exceptions when set in these 2 instructions293defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_uint>;294defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_sint>;295let FPDPRounding = 1, isReMaterializable = 0 in {296 // V_CVT_F16_F32 and V_CVT_F32_F16 are special cases because they are297 // present in targets without Has16BitInsts. Otherwise they could use298 // class VOP1Inst_t16299 let OtherPredicates = [NotHasTrue16BitInsts] in300 defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, any_fpround>;301 let OtherPredicates = [UseRealTrue16Insts] in302 defm V_CVT_F16_F32_t16 : VOP1Inst <"v_cvt_f16_f32_t16", VOPProfile_True16<VOP_F16_F32>, any_fpround>;303 let OtherPredicates = [UseFakeTrue16Insts] in304 defm V_CVT_F16_F32_fake16 : VOP1Inst <"v_cvt_f16_f32_fake16", VOPProfile_Fake16<VOP_F16_F32>, any_fpround>;305} // End FPDPRounding = 1, isReMaterializable = 0306let OtherPredicates = [NotHasTrue16BitInsts] in307 defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_F16, any_fpextend>;308let OtherPredicates = [UseRealTrue16Insts] in309 defm V_CVT_F32_F16_t16 : VOP1Inst <"v_cvt_f32_f16_t16", VOPProfile_True16<VOP_F32_F16>, any_fpextend>;310let OtherPredicates = [UseFakeTrue16Insts] in311 defm V_CVT_F32_F16_fake16 : VOP1Inst <"v_cvt_f32_f16_fake16", VOPProfile_Fake16<VOP_F32_F16>, any_fpextend>;312 313let SubtargetPredicate = HasGFX950Insts, OtherPredicates = [HasBF16ConversionInsts] in {314 defm V_CVT_F32_BF16 : VOP1Inst_t16 <"v_cvt_f32_bf16", VOP_F32_BF16>;315}316let SubtargetPredicate = isGFX1250Plus, OtherPredicates = [HasBF16ConversionInsts] in {317 let True16Predicate = UseRealTrue16Insts in318 defm V_CVT_F32_BF16_gfx1250_t16 : VOP1Inst <"V_CVT_F32_BF16_gfx1250_t16", VOPProfile_CVT_F32_BF16_gfx1250_t16>;319 let True16Predicate = UseFakeTrue16Insts in320 defm V_CVT_F32_BF16_gfx1250_fake16 : VOP1Inst <"V_CVT_F32_BF16_gfx1250_fake16", VOPProfile_CVT_F32_BF16_gfx1250_fake16>;321}322 323let ReadsModeReg = 0, mayRaiseFPException = 0 in {324defm V_CVT_RPI_I32_F32 : VOP1Inst <"v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>;325defm V_CVT_FLR_I32_F32 : VOP1Inst <"v_cvt_flr_i32_f32", VOP_I32_F32, cvt_flr_i32_f32>;326defm V_CVT_OFF_F32_I4 : VOP1Inst <"v_cvt_off_f32_i4", VOP1_F32_I32, int_amdgcn_cvt_off_f32_i4>;327} // End ReadsModeReg = 0, mayRaiseFPException = 0328} // End SchedRW = [WriteFloatCvt]329 330let ReadsModeReg = 0, mayRaiseFPException = 0 in {331defm V_CVT_F32_UBYTE0 : VOP1Inst <"v_cvt_f32_ubyte0", VOP1_F32_I32, AMDGPUcvt_f32_ubyte0>;332defm V_CVT_F32_UBYTE1 : VOP1Inst <"v_cvt_f32_ubyte1", VOP1_F32_I32, AMDGPUcvt_f32_ubyte1>;333defm V_CVT_F32_UBYTE2 : VOP1Inst <"v_cvt_f32_ubyte2", VOP1_F32_I32, AMDGPUcvt_f32_ubyte2>;334defm V_CVT_F32_UBYTE3 : VOP1Inst <"v_cvt_f32_ubyte3", VOP1_F32_I32, AMDGPUcvt_f32_ubyte3>;335} // ReadsModeReg = 0, mayRaiseFPException = 0336 337defm V_FRACT_F32 : VOP1Inst <"v_fract_f32", VOP_F32_F32, AMDGPUfract>;338defm V_TRUNC_F32 : VOP1Inst <"v_trunc_f32", VOP_F32_F32, ftrunc>;339defm V_CEIL_F32 : VOP1Inst <"v_ceil_f32", VOP_F32_F32, fceil>;340defm V_RNDNE_F32 : VOP1Inst <"v_rndne_f32", VOP_F32_F32, froundeven>;341defm V_FLOOR_F32 : VOP1Inst <"v_floor_f32", VOP_F32_F32, ffloor>;342 343let TRANS = 1, SchedRW = [WriteTrans32] in {344defm V_EXP_F32 : VOP1Inst <"v_exp_f32", VOP_F32_F32, AMDGPUexp>;345defm V_LOG_F32 : VOP1Inst <"v_log_f32", VOP_F32_F32, AMDGPUlog>;346defm V_RCP_F32 : VOP1Inst <"v_rcp_f32", VOP_F32_F32, AMDGPUrcp>;347defm V_RCP_IFLAG_F32 : VOP1Inst <"v_rcp_iflag_f32", VOP_F32_F32, AMDGPUrcp_iflag>;348defm V_RSQ_F32 : VOP1Inst <"v_rsq_f32", VOP_F32_F32, AMDGPUrsq>;349defm V_SQRT_F32 : VOP1Inst <"v_sqrt_f32", VOP_F32_F32, int_amdgcn_sqrt>;350} // End TRANS = 1, SchedRW = [WriteTrans32]351 352let TRANS = 1, SchedRW = [WriteTrans64] in {353defm V_RCP_F64 : VOP1Inst <"v_rcp_f64", VOP_F64_F64_NO_DPP, AMDGPUrcp>;354defm V_RSQ_F64 : VOP1Inst <"v_rsq_f64", VOP_F64_F64_NO_DPP, AMDGPUrsq>;355defm V_SQRT_F64 : VOP1Inst <"v_sqrt_f64", VOP_F64_F64_NO_DPP, int_amdgcn_sqrt>;356} // End TRANS = 1, SchedRW = [WriteTrans64]357 358let TRANS = 1, SchedRW = [WriteTrans32] in {359defm V_SIN_F32 : VOP1Inst <"v_sin_f32", VOP_F32_F32, AMDGPUsin>;360defm V_COS_F32 : VOP1Inst <"v_cos_f32", VOP_F32_F32, AMDGPUcos>;361 362let SubtargetPredicate = HasTanhInsts in363defm V_TANH_F32 : VOP1Inst <"v_tanh_f32", VOP_F32_F32, int_amdgcn_tanh>;364} // End TRANS = 1, SchedRW = [WriteTrans32]365 366defm V_NOT_B32 : VOP1Inst <"v_not_b32", VOP_I32_I32>;367defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32, DivergentUnaryFrag<bitreverse>>;368defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32, AMDGPUffbh_u32>;369defm V_FFBL_B32 : VOP1Inst <"v_ffbl_b32", VOP_I32_I32, AMDGPUffbl_b32>;370defm V_FFBH_I32 : VOP1Inst <"v_ffbh_i32", VOP_I32_I32, AMDGPUffbh_i32>;371 372let SchedRW = [WriteDoubleAdd] in {373defm V_FREXP_EXP_I32_F64 : VOP1Inst <"v_frexp_exp_i32_f64", VOP_I32_F64_SPECIAL_OMOD, int_amdgcn_frexp_exp>;374defm V_FREXP_MANT_F64 : VOP1Inst <"v_frexp_mant_f64", VOP_F64_F64, int_amdgcn_frexp_mant>;375let FPDPRounding = 1 in {376defm V_FRACT_F64 : VOP1Inst <"v_fract_f64", VOP_F64_F64, AMDGPUfract>;377} // End FPDPRounding = 1378} // End SchedRW = [WriteDoubleAdd]379 380defm V_FREXP_EXP_I32_F32 : VOP1Inst <"v_frexp_exp_i32_f32", VOP_I32_F32, int_amdgcn_frexp_exp>;381defm V_FREXP_MANT_F32 : VOP1Inst <"v_frexp_mant_f32", VOP_F32_F32, int_amdgcn_frexp_mant>;382} // End isReMaterializable = 1383 384defm V_CLREXCP : VOP1Inst <"v_clrexcp", VOP_NO_EXT<VOP_NONE>>;385 386// Restrict src0 to be VGPR387def VOP_MOVRELS : VOPProfile<[i32, i32, untyped, untyped]> {388 let Src0RC32 = VRegSrc_32;389 let Src0RC64 = VRegSrc_32;390}391 392def VOP_PERMLANE_SWAP : VOPProfile<[i32, i32, untyped, untyped]> {393 let Outs32 = (outs DstRC:$vdst, VRegSrc_32:$src0_out);394 let Outs64 = (outs DstRC64:$vdst, VRegSrc_32:$src0_out);395 396 let Src0RC32 = VRegSrc_32;397 let Src0RC64 = VRegSrc_32;398 let HasClamp = 0;399 let HasExtVOP3DPP = 0;400 let HasExtDPP = 0;401 let HasExtSDWA = 0;402 403 let Ins32 = (ins DstRC:$vdst_in, Src0RC32:$src0);404 let Ins64 = (ins DstRC64:$vdst_in, Src0RC64:$src0, Dpp16FI:$fi, DppBoundCtrl:$bound_ctrl);405 let InsVOP3OpSel = (ins Src0RC64:$vdst_in, Src0RC64:$src0, Dpp16FI:$fi, DppBoundCtrl:$bound_ctrl);406 let Asm64 = "$vdst, $src0$bound_ctrl$fi";407}408 409// Special case because there are no true output operands. Hack vdst410// to be a src operand. The custom inserter must add a tied implicit411// def and use of the super register since there seems to be no way to412// add an implicit def of a virtual register in tablegen.413class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {414 let Src0RC32 = VOPDstOperand<VGPR_32>;415 let Src0RC64 = VOPDstOperand<VGPR_32>;416 417 let Outs = (outs);418 let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);419 let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);420 let Asm32 = getAsm32<1, 1>.ret;421 422 let OutsSDWA = (outs Src0RC32:$vdst);423 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,424 Clamp:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,425 src0_sel:$src0_sel);426 let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret;427 428 let OutsDPP = (outs Src0RC32:$vdst);429 let InsDPP16 = (ins Src0RC32:$old, Src0RC32:$src0,430 dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,431 DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl, Dpp16FI:$fi);432 let AsmDPP16 = getAsmDPP16<1, 1, 0>.ret;433 let InsDPP8 = (ins Src0RC32:$old, Src0RC32:$src0, dpp8:$dpp8, Dpp8FI:$fi);434 let AsmDPP8 = getAsmDPP8<1, 1, 0>.ret;435 436 let OutsVOP3DPP = (outs Src0RC64:$vdst);437 let InsVOP3DPP = getInsVOP3DPP<InsVOP3Base, Src0RC64, NumSrcArgs>.ret;438 let InsVOP3DPP16 = getInsVOP3DPP16<InsVOP3Base, Src0RC64, NumSrcArgs>.ret;439 let InsVOP3DPP8 = getInsVOP3DPP8<InsVOP3Base, Src0RC64, NumSrcArgs>.ret;440 441 let AsmVOP3Base =442 getAsmVOP3Base<NumSrcArgs, 1 /* HasDst */, HasClamp,443 HasOpSel, HasOMod, IsVOP3P, HasModifiers,444 HasModifiers, HasModifiers, HasModifiers>.ret;445 446 let HasDst = 0;447 let EmitDst = 1; // force vdst emission448}449 450def VOP_MOVRELD : VOP_MOVREL<VSrc_b32>;451def VOP_MOVRELSD : VOP_MOVREL<VRegSrc_32>;452 453let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in {454 // v_movreld_b32 is a special case because the destination output455 // register is really a source. It isn't actually read (but may be456 // written), and is only to provide the base register to start457 // indexing from. Tablegen seems to not let you define an implicit458 // virtual register output for the super register being written into,459 // so this must have an implicit def of the register added to it.460defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>;461defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_MOVRELS>;462defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>;463} // End Uses = [M0, EXEC]464 465let isReMaterializable = 1 in {466let SubtargetPredicate = isGFX6GFX7 in {467 let TRANS = 1, SchedRW = [WriteTrans32] in {468 defm V_LOG_CLAMP_F32 :469 VOP1Inst<"v_log_clamp_f32", VOP_F32_F32, int_amdgcn_log_clamp>;470 defm V_RCP_CLAMP_F32 :471 VOP1Inst<"v_rcp_clamp_f32", VOP_F32_F32>;472 defm V_RCP_LEGACY_F32 :473 VOP1Inst<"v_rcp_legacy_f32", VOP_F32_F32, AMDGPUrcp_legacy>;474 defm V_RSQ_CLAMP_F32 :475 VOP1Inst<"v_rsq_clamp_f32", VOP_F32_F32, AMDGPUrsq_clamp>;476 defm V_RSQ_LEGACY_F32 :477 VOP1Inst<"v_rsq_legacy_f32", VOP_F32_F32, int_amdgcn_rsq_legacy>;478 } // End TRANS = 1, SchedRW = [WriteTrans32]479 480 let SchedRW = [WriteTrans64] in {481 defm V_RCP_CLAMP_F64 :482 VOP1Inst<"v_rcp_clamp_f64", VOP_F64_F64>;483 defm V_RSQ_CLAMP_F64 :484 VOP1Inst<"v_rsq_clamp_f64", VOP_F64_F64, AMDGPUrsq_clamp>;485 } // End SchedRW = [WriteTrans64]486} // End SubtargetPredicate = isGFX6GFX7487 488let SubtargetPredicate = isGFX7GFX8GFX9 in {489 let TRANS = 1, SchedRW = [WriteTrans32] in {490 defm V_LOG_LEGACY_F32 : VOP1Inst<"v_log_legacy_f32", VOP_F32_F32>;491 defm V_EXP_LEGACY_F32 : VOP1Inst<"v_exp_legacy_f32", VOP_F32_F32>;492 } // End TRANS = 1, SchedRW = [WriteTrans32]493} // End SubtargetPredicate = isGFX7GFX8GFX9494 495let SubtargetPredicate = isGFX7Plus in {496 let SchedRW = [WriteDoubleAdd] in {497 defm V_TRUNC_F64 : VOP1Inst<"v_trunc_f64", VOP_F64_F64, ftrunc>;498 defm V_CEIL_F64 : VOP1Inst<"v_ceil_f64", VOP_F64_F64, fceil>;499 defm V_RNDNE_F64 : VOP1Inst<"v_rndne_f64", VOP_F64_F64, froundeven>;500 defm V_FLOOR_F64 : VOP1Inst<"v_floor_f64", VOP_F64_F64, ffloor>;501 } // End SchedRW = [WriteDoubleAdd]502} // End SubtargetPredicate = isGFX7Plus503} // End isReMaterializable = 1504 505let FPDPRounding = 1 in {506defm V_CVT_F16_U16 : VOP1Inst_t16_with_profiles <"v_cvt_f16_u16", VOP1_F16_I16, VOP1_F16_I16_t16, VOP1_F16_I16_fake16, uint_to_fp>;507defm V_CVT_F16_I16 : VOP1Inst_t16_with_profiles <"v_cvt_f16_i16", VOP1_F16_I16, VOP1_F16_I16_t16, VOP1_F16_I16_fake16, sint_to_fp>;508 509} // End FPDPRounding = 1510// OMod clears exceptions when set in these two instructions511defm V_CVT_U16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_u16_f16",512 VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16, fp_to_uint>;513defm V_CVT_I16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_i16_f16",514 VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16, fp_to_sint>;515 516 517let HasClamp = 0, HasOMod = 0 in {518def V_TRANS_BF16_Profile : VOPProfile <[bf16, bf16, untyped, untyped]>;519def V_TRANS_BF16_t16_Profile : VOPProfile_True16 <VOP_BF16_BF16>;520def V_TRANS_BF16_fake16_Profile : VOPProfile_Fake16 <VOP_BF16_BF16>;521}522 523let TRANS = 1, SchedRW = [WriteTrans32] in {524defm V_RCP_F16 : VOP1Inst_t16 <"v_rcp_f16", VOP_F16_F16, AMDGPUrcp>;525defm V_SQRT_F16 : VOP1Inst_t16 <"v_sqrt_f16", VOP_F16_F16, any_amdgcn_sqrt>;526defm V_RSQ_F16 : VOP1Inst_t16 <"v_rsq_f16", VOP_F16_F16, AMDGPUrsq>;527defm V_LOG_F16 : VOP1Inst_t16 <"v_log_f16", VOP_F16_F16, AMDGPUlogf16>;528defm V_EXP_F16 : VOP1Inst_t16 <"v_exp_f16", VOP_F16_F16, AMDGPUexpf16>;529defm V_SIN_F16 : VOP1Inst_t16 <"v_sin_f16", VOP_F16_F16, AMDGPUsin>;530defm V_COS_F16 : VOP1Inst_t16 <"v_cos_f16", VOP_F16_F16, AMDGPUcos>;531 532let SubtargetPredicate = HasTanhInsts in {533defm V_TANH_F16 : VOP1Inst_t16 <"v_tanh_f16", VOP_F16_F16, int_amdgcn_tanh>;534}535 536let SubtargetPredicate = HasBF16TransInsts in {537defm V_TANH_BF16 : VOP1Inst_t16_with_profiles<"v_tanh_bf16", V_TRANS_BF16_Profile,538 V_TRANS_BF16_t16_Profile, V_TRANS_BF16_fake16_Profile,539 int_amdgcn_tanh>;540defm V_RCP_BF16 : VOP1Inst_t16_with_profiles<"v_rcp_bf16", V_TRANS_BF16_Profile,541 V_TRANS_BF16_t16_Profile, V_TRANS_BF16_fake16_Profile,542 AMDGPUrcp>;543defm V_SQRT_BF16 : VOP1Inst_t16_with_profiles<"v_sqrt_bf16", V_TRANS_BF16_Profile,544 V_TRANS_BF16_t16_Profile, V_TRANS_BF16_fake16_Profile,545 any_amdgcn_sqrt>;546defm V_RSQ_BF16 : VOP1Inst_t16_with_profiles<"v_rsq_bf16", V_TRANS_BF16_Profile,547 V_TRANS_BF16_t16_Profile, V_TRANS_BF16_fake16_Profile,548 AMDGPUrsq>;549defm V_LOG_BF16 : VOP1Inst_t16_with_profiles<"v_log_bf16", V_TRANS_BF16_Profile,550 V_TRANS_BF16_t16_Profile, V_TRANS_BF16_fake16_Profile,551 AMDGPUlogf16>;552defm V_EXP_BF16 : VOP1Inst_t16_with_profiles<"v_exp_bf16", V_TRANS_BF16_Profile,553 V_TRANS_BF16_t16_Profile, V_TRANS_BF16_fake16_Profile,554 AMDGPUexpf16>;555defm V_SIN_BF16 : VOP1Inst_t16_with_profiles<"v_sin_bf16", V_TRANS_BF16_Profile,556 V_TRANS_BF16_t16_Profile, V_TRANS_BF16_fake16_Profile,557 AMDGPUsin>;558defm V_COS_BF16 : VOP1Inst_t16_with_profiles<"v_cos_bf16", V_TRANS_BF16_Profile,559 V_TRANS_BF16_t16_Profile, V_TRANS_BF16_fake16_Profile,560 AMDGPUcos>;561}562} // End TRANS = 1, SchedRW = [WriteTrans32]563defm V_FREXP_MANT_F16 : VOP1Inst_t16 <"v_frexp_mant_f16", VOP_F16_F16, int_amdgcn_frexp_mant>;564defm V_FREXP_EXP_I16_F16 : VOP1Inst_t16_with_profiles <"v_frexp_exp_i16_f16",565 VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16, int_amdgcn_frexp_exp>;566defm V_FLOOR_F16 : VOP1Inst_t16 <"v_floor_f16", VOP_F16_F16, ffloor>;567defm V_CEIL_F16 : VOP1Inst_t16 <"v_ceil_f16", VOP_F16_F16, fceil>;568defm V_TRUNC_F16 : VOP1Inst_t16 <"v_trunc_f16", VOP_F16_F16, ftrunc>;569defm V_RNDNE_F16 : VOP1Inst_t16 <"v_rndne_f16", VOP_F16_F16, froundeven>;570let FPDPRounding = 1 in {571defm V_FRACT_F16 : VOP1Inst_t16 <"v_fract_f16", VOP_F16_F16, AMDGPUfract>;572} // End FPDPRounding = 1573 574let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in {575def : GCNPat<576 (f32 (f16_to_fp i16:$src)),577 (V_CVT_F32_F16_e32 $src)578>;579def : GCNPat<580 (i16 (AMDGPUfp_to_f16 f32:$src)),581 (V_CVT_F16_F32_e32 $src)582>;583}584let True16Predicate = UseRealTrue16Insts in {585def : GCNPat<586 (f32 (f16_to_fp i16:$src)),587 (V_CVT_F32_F16_t16_e32 $src)588>;589def : GCNPat<590 (i16 (AMDGPUfp_to_f16 f32:$src)),591 (V_CVT_F16_F32_t16_e32 $src)592>;593}594let True16Predicate = UseFakeTrue16Insts in {595def : GCNPat<596 (f32 (f16_to_fp i16:$src)),597 (V_CVT_F32_F16_fake16_e32 $src)598>;599def : GCNPat<600 (i16 (AMDGPUfp_to_f16 f32:$src)),601 (V_CVT_F16_F32_fake16_e32 $src)602>;603}604 605def VOP_SWAP_I32 : VOPProfile<[i32, i32, untyped, untyped]> {606 let Outs32 = (outs VGPR_32:$vdst, VRegSrc_32:$vdst1);607 let Ins32 = (ins VRegSrc_32:$src0, VGPR_32:$src1);608 let Asm32 = " $vdst, $src0";609}610 611let SubtargetPredicate = isGFX9Plus in {612 def V_SWAP_B32 : VOP1_Pseudo<"v_swap_b32", VOP_SWAP_I32, [], 1> {613 let Constraints = "$vdst = $src1, $vdst1 = $src0";614 let SchedRW = [Write64Bit, Write64Bit];615 }616 617 let isReMaterializable = 1 in618 defm V_SAT_PK_U8_I16 : VOP1Inst_t16<"v_sat_pk_u8_i16", VOP_I16_I32>;619} // End SubtargetPredicate = isGFX9Plus620 621let mayRaiseFPException = 0, SubtargetPredicate = HasCvtNormInsts in {622defm V_CVT_NORM_I16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_norm_i16_f16",623 VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16>;624defm V_CVT_NORM_U16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_norm_u16_f16",625 VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16>;626} // End mayRaiseFPException = 0, SubtargetPredicate = HasCvtNormInsts627 628let SubtargetPredicate = isGFX9Only in {629 defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>;630} // End SubtargetPredicate = isGFX9Only631 632class VOPProfile_Base_CVT_F32_F8<ValueType vt> : VOPProfileI2F <vt, i32> {633 let HasExtDPP = 1;634 let HasExtSDWA = 1;635 let HasExtSDWA9 = 1;636 let HasExt = 1;637 let DstRCSDWA = getVALUDstForVT<vt>.ret;638 let InsSDWA = (ins Bin32SDWAInputMods:$src0_modifiers, Src0SDWA:$src0,639 Clamp:$clamp, omod:$omod, src0_sel:$src0_sel);640 let AsmSDWA = "$vdst, $src0_modifiers$clamp$omod $src0_sel"; // No dst_sel641 let AsmSDWA9 = AsmSDWA;642 let EmitDstSel = 0;643}644 645def VOPProfileCVT_F32_F8 : VOPProfile_Base_CVT_F32_F8 <f32>;646def VOPProfileCVT_PK_F32_F8 : VOPProfile_Base_CVT_F32_F8 <v2f32>;647 648let OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0,649 SchedRW = [WriteFloatCvt] in {650 defm V_CVT_F32_FP8 : VOP1Inst<"v_cvt_f32_fp8", VOPProfileCVT_F32_F8>;651 defm V_CVT_F32_BF8 : VOP1Inst<"v_cvt_f32_bf8", VOPProfileCVT_F32_F8>;652 defm V_CVT_PK_F32_FP8 : VOP1Inst<"v_cvt_pk_f32_fp8", VOPProfileCVT_PK_F32_F8>;653 defm V_CVT_PK_F32_BF8 : VOP1Inst<"v_cvt_pk_f32_bf8", VOPProfileCVT_PK_F32_F8>;654}655 656class Cvt_F32_F8_Pat<SDPatternOperator node, int index,657 VOP1_SDWA_Pseudo inst_sdwa> : GCNPat<658 (f32 (node i32:$src, index)),659 (inst_sdwa 0, $src, 0, 0, index)660>;661 662let SubtargetPredicate = HasFP8ConversionInsts in {663let OtherPredicates = [HasCvtFP8VOP1Bug] in {664 def : GCNPat<(f32 (int_amdgcn_cvt_f32_fp8 i32:$src, 0)),665 (V_CVT_F32_FP8_sdwa 0, $src, 0, 0, 0)>;666 def : GCNPat<(f32 (int_amdgcn_cvt_f32_bf8 i32:$src, 0)),667 (V_CVT_F32_BF8_sdwa 0, $src, 0, 0, 0)>;668}669 670let OtherPredicates = [HasNoCvtFP8VOP1Bug, HasSDWA] in { // FIXME: HasSDWA is a substitute for !gfx12671 def : GCNPat<(f32 (int_amdgcn_cvt_f32_fp8 i32:$src, 0)),672 (V_CVT_F32_FP8_e32 $src)>;673 def : GCNPat<(f32 (int_amdgcn_cvt_f32_bf8 i32:$src, 0)),674 (V_CVT_F32_BF8_e32 $src)>;675}676 677let OtherPredicates = [HasSDWA] in {678foreach Index = [1, 2, 3] in {679 def : Cvt_F32_F8_Pat<int_amdgcn_cvt_f32_fp8, Index, V_CVT_F32_FP8_sdwa>;680 def : Cvt_F32_F8_Pat<int_amdgcn_cvt_f32_bf8, Index, V_CVT_F32_BF8_sdwa>;681}682} // End OtherPredicates = [HasSDWA]683 684} // End SubtargetPredicate = HasFP8ConversionInsts685 686class Cvt_PK_F32_F8_Pat<SDPatternOperator node, int index,687 VOP1_Pseudo inst_e32, VOP1_SDWA_Pseudo inst_sdwa> : GCNPat<688 (v2f32 (node i32:$src, index)),689 !if (index,690 (inst_sdwa 0, $src, 0, 0, SDWA.WORD_1),691 (inst_e32 $src))692>;693 694let SubtargetPredicate = HasFP8ConversionInsts, OtherPredicates = [HasSDWA] in {695 foreach Index = [0, -1] in {696 def : Cvt_PK_F32_F8_Pat<int_amdgcn_cvt_pk_f32_fp8, Index,697 V_CVT_PK_F32_FP8_e32, V_CVT_PK_F32_FP8_sdwa>;698 def : Cvt_PK_F32_F8_Pat<int_amdgcn_cvt_pk_f32_bf8, Index,699 V_CVT_PK_F32_BF8_e32, V_CVT_PK_F32_BF8_sdwa>;700 }701}702 703let HasClamp = 0, HasOMod = 0, HasExtDPP = 0, HasExtVOP3DPP = 0,704 HasOpSel = 1 in {705 // Input modifiers are not supported706 // NB: fake16 VOP1 does not support op_sel.707 def VOPProfile_Base_CVT_PK_F32_F8_fake16 : VOPProfile_Fake16<VOPProfile<[v2f32, f16, untyped, untyped]>> {708 let Src0Mod = IntT16InputMods<1/*IsFake16*/>;709 }710 def VOPProfile_Base_CVT_PK_F32_F8_t16 : VOPProfile_True16<VOPProfile<[v2f32, f16, untyped, untyped]>> {711 let Src0Mod = IntT16InputMods<0/*IsFake16*/>;712 }713}714 715class VOPProfile_Base_CVT_F_F8_ByteSel<ValueType DstVT, bit _HasClamp = 0> :716 VOPProfile<[DstVT, i32, untyped, untyped]> {717 let HasClamp = _HasClamp;718 let HasFP8SrcByteSel = 1;719 let HasOpSel = 0;720 let HasExtDPP = 1;721 let HasExtVOP3DPP = 1;722 let HasExtSDWA = 0;723 let HasOMod = 0;724 let HasModifiers = 0;725}726 727let IsSingle = 0, HasOpSel = 1, HasModifiers = 1 in {728def V_CVT_F16_F8_Profile : VOPProfile_Base_CVT_F_F8_ByteSel<f16>;729def V_CVT_F16_F8_True16_Profile : VOP3_Profile_True16<V_CVT_F16_F8_Profile>;730def V_CVT_F16_F8_Fake16_Profile : VOP3_Profile_Fake16<V_CVT_F16_F8_Profile>;731}732 733let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts],734 mayRaiseFPException = 0, SchedRW = [WriteFloatCvt] in {735 let SubtargetPredicate = isGFX12PlusNot12_50 in736 defm V_CVT_F32_FP8_OP_SEL : VOP1Inst<"v_cvt_f32_fp8_op_sel", VOPProfile_Base_CVT_F_F8_ByteSel<f32>>;737 let SubtargetPredicate = isGFX125xOnly in738 defm V_CVT_F32_FP8_gfx1250 : VOP1Inst<"v_cvt_f32_fp8_gfx1250", VOPProfile_Base_CVT_F_F8_ByteSel<f32, 1>>;739 740 defm V_CVT_F32_BF8_OP_SEL : VOP1Inst<"v_cvt_f32_bf8_op_sel", VOPProfile_Base_CVT_F_F8_ByteSel<f32>>;741 742 let True16Predicate = UseFakeTrue16Insts in {743 defm V_CVT_PK_F32_FP8_fake16 : VOP1Inst<"v_cvt_pk_f32_fp8_fake16", VOPProfile_Base_CVT_PK_F32_F8_fake16>;744 defm V_CVT_PK_F32_BF8_fake16 : VOP1Inst<"v_cvt_pk_f32_bf8_fake16", VOPProfile_Base_CVT_PK_F32_F8_fake16>;745 }746 let True16Predicate = UseRealTrue16Insts in {747 defm V_CVT_PK_F32_FP8_t16 : VOP1Inst<"v_cvt_pk_f32_fp8_t16", VOPProfile_Base_CVT_PK_F32_F8_t16>;748 defm V_CVT_PK_F32_BF8_t16 : VOP1Inst<"v_cvt_pk_f32_bf8_t16", VOPProfile_Base_CVT_PK_F32_F8_t16>;749 }750}751 752class Cvt_F_F8_Pat_ByteSel<SDPatternOperator node, VOP3_Pseudo inst, bit HasOpSel = 0> : GCNPat<753 (node i32:$src0, timm:$byte_sel),754 !if(HasOpSel, (inst 0, $src0, (as_i32timm $byte_sel)),755 (inst $src0, (as_i32timm $byte_sel)))756>;757 758let OtherPredicates = [HasFP8ConversionInsts] in {759 let SubtargetPredicate = isGFX12PlusNot12_50 in760 def : Cvt_F_F8_Pat_ByteSel<int_amdgcn_cvt_f32_fp8, V_CVT_F32_FP8_OP_SEL_e64>;761 let SubtargetPredicate = isGFX125xOnly in {762 def : GCNPat<(int_amdgcn_cvt_f32_fp8 i32:$src0, timm:$byte_sel),763 (V_CVT_F32_FP8_gfx1250_e64 $src0, DSTCLAMP.NONE, (as_i32timm $byte_sel))>;764 def : GCNPat<(int_amdgcn_cvt_f32_fp8_e5m3 i32:$src0, timm:$byte_sel),765 (V_CVT_F32_FP8_gfx1250_e64 $src0, DSTCLAMP.ENABLE, (as_i32timm $byte_sel))>;766 }767 let SubtargetPredicate = isGFX12Plus in768 def : Cvt_F_F8_Pat_ByteSel<int_amdgcn_cvt_f32_bf8, V_CVT_F32_BF8_OP_SEL_e64>;769}770 771class Cvt_PK_F32_F8_Pat_OpSel<SDPatternOperator node, int index,772 VOP1_Pseudo inst_e32, VOP3_Pseudo inst_e64> : GCNPat<773 (v2f32 (node i32:$src, index)),774 !if (index,775 (inst_e64 SRCMODS.OP_SEL_0, $src, 0),776 (inst_e32 $src))777>;778 779let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts] in {780 foreach Index = [0, -1] in {781 def : Cvt_PK_F32_F8_Pat_OpSel<int_amdgcn_cvt_pk_f32_fp8, Index,782 V_CVT_PK_F32_FP8_fake16_e32, V_CVT_PK_F32_FP8_fake16_e64>;783 def : Cvt_PK_F32_F8_Pat_OpSel<int_amdgcn_cvt_pk_f32_bf8, Index,784 V_CVT_PK_F32_BF8_fake16_e32, V_CVT_PK_F32_BF8_fake16_e64>;785 }786}787 788// FIXME-TRUE16: True16 versions of these instructions are untested.789let HasExtSDWA = 0, HasOpSel = 1, EmitDstSel = 0, HasOMod = 0, HasModifiers = 1 in {790def VOPProfile_CVT_PK_F16_F8 : VOPProfile<[v2f16, i16, untyped, untyped]>;791def VOPProfile_CVT_PK_F16_F8_true16 : VOP3_Profile_True16<VOPProfile_CVT_PK_F16_F8>;792def VOPProfile_CVT_PK_F16_F8_fake16 : VOP3_Profile_Fake16<VOPProfile_CVT_PK_F16_F8>;793}794 795let SubtargetPredicate = isGFX1250Plus in {796 let mayRaiseFPException = 0, SchedRW = [WriteFloatCvt] in {797 defm V_CVT_F16_FP8 : VOP1Inst_t16_with_profiles<"v_cvt_f16_fp8",798 V_CVT_F16_F8_Profile, V_CVT_F16_F8_True16_Profile, V_CVT_F16_F8_Fake16_Profile>;799 defm V_CVT_F16_BF8 : VOP1Inst_t16_with_profiles<"v_cvt_f16_bf8",800 V_CVT_F16_F8_Profile, V_CVT_F16_F8_True16_Profile, V_CVT_F16_F8_Fake16_Profile>;801 defm V_CVT_PK_F16_FP8 : VOP1Inst_t16_with_profiles<"v_cvt_pk_f16_fp8",802 VOPProfile_CVT_PK_F16_F8, VOPProfile_CVT_PK_F16_F8_true16, VOPProfile_CVT_PK_F16_F8_fake16,803 int_amdgcn_cvt_pk_f16_fp8>;804 defm V_CVT_PK_F16_BF8 : VOP1Inst_t16_with_profiles<"v_cvt_pk_f16_bf8",805 VOPProfile_CVT_PK_F16_F8, VOPProfile_CVT_PK_F16_F8_true16, VOPProfile_CVT_PK_F16_F8_fake16,806 int_amdgcn_cvt_pk_f16_bf8>;807 }808 809 let True16Predicate = UseRealTrue16Insts in {810 def : Cvt_F_F8_Pat_ByteSel<int_amdgcn_cvt_f16_fp8, V_CVT_F16_FP8_t16_e64, 1>;811 def : Cvt_F_F8_Pat_ByteSel<int_amdgcn_cvt_f16_bf8, V_CVT_F16_BF8_t16_e64, 1>;812 }813 let True16Predicate = UseFakeTrue16Insts in {814 def : Cvt_F_F8_Pat_ByteSel<int_amdgcn_cvt_f16_fp8, V_CVT_F16_FP8_fake16_e64, 1>;815 def : Cvt_F_F8_Pat_ByteSel<int_amdgcn_cvt_f16_bf8, V_CVT_F16_BF8_fake16_e64, 1>;816 }817 818 defm V_SAT_PK4_I4_I8 : VOP1Inst_t16<"v_sat_pk4_i4_i8", VOP1_I16_I32, int_amdgcn_sat_pk4_i4_i8>;819 defm V_SAT_PK4_U4_U8 : VOP1Inst_t16<"v_sat_pk4_u4_u8", VOP1_I16_I32, int_amdgcn_sat_pk4_u4_u8>;820} // End SubtargetPredicate = isGFX1250Plus821 822let SubtargetPredicate = isGFX10Plus in {823 defm V_PIPEFLUSH : VOP1Inst<"v_pipeflush", VOP_NO_EXT<VOP_NONE>>;824 825 let Uses = [M0] in {826 defm V_MOVRELSD_2_B32 :827 VOP1Inst<"v_movrelsd_2_b32", VOP_MOVRELSD>;828 829 def V_SWAPREL_B32 : VOP1_Pseudo<"v_swaprel_b32", VOP_SWAP_I32, [], 1> {830 let Constraints = "$vdst = $src1, $vdst1 = $src0";831 let SchedRW = [Write64Bit, Write64Bit];832 }833 } // End Uses = [M0]834} // End SubtargetPredicate = isGFX10Plus835 836def VOPProfileAccMov : VOP_NO_EXT<VOP_I32_I32> {837 let DstRC = RegisterOperand<AGPR_32>;838 let Src0RC32 = ARegSrc_32;839 let Asm32 = " $vdst, $src0";840}841 842def V_ACCVGPR_MOV_B32 : VOP1_Pseudo<"v_accvgpr_mov_b32", VOPProfileAccMov, [], 1> {843 let SubtargetPredicate = isGFX90APlus;844 let isReMaterializable = 1;845 let isAsCheapAsAMove = 1;846}847 848def VOP_SWAP_I16 : VOPProfile_True16<VOP_I16_I16> {849 let Outs32 = (outs VOPDstOperand_t16Lo128:$vdst,850 VOPSrcEncodedDstOperand_t16Lo128:$vdst1);851 let Ins32 = (ins VOPSrcEncodedDstOperand_t16Lo128:$src0,852 VOPDstOperand_t16Lo128:$src1);853 let Asm32 = "$vdst, $src0";854}855 856let SubtargetPredicate = isGFX11Plus in {857 def V_SWAP_B16 : VOP1_Pseudo<"v_swap_b16", VOP_SWAP_I16, [], /* VOP1Only= */true> {858 let Constraints = "$vdst = $src1, $vdst1 = $src0";859 let SchedRW = [Write64Bit, Write64Bit];860 let True16Predicate = UseRealTrue16Insts;861 }862 // Restrict src0 to be VGPR863 def V_PERMLANE64_B32 : VOP1_Pseudo<"v_permlane64_b32", VOP_MOVRELS,864 [], /*VOP1Only=*/ 1>;865 let isAsCheapAsAMove = 1 in866 defm V_MOV_B16 : VOP1Inst_t16<"v_mov_b16", VOP_I16_I16>;867 defm V_NOT_B16 : VOP1Inst_t16<"v_not_b16", VOP_I16_I16>;868 defm V_CVT_I32_I16 : VOP1Inst_t16<"v_cvt_i32_i16", VOP_I32_I16>;869 defm V_CVT_U32_U16 : VOP1Inst_t16<"v_cvt_u32_u16", VOP_I32_I16>;870} // End SubtargetPredicate = isGFX11Plus871 872let SubtargetPredicate = HasPrngInst in873defm V_PRNG_B32 : VOP1Inst <"v_prng_b32", VOP_I32_I32, int_amdgcn_prng_b32>;874 875let Constraints = "$vdst = $vdst_in, $src0_out = $src0",876 SchedRW = [Write32Bit, Write32Bit],877 isConvergent = 1 in {878let SubtargetPredicate = HasPermlane16Swap in {879defm V_PERMLANE16_SWAP_B32 : VOP1Inst<"v_permlane16_swap_b32", VOP_PERMLANE_SWAP>;880}881 882let SubtargetPredicate = HasPermlane32Swap in {883defm V_PERMLANE32_SWAP_B32 : VOP1Inst<"v_permlane32_swap_b32", VOP_PERMLANE_SWAP>;884}885}886 887foreach vt = Reg32Types.types in {888 def : GCNPat<(int_amdgcn_permlane64 (vt VRegSrc_32:$src0)),889 (vt (V_PERMLANE64_B32 (vt VRegSrc_32:$src0)))890 >;891}892 893//===----------------------------------------------------------------------===//894// Target-specific instruction encodings.895//===----------------------------------------------------------------------===//896 897class VOP1_DPP<bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile p = ps.Pfl, bit isDPP16 = 0> :898 VOP_DPP<ps.OpName, p, isDPP16> {899 let hasSideEffects = ps.hasSideEffects;900 let Defs = ps.Defs;901 let SchedRW = ps.SchedRW;902 let Uses = ps.Uses;903 let TRANS = ps.TRANS;904 let SubtargetPredicate = ps.SubtargetPredicate;905 let OtherPredicates = ps.OtherPredicates;906 907 bits<8> vdst;908 let Inst{8-0} = 0xfa;909 let Inst{16-9} = op;910 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);911 let Inst{31-25} = 0x3f;912}913 914class VOP1_DPP16<bits<8> op, VOP1_DPP_Pseudo ps, int subtarget, VOPProfile p = ps.Pfl> :915 VOP1_DPP<op, ps, p, 1>,916 SIMCInstr <ps.PseudoInstr, subtarget> {917 let AssemblerPredicate = HasDPP16;918}919 920class VOP1_DPP16_Gen<bits<8> op, VOP1_DPP_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> :921 VOP1_DPP16 <op, ps, Gen.Subtarget, p> {922 let AssemblerPredicate = Gen.AssemblerPredicate;923 let DecoderNamespace = Gen.DecoderNamespace;924 let OtherPredicates = !listconcat(ps.OtherPredicates,925 !if(p.HasExt64BitDPP, [HasDPALU_DPP], []));926 let True16Predicate = ps.True16Predicate;927}928 929class VOP1_DPP8<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :930 VOP_DPP8<ps.OpName, p> {931 let hasSideEffects = ps.hasSideEffects;932 let Defs = ps.Defs;933 let SchedRW = ps.SchedRW;934 let Uses = ps.Uses;935 let SubtargetPredicate = ps.SubtargetPredicate;936 let OtherPredicates = ps.OtherPredicates;937 938 bits<8> vdst;939 let Inst{8-0} = fi;940 let Inst{16-9} = op;941 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);942 let Inst{31-25} = 0x3f;943}944 945class VOP1_DPP8_Gen<bits<8> op, VOP1_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> :946 VOP1_DPP8<op, ps, p> {947 let AssemblerPredicate = Gen.AssemblerPredicate;948 let DecoderNamespace = Gen.DecoderNamespace;949 let True16Predicate = ps.True16Predicate;950}951 952//===----------------------------------------------------------------------===//953// GFX11, GFX12954//===----------------------------------------------------------------------===//955 956multiclass VOP1Only_Real<GFXGen Gen, bits<9> op> {957 let IsSingle = 1 in958 def Gen.Suffix :959 VOP1_Real_Gen<!cast<VOP1_Pseudo>(NAME), Gen>,960 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;961}962 963multiclass VOP1_Real_e32<GFXGen Gen, bits<9> op, string opName = NAME> {964 defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");965 def _e32#Gen.Suffix :966 VOP1_Real_Gen<ps, Gen>,967 VOP1e<op{7-0}, ps.Pfl>;968}969 970multiclass VOP1_Real_e32_with_name<GFXGen Gen, bits<9> op, string opName,971 string asmName> {972 defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");973 let AsmString = asmName # ps.AsmOperands,974 DecoderNamespace = Gen.DecoderNamespace #975 !if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {976 defm NAME : VOP1_Real_e32<Gen, op, opName>;977 }978}979 980multiclass VOP1_Real_e64<GFXGen Gen, bits<9> op> {981 def _e64#Gen.Suffix :982 VOP3_Real_Gen<!cast<VOP3_Pseudo>(NAME#"_e64"), Gen>,983 VOP3e_gfx11_gfx12<{0, 1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;984}985 986multiclass VOP1_Real_dpp<GFXGen Gen, bits<9> op, string opName = NAME> {987 defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");988 def _dpp#Gen.Suffix : VOP1_DPP16_Gen<op{7-0}, !cast<VOP1_DPP_Pseudo>(opName#"_dpp"), Gen>;989}990 991multiclass VOP1_Real_dpp_with_name<GFXGen Gen, bits<9> op, string opName,992 string asmName> {993 defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");994 let AsmString = asmName # ps.Pfl.AsmDPP16,995 DecoderNamespace = Gen.DecoderNamespace #996 !if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {997 defm NAME : VOP1_Real_dpp<Gen, op, opName>;998 }999}1000 1001multiclass VOP1_Real_dpp8<GFXGen Gen, bits<9> op, string opName = NAME> {1002 defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");1003 if !not(ps.Pfl.HasExt64BitDPP) then1004 def _dpp8#Gen.Suffix : VOP1_DPP8_Gen<op{7-0}, ps, Gen>;1005}1006 1007multiclass VOP1_Real_dpp8_with_name<GFXGen Gen, bits<9> op, string opName,1008 string asmName> {1009 defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");1010 let AsmString = asmName # ps.Pfl.AsmDPP8,1011 DecoderNamespace = Gen.DecoderNamespace #1012 !if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {1013 if !not(ps.Pfl.HasExt64BitDPP) then1014 defm NAME : VOP1_Real_dpp8<Gen, op, opName>;1015 }1016}1017 1018multiclass VOP1_Realtriple_e64<GFXGen Gen, bits<9> op> :1019 VOP3_Realtriple<Gen, {0, 1, 1, op{6-0}}, /*isSingle=*/ 0, NAME>;1020 1021multiclass VOP1_Realtriple_e64_with_name<GFXGen Gen, bits<9> op, string opName,1022 string asmName> {1023 defm NAME : VOP3_Realtriple_with_name<Gen, {0, 1, 1, op{6-0}}, opName,1024 asmName>;1025}1026 1027multiclass VOP1_Real_FULL<GFXGen Gen, bits<9> op> :1028 VOP1_Real_e32<Gen, op>, VOP1_Realtriple_e64<Gen, op>,1029 VOP1_Real_dpp<Gen, op>, VOP1_Real_dpp8<Gen, op>;1030 1031multiclass VOP1_Real_NO_VOP3_with_name_gfx11<bits<9> op, string opName,1032 string asmName> {1033 defm NAME : VOP1_Real_e32_with_name<GFX11Gen, op, opName, asmName>,1034 VOP1_Real_dpp_with_name<GFX11Gen, op, opName, asmName>,1035 VOP1_Real_dpp8_with_name<GFX11Gen, op, opName, asmName>;1036 defvar ps = !cast<VOP1_Pseudo>(opName#"_e32");1037 def gfx11_alias : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {1038 let AssemblerPredicate = isGFX11Plus;1039 }1040}1041 1042multiclass VOP1_Real_NO_VOP3_with_name_gfx12<bits<9> op, string opName,1043 string asmName> {1044 defm NAME : VOP1_Real_e32_with_name<GFX12Gen, op, opName, asmName>,1045 VOP1_Real_dpp_with_name<GFX12Gen, op, opName, asmName>,1046 VOP1_Real_dpp8_with_name<GFX12Gen, op, opName, asmName>;1047}1048 1049multiclass VOP1_Real_FULL_with_name<GFXGen Gen, bits<9> op, string opName,1050 string asmName> :1051 VOP1_Real_e32_with_name<Gen, op, opName, asmName>,1052 VOP1_Real_dpp_with_name<Gen, op, opName, asmName>,1053 VOP1_Real_dpp8_with_name<Gen, op, opName, asmName>,1054 VOP1_Realtriple_e64_with_name<Gen, op, opName, asmName>;1055 1056multiclass VOP1_Real_NO_DPP<GFXGen Gen, bits<9> op> :1057 VOP1_Real_e32<Gen, op>, VOP1_Real_e64<Gen, op>;1058 1059multiclass VOP1_Real_with_DPP16<GFXGen Gen, bits<9> op> :1060 VOP1_Real_NO_DPP<Gen, op>,1061 VOP1_Real_dpp<Gen, op>,1062 VOP3_Real_dpp_Base<Gen, {0, 1, 1, op{6-0}}>;1063 1064multiclass VOP1_Real_FULL_t16_gfx11_gfx12<bits<9> op, string asmName,1065 string opName = NAME> :1066 VOP1_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,1067 VOP1_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;1068 1069multiclass VOP1_Real_FULL_with_name_gfx11_gfx12<bits<9> op, string opName,1070 string asmName> :1071 VOP1_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,1072 VOP1_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;1073 1074multiclass VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<1075 bits<9> op, string asmName = !tolower(NAME), string opName = NAME> {1076 defm opName#"_t16" :1077 VOP1_Real_FULL_with_name_gfx11_gfx12<op, opName#"_t16", asmName>;1078 defm opName#"_fake16":1079 VOP1_Real_FULL_with_name_gfx11_gfx12<op, opName#"_fake16", asmName>;1080}1081 1082multiclass VOP1Only_Real_gfx11_gfx12<bits<9> op> :1083 VOP1Only_Real<GFX11Gen, op>, VOP1Only_Real<GFX12Gen, op>;1084 1085multiclass VOP1_Real_FULL_gfx11_gfx12<bits<9> op> :1086 VOP1_Real_FULL<GFX11Gen, op>, VOP1_Real_FULL<GFX12Gen, op>;1087 1088multiclass VOP1_Real_FULL_t16_and_fake16_gfx1250<1089 bits<9> op, string asmName = !tolower(NAME), string opName = NAME> {1090 defm opName#"_t16" :1091 VOP1_Real_FULL_with_name<GFX1250Gen, op, opName#"_t16", asmName>;1092 defm opName#"_fake16":1093 VOP1_Real_FULL_with_name<GFX1250Gen, op, opName#"_fake16", asmName>;1094}1095 1096multiclass VOP1_Real_FULL_with_name_gfx11_gfx12_not_gfx1250<bits<9> op, string opName,1097 string asmName> :1098 VOP1_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,1099 VOP1_Real_FULL_with_name<GFX12Not12_50Gen, op, opName, asmName>;1100 1101multiclass VOP1_Real_OpSelIsDPP_gfx1250<bits<9> op> : VOP1_Real_e32<GFX1250Gen, op> {1102 defvar ps = !cast<VOP_Pseudo>(NAME#"_e64");1103 def _e64_gfx1250 :1104 VOP3_Real_Gen<ps, GFX1250Gen>,1105 VOP3OpSelIsDPP_gfx12<{0, 1, 1, op{6-0}}, ps.Pfl>;1106}1107 1108defm V_CVT_F32_FP8 : VOP1_Real_FULL_with_name_gfx11_gfx12_not_gfx1250<0x06c, "V_CVT_F32_FP8_OP_SEL", "v_cvt_f32_fp8">;1109defm V_CVT_F32_FP8 : VOP1_Real_FULL_with_name<GFX1250Gen, 0x06c, "V_CVT_F32_FP8_gfx1250", "v_cvt_f32_fp8">;1110 1111defm V_CVT_F32_BF8 : VOP1_Real_FULL_with_name<GFX12Gen, 0x06d, "V_CVT_F32_BF8_OP_SEL", "v_cvt_f32_bf8">;1112 1113defm V_CVT_PK_F32_FP8_fake16 : VOP1_Real_e32_with_name<GFX12Gen, 0x06e, "V_CVT_PK_F32_FP8_fake16", "v_cvt_pk_f32_fp8">;1114defm V_CVT_PK_F32_FP8_t16 : VOP1_Real_e32_with_name<GFX12Gen, 0x06e, "V_CVT_PK_F32_FP8_t16", "v_cvt_pk_f32_fp8">;1115defm V_CVT_PK_F32_FP8_fake16 : VOP3_Real_with_name<GFX12Gen, 0x1ee, "V_CVT_PK_F32_FP8_fake16", "v_cvt_pk_f32_fp8">;1116defm V_CVT_PK_F32_FP8_t16 : VOP3_Real_with_name<GFX12Gen, 0x1ee, "V_CVT_PK_F32_FP8_t16", "v_cvt_pk_f32_fp8">;1117defm V_CVT_PK_F32_BF8_fake16 : VOP1_Real_e32_with_name<GFX12Gen, 0x06f, "V_CVT_PK_F32_BF8_fake16", "v_cvt_pk_f32_bf8">;1118defm V_CVT_PK_F32_BF8_t16 : VOP1_Real_e32_with_name<GFX12Gen, 0x06f, "V_CVT_PK_F32_BF8_t16", "v_cvt_pk_f32_bf8">;1119defm V_CVT_PK_F32_BF8_fake16 : VOP3_Real_with_name<GFX12Gen, 0x1ef, "V_CVT_PK_F32_BF8_fake16", "v_cvt_pk_f32_bf8">;1120defm V_CVT_PK_F32_BF8_t16 : VOP3_Real_with_name<GFX12Gen, 0x1ef, "V_CVT_PK_F32_BF8_t16", "v_cvt_pk_f32_bf8">;1121 1122defm V_CVT_NEAREST_I32_F32 : VOP1_Real_FULL_with_name_gfx11_gfx12<0x00c,1123 "V_CVT_RPI_I32_F32", "v_cvt_nearest_i32_f32">;1124defm V_CVT_FLOOR_I32_F32 : VOP1_Real_FULL_with_name_gfx11_gfx12<0x00d,1125 "V_CVT_FLR_I32_F32", "v_cvt_floor_i32_f32">;1126defm V_CLZ_I32_U32 : VOP1_Real_FULL_with_name_gfx11_gfx12<0x039,1127 "V_FFBH_U32", "v_clz_i32_u32">;1128defm V_CTZ_I32_B32 : VOP1_Real_FULL_with_name_gfx11_gfx12<0x03a,1129 "V_FFBL_B32", "v_ctz_i32_b32">;1130defm V_CLS_I32 : VOP1_Real_FULL_with_name_gfx11_gfx12<0x03b,1131 "V_FFBH_I32", "v_cls_i32">;1132defm V_SWAP_B16 : VOP1Only_Real_gfx11_gfx12<0x066>;1133defm V_PERMLANE64_B32 : VOP1Only_Real_gfx11_gfx12<0x067>;1134defm V_MOV_B16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x01c, "v_mov_b16">;1135defm V_NOT_B16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x069>;1136defm V_CVT_I32_I16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x06a>;1137defm V_CVT_U32_U16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x06b>;1138 1139defm V_CVT_F16_U16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x050>;1140defm V_CVT_F16_I16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x051>;1141defm V_CVT_U16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x052>;1142defm V_CVT_I16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x053>;1143defm V_RCP_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x054, "v_rcp_f16">;1144defm V_RCP_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x054, "v_rcp_f16">;1145defm V_SQRT_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x055, "v_sqrt_f16">;1146defm V_SQRT_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x055, "v_sqrt_f16">;1147defm V_RSQ_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x056, "v_rsq_f16">;1148defm V_RSQ_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x056, "v_rsq_f16">;1149defm V_LOG_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x057, "v_log_f16">;1150defm V_LOG_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x057, "v_log_f16">;1151defm V_EXP_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16">;1152defm V_EXP_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16">;1153defm V_FREXP_MANT_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x059>;1154defm V_FREXP_EXP_I16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x05a>;1155defm V_FLOOR_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">;1156defm V_FLOOR_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">;1157defm V_CEIL_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05c, "v_ceil_f16">;1158defm V_CEIL_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05c, "v_ceil_f16">;1159defm V_TRUNC_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x05d>;1160defm V_RNDNE_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x05e>;1161defm V_FRACT_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x05f>;1162defm V_SIN_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x060>;1163defm V_COS_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x061>;1164defm V_SAT_PK_U8_I16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x062>;1165defm V_CVT_NORM_I16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x063>;1166defm V_CVT_NORM_U16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x064>;1167 1168defm V_CVT_F16_F32 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x00a>;1169defm V_CVT_F32_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x00b>;1170 1171defm V_MOV_B64 : VOP1_Real_FULL <GFX1250Gen, 0x1d>;1172 1173defm V_TANH_F32 : VOP1_Real_FULL<GFX1250Gen, 0x01e>;1174defm V_TANH_F16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x01f>;1175defm V_PERMLANE16_SWAP_B32 : VOP1_Real_OpSelIsDPP_gfx1250<0x049>;1176defm V_TANH_BF16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x04a>;1177defm V_PRNG_B32 : VOP1_Real_FULL<GFX1250Gen, 0x04b>;1178defm V_CVT_F32_BF16_gfx1250 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x072, "v_cvt_f32_bf16">;1179defm V_SAT_PK4_I4_I8 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x073>;1180defm V_SAT_PK4_U4_U8 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x074>;1181defm V_CVT_PK_F16_FP8 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x075>;1182defm V_CVT_PK_F16_BF8 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x076>;1183defm V_CVT_F16_FP8 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x077>;1184defm V_CVT_F16_BF8 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x078>;1185defm V_RCP_BF16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x079>;1186defm V_SQRT_BF16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x07a>;1187defm V_RSQ_BF16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x07b>;1188defm V_LOG_BF16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x07c>;1189defm V_EXP_BF16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x07d>;1190defm V_SIN_BF16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x07e>;1191defm V_COS_BF16 : VOP1_Real_FULL_t16_and_fake16_gfx1250<0x07f>;1192 1193//===----------------------------------------------------------------------===//1194// GFX10.1195//===----------------------------------------------------------------------===//1196 1197let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {1198 multiclass VOP1Only_Real_gfx10<bits<9> op> {1199 def _gfx10 :1200 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX10>,1201 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;1202 }1203 multiclass VOP1_Real_e32_gfx10<bits<9> op> {1204 def _e32_gfx10 :1205 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,1206 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;1207 }1208 multiclass VOP1_Real_e64_gfx10<bits<9> op> {1209 def _e64_gfx10 :1210 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,1211 VOP3e_gfx10<{0, 1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;1212 }1213 multiclass VOP1_Real_sdwa_gfx10<bits<9> op> {1214 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then1215 def _sdwa_gfx10 :1216 VOP_SDWA10_Real<!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,1217 VOP1_SDWA9Ae<op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;1218 }1219 multiclass VOP1_Real_dpp_gfx10<bits<9> op> {1220 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then1221 def _dpp_gfx10 : VOP1_DPP16<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10>;1222 }1223 multiclass VOP1_Real_dpp8_gfx10<bits<9> op> {1224 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then1225 def _dpp8_gfx10 : VOP1_DPP8<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32")>;1226 }1227} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"1228 1229multiclass VOP1_Real_gfx10<bits<9> op> :1230 VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,1231 VOP1_Real_sdwa_gfx10<op>, VOP1_Real_dpp_gfx10<op>,1232 VOP1_Real_dpp8_gfx10<op>;1233 1234multiclass VOP1_Real_gfx10_FULL_gfx11_gfx12<bits<9> op> :1235 VOP1_Real_gfx10<op>,1236 VOP1_Real_FULL<GFX11Gen, op>,1237 VOP1_Real_FULL<GFX12Gen, op>;1238 1239multiclass VOP1_Real_gfx10_NO_DPP_gfx11_gfx12<bits<9> op> :1240 VOP1_Real_gfx10<op>,1241 VOP1_Real_NO_DPP<GFX11Gen, op>,1242 VOP1_Real_NO_DPP<GFX12Gen, op>;1243 1244multiclass VOP1Only_Real_gfx10_gfx11_gfx12<bits<9> op> :1245 VOP1Only_Real_gfx10<op>,1246 VOP1Only_Real<GFX11Gen, op>,1247 VOP1Only_Real<GFX12Gen, op>;1248 1249defm V_PIPEFLUSH : VOP1_Real_gfx10_NO_DPP_gfx11_gfx12<0x01b>;1250defm V_MOVRELSD_2_B32 : VOP1_Real_gfx10_FULL_gfx11_gfx12<0x048>;1251defm V_CVT_F16_U16 : VOP1_Real_gfx10<0x050>;1252defm V_CVT_F16_I16 : VOP1_Real_gfx10<0x051>;1253defm V_CVT_U16_F16 : VOP1_Real_gfx10<0x052>;1254defm V_CVT_I16_F16 : VOP1_Real_gfx10<0x053>;1255defm V_RCP_F16 : VOP1_Real_gfx10<0x054>;1256defm V_SQRT_F16 : VOP1_Real_gfx10<0x055>;1257defm V_RSQ_F16 : VOP1_Real_gfx10<0x056>;1258defm V_LOG_F16 : VOP1_Real_gfx10<0x057>;1259defm V_EXP_F16 : VOP1_Real_gfx10<0x058>;1260defm V_FREXP_MANT_F16 : VOP1_Real_gfx10<0x059>;1261defm V_FREXP_EXP_I16_F16 : VOP1_Real_gfx10<0x05a>;1262defm V_FLOOR_F16 : VOP1_Real_gfx10<0x05b>;1263defm V_CEIL_F16 : VOP1_Real_gfx10<0x05c>;1264defm V_TRUNC_F16 : VOP1_Real_gfx10<0x05d>;1265defm V_RNDNE_F16 : VOP1_Real_gfx10<0x05e>;1266defm V_FRACT_F16 : VOP1_Real_gfx10<0x05f>;1267defm V_SIN_F16 : VOP1_Real_gfx10<0x060>;1268defm V_COS_F16 : VOP1_Real_gfx10<0x061>;1269defm V_SAT_PK_U8_I16 : VOP1_Real_gfx10<0x062>;1270defm V_CVT_NORM_I16_F16 : VOP1_Real_gfx10<0x063>;1271defm V_CVT_NORM_U16_F16 : VOP1_Real_gfx10<0x064>;1272 1273defm V_SWAP_B32 : VOP1Only_Real_gfx10_gfx11_gfx12<0x065>;1274defm V_SWAPREL_B32 : VOP1Only_Real_gfx10_gfx11_gfx12<0x068>;1275 1276//===----------------------------------------------------------------------===//1277// GFX7, GFX10, GFX11, GFX121278//===----------------------------------------------------------------------===//1279 1280let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {1281 multiclass VOP1_Real_e32_gfx7<bits<9> op> {1282 def _e32_gfx7 :1283 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,1284 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;1285 }1286 multiclass VOP1_Real_e64_gfx7<bits<9> op> {1287 def _e64_gfx7 :1288 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,1289 VOP3e_gfx6_gfx7<{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;1290 }1291} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"1292 1293multiclass VOP1_Real_gfx7<bits<9> op> :1294 VOP1_Real_e32_gfx7<op>, VOP1_Real_e64_gfx7<op>;1295 1296multiclass VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<bits<9> op> :1297 VOP1_Real_gfx7<op>, VOP1_Real_gfx10<op>, VOP1_Real_NO_DPP<GFX11Gen, op>,1298 VOP1_Real_with_DPP16<GFX12Gen, op>;1299 1300defm V_LOG_LEGACY_F32 : VOP1_Real_gfx7<0x045>;1301defm V_EXP_LEGACY_F32 : VOP1_Real_gfx7<0x046>;1302 1303defm V_TRUNC_F64 : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x017>;1304defm V_CEIL_F64 : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x018>;1305defm V_RNDNE_F64 : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x019>;1306defm V_FLOOR_F64 : VOP1_Real_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x01a>;1307 1308//===----------------------------------------------------------------------===//1309// GFX6, GFX7, GFX10, GFX11, GFX121310//===----------------------------------------------------------------------===//1311 1312let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {1313 multiclass VOP1_Real_e32_gfx6_gfx7<bits<9> op> {1314 def _e32_gfx6_gfx7 :1315 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,1316 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;1317 }1318 multiclass VOP1_Real_e64_gfx6_gfx7<bits<9> op> {1319 def _e64_gfx6_gfx7 :1320 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,1321 VOP3e_gfx6_gfx7<{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;1322 }1323 multiclass VOP1Only_Real_gfx6_gfx7<bits<9> op> {1324 def _gfx6_gfx7 :1325 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.SI>,1326 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;1327 }1328} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"1329 1330multiclass VOP1_Real_gfx6_gfx7<bits<9> op> :1331 VOP1_Real_e32_gfx6_gfx7<op>, VOP1_Real_e64_gfx6_gfx7<op>;1332 1333multiclass VOP1_Real_gfx6_gfx7_gfx10<bits<9> op> :1334 VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10<op>;1335 1336multiclass VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<bits<9> op> :1337 VOP1_Real_gfx6_gfx7_gfx10<op>, VOP1_Real_FULL<GFX11Gen, op>,1338 VOP1_Real_FULL<GFX12Gen, op>;1339 1340multiclass VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<bits<9> op> :1341 VOP1_Real_gfx6_gfx7_gfx10<op>, VOP1_Real_NO_DPP<GFX11Gen, op>,1342 VOP1_Real_NO_DPP<GFX12Gen, op>;1343 1344multiclass VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<bits<9> op> :1345 VOP1_Real_gfx6_gfx7_gfx10<op>, VOP1_Real_NO_DPP<GFX11Gen, op>,1346 VOP1_Real_with_DPP16<GFX12Gen, op>;1347 1348multiclass VOP1Only_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<9> op> :1349 VOP1Only_Real_gfx6_gfx7<op>, VOP1Only_Real_gfx10_gfx11_gfx12<op>;1350 1351defm V_LOG_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x026>;1352defm V_RCP_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x028>;1353defm V_RCP_LEGACY_F32 : VOP1_Real_gfx6_gfx7<0x029>;1354defm V_RSQ_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x02c>;1355defm V_RSQ_LEGACY_F32 : VOP1_Real_gfx6_gfx7<0x02d>;1356defm V_RCP_CLAMP_F64 : VOP1_Real_gfx6_gfx7<0x030>;1357defm V_RSQ_CLAMP_F64 : VOP1_Real_gfx6_gfx7<0x032>;1358 1359defm V_NOP : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x000>;1360defm V_MOV_B32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x001>;1361defm V_READFIRSTLANE_B32 : VOP1Only_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x002>;1362defm V_CVT_I32_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x003>;1363defm V_CVT_F64_I32 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x004>;1364defm V_CVT_F32_I32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x005>;1365defm V_CVT_F32_U32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x006>;1366defm V_CVT_U32_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x007>;1367defm V_CVT_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x008>;1368defm V_CVT_F16_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x00a>;1369defm V_CVT_F32_F16 : VOP1_Real_gfx6_gfx7_gfx10<0x00b>;1370defm V_CVT_RPI_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x00c>;1371defm V_CVT_FLR_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x00d>;1372defm V_CVT_OFF_F32_I4 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x00e>;1373defm V_CVT_F32_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x00f>;1374defm V_CVT_F64_F32 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x010>;1375defm V_CVT_F32_UBYTE0 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x011>;1376defm V_CVT_F32_UBYTE1 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x012>;1377defm V_CVT_F32_UBYTE2 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x013>;1378defm V_CVT_F32_UBYTE3 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x014>;1379defm V_CVT_U32_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x015>;1380defm V_CVT_F64_U32 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x016>;1381defm V_FRACT_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x020>;1382defm V_TRUNC_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x021>;1383defm V_CEIL_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x022>;1384defm V_RNDNE_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x023>;1385defm V_FLOOR_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x024>;1386defm V_EXP_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x025>;1387defm V_LOG_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x027>;1388defm V_RCP_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x02a>;1389defm V_RCP_IFLAG_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x02b>;1390defm V_RSQ_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x02e>;1391defm V_RCP_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x02f>;1392defm V_RSQ_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x031>;1393defm V_SQRT_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x033>;1394defm V_SQRT_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x034>;1395defm V_SIN_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x035>;1396defm V_COS_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x036>;1397defm V_NOT_B32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x037>;1398defm V_BFREV_B32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x038>;1399defm V_FFBH_U32 : VOP1_Real_gfx6_gfx7_gfx10<0x039>;1400defm V_FFBL_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x03a>;1401defm V_FFBH_I32 : VOP1_Real_gfx6_gfx7_gfx10<0x03b>;1402defm V_FREXP_EXP_I32_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x03c>;1403defm V_FREXP_MANT_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x03d>;1404defm V_FRACT_F64 : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_with_DPP16_gfx12<0x03e>;1405defm V_FREXP_EXP_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x03f>;1406defm V_FREXP_MANT_F32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x040>;1407defm V_CLREXCP : VOP1_Real_gfx6_gfx7_gfx10<0x041>;1408defm V_MOVRELD_B32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x042>;1409defm V_MOVRELS_B32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x043>;1410defm V_MOVRELSD_B32 : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x044>;1411 1412//===----------------------------------------------------------------------===//1413// GFX8, GFX9 (VI).1414//===----------------------------------------------------------------------===//1415 1416class VOP1_DPPe <bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :1417 VOP_DPPe <P> {1418 bits<8> vdst;1419 let Inst{8-0} = 0xfa; // dpp1420 let Inst{16-9} = op;1421 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);1422 let Inst{31-25} = 0x3f; //encoding1423}1424 1425let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {1426 multiclass VOP1Only_Real_vi <bits<10> op> {1427 def _vi :1428 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,1429 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;1430 }1431 1432 multiclass VOP1_Real_e32e64_vi <bits<10> op> {1433 def _e32_vi :1434 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,1435 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;1436 def _e64_vi :1437 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,1438 VOP3e_vi <!add(0x140, op), !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;1439 }1440}1441 1442multiclass VOP1_Real_vi <bits<10> op> {1443 defm NAME : VOP1_Real_e32e64_vi <op>;1444 1445 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA then1446 def _sdwa_vi :1447 VOP_SDWA8_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,1448 VOP1_SDWAe <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;1449 1450 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then1451 def _sdwa_gfx9 :1452 VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,1453 VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;1454 1455 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then1456 def _dpp_vi :1457 VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,1458 VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")> {1459 let AssemblerPredicate = isGFX8GFX9;1460 }1461}1462 1463defm V_NOP : VOP1_Real_vi <0x0>;1464defm V_MOV_B32 : VOP1_Real_vi <0x1>;1465defm V_READFIRSTLANE_B32 : VOP1Only_Real_vi <0x2>;1466defm V_CVT_I32_F64 : VOP1_Real_vi <0x3>;1467defm V_CVT_F64_I32 : VOP1_Real_vi <0x4>;1468defm V_CVT_F32_I32 : VOP1_Real_vi <0x5>;1469defm V_CVT_F32_U32 : VOP1_Real_vi <0x6>;1470defm V_CVT_U32_F32 : VOP1_Real_vi <0x7>;1471defm V_CVT_I32_F32 : VOP1_Real_vi <0x8>;1472defm V_CVT_F16_F32 : VOP1_Real_vi <0xa>;1473defm V_CVT_F32_F16 : VOP1_Real_vi <0xb>;1474defm V_CVT_RPI_I32_F32 : VOP1_Real_vi <0xc>;1475defm V_CVT_FLR_I32_F32 : VOP1_Real_vi <0xd>;1476defm V_CVT_OFF_F32_I4 : VOP1_Real_vi <0xe>;1477defm V_CVT_F32_F64 : VOP1_Real_vi <0xf>;1478defm V_CVT_F64_F32 : VOP1_Real_vi <0x10>;1479defm V_CVT_F32_UBYTE0 : VOP1_Real_vi <0x11>;1480defm V_CVT_F32_UBYTE1 : VOP1_Real_vi <0x12>;1481defm V_CVT_F32_UBYTE2 : VOP1_Real_vi <0x13>;1482defm V_CVT_F32_UBYTE3 : VOP1_Real_vi <0x14>;1483defm V_CVT_U32_F64 : VOP1_Real_vi <0x15>;1484defm V_CVT_F64_U32 : VOP1_Real_vi <0x16>;1485defm V_FRACT_F32 : VOP1_Real_vi <0x1b>;1486defm V_TRUNC_F32 : VOP1_Real_vi <0x1c>;1487defm V_CEIL_F32 : VOP1_Real_vi <0x1d>;1488defm V_RNDNE_F32 : VOP1_Real_vi <0x1e>;1489defm V_FLOOR_F32 : VOP1_Real_vi <0x1f>;1490defm V_EXP_F32 : VOP1_Real_vi <0x20>;1491defm V_LOG_F32 : VOP1_Real_vi <0x21>;1492defm V_RCP_F32 : VOP1_Real_vi <0x22>;1493defm V_RCP_IFLAG_F32 : VOP1_Real_vi <0x23>;1494defm V_RSQ_F32 : VOP1_Real_vi <0x24>;1495defm V_RCP_F64 : VOP1_Real_vi <0x25>;1496defm V_RSQ_F64 : VOP1_Real_vi <0x26>;1497defm V_SQRT_F32 : VOP1_Real_vi <0x27>;1498defm V_SQRT_F64 : VOP1_Real_vi <0x28>;1499defm V_SIN_F32 : VOP1_Real_vi <0x29>;1500defm V_COS_F32 : VOP1_Real_vi <0x2a>;1501defm V_NOT_B32 : VOP1_Real_vi <0x2b>;1502defm V_BFREV_B32 : VOP1_Real_vi <0x2c>;1503defm V_FFBH_U32 : VOP1_Real_vi <0x2d>;1504defm V_FFBL_B32 : VOP1_Real_vi <0x2e>;1505defm V_FFBH_I32 : VOP1_Real_vi <0x2f>;1506defm V_FREXP_EXP_I32_F64 : VOP1_Real_vi <0x30>;1507defm V_FREXP_MANT_F64 : VOP1_Real_vi <0x31>;1508defm V_FRACT_F64 : VOP1_Real_vi <0x32>;1509defm V_FREXP_EXP_I32_F32 : VOP1_Real_vi <0x33>;1510defm V_FREXP_MANT_F32 : VOP1_Real_vi <0x34>;1511defm V_CLREXCP : VOP1_Real_vi <0x35>;1512defm V_MOVRELD_B32 : VOP1_Real_e32e64_vi <0x36>;1513defm V_MOVRELS_B32 : VOP1_Real_e32e64_vi <0x37>;1514defm V_MOVRELSD_B32 : VOP1_Real_e32e64_vi <0x38>;1515defm V_TRUNC_F64 : VOP1_Real_vi <0x17>;1516defm V_CEIL_F64 : VOP1_Real_vi <0x18>;1517defm V_FLOOR_F64 : VOP1_Real_vi <0x1A>;1518defm V_RNDNE_F64 : VOP1_Real_vi <0x19>;1519defm V_LOG_LEGACY_F32 : VOP1_Real_vi <0x4c>;1520defm V_EXP_LEGACY_F32 : VOP1_Real_vi <0x4b>;1521defm V_CVT_F16_U16 : VOP1_Real_vi <0x39>;1522defm V_CVT_F16_I16 : VOP1_Real_vi <0x3a>;1523defm V_CVT_U16_F16 : VOP1_Real_vi <0x3b>;1524defm V_CVT_I16_F16 : VOP1_Real_vi <0x3c>;1525defm V_RCP_F16 : VOP1_Real_vi <0x3d>;1526defm V_SQRT_F16 : VOP1_Real_vi <0x3e>;1527defm V_RSQ_F16 : VOP1_Real_vi <0x3f>;1528defm V_LOG_F16 : VOP1_Real_vi <0x40>;1529defm V_EXP_F16 : VOP1_Real_vi <0x41>;1530defm V_FREXP_MANT_F16 : VOP1_Real_vi <0x42>;1531defm V_FREXP_EXP_I16_F16 : VOP1_Real_vi <0x43>;1532defm V_FLOOR_F16 : VOP1_Real_vi <0x44>;1533defm V_CEIL_F16 : VOP1_Real_vi <0x45>;1534defm V_TRUNC_F16 : VOP1_Real_vi <0x46>;1535defm V_RNDNE_F16 : VOP1_Real_vi <0x47>;1536defm V_FRACT_F16 : VOP1_Real_vi <0x48>;1537defm V_SIN_F16 : VOP1_Real_vi <0x49>;1538defm V_COS_F16 : VOP1_Real_vi <0x4a>;1539defm V_SWAP_B32 : VOP1Only_Real_vi <0x51>;1540 1541defm V_SAT_PK_U8_I16 : VOP1_Real_vi<0x4f>;1542defm V_CVT_NORM_I16_F16 : VOP1_Real_vi<0x4d>;1543defm V_CVT_NORM_U16_F16 : VOP1_Real_vi<0x4e>;1544 1545defm V_ACCVGPR_MOV_B32 : VOP1Only_Real_vi<0x52>;1546 1547let VOP1 = 1, SubtargetPredicate = isGFX8GFX9, Uses = [EXEC, M0], Size = V_MOV_B32_e32.Size in {1548 1549// Copy of v_mov_b32 with $vdst as a use operand for use with VGPR1550// indexing mode. vdst can't be treated as a def for codegen purposes,1551// and an implicit use and def of the super register should be added.1552def V_MOV_B32_indirect_write : VPseudoInstSI<(outs),1553 (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32, 0>.ret:$src0)>,1554 PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,1555 getVOPSrc0ForVT<i32, 0>.ret:$src0)>;1556 1557// Copy of v_mov_b32 for use with VGPR indexing mode. An implicit use of the1558// super register should be added.1559def V_MOV_B32_indirect_read : VPseudoInstSI<1560 (outs getVALUDstForVT<i32>.ret:$vdst),1561 (ins getVOPSrc0ForVT<i32, 0>.ret:$src0)>,1562 PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,1563 getVOPSrc0ForVT<i32, 0>.ret:$src0)>;1564 1565} // End VOP1 = 1, SubtargetPredicate = isGFX8GFX9, Uses = [M0]1566 1567let OtherPredicates = [isGFX8Plus] in {1568 1569def : GCNPat <1570 (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask,1571 timm:$bank_mask, timm:$bound_ctrl)),1572 (V_MOV_B32_dpp VGPR_32:$src, VGPR_32:$src, (as_i32timm $dpp_ctrl),1573 (as_i32timm $row_mask), (as_i32timm $bank_mask),1574 (as_i1timm $bound_ctrl))1575>;1576 1577foreach vt = Reg32Types.types in {1578def : GCNPat <1579 (vt (int_amdgcn_update_dpp vt:$old, vt:$src, timm:$dpp_ctrl,1580 timm:$row_mask, timm:$bank_mask,1581 timm:$bound_ctrl)),1582 (V_MOV_B32_dpp VGPR_32:$old, VGPR_32:$src, (as_i32timm $dpp_ctrl),1583 (as_i32timm $row_mask), (as_i32timm $bank_mask),1584 (as_i1timm $bound_ctrl))1585>;1586}1587 1588} // End OtherPredicates = [isGFX8Plus]1589 1590let OtherPredicates = [isGFX8Plus, NotUseRealTrue16Insts] in {1591def : GCNPat<1592 (i32 (anyext i16:$src)),1593 (COPY $src)1594>;1595 1596def : GCNPat<1597 (i64 (anyext i16:$src)),1598 (REG_SEQUENCE VReg_64,1599 (i32 (COPY $src)), sub0,1600 (V_MOV_B32_e32 (i32 0)), sub1)1601>;1602 1603def : GCNPat<1604 (i16 (trunc i32:$src)),1605 (COPY $src)1606>;1607 1608def : GCNPat <1609 (i16 (trunc i64:$src)),1610 (EXTRACT_SUBREG $src, sub0)1611>;1612 1613} // End OtherPredicates = [isGFX8Plus, p]1614 1615let True16Predicate = UseRealTrue16Insts in {1616def : GCNPat<1617 (i32 (UniformUnaryFrag<anyext> i16:$src)),1618 (COPY $src)1619>;1620 1621def : GCNPat<1622 (i32 (DivergentUnaryFrag<anyext> i16:$src)),1623 (REG_SEQUENCE VGPR_32, $src, lo16, (i16 (IMPLICIT_DEF)), hi16)1624>;1625 1626def : GCNPat<1627 (i64 (UniformUnaryFrag<anyext> i16:$src)),1628 (REG_SEQUENCE VReg_64,1629 (i32 (COPY $src)), sub0,1630 (V_MOV_B32_e32 (i32 0)), sub1)1631>;1632 1633def : GCNPat<1634 (i64 (DivergentUnaryFrag<anyext> i16:$src)),1635 (REG_SEQUENCE VReg_64, $src, lo16, (i16 (IMPLICIT_DEF)), hi16, (i32 (IMPLICIT_DEF)), sub1)1636>;1637 1638def : GCNPat<1639 (i16 (UniformUnaryFrag<trunc> i32:$src)),1640 (COPY $src)1641>;1642 1643def : GCNPat<1644 (i16 (DivergentUnaryFrag<trunc> i32:$src)),1645 (EXTRACT_SUBREG $src, lo16)1646>;1647 1648def : GCNPat <1649 (i16 (UniformUnaryFrag<trunc> i64:$src)),1650 (EXTRACT_SUBREG $src, sub0)1651>;1652 1653def : GCNPat <1654 (i16 (DivergentUnaryFrag<trunc> i64:$src)),1655 (EXTRACT_SUBREG $src, lo16)1656>;1657 1658} // End OtherPredicates = [UseRealTrue16Insts]1659 1660//===----------------------------------------------------------------------===//1661// GFX91662//===----------------------------------------------------------------------===//1663 1664let DecoderNamespace = "GFX9" in {1665 multiclass VOP1_Real_gfx9 <bits<10> op> {1666 defm NAME : VOP1_Real_e32e64_vi <op>;1667 1668 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then1669 def _sdwa_gfx9 :1670 VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,1671 VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;1672 1673 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then1674 def _dpp_gfx9 :1675 VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,1676 VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")>;1677 }1678 1679 multiclass VOP1_Real_NoDstSel_SDWA_gfx9 <bits<10> op> {1680 defm NAME : VOP1_Real_e32e64_vi <op>;1681 1682 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then1683 def _sdwa_gfx9 :1684 VOP_SDWA9_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,1685 VOP1_SDWA9Ae <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {1686 let Inst{42-40} = 6;1687 }1688 1689 if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then1690 def _dpp_gfx9 :1691 VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,1692 VOP1_DPPe<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp")>;1693 }1694}1695 1696/// Special case of VOP1 instructions, with a VOP3 form where op_sel1697/// is used for DPP operands.1698multiclass VOP1_OpSel_Real_e32e64_gfx9 <bits<10> op> {1699 let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {1700 def _e32_gfx9 :1701 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,1702 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;1703 1704 def _e64_gfx9 :1705 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,1706 VOP3OpSelIsDPP_gfx9<!add(0x140, op), !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;1707 }1708}1709 1710defm V_SCREEN_PARTITION_4SE_B32 : VOP1_Real_gfx9 <0x37>;1711 1712let AssemblerPredicate = isGFX940Plus in1713defm V_MOV_B64 : VOP1_Real_gfx9 <0x38>;1714 1715defm V_CVT_F32_BF16 : VOP1_Real_gfx9 <0x5b>;1716 1717defm V_CVT_F32_FP8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x54>;1718defm V_CVT_F32_BF8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x55>;1719defm V_CVT_PK_F32_FP8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x56>;1720defm V_CVT_PK_F32_BF8 : VOP1_Real_NoDstSel_SDWA_gfx9<0x57>;1721 1722defm V_PRNG_B32 : VOP1_Real_gfx9 <0x58>;1723 1724let isConvergent = 1 in {1725defm V_PERMLANE16_SWAP_B32 : VOP1_OpSel_Real_e32e64_gfx9<0x059>;1726defm V_PERMLANE32_SWAP_B32 : VOP1_OpSel_Real_e32e64_gfx9<0x05a>;1727}1728 1729class MovDPP8Pattern<Predicate Pred, Instruction Inst, ValueType vt> : GCNPat <1730 (vt (int_amdgcn_mov_dpp8 vt:$src, timm:$dpp8)),1731 (Inst VGPR_32:$src, VGPR_32:$src, (as_i32timm $dpp8), (i32 DPP8Mode.FI_0))> {1732 let OtherPredicates = [Pred];1733}1734 1735foreach vt = Reg32Types.types in {1736 def : MovDPP8Pattern<isGFX10Only, V_MOV_B32_dpp8_gfx10, vt>;1737 def : MovDPP8Pattern<isGFX11Only, V_MOV_B32_dpp8_gfx11, vt>;1738 def : MovDPP8Pattern<isGFX12Only, V_MOV_B32_dpp8_gfx12, vt>;1739}1740