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1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// VOP2 Classes11//===----------------------------------------------------------------------===//12 13class VOP2e <bits<6> op, VOPProfile P> : Enc32 {14 bits<8> vdst;15 bits<9> src0;16 bits<8> src1;17 18 let Inst{8-0} = !if(P.HasSrc0, src0, 0);19 let Inst{16-9} = !if(P.HasSrc1, src1, 0);20 let Inst{24-17} = !if(P.EmitDst, vdst, 0);21 let Inst{30-25} = op;22 let Inst{31} = 0x0; //encoding23}24 25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {26 bits<8> vdst;27 bits<9> src0;28 bits<8> src1;29 bits<32> imm;30 31 let Inst{8-0} = !if(P.HasSrc0, src0, 0);32 let Inst{16-9} = !if(P.HasSrc1, src1, 0);33 let Inst{24-17} = !if(P.EmitDst, vdst, 0);34 let Inst{30-25} = op;35 let Inst{31} = 0x0; // encoding36 let Inst{63-32} = imm;37}38 39class VOP2_MADK64e <bits<6> op, VOPProfile P> : Enc96 {40 bits<8> vdst;41 bits<9> src0;42 bits<8> src1;43 bits<64> imm;44 45 let Inst{8-0} = !if(P.HasSrc0, src0, 0);46 let Inst{16-9} = !if(P.HasSrc1, src1, 0);47 let Inst{24-17} = !if(P.EmitDst, vdst, 0);48 let Inst{30-25} = op;49 let Inst{31} = 0x0; // encoding50 let Inst{95-32} = imm;51}52 53class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {54 bits<8> vdst;55 bits<8> src1;56 57 let Inst{8-0} = 0xf9; // sdwa58 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);59 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);60 let Inst{30-25} = op;61 let Inst{31} = 0x0; // encoding62}63 64class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {65 bits<8> vdst;66 bits<9> src1;67 68 let Inst{8-0} = 0xf9; // sdwa69 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);70 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);71 let Inst{30-25} = op;72 let Inst{31} = 0x0; // encoding73 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr74}75 76class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :77 VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {78 79 let AsmOperands = P.Asm32;80 81 let Size = 4;82 let mayLoad = 0;83 let mayStore = 0;84 let hasSideEffects = 0;85 86 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);87 88 let mayRaiseFPException = ReadsModeReg;89 90 let VOP2 = 1;91 let VALU = 1;92 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);93 94 let AsmVariantName = AMDGPUAsmVariants.Default;95}96 97class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemonic> :98 VOP_Real <ps>,99 InstSI <ps.OutOperandList, ps.InOperandList, real_name # ps.AsmOperands, []>,100 SIMCInstr <ps.PseudoInstr, EncodingFamily> {101 102 let VALU = 1;103 let VOP2 = 1;104 let isPseudo = 0;105 let isCodeGenOnly = 0;106 107 let Constraints = ps.Constraints;108 109 // copy relevant pseudo op flags110 let SubtargetPredicate = ps.SubtargetPredicate;111 let True16Predicate = ps.True16Predicate;112 let OtherPredicates = ps.OtherPredicates;113 let AsmMatchConverter = ps.AsmMatchConverter;114 let AsmVariantName = ps.AsmVariantName;115 let Constraints = ps.Constraints;116 let TSFlags = ps.TSFlags;117 let UseNamedOperandTable = ps.UseNamedOperandTable;118 let Uses = ps.Uses;119 let Defs = ps.Defs;120 let SchedRW = ps.SchedRW;121 let mayLoad = ps.mayLoad;122 let mayStore = ps.mayStore;123 let isConvergent = ps.isConvergent;124}125 126class VOP2_Real_Gen <VOP2_Pseudo ps, GFXGen Gen, string real_name = ps.Mnemonic> :127 VOP2_Real <ps, Gen.Subtarget, real_name> {128 let AssemblerPredicate = Gen.AssemblerPredicate;129 let True16Predicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, NoTrue16Predicate);130 let DecoderNamespace = Gen.DecoderNamespace#131 !if(ps.Pfl.IsRealTrue16, "", "_FAKE16");132}133 134class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :135 VOP_SDWA_Pseudo <OpName, P, pattern> {136 let AsmMatchConverter = "cvtSdwaVOP2";137}138 139class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :140 VOP_DPP_Pseudo <OpName, P, pattern> {141}142 143 144class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {145 list<dag> ret = !if(P.HasModifiers,146 [(set P.DstVT:$vdst,147 (node (P.Src0VT148 !if(P.HasOMod,149 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),150 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),151 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],152 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);153}154 155multiclass VOP2Inst_e32<string opName,156 VOPProfile P,157 SDPatternOperator node = null_frag,158 string revOp = opName> {159 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,160 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;161}162multiclass163 VOP2Inst_e32_VOPD<string opName, VOPProfile P, bits<6> VOPDOp,164 string VOPDName, SDPatternOperator node = null_frag,165 string revOp = opName> {166 defm NAME : VOP2Inst_e32<opName, P, node, revOp>,167 VOPD_Component<VOPDOp, VOPDName>;168}169multiclass VOP2Inst_e64<string opName,170 VOPProfile P,171 SDPatternOperator node = null_frag,172 string revOp = opName> {173 def _e64 : VOP3InstBase <opName, P, node, 1>,174 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;175 176 if P.HasExtVOP3DPP then177 def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {178 let SubtargetPredicate = isGFX11Plus;179 }180 else if P.HasExt64BitDPP then181 def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {182 let OtherPredicates = [HasDPALU_DPP];183 }184}185 186multiclass VOP2Inst_e64_VOPD<string opName,187 VOPProfile P, bits<6> VOPDOp,188 string VOPDName,189 SDPatternOperator node = null_frag,190 string revOp = opName> {191 defm NAME: VOP2Inst_e64<opName, P, node, revOp>,192 VOPD_Component<VOPDOp, VOPDName>;193}194 195multiclass VOP2Inst_sdwa<string opName,196 VOPProfile P,197 string revOp = opName> {198 if P.HasExtSDWA then199 def _sdwa : VOP2_SDWA_Pseudo <opName, P>,200 Commutable_REV<revOp#"_sdwa", !eq(revOp, opName)>;201}202 203multiclass VOP2Inst<string opName,204 VOPProfile P,205 SDPatternOperator node = null_frag,206 string revOp = opName> :207 VOP2Inst_e32<opName, P, node, revOp>,208 VOP2Inst_e64<opName, P, node, revOp>,209 VOP2Inst_sdwa<opName, P, revOp> {210 if P.HasExtDPP then211 def _dpp : VOP2_DPP_Pseudo <opName, P>;212}213 214multiclass VOP2Inst_t16<string opName,215 VOPProfile P,216 SDPatternOperator node = null_frag,217 string revOp = opName> {218 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in {219 defm NAME : VOP2Inst<opName, P, node, revOp>;220 }221 let SubtargetPredicate = UseRealTrue16Insts in {222 defm _t16 : VOP2Inst<opName#"_t16", VOPProfile_True16<P>, node, revOp#"_t16">;223 }224 let SubtargetPredicate = UseFakeTrue16Insts in {225 defm _fake16 : VOP2Inst<opName#"_fake16", VOPProfile_Fake16<P>, node, revOp#"_fake16">;226 }227}228 229// Creating a _t16_e32 pseudo when there is no corresponding real instruction on230// any subtarget is a problem. It makes getMCOpcodeGen return -1, which we231// assume means the instruction is already a real. The fix is to not create that232// _t16_e32 pseudo233multiclass VOP2Inst_e64_t16<string opName,234 VOPProfile P,235 SDPatternOperator node = null_frag,236 string revOp = opName> {237 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in {238 defm NAME : VOP2Inst<opName, P, node, revOp>;239 let SubtargetPredicate = isGFX10Only in {240 // V_MAX_I16 etc use VOP3 encoding and allow OP_SEL241 def _opsel_e64 : VOP3InstBase <opName#"_vop3", VOP3_Profile<P, VOP3_OPSEL>, node, 1>,242 Commutable_REV<revOp#"_vop3_e64", !eq(revOp, opName)>;243 }244 }245 let SubtargetPredicate = UseRealTrue16Insts in {246 defm _t16 : VOP2Inst_e64<opName#"_t16", VOPProfile_True16<P>, node, revOp#"_t16">;247 }248 let SubtargetPredicate = UseFakeTrue16Insts in {249 defm _fake16 : VOP2Inst_e64<opName#"_fake16", VOPProfile_Fake16<P>, node, revOp#"_fake16">;250 }251}252 253multiclass VOP2Inst_VOPD<string opName,254 VOPProfile P,255 bits<6> VOPDOp,256 string VOPDName,257 SDPatternOperator node = null_frag,258 string revOp = opName> :259 VOP2Inst_e32_VOPD<opName, P, VOPDOp, VOPDName, node, revOp>,260 VOP2Inst_e64_VOPD<opName, P, VOPDOp, VOPDName, node, revOp>,261 VOP2Inst_sdwa<opName, P, revOp> {262 if P.HasExtDPP then263 def _dpp : VOP2_DPP_Pseudo <opName, P>;264}265 266multiclass VOP2bInst <string opName,267 VOPProfile P,268 SDPatternOperator node = null_frag,269 string revOp = opName,270 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {271 let SchedRW = [Write32Bit, WriteSALU] in {272 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {273 def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,274 Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {275 let usesCustomInserter = true;276 }277 278 if P.HasExtSDWA then279 def _sdwa : VOP2_SDWA_Pseudo <opName, P>,280 Commutable_REV<revOp#"_sdwa", !eq(revOp, opName)> {281 let AsmMatchConverter = "cvtSdwaVOP2b";282 }283 if P.HasExtDPP then284 def _dpp : VOP2_DPP_Pseudo <opName, P>;285 } // End Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC]286 287 def _e64 : VOP3InstBase <opName, P, node, 1>,288 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;289 290 if P.HasExtVOP3DPP then291 def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {292 let SubtargetPredicate = isGFX11Plus;293 }294 else if P.HasExt64BitDPP then295 def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {296 let OtherPredicates = [HasDPALU_DPP];297 }298 }299}300 301class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,302 string OpName, string opnd> :303 InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),304 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,305 ps.Pfl.Src1RC32:$src1),306 1, inst.AsmVariantName>,307 PredicateControl {308}309 310multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {311 let WaveSizePredicate = isWave32 in {312 def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;313 }314 let WaveSizePredicate = isWave64 in {315 def : VOP2bInstAlias<ps, inst, OpName, "vcc">;316 }317}318 319multiclass320 VOP2eInst_Base<string opName, VOPProfile P, bits<6> VOPDOp, string VOPDName,321 SDPatternOperator node, string revOp, bit useSGPRInput> {322 323 let SchedRW = [Write32Bit] in {324 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {325 if !empty(VOPDName) then326 def _e32 : VOP2_Pseudo <opName, P>,327 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;328 else329 def _e32 : VOP2_Pseudo <opName, P>,330 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>,331 VOPD_Component<VOPDOp, VOPDName>;332 333 if P.HasExtSDWA then334 def _sdwa : VOP2_SDWA_Pseudo <opName, P> {335 let AsmMatchConverter = "cvtSdwaVOP2e";336 }337 338 if P.HasExtDPP then339 def _dpp : VOP2_DPP_Pseudo <opName, P>;340 }341 342 let isReMaterializable = 1 in {343 if !empty(VOPDName) then344 def _e64 : VOP3InstBase <opName, P, node, 1>,345 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;346 else347 def _e64 : VOP3InstBase <opName, P, node, 1>,348 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>,349 VOPD_Component<VOPDOp, VOPDName>;350 }351 352 if P.HasExtVOP3DPP then353 def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {354 let SubtargetPredicate = isGFX11Plus;355 }356 else if P.HasExt64BitDPP then357 def _e64_dpp : VOP3_DPP_Pseudo <opName, P> {358 let OtherPredicates = [HasDPALU_DPP];359 }360 }361}362 363multiclass364 VOP2eInst<string opName, VOPProfile P, SDPatternOperator node = null_frag,365 string revOp = opName, bit useSGPRInput = !eq(P.NumSrcArgs, 3)>366 : VOP2eInst_Base<opName, P, 0, "", node, revOp, useSGPRInput>;367 368multiclass369 VOP2eInst_VOPD<string opName, VOPProfile P, bits<6> VOPDOp, string VOPDName,370 SDPatternOperator node = null_frag, string revOp = opName,371 bit useSGPRInput = !eq(P.NumSrcArgs, 3)>372 : VOP2eInst_Base<opName, P, VOPDOp, VOPDName, node, revOp, useSGPRInput>;373 374class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :375 InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,376 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,377 ps.Pfl.Src1RC32:$src1),378 1, inst.AsmVariantName>,379 PredicateControl;380 381class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :382 InstAlias <ps.OpName#" "#ps.Pfl.Asm64,383 (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,384 ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, Clamp:$clamp),385 1, inst.AsmVariantName>,386 PredicateControl;387 388multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {389 let WaveSizePredicate = isWave32 in {390 def : VOP2eInstAlias<ps, inst, "vcc_lo">;391 }392 let WaveSizePredicate = isWave64 in {393 def : VOP2eInstAlias<ps, inst, "vcc">;394 }395}396 397class VOP_MADK_Base<ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {398 string AsmVOPDX_immX = ?;399}400 401class VOP_MADAK <ValueType vt> : VOP_MADK_Base<vt> {402 field Operand ImmOpType = !if(!eq(vt.Size, 32), KImmFP32,403 !if(!eq(vt.Size, 64), KImmFP64,404 KImmFP16));405 field dag Ins32 = !if(!eq(vt.Size, 32),406 (ins VSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm),407 !if(!eq(vt.Size, 64),408 (ins VSrc_f64:$src0, VReg_64_AlignTarget:$src1, ImmOpType:$imm),409 (ins VSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm)));410 field dag InsVOPDX = (ins VSrc_f32:$src0X, VGPR_32:$vsrc1X, ImmOpType:$imm);411 let InsVOPDX_immX = (ins VSrc_f32:$src0X, VGPR_32:$vsrc1X, ImmOpType:$immX);412 field dag InsVOPDY = (ins VSrc_f32:$src0Y, VGPR_32:$vsrc1Y, ImmOpType:$imm);413 414 field string Asm32 = "$vdst, $src0, $src1, $imm";415 field string AsmVOPDX = "$vdstX, $src0X, $vsrc1X, $imm";416 let AsmVOPDX_immX = "$vdstX, $src0X, $vsrc1X, $immX";417 field string AsmVOPDY = "$vdstY, $src0Y, $vsrc1Y, $imm";418 field bit HasExt = 0;419 let IsSingle = 1;420}421 422def VOP_MADAK_F16 : VOP_MADAK <f16>;423def VOP_MADAK_F16_t16 : VOP_MADAK <f16> {424 let IsTrue16 = 1;425 let IsRealTrue16 = 1;426 let DstRC = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 0/*IsVOP3Encoding*/>.ret;427 let Ins32 = (ins VSrcT_f16_Lo128:$src0, VGPROp_16_Lo128:$src1, ImmOpType:$imm);428}429def VOP_MADAK_F16_fake16 : VOP_MADAK <f16> {430 let IsTrue16 = 1;431 let DstRC = getVALUDstForVT_fake16<DstVT>.ret;432 let Ins32 = (ins VSrcFake16_f16_Lo128:$src0, VGPROp_32_Lo128:$src1, ImmOpType:$imm);433}434def VOP_MADAK_F32 : VOP_MADAK <f32>;435def VOP_MADAK_F64 : VOP_MADAK <f64>;436 437class VOP_MADMK <ValueType vt> : VOP_MADK_Base<vt> {438 field Operand ImmOpType = !if(!eq(vt.Size, 32), KImmFP32,439 !if(!eq(vt.Size, 64), KImmFP64,440 KImmFP16));441 field dag Ins32 = !if(!eq(vt.Size, 32),442 (ins VSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1),443 !if(!eq(vt.Size, 64),444 (ins VSrc_f64:$src0, ImmOpType:$imm, VReg_64:$src1),445 (ins VSrc_f16:$src0, ImmOpType:$imm, VGPR_32:$src1)));446 field dag InsVOPDX = (ins VSrc_f32:$src0X, ImmOpType:$imm, VGPR_32:$vsrc1X);447 let InsVOPDX_immX = (ins VSrc_f32:$src0X, ImmOpType:$immX, VGPR_32:$vsrc1X);448 field dag InsVOPDY = (ins VSrc_f32:$src0Y, ImmOpType:$imm, VGPR_32:$vsrc1Y);449 450 field string Asm32 = "$vdst, $src0, $imm, $src1";451 field string AsmVOPDX = "$vdstX, $src0X, $imm, $vsrc1X";452 let AsmVOPDX_immX = "$vdstX, $src0X, $immX, $vsrc1X";453 field string AsmVOPDY = "$vdstY, $src0Y, $imm, $vsrc1Y";454 field bit HasExt = 0;455 let IsSingle = 1;456}457 458def VOP_MADMK_F16 : VOP_MADMK <f16>;459def VOP_MADMK_F16_t16 : VOP_MADMK <f16> {460 let IsTrue16 = 1;461 let IsRealTrue16 = 1;462 let DstRC = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 0/*IsVOP3Encoding*/>.ret;463 let Ins32 = (ins VSrcT_f16_Lo128:$src0, ImmOpType:$imm, VGPROp_16_Lo128:$src1);464}465def VOP_MADMK_F16_fake16 : VOP_MADMK <f16> {466 let IsTrue16 = 1;467 let DstRC = getVALUDstForVT_fake16<DstVT>.ret;468 let Ins32 = (ins VSrcFake16_f16_Lo128:$src0, ImmOpType:$imm, VGPROp_32_Lo128:$src1);469}470def VOP_MADMK_F32 : VOP_MADMK <f32>;471def VOP_MADMK_F64 : VOP_MADMK <f64>;472 473// Returns the vreg register class to use for sources of VOP3 instructions for the474// given VT.475class getVOP3VRegForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> {476 RegisterOperand ret =477 !cond(!eq(VT.Size, 128) : RegisterOperand<VReg_128_AlignTarget>,478 !eq(VT.Size, 96) : RegisterOperand<VReg_96_AlignTarget>,479 !eq(VT.Size, 64) : RegisterOperand<VReg_64_AlignTarget>,480 !eq(VT.Size, 48) : RegisterOperand<VReg_64_AlignTarget>,481 !eq(VT.Size, 16) : !if(IsTrue16,482 !if(IsFake16, RegisterOperand<VGPR_32>,483 RegisterOperand<VGPR_16>),484 RegisterOperand<VGPR_32>),485 1 : RegisterOperand<VGPR_32>);486}487 488// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory489// and processing time but it makes it easier to convert to mad.490class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> {491 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT>.ret:$src2);492 // Src2 must accept the same operand types as vdst, namely VGPRs only493 let Src2RC64 = getVOP3VRegForVT<Src2VT, IsTrue16, !not(IsRealTrue16)>.ret;494 let Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, 3,495 HasClamp, HasModifiers, HasModifiers, HasOMod,496 Src0Mod, Src1Mod, Src2Mod>.ret;497 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,498 Src1ModDPP:$src1_modifiers, Src1DPP:$src1,499 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument500 dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,501 DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);502 let InsDPP16 = !con(InsDPP, (ins Dpp16FI:$fi));503 let InsVOP3Base = getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP, RegisterOperand<VGPR_32>, 3,504 HasClamp, HasModifiers, HasModifiers, HasOMod,505 Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod, HasOpSel>.ret;506 // We need a dummy src2 tied to dst to track the use of that register for s_delay_alu507 let InsVOPDX = (ins Src0RC32:$src0X, Src1RC32:$vsrc1X, VGPROp_32:$src2X);508 let InsVOPDY = (ins Src0RC32:$src0Y, Src1RC32:$vsrc1Y, VGPROp_32:$src2Y);509 let InsVOPD3X = (ins Src0ModVOPD3:$src0X_modifiers, Src0VOPD3:$src0X,510 Src1ModVOPD3:$vsrc1X_modifiers, Src1RC32:$vsrc1X,511 VGPROp_32:$src2X);512 let InsVOPD3Y = (ins Src0ModVOPD3:$src0Y_modifiers, Src0VOPD3:$src0Y,513 Src1ModVOPD3:$vsrc1Y_modifiers, Src1RC32:$vsrc1Y,514 VGPROp_32:$src2Y);515 516 let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,517 Src1ModDPP:$src1_modifiers, Src1DPP:$src1,518 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument519 dpp8:$dpp8, Dpp8FI:$fi);520 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,521 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,522 getVregSrcForVT<Src2VT>.ret:$src2, // stub argument523 Clamp:$clamp, omod:$omod,524 dst_sel:$dst_sel, dst_unused:$dst_unused,525 src0_sel:$src0_sel, src1_sel:$src1_sel);526 let Asm32 = getAsm32<1, 2, vt0>.ret;527 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret;528 let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret;529 let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;530 let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret;531 let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret;532 let AsmVOP3Base =533 getAsmVOP3Base<2 /*NumSrcArgs*/, HasDst, HasClamp,534 HasOpSel, HasOMod, IsVOP3P, HasModifiers,535 HasModifiers, HasModifiers,536 0 /*Src2HasMods*/, DstVT>.ret;537 let HasSrc2 = 0;538 let HasSrc2Mods = 0;539 let HasVOPD3Src2 = 0;540 541 let HasExt = 1;542 let HasExtDPP = 1;543 let HasExt32BitDPP = 1;544 let HasExtSDWA = 1;545 let HasExtSDWA9 = 0;546 let TieRegDPP = "$src2";547}548 549def VOP_MAC_F16 : VOP_MAC <f16>;550def VOP_MAC_F16_t16 : VOP_MAC <f16> {551 let IsTrue16 = 1;552 let IsRealTrue16 = 1;553 let HasOpSel = 1;554 let DstRC = VOPDstOperand_t16Lo128;555 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;556 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;557 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret:$src2);558 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;559 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;560 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;561 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret;562 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret;563 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret;564 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,565 Src1ModDPP:$src1_modifiers, Src1DPP:$src1,566 getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret:$src2, // stub argument567 dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,568 DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);569 let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,570 Src1ModDPP:$src1_modifiers, Src1DPP:$src1,571 getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret:$src2, // stub argument572 dpp8:$dpp8, Dpp8FI:$fi);573 let DstRC64 = getVALUDstForVT<DstVT, 1/*IsTrue*/, 1/*IsVOP3Encoding*/>.ret;574 let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret;575 let Src1RC64 = getVOP3SrcForVT<Src1VT, 1/*IsTrue16*/>.ret;576 let Src0VOP3DPP = VGPROp_16;577 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;578 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret;579 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret;580 let Src1ModVOP3DPP = getSrcModVOP3VC<Src1VT, 0/*IsFake16*/>.ret;581 let Src2ModVOP3DPP = getSrcModVOP3VC<Src2VT, 0/*IsFake16*/>.ret;582 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;583 let Src1Mod = getSrcMod<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;584 let Src2Mod = getSrcMod<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;585}586def VOP_MAC_F16_fake16 : VOP_MAC <f16> {587 let IsTrue16 = 1;588 let DstRC = getVALUDstForVT_fake16<DstVT>.ret;589 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;590 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;591 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret:$src2);592 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;593 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;594 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;595 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret;596 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret;597 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret;598 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,599 Src1ModDPP:$src1_modifiers, Src1DPP:$src1,600 getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret:$src2, // stub argument601 dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,602 DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);603 let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,604 Src1ModDPP:$src1_modifiers, Src1DPP:$src1,605 getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret:$src2, // stub argument606 dpp8:$dpp8, Dpp8FI:$fi);607 let DstRC64 = getVALUDstForVT<DstVT>.ret;608 let Src0VOP3DPP = VGPROp_32;609 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;610 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret;611 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 1/*IsFake16*/>.ret;612 let Src1ModVOP3DPP = getSrcModVOP3VC<Src1VT, 1/*IsFake16*/>.ret;613 let Src2ModVOP3DPP = getSrcModVOP3VC<Src2VT, 1/*IsFake16*/>.ret;614 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;615 let Src1Mod = getSrcMod<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;616 let Src2Mod = getSrcMod<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;617}618 619def VOP_MAC_F32 : VOP_MAC <f32>;620let HasExtDPP = 0, HasExt32BitDPP = 0 in621def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>;622let HasExtSDWA = 0, HasExt32BitDPP = 0, HasExt64BitDPP = 1 in623def VOP_MAC_F64 : VOP_MAC <f64>;624 625class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> {626 let HasClamp = 0;627 let HasExtSDWA = 0;628 let HasOpSel = 0;629 let IsPacked = 0;630}631 632def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> {633 let Src0ModDPP = FPVRegInputMods;634 let Src1ModDPP = FPVRegInputMods;635 let HasClamp = 1;636}637 638def VOP_DOT_ACC_F32_V2BF16 : VOP_DOT_ACC<f32, v2bf16> {639 let Src0ModDPP = FPVRegInputMods;640 let Src1ModDPP = FPVRegInputMods;641 let HasClamp = 1;642}643 644def VOP_DOT_ACC_I32_I32 : VOP_DOT_ACC<i32, i32> {645 let HasExtVOP3DPP = 0;646 let HasSrc0Mods = 1;647 let HasSrc1Mods = 1;648 let HasClamp = 1;649 650 let Src0Mod = Int32InputMods;651 let Src1Mod = Int32InputMods;652 let Ins64 = getIns64<Src0RC64, Src1RC64, getVregSrcForVT<Src2VT>.ret,653 3 /*NumSrcArgs*/, HasClamp, 1 /*HasModifiers*/,654 1 /*HasSrc2Mods*/, HasOMod,655 Src0Mod, Src1Mod, Src2Mod>.ret;656 let Asm64 = "$vdst, $src0, $src1$clamp";657}658 659// Write out to vcc or arbitrary SGPR.660def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], /*EnableClamp=*/1> {661 let Asm32 = "$vdst, vcc, $src0, $src1";662 let AsmVOP3Base = "$vdst, $sdst, $src0, $src1$clamp";663 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";664 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";665 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";666 let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";667 let AsmDPP16 = AsmDPP#"$fi";668 let InsDPP = (ins DstRCDPP:$old,669 Src0DPP:$src0,670 Src1DPP:$src1,671 dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,672 DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);673 let InsDPP16 = !con(InsDPP, (ins Dpp16FI:$fi));674 let InsDPP8 = (ins DstRCDPP:$old,675 Src0DPP:$src0,676 Src1DPP:$src1,677 dpp8:$dpp8, Dpp8FI:$fi);678 let Outs32 = (outs DstRC:$vdst);679 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);680 let OutsVOP3DPP = Outs64;681 let OutsVOP3DPP8 = Outs64;682}683 684// Write out to vcc or arbitrary SGPR and read in from vcc or685// arbitrary SGPR.686def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableClamp=*/1> {687 let HasSrc2Mods = 0;688 let Asm32 = "$vdst, vcc, $src0, $src1, vcc";689 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";690 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";691 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";692 let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";693 let AsmDPP16 = AsmDPP#"$fi";694 let Outs32 = (outs DstRC:$vdst);695 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);696 let AsmVOP3Base = "$vdst, $sdst, $src0, $src1, $src2$clamp";697 let OutsVOP3DPP = Outs64;698 let OutsVOP3DPP8 = Outs64;699 700 // Suppress src2 implied by type since the 32-bit encoding uses an701 // implicit VCC use.702 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);703 704 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,705 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,706 Clamp:$clamp,707 dst_sel:$dst_sel, dst_unused:$dst_unused,708 src0_sel:$src0_sel, src1_sel:$src1_sel);709 710 let InsDPP = (ins DstRCDPP:$old,711 Src0DPP:$src0,712 Src1DPP:$src1,713 dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,714 DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);715 let InsDPP16 = !con(InsDPP, (ins Dpp16FI:$fi));716 let InsDPP8 = (ins DstRCDPP:$old,717 Src0DPP:$src0,718 Src1DPP:$src1,719 dpp8:$dpp8, Dpp8FI:$fi);720 721 let HasExt = 1;722 let HasExtDPP = 1;723 let HasExt32BitDPP = 1;724 let HasExtSDWA = 1;725 let HasExtSDWA9 = 1;726}727 728// Read in from vcc or arbitrary SGPR.729class VOP2e_SGPR<list<ValueType> ArgVT> : VOPProfile<ArgVT> {730 let Asm32 = "$vdst, $src0, $src1";731 let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";732 let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";733 let AsmDPP = "$vdst, $src0_modifiers, $src1_modifiers, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";734 let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";735 let AsmDPP16 = AsmDPP#"$fi";736 let AsmVOP3Base = "$vdst, $src0_modifiers, $src1_modifiers, $src2";737 738 let Outs32 = (outs DstRC:$vdst);739 let Outs64 = (outs DstRC64:$vdst);740 741 // Suppress src2 implied by type since the 32-bit encoding uses an742 // implicit VCC use.743 let Ins32 = (ins VSrc_f32:$src0, Src1RC32:$src1);744 745 let HasModifiers = 1;746 747 // Select FP modifiers for VOP3748 let Src0Mod = !if(!eq(Src0VT.Size, 16), FP16InputMods, FP32InputMods);749 let Src1Mod = Src0Mod;750 751 let HasSrc0IntMods = 0;752 let HasSrc1IntMods = 0;753 let HasSrc0FloatMods = 1;754 let HasSrc1FloatMods = 1;755 let InsSDWA = (ins FP32SDWAInputMods:$src0_modifiers, SDWASrc_f32:$src0,756 FP32SDWAInputMods:$src1_modifiers, SDWASrc_f32:$src1,757 Clamp:$clamp,758 dst_sel:$dst_sel, dst_unused:$dst_unused,759 src0_sel:$src0_sel, src1_sel:$src1_sel);760 761 let InsDPP = (ins DstRCDPP:$old,762 FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,763 FPVRegInputMods:$src1_modifiers, Src1DPP:$src1,764 dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,765 DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);766 let InsDPP16 = !con(InsDPP, (ins Dpp16FI:$fi));767 let InsDPP8 = (ins DstRCDPP:$old,768 FPVRegInputMods:$src0_modifiers, Src0DPP:$src0,769 FPVRegInputMods:$src1_modifiers, Src1DPP:$src1,770 dpp8:$dpp8, Dpp8FI:$fi);771 772 let Src0ModVOP3DPP = FPVRegInputMods;773 let Src1ModVOP3DPP = FP32VCSrcInputMods;774 775 let HasExt = 1;776 let HasExtDPP = 1;777 let HasExt32BitDPP = 1;778 let HasExtSDWA = 1;779 let HasExtSDWA9 = 1;780}781 782def VOP2e_I32_I32_I32_I1 : VOP2e_SGPR<[i32, i32, i32, i1]> {783 let Src2VOPD3 = SSrc_i1;784 let InsVOPD3X = (ins FP32VCSrcInputMods:$src0X_modifiers, Src0VOPD3:$src0X, FP32VRegSrcInputMods:$vsrc1X_modifiers, Src1VOPD3:$vsrc1X, Src2VOPD3:$vsrc2X);785 let InsVOPD3Y = (ins FP32VCSrcInputMods:$src0Y_modifiers, Src0VOPD3:$src0Y, FP32VRegSrcInputMods:$vsrc1Y_modifiers, Src1VOPD3:$vsrc1Y, Src2VOPD3:$vsrc2Y);786 let AsmVOPD3X = "$vdstX, $src0X_modifiers, $vsrc1X_modifiers, $vsrc2X";787 let AsmVOPD3Y = "$vdstY, $src0Y_modifiers, $vsrc1Y_modifiers, $vsrc2Y";788 let HasVOPD3Src2 = 0;789}790def VOP2e_I16_I16_I16_I1 : VOP2e_SGPR<[i16, i16, i16, i1]>;791// V_CNDMASK_B16 is VOP3 only792def VOP2e_I16_I16_I16_I1_true16 : VOP2e_SGPR<[i16, i16, i16, i1]> {793 let IsTrue16 = 1;794 let IsRealTrue16 = 1;795 let HasOpSel = 1;796 let DstRC64 = getVALUDstForVT<DstVT, 1, 1>.ret;797 let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret;798 let Src1RC64 = getVOP3SrcForVT<Src1VT, 1/*IsTrue16*/>.ret;799 let Src2RC64 = getVOP3SrcForVT<Src2VT, 1/*IsTrue16*/>.ret;800 let Src0Mod = getSrc0Mod<f16, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;801 let Src1Mod = getSrcMod<f16, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;802 let HasSrc2Mods = 0;803 let InsVOP3OpSel = getInsVOP3Base<Src0RC64, Src1RC64,804 Src2RC64, NumSrcArgs,805 HasClamp, 1/*HasModifiers*/, 0/*HasSrc2Mods*/, HasOMod,806 Src0Mod, Src1Mod, Src2Mod, 1/*HasOpSel*/>.ret;807 let Src0VOP3DPP = VGPROp_16;808 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;809 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<f16, DstVT, 0/*IsFake16*/>.ret;810 let Src1ModVOP3DPP = getSrcModVOP3VC<f16, 0/*IsFake16*/>.ret;811}812def VOP2e_I16_I16_I16_I1_fake16 : VOP2e_SGPR<[i16, i16, i16, i1]> {813 let IsTrue16 = 1;814 let DstRC64 = getVALUDstForVT<DstVT>.ret;815 816 let Src0Mod = getSrc0Mod<f16, DstVT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;817 let Src1Mod = getSrcMod<f16, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;818 819 let Src0VOP3DPP = VGPROp_32;820 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;821 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<f16, DstVT, 1/*IsFake16*/>.ret;822 let Src1ModVOP3DPP = getSrcModVOP3VC<f16, 1/*IsFake16*/>.ret;823}824 825def VOP_READLANE : VOPProfile<[i32, i32, i32, untyped]> {826 let Outs32 = (outs SReg_32_XM0:$vdst);827 let Outs64 = Outs32;828 let Ins32 = (ins VRegOrLdsSrc_32:$src0, SCSrc_b32:$src1);829 let Ins64 = Ins32;830 let Asm32 = " $vdst, $src0, $src1";831 let Asm64 = Asm32;832 833 let HasExt = 0;834 let HasExtDPP = 0;835 let HasExt32BitDPP = 0;836 let HasExt64BitDPP = 0;837 let HasExtSDWA = 0;838 let HasExtSDWA9 = 0;839}840 841def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {842 let Outs32 = (outs VGPR_32:$vdst);843 let Outs64 = Outs32;844 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in);845 let Ins64 = Ins32;846 let Asm32 = " $vdst, $src0, $src1";847 let Asm64 = Asm32;848 let HasSrc2 = 0;849 let HasSrc2Mods = 0;850 851 let HasExt = 0;852 let HasExtDPP = 0;853 let HasExt32BitDPP = 0;854 let HasExt64BitDPP = 0;855 let HasExtSDWA = 0;856 let HasExtSDWA9 = 0;857}858 859//===----------------------------------------------------------------------===//860// VOP2 Instructions861//===----------------------------------------------------------------------===//862 863let SubtargetPredicate = isGFX11Plus, True16Predicate = UseRealTrue16Insts in864defm V_CNDMASK_B16_t16 : VOP2eInst <"v_cndmask_b16_t16", VOP2e_I16_I16_I16_I1_true16>;865let SubtargetPredicate = isGFX11Plus, True16Predicate = UseFakeTrue16Insts in866defm V_CNDMASK_B16_fake16 : VOP2eInst <"v_cndmask_b16_fake16", VOP2e_I16_I16_I16_I1_fake16>;867defm V_CNDMASK_B32 : VOP2eInst_VOPD <"v_cndmask_b32", VOP2e_I32_I32_I32_I1, 0x9, "v_cndmask_b32">;868let SubtargetPredicate = HasMadMacF32Insts, isReMaterializable = 1 in869def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;870 871let isCommutable = 1 in {872let isReMaterializable = 1 in {873defm V_ADD_F32 : VOP2Inst_VOPD <"v_add_f32", VOP_F32_F32_F32, 0x4, "v_add_f32", any_fadd>;874defm V_SUB_F32 : VOP2Inst_VOPD <"v_sub_f32", VOP_F32_F32_F32, 0x5, "v_sub_f32", any_fsub>;875defm V_SUBREV_F32 : VOP2Inst_VOPD <"v_subrev_f32", VOP_F32_F32_F32, 0x6, "v_subrev_f32", null_frag, "v_sub_f32">;876defm V_MUL_LEGACY_F32 : VOP2Inst_VOPD <"v_mul_legacy_f32", VOP_F32_F32_F32, 0x7, "v_mul_dx9_zero_f32", AMDGPUfmul_legacy>;877defm V_MUL_F32 : VOP2Inst_VOPD <"v_mul_f32", VOP_F32_F32_F32, 0x3, "v_mul_f32", any_fmul>;878defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;879defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>;880defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;881defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>;882defm V_MIN_F32 : VOP2Inst_VOPD <"v_min_f32", VOP_F32_F32_F32, 0xb, "v_min_f32", fminnum_like>;883defm V_MAX_F32 : VOP2Inst_VOPD <"v_max_f32", VOP_F32_F32_F32, 0xa, "v_max_f32", fmaxnum_like>;884defm V_MIN_I32 : VOP2Inst_VOPD <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, 0x18, "v_min_i32", smin>;885defm V_MAX_I32 : VOP2Inst_VOPD <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, 0x17, "v_max_i32", smax>;886defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;887defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;888defm V_LSHRREV_B32 : VOP2Inst_VOPD <"v_lshrrev_b32", VOP_I32_I32_I32, 0x15, "v_lshrrev_b32", clshr_rev_32, "v_lshr_b32">;889defm V_ASHRREV_I32 : VOP2Inst_VOPD <"v_ashrrev_i32", VOP_I32_I32_I32, 0x16, "v_ashrrev_i32", cashr_rev_32, "v_ashr_i32">;890defm V_LSHLREV_B32 : VOP2Inst_VOPD <"v_lshlrev_b32", VOP_I32_I32_I32, 0x11, "v_lshlrev_b32", clshl_rev_32, "v_lshl_b32">;891defm V_AND_B32 : VOP2Inst_VOPD <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, 0x12, "v_and_b32", and>;892defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;893defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;894} // End isReMaterializable = 1895 896let mayRaiseFPException = 0 in {897let OtherPredicates = [HasMadMacF32Insts] in {898let Constraints = "$vdst = $src2",899 isConvertibleToThreeAddress = 1 in {900defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;901 902let SubtargetPredicate = isGFX6GFX7GFX10 in903defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>;904} // End Constraints = "$vdst = $src2",905 // isConvertibleToThreeAddress = 1906 907let isReMaterializable = 1 in908def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;909} // End OtherPredicates = [HasMadMacF32Insts]910} // End mayRaiseFPException = 0911 912// No patterns so that the scalar instructions are always selected.913// The scalar versions will be replaced with vector when needed later.914defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32">;915defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32">;916defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;917defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;918 919 920let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1 in {921 defm V_SUB_U32 : VOP2Inst_VOPD <"v_sub_u32", VOP_I32_I32_I32_ARITH, 0x14, "v_sub_nc_u32", null_frag, "v_sub_u32">;922 defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32">;923}924 925let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1, isAdd = 1 in {926 defm V_ADD_U32 : VOP2Inst_VOPD <"v_add_u32", VOP_I32_I32_I32_ARITH, 0x10, "v_add_nc_u32", null_frag, "v_add_u32">;927}928 929let isAdd = 1 in {930 defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32">;931 defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32">;932}933 934let isReMaterializable = 1 in {935let SubtargetPredicate = HasAddSubU64Insts, SchedRW = [Write64Bit] in {936defm V_ADD_U64 : VOP2Inst <"v_add_nc_u64", VOP_I64_I64_I64_ARITH>;937// We don't actually have something like V_SUBREV_U64 so V_SUB_U64 can't be treated as commutable.938let isCommutable = 0 in939defm V_SUB_U64 : VOP2Inst <"v_sub_nc_u64", VOP_I64_I64_I64_ARITH>;940} // End SubtargetPredicate = HasAddSubU64Insts, SchedRW = [Write64Bit]941let SubtargetPredicate = isGFX1250Plus, SchedRW = [WriteDouble] in942defm V_MUL_U64 : VOP2Inst <"v_mul_u64", VOP_I64_I64_I64, DivergentBinFrag<mul>>;943} // End isReMaterializable = 1944 945} // End isCommutable = 1946 947// These are special and do not read the exec mask.948let isConvergent = 1, Uses = []<Register> in {949def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE, []>;950let IsNeverUniform = 1, Constraints = "$vdst = $vdst_in" in {951def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, []>;952} // End IsNeverUniform, $vdst = $vdst_in953} // End isConvergent = 1954 955foreach vt = Reg32Types.types in {956 def : GCNPat<(vt (int_amdgcn_readlane vt:$src0, i32:$src1)),957 (V_READLANE_B32 VRegOrLdsSrc_32:$src0, SCSrc_b32:$src1)958 >;959 960 def : GCNPat<(vt (int_amdgcn_writelane vt:$src0, i32:$src1, vt:$src2)),961 (V_WRITELANE_B32 SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$src2)962 >;963}964 965let isReMaterializable = 1 in {966defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_I32_I32_I32>;967defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_I32_I32_I32, add_ctpop>;968let IsNeverUniform = 1 in {969defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_lo>;970defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_hi>;971} // End IsNeverUniform = 1972defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, any_fldexp>;973 974let ReadsModeReg = 0, mayRaiseFPException = 0, SubtargetPredicate = HasCvtPkNormVOP2Insts in {975defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_V2I16_F32_F32, AMDGPUpknorm_i16_f32>;976defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_V2I16_F32_F32, AMDGPUpknorm_u16_f32>;977}978 979defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_V2F16_F32_F32, AMDGPUpkrtz_f16_f32>;980defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_V2I16_I32_I32, AMDGPUpk_u16_u32>;981defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_V2I16_I32_I32, AMDGPUpk_i16_i32>;982 983 984let SubtargetPredicate = isGFX6GFX7 in {985defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;986defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;987} // End SubtargetPredicate = isGFX6GFX7988 989let isCommutable = 1 in {990let SubtargetPredicate = isGFX6GFX7 in {991defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, csrl_32>;992defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, csra_32>;993defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, cshl_32>;994} // End SubtargetPredicate = isGFX6GFX7995} // End isCommutable = 1996} // End isReMaterializable = 1997 998defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"999 1000class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :1001 GCNPat<1002 (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),1003 !if(!cast<Commutable_REV>(Inst).IsOrig,1004 (Inst $src0, $src1),1005 (Inst $src1, $src0)1006 )1007 >;1008 1009class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :1010 GCNPat<1011 (DivergentBinFrag<Op> Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),1012 !if(!cast<Commutable_REV>(Inst).IsOrig,1013 (Inst $src0, $src1, 0),1014 (Inst $src1, $src0, 0)1015 )1016 >;1017 1018def : DivergentBinOp<csrl_32, V_LSHRREV_B32_e64>;1019def : DivergentBinOp<csra_32, V_ASHRREV_I32_e64>;1020def : DivergentBinOp<cshl_32, V_LSHLREV_B32_e64>;1021 1022let SubtargetPredicate = HasAddNoCarryInsts in {1023 def : DivergentClampingBinOp<add, V_ADD_U32_e64>;1024 def : DivergentClampingBinOp<sub, V_SUB_U32_e64>;1025}1026 1027let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {1028def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>;1029def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>;1030}1031 1032def : DivergentBinOp<adde, V_ADDC_U32_e32>;1033def : DivergentBinOp<sube, V_SUBB_U32_e32>;1034 1035class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst, ValueType vt = i64> :1036 GCNPat<1037 (DivergentBinFrag<Op> vt:$src0, vt:$src1),1038 (REG_SEQUENCE VReg_64,1039 (Inst1040 (i32 (EXTRACT_SUBREG $src0, sub0)),1041 (i32 (EXTRACT_SUBREG $src1, sub0))1042 ), sub0,1043 (Inst1044 (i32 (EXTRACT_SUBREG $src0, sub1)),1045 (i32 (EXTRACT_SUBREG $src1, sub1))1046 ), sub11047 )1048 >;1049 1050def : divergent_i64_BinOp <and, V_AND_B32_e64>;1051def : divergent_i64_BinOp <or, V_OR_B32_e64>;1052def : divergent_i64_BinOp <xor, V_XOR_B32_e64>;1053 1054def : divergent_i64_BinOp <and, V_AND_B32_e64, v2i32>;1055def : divergent_i64_BinOp <or, V_OR_B32_e64, v2i32>;1056def : divergent_i64_BinOp <xor, V_XOR_B32_e64, v2i32>;1057 1058// mul24 w/ 64 bit output.1059class mul24_64_Pat<SDPatternOperator Op, Instruction InstLo, Instruction InstHi> : GCNPat<1060 (i64 (Op i32:$src0, i32:$src1)),1061 (REG_SEQUENCE VReg_64,1062 (InstLo $src0, $src1), sub0,1063 (InstHi $src0, $src1), sub1)1064>;1065 1066def : mul24_64_Pat<AMDGPUmul_i24, V_MUL_I32_I24_e64, V_MUL_HI_I32_I24_e64>;1067def : mul24_64_Pat<AMDGPUmul_u24, V_MUL_U32_U24_e64, V_MUL_HI_U32_U24_e64>;1068 1069//===----------------------------------------------------------------------===//1070// 16-Bit Operand Instructions1071//===----------------------------------------------------------------------===//1072 1073// The ldexp.f16 intrinsic expects a integer src1 operand, though the hardware1074// encoding treats src1 as an f161075def LDEXP_F16_VOPProfile : VOPProfile <[f16, f16, f16, untyped]> {1076 let Src1Mod = Int32InputMods;1077 let Src1ModDPP = IntVRegInputMods;1078 let Src1ModVOP3DPP = IntVRegInputMods;1079 // SDWA sext is the only modifier allowed.1080 let HasSrc1IntMods = 1;1081 let HasSrc1FloatMods = 0;1082 let Src1ModSDWA = Int16SDWAInputMods;1083}1084def LDEXP_F16_VOPProfile_True16 : VOPProfile_True16<VOP_F16_F16_F16> {1085 let Src1Mod = IntT16InputMods<0/*IsFake16*/>;1086 let Src1ModDPP = IntT16_Lo128VRegInputMods<0/*IsFake16*/>;1087 let Src1ModVOP3DPP = IntT16VCSrcInputMods<0/*IsFake16*/>;1088}1089def LDEXP_F16_VOPProfile_Fake16 : VOPProfile_Fake16<VOP_F16_F16_F16> {1090 let Src1Mod = Int32InputMods;1091 let Src1ModDPP = IntT16_Lo128VRegInputMods<1/*IsFake16*/>;1092 let Src1ModVOP3DPP = IntT16VCSrcInputMods<1/*IsFake16*/>;1093}1094 1095let isReMaterializable = 1 in {1096let FPDPRounding = 1 in {1097 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in1098 defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", LDEXP_F16_VOPProfile>;1099 let SubtargetPredicate = UseRealTrue16Insts in1100 defm V_LDEXP_F16_t16 : VOP2Inst <"v_ldexp_f16_t16", LDEXP_F16_VOPProfile_True16>;1101 let SubtargetPredicate = UseFakeTrue16Insts in1102 defm V_LDEXP_F16_fake16 : VOP2Inst <"v_ldexp_f16_fake16", LDEXP_F16_VOPProfile_Fake16, null_frag, "v_ldexp_f16_fake16">;1103} // End FPDPRounding = 11104defm V_LSHLREV_B16 : VOP2Inst_e64_t16 <"v_lshlrev_b16", VOP_I16_I16_I16, clshl_rev_16>;1105defm V_LSHRREV_B16 : VOP2Inst_e64_t16 <"v_lshrrev_b16", VOP_I16_I16_I16, clshr_rev_16>;1106defm V_ASHRREV_I16 : VOP2Inst_e64_t16 <"v_ashrrev_i16", VOP_I16_I16_I16, cashr_rev_16>;1107let isCommutable = 1 in {1108let FPDPRounding = 1 in {1109defm V_ADD_F16 : VOP2Inst_t16 <"v_add_f16", VOP_F16_F16_F16, any_fadd>;1110defm V_SUB_F16 : VOP2Inst_t16 <"v_sub_f16", VOP_F16_F16_F16, any_fsub>;1111defm V_SUBREV_F16 : VOP2Inst_t16 <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;1112defm V_MUL_F16 : VOP2Inst_t16 <"v_mul_f16", VOP_F16_F16_F16, any_fmul>;1113} // End FPDPRounding = 11114defm V_MUL_LO_U16 : VOP2Inst_e64_t16 <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;1115defm V_MAX_F16 : VOP2Inst_t16 <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;1116defm V_MIN_F16 : VOP2Inst_t16 <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;1117defm V_MAX_U16 : VOP2Inst_e64_t16 <"v_max_u16", VOP_I16_I16_I16, umax>;1118defm V_MAX_I16 : VOP2Inst_e64_t16 <"v_max_i16", VOP_I16_I16_I16, smax>;1119defm V_MIN_U16 : VOP2Inst_e64_t16 <"v_min_u16", VOP_I16_I16_I16, umin>;1120defm V_MIN_I16 : VOP2Inst_e64_t16 <"v_min_i16", VOP_I16_I16_I16, smin>;1121} // End isCommutable = 11122} // End isReMaterializable = 11123 1124class LDEXP_F16_Pat <SDPatternOperator op, VOP_Pseudo inst, VOPProfile P = inst.Pfl> : GCNPat <1125 (P.DstVT (op (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),1126 (i16 (VOP3Mods0 P.Src1VT:$src1, i32:$src1_modifiers)))),1127 (inst $src0_modifiers, $src0,1128 $src1_modifiers, $src1,1129 $clamp, /* clamp */1130 $omod /* omod */)1131>;1132 1133let OtherPredicates = [NotHasTrue16BitInsts] in1134def : LDEXP_F16_Pat<any_fldexp, V_LDEXP_F16_e64>;1135 1136class LDEXP_F16_t16_Pat <SDPatternOperator op, VOP_Pseudo inst, VOPProfile P = inst.Pfl> : GCNPat <1137 (P.DstVT (op (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),1138 (i16 (VOP3Mods0 P.Src1VT:$src1, i32:$src1_modifiers)))),1139 (inst $src0_modifiers, $src0,1140 $src1_modifiers, $src1,1141 $clamp, /* clamp */1142 $omod, /* omod */1143 0) /* op_sel */1144>;1145 1146let OtherPredicates = [UseRealTrue16Insts] in1147def : LDEXP_F16_t16_Pat<any_fldexp, V_LDEXP_F16_t16_e64>;1148 1149let OtherPredicates = [UseFakeTrue16Insts] in1150def : LDEXP_F16_Pat<any_fldexp, V_LDEXP_F16_fake16_e64>;1151 1152let SubtargetPredicate = isGFX11Plus in {1153 let isCommutable = 1 in {1154 defm V_AND_B16_t16 : VOP2Inst_e64 <"v_and_b16_t16", VOPProfile_True16<VOP_I16_I16_I16>, and>;1155 defm V_AND_B16_fake16 : VOP2Inst_e64 <"v_and_b16_fake16", VOPProfile_Fake16<VOP_I16_I16_I16>, and>;1156 defm V_OR_B16_t16 : VOP2Inst_e64 <"v_or_b16_t16", VOPProfile_True16<VOP_I16_I16_I16>, or>;1157 defm V_OR_B16_fake16 : VOP2Inst_e64 <"v_or_b16_fake16", VOPProfile_Fake16<VOP_I16_I16_I16>, or>;1158 defm V_XOR_B16_t16 : VOP2Inst_e64 <"v_xor_b16_t16", VOPProfile_True16<VOP_I16_I16_I16>, xor>;1159 defm V_XOR_B16_fake16 : VOP2Inst_e64 <"v_xor_b16_fake16", VOPProfile_Fake16<VOP_I16_I16_I16>, xor>;1160 } // End isCommutable = 11161} // End SubtargetPredicate = isGFX11Plus1162 1163let FPDPRounding = 1, isReMaterializable = 1, FixedSize = 1 in {1164let SubtargetPredicate = isGFX10Plus, True16Predicate = NotHasTrue16BitInsts in {1165 def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">;1166}1167let True16Predicate = UseRealTrue16Insts in {1168 def V_FMAMK_F16_t16 : VOP2_Pseudo <"v_fmamk_f16_t16", VOP_MADMK_F16_t16, [], "">;1169}1170let True16Predicate = UseFakeTrue16Insts in {1171 def V_FMAMK_F16_fake16 : VOP2_Pseudo <"v_fmamk_f16_fake16", VOP_MADMK_F16_fake16, [], "">;1172}1173 1174let isCommutable = 1 in {1175let SubtargetPredicate = isGFX10Plus, True16Predicate = NotHasTrue16BitInsts in {1176 def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">;1177}1178let True16Predicate = UseRealTrue16Insts in {1179 def V_FMAAK_F16_t16 : VOP2_Pseudo <"v_fmaak_f16_t16", VOP_MADAK_F16_t16, [], "">;1180}1181let True16Predicate = UseFakeTrue16Insts in {1182 def V_FMAAK_F16_fake16 : VOP2_Pseudo <"v_fmaak_f16_fake16", VOP_MADAK_F16_fake16, [], "">;1183}1184} // End isCommutable = 11185} // End FPDPRounding = 1, isReMaterializable = 1, FixedSize = 11186 1187let Constraints = "$vdst = $src2",1188 isConvertibleToThreeAddress = 1,1189 isCommutable = 1 in {1190let SubtargetPredicate = isGFX10Plus in {1191let True16Predicate = NotHasTrue16BitInsts in {1192 defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;1193}1194let True16Predicate = UseRealTrue16Insts in {1195 defm V_FMAC_F16_t16 : VOP2Inst <"v_fmac_f16_t16", VOP_MAC_F16_t16>;1196}1197let True16Predicate = UseFakeTrue16Insts in {1198 defm V_FMAC_F16_fake16 : VOP2Inst <"v_fmac_f16_fake16", VOP_MAC_F16_fake16>;1199}1200} // End SubtargetPredicate = isGFX10Plus1201} // End FMAC Constraints1202 1203let SubtargetPredicate = Has16BitInsts in {1204let isReMaterializable = 1 in {1205let FPDPRounding = 1 in {1206 def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;1207} // End FPDPRounding = 11208let isCommutable = 1 in {1209let mayRaiseFPException = 0 in {1210 def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;1211}1212let SubtargetPredicate = isGFX8GFX9 in {1213 defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;1214 defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;1215 defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;1216}1217} // End isCommutable = 11218} // End isReMaterializable = 11219 1220// FIXME: Missing FPDPRounding1221let Constraints = "$vdst = $src2",1222 isConvertibleToThreeAddress = 1, isCommutable = 1 in {1223defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;1224}1225} // End SubtargetPredicate = Has16BitInsts1226 1227 1228let SubtargetPredicate = HasDLInsts in {1229 1230let isReMaterializable = 1 in1231defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32, xnor>;1232 1233def : GCNPat<1234 (i32 (DivergentUnaryFrag<not> (xor_oneuse i32:$src0, i32:$src1))),1235 (i32 (V_XNOR_B32_e64 $src0, $src1))1236>;1237 1238def : GCNPat<1239 (i32 (DivergentBinFrag<xor_oneuse> (not i32:$src0), i32:$src1)),1240 (i32 (V_XNOR_B32_e64 $src0, $src1))1241>;1242 1243def : GCNPat<1244 (i64 (DivergentUnaryFrag<not> (xor_oneuse i64:$src0, i64:$src1))),1245 (REG_SEQUENCE VReg_64, (i32 (V_XNOR_B32_e641246 (i32 (EXTRACT_SUBREG $src0, sub0)),1247 (i32 (EXTRACT_SUBREG $src1, sub0)))), sub0,1248 (i32 (V_XNOR_B32_e641249 (i32 (EXTRACT_SUBREG $src0, sub1)),1250 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1)1251>;1252 1253def : GCNPat<1254 (i64 (DivergentBinFrag<xor_oneuse> (not i64:$src0), i64:$src1)),1255 (REG_SEQUENCE VReg_64, (i32 (V_XNOR_B32_e641256 (i32 (EXTRACT_SUBREG $src0, sub0)),1257 (i32 (EXTRACT_SUBREG $src1, sub0)))), sub0,1258 (i32 (V_XNOR_B32_e641259 (i32 (EXTRACT_SUBREG $src0, sub1)),1260 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1)1261>;1262 1263let Constraints = "$vdst = $src2",1264 isConvertibleToThreeAddress = 1,1265 isCommutable = 1 in1266defm V_FMAC_F32 : VOP2Inst_VOPD <"v_fmac_f32", VOP_MAC_F32, 0x0, "v_fmac_f32">;1267} // End SubtargetPredicate = HasDLInsts1268 1269let SubtargetPredicate = HasFmaLegacy32 in {1270 1271let Constraints = "$vdst = $src2",1272 isConvertibleToThreeAddress = 1,1273 isCommutable = 1 in1274defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>;1275 1276} // End SubtargetPredicate = HasFmaLegacy321277 1278let SubtargetPredicate = HasFmacF64Inst,1279 Constraints = "$vdst = $src2",1280 isConvertibleToThreeAddress = 1,1281 isCommutable = 1,1282 SchedRW = [WriteDoubleAdd] in1283defm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>;1284 1285let Constraints = "$vdst = $src2",1286 isConvertibleToThreeAddress = 1,1287 isCommutable = 1,1288 IsDOT = 1 in {1289 let SubtargetPredicate = HasDot5Insts in1290 defm V_DOT2C_F32_F16 : VOP2Inst_VOPD<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16, 0xc, "v_dot2acc_f32_f16">;1291 let SubtargetPredicate = HasDot6Insts in1292 defm V_DOT4C_I32_I8 : VOP2Inst<"v_dot4c_i32_i8", VOP_DOT_ACC_I32_I32>;1293 1294 let SubtargetPredicate = HasDot4Insts in1295 defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>;1296 let SubtargetPredicate = HasDot3Insts in1297 defm V_DOT8C_I32_I4 : VOP2Inst<"v_dot8c_i32_i4", VOP_DOT_ACC_I32_I32>;1298 1299 let SubtargetPredicate = HasDot13Insts in1300 defm V_DOT2C_F32_BF16 : VOP2Inst_VOPD<"v_dot2c_f32_bf16", VOP_DOT_ACC_F32_V2BF16, 0xd, "v_dot2acc_f32_bf16">;1301}1302 1303let AddedComplexity = 30 in {1304 def : GCNPat<1305 (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),1306 (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))1307 > {1308 let SubtargetPredicate = HasDot5Insts;1309 }1310 def : GCNPat<1311 (f32 (int_amdgcn_fdot2_f32_bf16 v2bf16:$src0, v2bf16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),1312 (f32 (V_DOT2C_F32_BF16_e32 $src0, $src1, $src2))1313 > {1314 let SubtargetPredicate = HasDot13Insts;1315 }1316 def : GCNPat<1317 (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),1318 (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2))1319 > {1320 let SubtargetPredicate = HasDot6Insts;1321 }1322 def : GCNPat<1323 (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),1324 (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2))1325 > {1326 let SubtargetPredicate = HasDot4Insts;1327 }1328 def : GCNPat<1329 (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),1330 (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2))1331 > {1332 let SubtargetPredicate = HasDot3Insts;1333 }1334} // End AddedComplexity = 301335 1336let SubtargetPredicate = HasFmaakFmamkF32Insts, isReMaterializable = 1, CanBeVOPD3X = 0, FixedSize = 1 in {1337def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">, VOPD_Component<0x2, "v_fmamk_f32">;1338 1339let isCommutable = 1 in1340def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">, VOPD_Component<0x1, "v_fmaak_f32">;1341} // End SubtargetPredicate = HasFmaakFmamkF32Insts, isReMaterializable = 1, CanBeVOPD3X = 0, FixedSize = 11342 1343let SubtargetPredicate = HasFmaakFmamkF64Insts, isReMaterializable = 1,1344 FixedSize = 1, Size = 12, SchedRW = [Write64Bit] in {1345def V_FMAMK_F64 : VOP2_Pseudo<"v_fmamk_f64", VOP_MADMK_F64, [], "">;1346 1347let isCommutable = 1 in1348def V_FMAAK_F64 : VOP2_Pseudo<"v_fmaak_f64", VOP_MADAK_F64, [], "">;1349} // End SubtargetPredicate = HasFmaakFmamkF64Insts, isReMaterializable = 1, FixedSize = 1, Size = 12, SchedRW = [Write64Bit]1350 1351let SubtargetPredicate = HasPkFmacF16Inst in {1352// FIXME: V_PK_FMAC_F16 is currently not used in instruction selection.1353// If this changes, ensure the DPP variant is not used for GFX11+.1354defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;1355} // End SubtargetPredicate = HasPkFmacF16Inst1356 1357// Note: 16-bit instructions produce a 0 result in the high 16-bits1358// on GFX8 and GFX9 and preserve high 16 bits on GFX10+1359multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> {1360 1361def : GCNPat<1362 (i32 (zext (op i16:$src0, i16:$src1))),1363 (inst VSrc_b16:$src0, VSrc_b16:$src1)1364>;1365 1366def : GCNPat<1367 (i64 (zext (op i16:$src0, i16:$src1))),1368 (REG_SEQUENCE VReg_64,1369 (inst $src0, $src1), sub0,1370 (V_MOV_B32_e32 (i32 0)), sub1)1371>;1372}1373 1374class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <1375 (i16 (ext i1:$src)),1376 (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),1377 (i32 0/*src1mod*/), (i32 1/*src1*/),1378 $src)1379>;1380 1381let True16Predicate = NotUseRealTrue16Insts in {1382def : GCNPat <1383 (and i16:$src0, i16:$src1),1384 (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)1385>;1386 1387def : GCNPat <1388 (or i16:$src0, i16:$src1),1389 (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)1390>;1391 1392def : GCNPat <1393 (xor i16:$src0, i16:$src1),1394 (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)1395>;1396}1397 1398def : GCNPat <1399 (and v2i16:$src0, v2i16:$src1),1400 (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)1401>;1402 1403def : GCNPat <1404 (or v2i16:$src0, v2i16:$src1),1405 (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)1406>;1407 1408def : GCNPat <1409 (xor v2i16:$src0, v2i16:$src1),1410 (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)1411>;1412 1413let Predicates = [Has16BitInsts, isGFX8GFX9] in {1414 1415// Undo sub x, c -> add x, -c canonicalization since c is more likely1416// an inline immediate than -c.1417// TODO: Also do for 64-bit.1418def : GCNPat<1419 (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),1420 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)1421>;1422 1423def : GCNPat<1424 (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),1425 (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)1426>;1427 1428defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;1429defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>;1430defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;1431defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>;1432defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>;1433defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>;1434defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>;1435defm : Arithmetic_i16_0Hi_Pats<clshl_rev_16, V_LSHLREV_B16_e64>;1436defm : Arithmetic_i16_0Hi_Pats<clshr_rev_16, V_LSHRREV_B16_e64>;1437defm : Arithmetic_i16_0Hi_Pats<cashr_rev_16, V_ASHRREV_I16_e64>;1438 1439} // End Predicates = [Has16BitInsts, isGFX8GFX9]1440 1441let Predicates = [Has16BitInsts] in {1442 1443def : ZExt_i16_i1_Pat<zext>;1444def : ZExt_i16_i1_Pat<anyext>;1445 1446def : GCNPat <1447 (i16 (sext i1:$src)),1448 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),1449 /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)1450>;1451 1452} // End Predicates = [Has16BitInsts]1453 1454 1455let SubtargetPredicate = HasIntClamp in {1456// Set clamp bit for saturation.1457def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;1458def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;1459}1460 1461let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in {1462let AddedComplexity = 1 in { // Prefer over form with carry-out.1463def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;1464def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;1465}1466}1467 1468let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in {1469def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;1470def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;1471}1472 1473let SubtargetPredicate = isGFX12Plus, isReMaterializable = 1 in {1474 let SchedRW = [WriteDoubleAdd], isCommutable = 1, FPDPRounding = 1 in {1475 defm V_ADD_F64_pseudo : VOP2Inst_VOPD <"v_add_f64_pseudo", VOP_F64_F64_F64, 0x21, "v_add_f64", any_fadd>;1476 defm V_MUL_F64_pseudo : VOP2Inst_VOPD <"v_mul_f64_pseudo", VOP_F64_F64_F64, 0x22, "v_mul_f64", fmul>;1477 } // End SchedRW = [WriteDoubleAdd], isCommutable = 1, FPDPRounding = 11478 let SchedRW = [Write64Bit] in {1479 defm V_LSHLREV_B64_pseudo : VOP2Inst <"v_lshlrev_b64_pseudo", VOP_I64_I32_I64, clshl_rev_64>;1480 } // End SchedRW = [Write64Bit]1481} // End SubtargetPredicate = isGFX12Plus, isReMaterializable = 11482 1483let SubtargetPredicate = HasIEEEMinimumMaximumInsts, isReMaterializable = 1,1484 SchedRW = [WriteDoubleAdd], isCommutable = 1 in {1485 defm V_MIN_NUM_F64 : VOP2Inst_VOPD <"v_min_num_f64", VOP_F64_F64_F64, 0x24, "v_min_num_f64", fminnum_like>;1486 defm V_MAX_NUM_F64 : VOP2Inst_VOPD <"v_max_num_f64", VOP_F64_F64_F64, 0x23, "v_max_num_f64", fmaxnum_like>;1487}1488 1489//===----------------------------------------------------------------------===//1490// DPP Encodings1491//===----------------------------------------------------------------------===//1492 1493class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,1494 string opName = ps.OpName, VOPProfile p = ps.Pfl,1495 bit IsDPP16 = 0> :1496 VOP_DPP<opName, p, IsDPP16> {1497 let hasSideEffects = ps.hasSideEffects;1498 let Defs = ps.Defs;1499 let SchedRW = ps.SchedRW;1500 let Uses = ps.Uses;1501 1502 bits<8> vdst;1503 bits<8> src1;1504 let Inst{8-0} = 0xfa;1505 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0);1506 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);1507 let Inst{30-25} = op;1508 let Inst{31} = 0x0;1509}1510 1511class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,1512 string opName = ps.OpName, VOPProfile p = ps.Pfl> :1513 VOP2_DPP<op, ps, opName, p, 1> {1514 let AssemblerPredicate = HasDPP16;1515 let SubtargetPredicate = ps.SubtargetPredicate;1516 let OtherPredicates = !listconcat(ps.OtherPredicates,1517 !if(p.HasExt64BitDPP, [HasDPALU_DPP], []),1518 !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts], []));1519}1520 1521class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps, int subtarget,1522 string opName = ps.OpName, VOPProfile p = ps.Pfl> :1523 Base_VOP2_DPP16<op, ps, opName, p>,1524 SIMCInstr <ps.PseudoInstr, subtarget>;1525 1526class VOP2_DPP16_Gen<bits<6> op, VOP2_DPP_Pseudo ps, GFXGen Gen,1527 string opName = ps.OpName, VOPProfile p = ps.Pfl> :1528 VOP2_DPP16<op, ps, Gen.Subtarget, opName, p> {1529 let AssemblerPredicate = Gen.AssemblerPredicate;1530 let True16Predicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, NoTrue16Predicate);1531 let DecoderNamespace = Gen.DecoderNamespace#1532 !if(ps.Pfl.IsRealTrue16, "", "_FAKE16");1533}1534 1535class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,1536 VOPProfile p = ps.Pfl> :1537 VOP_DPP8<ps.OpName, p> {1538 let hasSideEffects = ps.hasSideEffects;1539 let Defs = ps.Defs;1540 let SchedRW = ps.SchedRW;1541 let Uses = ps.Uses;1542 1543 bits<8> vdst;1544 bits<8> src1;1545 1546 let Inst{8-0} = fi;1547 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0);1548 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);1549 let Inst{30-25} = op;1550 let Inst{31} = 0x0;1551 1552 let SubtargetPredicate = ps.SubtargetPredicate;1553 let OtherPredicates = ps.OtherPredicates;1554}1555 1556class VOP2_DPP8_Gen<bits<6> op, VOP2_Pseudo ps, GFXGen Gen,1557 VOPProfile p = ps.Pfl> :1558 VOP2_DPP8<op, ps, p> {1559 let AssemblerPredicate = Gen.AssemblerPredicate;1560 let True16Predicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts, NoTrue16Predicate);1561 let DecoderNamespace = Gen.DecoderNamespace#1562 !if(ps.Pfl.IsRealTrue16, "", "_FAKE16");1563}1564 1565//===----------------------------------------------------------------------===//1566// GFX11, GFX121567//===----------------------------------------------------------------------===//1568 1569//===------------------------------- VOP2 -------------------------------===//1570multiclass VOP2Only_Real_MADK<GFXGen Gen, bits<6> op> {1571 def Gen.Suffix :1572 VOP2_Real_Gen<!cast<VOP2_Pseudo>(NAME), Gen>,1573 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;1574}1575 1576multiclass VOP2Only_Real_MADK64<GFXGen Gen, bits<6> op> {1577 def Gen.Suffix :1578 VOP2_Real_Gen<!cast<VOP2_Pseudo>(NAME), Gen>,1579 VOP2_MADK64e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl> {1580 let DecoderNamespace = Gen.DecoderNamespace;1581 }1582}1583 1584multiclass VOP2Only_Real_MADK_with_name<GFXGen Gen, bits<6> op, string asmName,1585 string opName = NAME> {1586 def Gen.Suffix :1587 VOP2_Real_Gen<!cast<VOP2_Pseudo>(opName), Gen>,1588 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {1589 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);1590 let AsmString = asmName # ps.AsmOperands;1591 }1592}1593 1594multiclass VOP2_Real_e32<GFXGen Gen, bits<6> op> {1595 def _e32#Gen.Suffix :1596 VOP2_Real_Gen<!cast<VOP2_Pseudo>(NAME#"_e32"), Gen>,1597 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;1598}1599 1600multiclass VOP2Only_Real_e32<GFXGen Gen, bits<6> op> {1601 let IsSingle = 1 in1602 defm NAME: VOP2_Real_e32<Gen, op>;1603}1604 1605multiclass VOP2_Real_e64<GFXGen Gen, bits<6> op> {1606 def _e64#Gen.Suffix :1607 VOP3_Real_Gen<!cast<VOP3_Pseudo>(NAME#"_e64"), Gen>,1608 VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;1609}1610 1611multiclass VOP2_Real_dpp<GFXGen Gen, bits<6> op> {1612 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then1613 def _dpp#Gen.Suffix : VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), Gen>;1614}1615 1616multiclass VOP2_Real_dpp8<GFXGen Gen, bits<6> op> {1617 defvar ps = !cast<VOP2_Pseudo>(NAME#"_e32");1618 if !and(ps.Pfl.HasExtDPP, !not(ps.Pfl.HasExt64BitDPP)) then1619 def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen>;1620}1621 1622//===------------------------- VOP2 (with name) -------------------------===//1623multiclass VOP2_Real_e32_with_name<GFXGen Gen, bits<6> op, string opName,1624 string asmName, bit single = 0> {1625 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");1626 def _e32#Gen.Suffix :1627 VOP2_Real_Gen<ps, Gen, asmName>,1628 VOP2e<op{5-0}, ps.Pfl> {1629 let AsmString = asmName # ps.AsmOperands;1630 let IsSingle = single;1631 }1632}1633multiclass VOP2_Real_e64_with_name<GFXGen Gen, bits<6> op, string opName,1634 string asmName> {1635 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64");1636 def _e64#Gen.Suffix :1637 VOP3_Real_Gen<ps, Gen>,1638 VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, ps.Pfl> {1639 let AsmString = asmName # ps.AsmOperands;1640 }1641}1642 1643multiclass VOP2_Real_dpp_with_name<GFXGen Gen, bits<6> op, string opName,1644 string asmName> {1645 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");1646 if ps.Pfl.HasExtDPP then1647 def _dpp#Gen.Suffix : VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), Gen> {1648 let AsmString = asmName # ps.Pfl.AsmDPP16;1649 }1650}1651multiclass VOP2_Real_dpp8_with_name<GFXGen Gen, bits<6> op, string opName,1652 string asmName> {1653 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");1654 if !and(ps.Pfl.HasExtDPP, !not(ps.Pfl.HasExt64BitDPP)) then1655 def _dpp8#Gen.Suffix : VOP2_DPP8_Gen<op, ps, Gen> {1656 let AsmString = asmName # ps.Pfl.AsmDPP8;1657 }1658}1659 1660//===------------------------------ VOP2be ------------------------------===//1661multiclass VOP2be_Real_e32<GFXGen Gen, bits<6> op, string opName, string asmName> {1662 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");1663 def _e32#Gen.Suffix :1664 VOP2_Real_Gen<ps, Gen>,1665 VOP2e<op{5-0}, ps.Pfl> {1666 let AsmString = asmName # !subst(", vcc", "", ps.AsmOperands);1667 }1668}1669multiclass VOP2be_Real_dpp<GFXGen Gen, bits<6> op, string opName, string asmName> {1670 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then1671 def _dpp#Gen.Suffix :1672 VOP2_DPP16_Gen<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), Gen, asmName> {1673 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;1674 let AsmString = asmName # !subst(", vcc", "", AsmDPP);1675 }1676 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then1677 def _dpp_w32#Gen.Suffix :1678 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {1679 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;1680 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);1681 let isAsmParserOnly = 1;1682 let WaveSizePredicate = isWave32;1683 let AssemblerPredicate = Gen.AssemblerPredicate;1684 let DecoderNamespace = Gen.DecoderNamespace;1685 }1686 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP then1687 def _dpp_w64#Gen.Suffix :1688 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {1689 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;1690 let AsmString = asmName # AsmDPP;1691 let isAsmParserOnly = 1;1692 let WaveSizePredicate = isWave64;1693 let AssemblerPredicate = Gen.AssemblerPredicate;1694 let DecoderNamespace = Gen.DecoderNamespace;1695 }1696}1697multiclass VOP2be_Real_dpp8<GFXGen Gen, bits<6> op, string opName, string asmName> {1698 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");1699 if !and(ps.Pfl.HasExtDPP, !not(ps.Pfl.HasExt64BitDPP)) then {1700 def _dpp8#Gen.Suffix :1701 VOP2_DPP8_Gen<op, ps, Gen> {1702 string AsmDPP8 = ps.Pfl.AsmDPP8;1703 let AsmString = asmName # !subst(", vcc", "", AsmDPP8);1704 }1705 def _dpp8_w32#Gen.Suffix :1706 VOP2_DPP8<op, ps> {1707 string AsmDPP8 = ps.Pfl.AsmDPP8;1708 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);1709 let isAsmParserOnly = 1;1710 let WaveSizePredicate = isWave32;1711 let AssemblerPredicate = Gen.AssemblerPredicate;1712 let DecoderNamespace = Gen.DecoderNamespace;1713 }1714 def _dpp8_w64#Gen.Suffix :1715 VOP2_DPP8<op, ps> {1716 string AsmDPP8 = ps.Pfl.AsmDPP8;1717 let AsmString = asmName # AsmDPP8;1718 let isAsmParserOnly = 1;1719 let WaveSizePredicate = isWave64;1720 let AssemblerPredicate = Gen.AssemblerPredicate;1721 let DecoderNamespace = Gen.DecoderNamespace;1722 }1723 }1724}1725 1726// We don't want to override separate decoderNamespaces within these1727multiclass VOP2_Realtriple_e64<GFXGen Gen, bits<6> op> :1728 VOP3_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, NAME>;1729 1730multiclass VOP2_Realtriple_e64_with_name<GFXGen Gen, bits<6> op, string opName,1731 string asmName> {1732 defm NAME : VOP3_Realtriple_with_name<Gen, {0, 1, 0, 0, op{5-0}}, opName, asmName> ;1733}1734 1735multiclass VOP2be_Real<GFXGen Gen, bits<6> op, string opName, string asmName> :1736 VOP2be_Real_e32<Gen, op, opName, asmName>,1737 VOP3be_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, opName, asmName>,1738 VOP2be_Real_dpp<Gen, op, opName, asmName>,1739 VOP2be_Real_dpp8<Gen, op, opName, asmName>;1740 1741// Only for CNDMASK1742multiclass VOP2e_Real<GFXGen Gen, bits<6> op, string opName, string asmName> :1743 VOP2_Real_e32<Gen, op>,1744 VOP2_Realtriple_e64<Gen, op>,1745 VOP2be_Real_dpp<Gen, op, opName, asmName>,1746 VOP2be_Real_dpp8<Gen, op, opName, asmName>;1747 1748multiclass VOP2Only_Real<GFXGen Gen, bits<6> op> :1749 VOP2Only_Real_e32<Gen, op>,1750 VOP2_Real_dpp<Gen, op>,1751 VOP2_Real_dpp8<Gen, op>;1752 1753multiclass VOP2_Real_FULL<GFXGen Gen, bits<6> op> :1754 VOP2_Realtriple_e64<Gen, op>,1755 VOP2_Real_e32<Gen, op>,1756 VOP2_Real_dpp<Gen, op>,1757 VOP2_Real_dpp8<Gen, op>;1758 1759multiclass VOP2_Real_NO_VOP3_with_name<GFXGen Gen, bits<6> op, string opName,1760 string asmName, bit isSingle = 0> {1761 defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName, isSingle>,1762 VOP2_Real_dpp_with_name<Gen, op, opName, asmName>,1763 VOP2_Real_dpp8_with_name<Gen, op, opName, asmName>;1764 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");1765 def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {1766 let AssemblerPredicate = Gen.AssemblerPredicate;1767 }1768}1769 1770multiclass VOP2_Real_FULL_with_name<GFXGen Gen, bits<6> op, string opName,1771 string asmName> :1772 VOP2_Realtriple_e64_with_name<Gen, op, opName, asmName>,1773 VOP2_Real_NO_VOP3_with_name<Gen, op, opName, asmName>;1774 1775multiclass VOP2_Real_NO_DPP<GFXGen Gen, bits<6> op> :1776 VOP2_Real_e32<Gen, op>, VOP2_Real_e64<Gen, op>;1777 1778multiclass VOP2_Real_NO_DPP_with_name<GFXGen Gen, bits<6> op, string opName,1779 string asmName> {1780 defm NAME : VOP2_Real_e32_with_name<Gen, op, opName, asmName>,1781 VOP2_Real_e64_with_name<Gen, op, opName, asmName>;1782 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");1783 def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {1784 let AssemblerPredicate = Gen.AssemblerPredicate;1785 }1786}1787 1788multiclass VOP2_Real_with_DPP16_with_alias<GFXGen Gen, bits<6> op, string alias> {1789 defm NAME : VOP2_Real_e32<Gen, op>,1790 VOP2_Real_dpp<Gen, op>,1791 VOP2_Real_e64<Gen, op>,1792 VOP3_Real_dpp_Base<Gen, {0, 1, 0, 0, op{5-0}}>;1793 def Gen.Suffix#"_alias" : AMDGPUMnemonicAlias<alias, NAME> {1794 let AssemblerPredicate = Gen.AssemblerPredicate;1795 }1796}1797 1798//===----------------------------------------------------------------------===//1799// GFX12.1800//===----------------------------------------------------------------------===//1801 1802multiclass VOP2be_Real_gfx12<bits<6> op, string opName, string asmName> :1803 VOP2be_Real<GFX12Gen, op, opName, asmName>;1804 1805// Only for CNDMASK1806multiclass VOP2e_Real_gfx12<bits<6> op, string opName, string asmName> :1807 VOP2e_Real<GFX12Gen, op, opName, asmName>;1808 1809multiclass VOP2_Real_FULL_with_name_gfx12<bits<6> op, string opName,1810 string asmName> :1811 VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;1812 1813multiclass VOP2_Real_FULL_t16_gfx12<bits<6> op, string opName,1814 string asmName, string alias> {1815 defm NAME : VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;1816 def _gfx12_2nd_alias : AMDGPUMnemonicAlias<alias, asmName> {1817 let AssemblerPredicate = isGFX12Only;1818 }1819}1820 1821multiclass VOP2_Real_with_DPP16_with_alias_gfx12<bits<6> op, string alias> :1822 VOP2_Real_with_DPP16_with_alias<GFX12Gen, op, alias>;1823 1824multiclass VOP2_Real_FULL_t16_and_fake16_gfx12<bits<6> op, string opName,1825 string asmName, string alias> {1826 defm _t16: VOP2_Real_FULL_t16_gfx12<op, opName#"_t16", asmName, alias>;1827 defm _fake16: VOP2_Real_FULL_t16_gfx12<op, opName#"_fake16", asmName, alias>;1828}1829 1830multiclass VOP2_Real_NO_DPP_with_name_gfx12<bits<6> op, string opName,1831 string asmName> :1832 VOP2_Real_NO_DPP_with_name<GFX12Gen, op, opName, asmName>;1833 1834defm V_ADD_F64 : VOP2_Real_FULL_with_name_gfx12<0x002, "V_ADD_F64_pseudo", "v_add_f64">;1835defm V_MUL_F64 : VOP2_Real_FULL_with_name_gfx12<0x006, "V_MUL_F64_pseudo", "v_mul_f64">;1836defm V_LSHLREV_B64 : VOP2_Real_FULL_with_name_gfx12<0x01f, "V_LSHLREV_B64_pseudo", "v_lshlrev_b64">;1837defm V_MIN_NUM_F64 : VOP2_Real_with_DPP16_with_alias_gfx12<0x00d, "v_min_f64">;1838defm V_MAX_NUM_F64 : VOP2_Real_with_DPP16_with_alias_gfx12<0x00e, "v_max_f64">;1839 1840defm V_CNDMASK_B32 : VOP2e_Real_gfx12<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;1841defm V_ADD_CO_CI_U32 :1842 VOP2be_Real_gfx12<0x020, "V_ADDC_U32", "v_add_co_ci_u32">;1843defm V_SUB_CO_CI_U32 :1844 VOP2be_Real_gfx12<0x021, "V_SUBB_U32", "v_sub_co_ci_u32">;1845defm V_SUBREV_CO_CI_U32 :1846 VOP2be_Real_gfx12<0x022, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;1847 1848defm V_MIN_NUM_F32 : VOP2_Real_FULL_with_name_gfx12<0x015, "V_MIN_F32", "v_min_num_f32">;1849defm V_MAX_NUM_F32 : VOP2_Real_FULL_with_name_gfx12<0x016, "V_MAX_F32", "v_max_num_f32">;1850defm V_MIN_NUM_F16 : VOP2_Real_FULL_t16_and_fake16_gfx12<0x030, "V_MIN_F16", "v_min_num_f16", "v_min_f16">;1851defm V_MAX_NUM_F16 : VOP2_Real_FULL_t16_and_fake16_gfx12<0x031, "V_MAX_F16", "v_max_num_f16", "v_max_f16">;1852 1853let SubtargetPredicate = isGFX12Plus in {1854 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx12>;1855 1856 defm : VOP2bInstAliases<1857 V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx12, "v_add_co_ci_u32">;1858 defm : VOP2bInstAliases<1859 V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx12, "v_sub_co_ci_u32">;1860 defm : VOP2bInstAliases<1861 V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx12, "v_subrev_co_ci_u32">;1862} // End SubtargetPredicate = isGFX12Plus1863 1864let SubtargetPredicate = HasFmacF64Inst in1865defm V_FMAC_F64 : VOP2_Real_FULL<GFX12Gen, 0x17>;1866 1867defm V_FMAMK_F64 : VOP2Only_Real_MADK64<GFX1250Gen, 0x23>;1868defm V_FMAAK_F64 : VOP2Only_Real_MADK64<GFX1250Gen, 0x24>;1869defm V_ADD_U64 : VOP2_Real_FULL<GFX1250Gen, 0x28>;1870defm V_SUB_U64 : VOP2_Real_FULL<GFX1250Gen, 0x29>;1871defm V_MUL_U64 : VOP2_Real_NO_DPP<GFX1250Gen, 0x2a>;1872 1873//===----------------------------------------------------------------------===//1874// GFX11.1875//===----------------------------------------------------------------------===//1876 1877multiclass VOP2be_Real_gfx11<bits<6> op, string opName, string asmName> :1878 VOP2be_Real<GFX11Gen, op, opName, asmName>;1879 1880// Only for CNDMASK1881multiclass VOP2e_Real_gfx11<bits<6> op, string opName, string asmName> :1882 VOP2e_Real<GFX11Gen, op, opName, asmName>;1883 1884multiclass VOP2_Real_NO_VOP3_with_name_gfx11<bits<6> op, string opName,1885 string asmName, bit isSingle = 0> {1886 defm NAME : VOP2_Real_e32_with_name<GFX11Gen, op, opName, asmName, isSingle>,1887 VOP2_Real_dpp_with_name<GFX11Gen, op, opName, asmName>,1888 VOP2_Real_dpp8_with_name<GFX11Gen, op, opName, asmName>;1889 defvar ps = !cast<VOP2_Pseudo>(opName#"_e32");1890 def _gfx11_alias : AMDGPUMnemonicAlias<ps.Mnemonic, asmName> {1891 let AssemblerPredicate = isGFX11Only;1892 }1893}1894 1895multiclass VOP2_Real_FULL_t16_gfx11<bits<6> op, string asmName, string opName = NAME> :1896 VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>;1897 1898multiclass VOP2_Real_FULL_t16_and_fake16_gfx11<bits<6> op, string asmName, string opName = NAME> {1899 defm opName#"_t16": VOP2_Real_FULL_t16_gfx11<op, asmName, opName#"_t16">;1900 defm opName#"_fake16": VOP2_Real_FULL_t16_gfx11<op, asmName, opName#"_fake16">;1901}1902 1903multiclass VOP2_Real_NO_DPP_with_name_gfx11<bits<6> op, string opName,1904 string asmName> :1905 VOP2_Real_NO_DPP_with_name<GFX11Gen, op, opName, asmName>;1906 1907multiclass VOP2_Real_FULL_gfx11_gfx12<bits<6> op> :1908 VOP2_Real_FULL<GFX11Gen, op>, VOP2_Real_FULL<GFX12Gen, op>;1909 1910multiclass VOP2_Real_FULL_with_name_gfx11_gfx12<bits<6> op, string opName,1911 string asmName> :1912 VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,1913 VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;1914 1915multiclass VOP2_Real_e32_gfx11_gfx12<bits<6> op> :1916 VOP2Only_Real_e32<GFX11Gen, op>, VOP2Only_Real_e32<GFX12Gen, op>;1917 1918multiclass VOP3Only_Realtriple_gfx11_gfx12<bits<10> op> :1919 VOP3Only_Realtriple<GFX11Gen, op>, VOP3Only_Realtriple<GFX12Gen, op>;1920 1921multiclass VOP3Only_Realtriple_t16_gfx11_gfx12<bits<10> op, string asmName, string OpName = NAME> :1922 VOP3_Realtriple_t16_gfx11<op, asmName, OpName, "", /*IsSingle*/1>,1923 VOP3_Realtriple_t16_gfx12<op, asmName, OpName, "", /*IsSingle*/1>;1924 1925multiclass VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<bits<10> op, string asmName, string OpName = NAME> {1926 defm _t16: VOP3Only_Realtriple_t16_gfx11_gfx12<op, asmName, OpName#"_t16">;1927 defm _fake16: VOP3Only_Realtriple_t16_gfx11_gfx12<op, asmName, OpName#"_fake16">;1928}1929 1930multiclass VOP3beOnly_Realtriple_gfx11_gfx12<bits<10> op> :1931 VOP3beOnly_Realtriple<GFX11Gen, op>, VOP3beOnly_Realtriple<GFX12Gen, op>;1932 1933multiclass VOP2Only_Real_MADK_t16_gfx11_gfx12<bits<6> op, string asmName,1934 string opName = NAME> :1935 VOP2Only_Real_MADK_with_name<GFX11Gen, op, asmName, opName>,1936 VOP2Only_Real_MADK_with_name<GFX12Gen, op, asmName, opName>;1937 1938multiclass VOP2Only_Real_MADK_t16_and_fake16_gfx11_gfx12<bits<6> op, string asmName,1939 string opName = NAME> {1940 defm _t16: VOP2Only_Real_MADK_t16_gfx11_gfx12<op, asmName, opName#"_t16">;1941 defm _fake16: VOP2Only_Real_MADK_t16_gfx11_gfx12<op, asmName, opName#"_fake16">;1942}1943 1944multiclass VOP2_Real_FULL_t16_gfx11_gfx12<bits<6> op, string asmName,1945 string opName = NAME> :1946 VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,1947 VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;1948 1949multiclass VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<bits<6> op, string asmName,1950 string opName = NAME> {1951 defm _t16: VOP2_Real_FULL_t16_gfx11_gfx12<op, asmName, opName#"_t16">;1952 defm _fake16: VOP2_Real_FULL_t16_gfx11_gfx12<op, asmName, opName#"_fake16">;1953}1954 1955multiclass VOP2_Real_FULL_gfx11<bits<6> op> :1956 VOP2_Real_FULL<GFX11Gen, op>;1957 1958defm V_CNDMASK_B32 : VOP2e_Real_gfx11<0x001, "V_CNDMASK_B32",1959 "v_cndmask_b32">;1960defm V_DOT2ACC_F32_F16 : VOP2_Real_NO_VOP3_with_name_gfx11<0x002,1961 "V_DOT2C_F32_F16", "v_dot2acc_f32_f16", 1>;1962defm V_FMAC_DX9_ZERO_F32 : VOP2_Real_NO_DPP_with_name_gfx11<0x006,1963 "V_FMAC_LEGACY_F32", "v_fmac_dx9_zero_f32">;1964defm V_MUL_DX9_ZERO_F32 : VOP2_Real_FULL_with_name_gfx11_gfx12<0x007,1965 "V_MUL_LEGACY_F32", "v_mul_dx9_zero_f32">;1966defm V_LSHLREV_B32 : VOP2_Real_FULL_gfx11_gfx12<0x018>;1967defm V_LSHRREV_B32 : VOP2_Real_FULL_gfx11_gfx12<0x019>;1968defm V_ASHRREV_I32 : VOP2_Real_FULL_gfx11_gfx12<0x01a>;1969defm V_ADD_CO_CI_U32 :1970 VOP2be_Real_gfx11<0x020, "V_ADDC_U32", "v_add_co_ci_u32">;1971defm V_SUB_CO_CI_U32 :1972 VOP2be_Real_gfx11<0x021, "V_SUBB_U32", "v_sub_co_ci_u32">;1973defm V_SUBREV_CO_CI_U32 :1974 VOP2be_Real_gfx11<0x022, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;1975 1976defm V_CVT_PK_RTZ_F16_F32 : VOP2_Real_FULL_with_name_gfx11_gfx12<0x02f,1977 "V_CVT_PKRTZ_F16_F32", "v_cvt_pk_rtz_f16_f32">;1978defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx11_gfx12<0x03c>;1979 1980defm V_ADD_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v_add_f16">;1981defm V_SUB_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">;1982defm V_SUBREV_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x034, "v_subrev_f16">;1983defm V_MUL_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x035, "v_mul_f16">;1984defm V_FMAC_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x036, "v_fmac_f16">;1985defm V_LDEXP_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x03b, "v_ldexp_f16">;1986defm V_MAX_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11<0x039, "v_max_f16">;1987defm V_MIN_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11<0x03a, "v_min_f16">;1988defm V_FMAMK_F16 : VOP2Only_Real_MADK_t16_and_fake16_gfx11_gfx12<0x037, "v_fmamk_f16">;1989defm V_FMAAK_F16 : VOP2Only_Real_MADK_t16_and_fake16_gfx11_gfx12<0x038, "v_fmaak_f16">;1990 1991// VOP3 only.1992defm V_CNDMASK_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x25d, "v_cndmask_b16">;1993defm V_LDEXP_F32 : VOP3Only_Realtriple_gfx11_gfx12<0x31c>;1994defm V_BFM_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31d>;1995defm V_BCNT_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31e>;1996defm V_MBCNT_LO_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31f>;1997defm V_MBCNT_HI_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x320>;1998defm V_CVT_PK_NORM_I16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x321, "V_CVT_PKNORM_I16_F32", "v_cvt_pk_norm_i16_f32">;1999defm V_CVT_PK_NORM_U16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x322, "V_CVT_PKNORM_U16_F32", "v_cvt_pk_norm_u16_f32">;2000defm V_CVT_PK_U16_U32 : VOP3Only_Realtriple_gfx11_gfx12<0x323>;2001defm V_CVT_PK_I16_I32 : VOP3Only_Realtriple_gfx11_gfx12<0x324>;2002defm V_ADD_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x300>;2003defm V_SUB_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x301>;2004defm V_SUBREV_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x302>;2005 2006let SubtargetPredicate = isGFX11Only in {2007 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx11>;2008 2009 defm : VOP2bInstAliases<2010 V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx11, "v_add_co_ci_u32">;2011 defm : VOP2bInstAliases<2012 V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx11, "v_sub_co_ci_u32">;2013 defm : VOP2bInstAliases<2014 V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx11, "v_subrev_co_ci_u32">;2015} // End SubtargetPredicate = isGFX11Only2016 2017//===----------------------------------------------------------------------===//2018// GFX10.2019//===----------------------------------------------------------------------===//2020 2021let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {2022 //===------------------------------- VOP2 -------------------------------===//2023 multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> {2024 def _gfx10 :2025 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,2026 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;2027 }2028 multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName,2029 string asmName> {2030 def _gfx10 :2031 VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,2032 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {2033 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);2034 let AsmString = asmName # ps.AsmOperands;2035 }2036 }2037 multiclass VOP2_Real_e32_gfx10<bits<6> op> {2038 def _e32_gfx10 :2039 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,2040 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;2041 }2042 multiclass VOP2_Real_e64_gfx10<bits<6> op> {2043 def _e64_gfx10 :2044 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,2045 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;2046 }2047 multiclass VOP2_Real_sdwa_gfx10<bits<6> op> {2048 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then2049 def _sdwa_gfx10 :2050 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,2051 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;2052 }2053 multiclass VOP2_Real_dpp_gfx10<bits<6> op> {2054 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then2055 def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10>;2056 }2057 multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {2058 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then2059 def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;2060 }2061 multiclass VOP2Only_Real_e32_gfx10<bits<6> op> {2062 let IsSingle = 1 in2063 defm NAME: VOP2_Real_e32_gfx10<op>;2064 }2065 multiclass VOP2_Real_e32_dpp_dpp8_gfx10<bits<6> op> :2066 VOP2Only_Real_e32_gfx10<op>,2067 VOP2_Real_dpp_gfx10<op>,2068 VOP2_Real_dpp8_gfx10<op>;2069 2070 //===------------------------- VOP2 (with name) -------------------------===//2071 multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName,2072 string asmName> {2073 def _e32_gfx10 :2074 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,2075 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {2076 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");2077 let AsmString = asmName # ps.AsmOperands;2078 }2079 }2080 multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName,2081 string asmName> {2082 def _e64_gfx10 :2083 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,2084 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},2085 !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {2086 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64");2087 let AsmString = asmName # ps.AsmOperands;2088 }2089 }2090 multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,2091 string asmName> {2092 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then2093 def _sdwa_gfx10 :2094 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,2095 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {2096 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");2097 let AsmString = asmName # ps.AsmOperands;2098 }2099 }2100 multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,2101 string asmName> {2102 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then2103 def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10> {2104 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");2105 let AsmString = asmName # ps.Pfl.AsmDPP16;2106 }2107 }2108 multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,2109 string asmName> {2110 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then2111 def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {2112 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");2113 let AsmString = asmName # ps.Pfl.AsmDPP8;2114 }2115 }2116 2117 //===------------------------------ VOP2be ------------------------------===//2118 multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {2119 def _e32_gfx10 :2120 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,2121 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {2122 VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");2123 let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);2124 }2125 }2126 multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> {2127 def _e64_gfx10 :2128 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,2129 VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},2130 !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {2131 VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");2132 let AsmString = asmName # Ps.AsmOperands;2133 }2134 }2135 multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> {2136 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then2137 def _sdwa_gfx10 :2138 VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,2139 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {2140 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");2141 let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);2142 }2143 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then2144 def _sdwa_w32_gfx10 :2145 Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,2146 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {2147 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");2148 let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);2149 let isAsmParserOnly = 1;2150 let WaveSizePredicate = isWave32;2151 }2152 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then2153 def _sdwa_w64_gfx10 :2154 Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,2155 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {2156 VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");2157 let AsmString = asmName # Ps.AsmOperands;2158 let isAsmParserOnly = 1;2159 let WaveSizePredicate = isWave64;2160 }2161 }2162 multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> {2163 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then2164 def _dpp_gfx10 :2165 VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10, asmName> {2166 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;2167 let AsmString = asmName # !subst(", vcc", "", AsmDPP);2168 }2169 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then2170 def _dpp_w32_gfx10 :2171 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {2172 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;2173 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);2174 let isAsmParserOnly = 1;2175 let WaveSizePredicate = isWave32;2176 }2177 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then2178 def _dpp_w64_gfx10 :2179 Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {2180 string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;2181 let AsmString = asmName # AsmDPP;2182 let isAsmParserOnly = 1;2183 let WaveSizePredicate = isWave64;2184 }2185 }2186 multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> {2187 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then2188 def _dpp8_gfx10 :2189 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {2190 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;2191 let AsmString = asmName # !subst(", vcc", "", AsmDPP8);2192 }2193 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then2194 def _dpp8_w32_gfx10 :2195 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {2196 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;2197 let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);2198 let isAsmParserOnly = 1;2199 let WaveSizePredicate = isWave32;2200 }2201 if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then2202 def _dpp8_w64_gfx10 :2203 VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {2204 string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;2205 let AsmString = asmName # AsmDPP8;2206 let isAsmParserOnly = 1;2207 let WaveSizePredicate = isWave64;2208 }2209 }2210 2211 //===----------------------------- VOP3Only -----------------------------===//2212 multiclass VOP3Only_Real_gfx10<bits<10> op> {2213 def _e64_gfx10 :2214 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,2215 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {2216 let IsSingle = 1;2217 }2218 }2219 2220 //===---------------------------- VOP3beOnly ----------------------------===//2221 multiclass VOP3beOnly_Real_gfx10<bits<10> op> {2222 def _e64_gfx10 :2223 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,2224 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {2225 let IsSingle = 1;2226 }2227 }2228} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"2229 2230multiclass VOP2Only_Real_MADK_gfx10_gfx11<bits<6> op> :2231 VOP2Only_Real_MADK_gfx10<op>, VOP2Only_Real_MADK<GFX11Gen, op>;2232 2233multiclass VOP2Only_Real_MADK_gfx10_gfx11_gfx12<bits<6> op> :2234 VOP2Only_Real_MADK_gfx10_gfx11<op>, VOP2Only_Real_MADK<GFX12Gen, op>;2235 2236multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :2237 VOP2be_Real_e32_gfx10<op, opName, asmName>,2238 VOP2be_Real_e64_gfx10<op, opName, asmName>,2239 VOP2be_Real_sdwa_gfx10<op, opName, asmName>,2240 VOP2be_Real_dpp_gfx10<op, opName, asmName>,2241 VOP2be_Real_dpp8_gfx10<op, opName, asmName>;2242 2243multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> :2244 VOP2_Real_e32_gfx10<op>,2245 VOP2_Real_e64_gfx10<op>,2246 VOP2be_Real_sdwa_gfx10<op, opName, asmName>,2247 VOP2be_Real_dpp_gfx10<op, opName, asmName>,2248 VOP2be_Real_dpp8_gfx10<op, opName, asmName>;2249 2250multiclass VOP2_Real_gfx10<bits<6> op> :2251 VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>,2252 VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>;2253 2254multiclass VOP2_Real_gfx10_gfx11<bits<6> op> :2255 VOP2_Real_gfx10<op>, VOP2_Real_FULL<GFX11Gen, op>;2256 2257multiclass VOP2_Real_gfx10_gfx11_gfx12<bits<6> op> :2258 VOP2_Real_gfx10_gfx11<op>, VOP2_Real_FULL<GFX12Gen, op>;2259 2260multiclass VOP2_Real_with_name_gfx10<bits<6> op, string opName,2261 string asmName> :2262 VOP2_Real_e32_gfx10_with_name<op, opName, asmName>,2263 VOP2_Real_e64_gfx10_with_name<op, opName, asmName>,2264 VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>,2265 VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,2266 VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;2267 2268multiclass VOP2_Real_with_name_gfx10_gfx11_gfx12<bits<6> op, string opName,2269 string asmName> :2270 VOP2_Real_with_name_gfx10<op, opName, asmName>,2271 VOP2_Real_FULL_with_name<GFX11Gen, op, opName, asmName>,2272 VOP2_Real_FULL_with_name<GFX12Gen, op, opName, asmName>;2273 2274// NB: Same opcode as v_mac_legacy_f322275let DecoderNamespace = "GFX10_B" in2276defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>;2277 2278defm V_XNOR_B32 : VOP2_Real_gfx10_gfx11_gfx12<0x01e>;2279defm V_FMAC_F32 : VOP2_Real_gfx10_gfx11_gfx12<0x02b>;2280defm V_FMAMK_F32 : VOP2Only_Real_MADK_gfx10_gfx11_gfx12<0x02c>;2281defm V_FMAAK_F32 : VOP2Only_Real_MADK_gfx10_gfx11_gfx12<0x02d>;2282defm V_ADD_F16 : VOP2_Real_gfx10<0x032>;2283defm V_SUB_F16 : VOP2_Real_gfx10<0x033>;2284defm V_SUBREV_F16 : VOP2_Real_gfx10<0x034>;2285defm V_MUL_F16 : VOP2_Real_gfx10<0x035>;2286defm V_FMAC_F16 : VOP2_Real_gfx10<0x036>;2287defm V_FMAMK_F16 : VOP2Only_Real_MADK_gfx10<0x037>;2288defm V_FMAAK_F16 : VOP2Only_Real_MADK_gfx10<0x038>;2289defm V_MAX_F16 : VOP2_Real_gfx10<0x039>;2290defm V_MIN_F16 : VOP2_Real_gfx10<0x03a>;2291defm V_LDEXP_F16 : VOP2_Real_gfx10<0x03b>;2292defm V_PK_FMAC_F16 : VOP2_Real_e32_dpp_dpp8_gfx10<0x03c>;2293 2294// VOP2 no carry-in, carry-out.2295defm V_ADD_NC_U32 :2296 VOP2_Real_with_name_gfx10_gfx11_gfx12<0x025, "V_ADD_U32", "v_add_nc_u32">;2297defm V_SUB_NC_U32 :2298 VOP2_Real_with_name_gfx10_gfx11_gfx12<0x026, "V_SUB_U32", "v_sub_nc_u32">;2299defm V_SUBREV_NC_U32 :2300 VOP2_Real_with_name_gfx10_gfx11_gfx12<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;2301 2302// VOP2 carry-in, carry-out.2303defm V_ADD_CO_CI_U32 :2304 VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">;2305defm V_SUB_CO_CI_U32 :2306 VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">;2307defm V_SUBREV_CO_CI_U32 :2308 VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;2309 2310defm V_CNDMASK_B32 :2311 VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;2312 2313// VOP3 only.2314defm V_BFM_B32 : VOP3Only_Real_gfx10<0x363>;2315defm V_BCNT_U32_B32 : VOP3Only_Real_gfx10<0x364>;2316defm V_MBCNT_LO_U32_B32 : VOP3Only_Real_gfx10<0x365>;2317defm V_MBCNT_HI_U32_B32 : VOP3Only_Real_gfx10<0x366>;2318defm V_LDEXP_F32 : VOP3Only_Real_gfx10<0x362>;2319defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>;2320defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>;2321defm V_CVT_PK_U16_U32 : VOP3Only_Real_gfx10<0x36a>;2322defm V_CVT_PK_I16_I32 : VOP3Only_Real_gfx10<0x36b>;2323 2324// VOP3 carry-out.2325defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>;2326defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>;2327defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>;2328 2329let SubtargetPredicate = isGFX10Only in {2330 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>;2331 2332 defm : VOP2bInstAliases<2333 V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">;2334 defm : VOP2bInstAliases<2335 V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">;2336 defm : VOP2bInstAliases<2337 V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">;2338} // End SubtargetPredicate = isGFX10Only2339 2340//===----------------------------------------------------------------------===//2341// GFX6, GFX7, GFX10, GFX112342//===----------------------------------------------------------------------===//2343 2344class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :2345 VOP_DPPe <P> {2346 bits<8> vdst;2347 bits<8> src1;2348 let Inst{8-0} = 0xfa; //dpp2349 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);2350 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);2351 let Inst{30-25} = op;2352 let Inst{31} = 0x0; //encoding2353}2354 2355let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {2356 multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> {2357 def _gfx6_gfx7 :2358 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,2359 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;2360 }2361 multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> {2362 def _gfx6_gfx7 :2363 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,2364 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;2365 }2366 multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string opName = NAME> {2367 def _e32_gfx6_gfx7 :2368 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.SI>,2369 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl>;2370 }2371 multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> {2372 def _e64_gfx6_gfx7 :2373 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>,2374 VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>;2375 }2376 multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string opName = NAME> {2377 def _e64_gfx6_gfx7 :2378 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.SI>,2379 VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>;2380 }2381} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"2382 2383multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> :2384 VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>;2385 2386multiclass VOP2_Real_gfx6_gfx7<bits<6> op> :2387 VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>;2388 2389multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> :2390 VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>;2391 2392multiclass VOP2_Real_gfx6_gfx7_gfx10_gfx11<bits<6> op> :2393 VOP2_Real_gfx6_gfx7_gfx10<op>, VOP2_Real_FULL<GFX11Gen, op>;2394 2395multiclass VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<6> op> :2396 VOP2_Real_gfx6_gfx7_gfx10_gfx11<op>, VOP2_Real_FULL<GFX12Gen, op>;2397 2398multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :2399 VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;2400 2401multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op,2402 string opName, string asmName> {2403 defvar ps32 = !cast<VOP2_Pseudo>(opName#"_e32");2404 defvar ps64 = !cast<VOP3_Pseudo>(opName#"_e64");2405 2406 let AsmString = asmName # ps32.AsmOperands in {2407 defm "" : VOP2_Real_e32_gfx6_gfx7<op, opName>;2408 }2409 2410 let AsmString = asmName # ps64.AsmOperands in {2411 defm "" : VOP2be_Real_e64_gfx6_gfx7<op, opName>;2412 }2413}2414 2415defm V_CNDMASK_B32 : VOP2_Real_gfx6_gfx7<0x000>;2416defm V_MIN_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00d>;2417defm V_MAX_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00e>;2418defm V_LSHR_B32 : VOP2_Real_gfx6_gfx7<0x015>;2419defm V_ASHR_I32 : VOP2_Real_gfx6_gfx7<0x017>;2420defm V_LSHL_B32 : VOP2_Real_gfx6_gfx7<0x019>;2421defm V_BFM_B32 : VOP2_Real_gfx6_gfx7<0x01e>;2422defm V_BCNT_U32_B32 : VOP2_Real_gfx6_gfx7<0x022>;2423defm V_MBCNT_LO_U32_B32 : VOP2_Real_gfx6_gfx7<0x023>;2424defm V_MBCNT_HI_U32_B32 : VOP2_Real_gfx6_gfx7<0x024>;2425defm V_LDEXP_F32 : VOP2_Real_gfx6_gfx7<0x02b>;2426defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>;2427defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>;2428defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>;2429defm V_CVT_PK_U16_U32 : VOP2_Real_gfx6_gfx7<0x030>;2430defm V_CVT_PK_I16_I32 : VOP2_Real_gfx6_gfx7<0x031>;2431 2432// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in2433// VI, but the VI instructions behave the same as the SI versions.2434defm V_ADD_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;2435defm V_SUB_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">;2436defm V_SUBREV_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">;2437defm V_ADDC_U32 : VOP2be_Real_gfx6_gfx7<0x028>;2438defm V_SUBB_U32 : VOP2be_Real_gfx6_gfx7<0x029>;2439defm V_SUBBREV_U32 : VOP2be_Real_gfx6_gfx7<0x02a>;2440 2441defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>;2442 2443let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {2444 defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>;2445} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)2446 2447let SubtargetPredicate = isGFX6GFX7 in {2448 defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;2449 defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>;2450 defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>;2451 defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>;2452 2453 def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;2454 def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;2455 def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;2456} // End SubtargetPredicate = isGFX6GFX72457 2458defm V_ADD_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x003>;2459defm V_SUB_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x004>;2460defm V_SUBREV_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x005>;2461defm V_MAC_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x006>;2462defm V_MUL_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x007>;2463defm V_MUL_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x008>;2464defm V_MUL_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x009>;2465defm V_MUL_HI_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00a>;2466defm V_MUL_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00b>;2467defm V_MUL_HI_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00c>;2468defm V_MIN_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00f>;2469defm V_MAX_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x010>;2470defm V_MIN_I32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x011>;2471defm V_MAX_I32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x012>;2472defm V_MIN_U32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x013>;2473defm V_MAX_U32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x014>;2474defm V_LSHRREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x016>;2475defm V_ASHRREV_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x018>;2476defm V_LSHLREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;2477defm V_AND_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01b>;2478defm V_OR_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01c>;2479defm V_XOR_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01d>;2480defm V_MAC_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;2481defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;2482defm V_MADMK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;2483defm V_MADAK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;2484 2485//===----------------------------------------------------------------------===//2486// GFX8, GFX9 (VI).2487//===----------------------------------------------------------------------===//2488 2489let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {2490 2491multiclass VOP2_Real_MADK_vi <bits<6> op> {2492 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,2493 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;2494}2495 2496multiclass VOP2_Real_MADK_gfx940 <bits<6> op> {2497 def _gfx940 : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX940>,2498 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl> {2499 let DecoderNamespace = "GFX9";2500 }2501}2502 2503multiclass VOP2_Real_e32_vi <bits<6> op> {2504 def _e32_vi :2505 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,2506 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;2507}2508 2509multiclass VOP2_Real_e64_vi <bits<10> op> {2510 def _e64_vi :2511 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,2512 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;2513}2514 2515multiclass VOP2_Real_e64only_vi <bits<10> op> {2516 def _e64_vi :2517 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,2518 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {2519 let IsSingle = 1;2520 }2521}2522 2523multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :2524 VOP2_Real_e32_vi<op>,2525 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;2526 2527} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"2528 2529multiclass VOP2_SDWA8_Real <bits<6> op> {2530 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA then2531 def _sdwa_vi :2532 VOP_SDWA8_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,2533 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;2534}2535 2536multiclass VOP2_SDWA9_Real <bits<6> op> {2537 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then2538 def _sdwa_gfx9 :2539 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,2540 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;2541}2542 2543let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in {2544 2545multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {2546 def _e32_vi :2547 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,2548 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {2549 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");2550 let AsmString = AsmName # ps.AsmOperands;2551 }2552 def _e64_vi :2553 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,2554 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {2555 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");2556 let AsmString = AsmName # ps.AsmOperands;2557 }2558 if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA then2559 def _sdwa_vi :2560 VOP_SDWA8_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,2561 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {2562 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");2563 let AsmString = AsmName # ps.AsmOperands;2564 }2565 if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP then2566 def _dpp_vi :2567 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>,2568 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {2569 VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");2570 let AsmString = AsmName # ps.AsmOperands;2571 }2572}2573 2574} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8"2575 2576let DecoderNamespace = "GFX9" in {2577 2578multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {2579 def _e32_gfx9 :2580 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,2581 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {2582 VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");2583 let AsmString = AsmName # ps.AsmOperands;2584 }2585 def _e64_gfx9 :2586 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,2587 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {2588 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");2589 let AsmString = AsmName # ps.AsmOperands;2590 }2591 if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9 then2592 def _sdwa_gfx9 :2593 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,2594 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {2595 VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");2596 let AsmString = AsmName # ps.AsmOperands;2597 }2598 if !cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP then2599 def _dpp_gfx9 :2600 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>,2601 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {2602 VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");2603 let AsmString = AsmName # ps.AsmOperands;2604 }2605}2606 2607multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {2608 def _e32_gfx9 :2609 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,2610 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;2611 def _e64_gfx9 :2612 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,2613 VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;2614 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then2615 def _sdwa_gfx9 :2616 VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,2617 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {2618 }2619 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then2620 def _dpp_gfx9 :2621 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,2622 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;2623}2624 2625} // End DecoderNamespace = "GFX9"2626 2627multiclass VOP2_Real_e32e64_vi <bits<6> op> :2628 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA8_Real<op>, VOP2_SDWA9_Real<op> {2629 2630 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then2631 def _dpp_vi :2632 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,2633 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;2634}2635 2636defm V_CNDMASK_B32 : VOP2_Real_e32e64_vi <0x0>;2637defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>;2638defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>;2639defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>;2640let OtherPredicates = [isGCN3ExcludingGFX90A] in2641defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>;2642defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>;2643defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>;2644defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>;2645defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>;2646defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>;2647defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>;2648defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>;2649defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>;2650defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>;2651defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>;2652defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>;2653defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>;2654defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>;2655defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>;2656defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>;2657defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>;2658defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>;2659defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>;2660defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>;2661defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>;2662 2663defm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32", "v_add_u32">;2664defm V_SUB_U32 : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32", "v_sub_u32">;2665defm V_SUBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32", "v_subrev_u32">;2666defm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "v_addc_u32">;2667defm V_SUBB_U32 : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32", "v_subb_u32">;2668defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;2669 2670let AssemblerPredicate = isGFX9Only in {2671defm V_ADD_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32", "v_add_co_u32">;2672defm V_SUB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32", "v_sub_co_u32">;2673defm V_SUBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32", "v_subrev_co_u32">;2674defm V_ADDC_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32", "v_addc_co_u32">;2675defm V_SUBB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32", "v_subb_co_u32">;2676defm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">;2677 2678defm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>;2679defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>;2680defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>;2681defm V_PK_FMAC_F16 : VOP2_Real_e32e64_gfx9<0x03c>;2682} // End AssemblerPredicate = isGFX9Only2683 2684defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>;2685defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>;2686defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>;2687defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>;2688defm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>;2689defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;2690defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;2691defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;2692defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>;2693defm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>;2694defm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>;2695 2696defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>;2697defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>;2698defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>;2699defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>;2700defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>;2701defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>;2702defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>;2703defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>;2704defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>;2705defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>;2706defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>;2707defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>;2708defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>;2709defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>;2710defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>;2711defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>;2712defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>;2713defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>;2714defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>;2715defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>;2716defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>;2717 2718let SubtargetPredicate = isGFX8GFX9 in {2719 2720// Aliases to simplify matching of floating-point instructions that2721// are VOP2 on SI and VOP3 on VI.2722class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias <2723 name#" $dst, $src0, $src1",2724 !if(inst.Pfl.HasOMod,2725 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),2726 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))2727>, PredicateControl {2728 let UseInstAsmMatchConverter = 0;2729 let AsmVariantName = AMDGPUAsmVariants.VOP3;2730}2731 2732def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;2733def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;2734def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;2735def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;2736def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;2737 2738defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;2739 2740} // End SubtargetPredicate = isGFX8GFX92741 2742let SubtargetPredicate = isGFX9Only in {2743 2744defm : VOP2bInstAliases<V_ADD_U32_e32, V_ADD_CO_U32_e32_gfx9, "v_add_co_u32">;2745defm : VOP2bInstAliases<V_ADDC_U32_e32, V_ADDC_CO_U32_e32_gfx9, "v_addc_co_u32">;2746defm : VOP2bInstAliases<V_SUB_U32_e32, V_SUB_CO_U32_e32_gfx9, "v_sub_co_u32">;2747defm : VOP2bInstAliases<V_SUBB_U32_e32, V_SUBB_CO_U32_e32_gfx9, "v_subb_co_u32">;2748defm : VOP2bInstAliases<V_SUBREV_U32_e32, V_SUBREV_CO_U32_e32_gfx9, "v_subrev_co_u32">;2749defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;2750 2751} // End SubtargetPredicate = isGFX9Only2752 2753let SubtargetPredicate = HasDLInsts in {2754 2755defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;2756defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;2757 2758} // End SubtargetPredicate = HasDLInsts2759 2760let DecoderNamespace = "GFX90A" in {2761 multiclass VOP2_Real_e32_gfx90a <bits<6> op> {2762 def _e32_gfx90a :2763 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX90A>,2764 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;2765 }2766 2767 multiclass VOP2_Real_e64_gfx90a <bits<10> op> {2768 def _e64_gfx90a :2769 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>,2770 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;2771 }2772 2773 multiclass Base_VOP2_Real_e32e64_gfx90a <bits<6> op> :2774 VOP2_Real_e32_gfx90a<op>,2775 VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>;2776 2777 multiclass VOP2_Real_e32e64_gfx90a <bits<6> op> :2778 Base_VOP2_Real_e32e64_gfx90a<op> {2779 2780 if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP then2781 def _dpp_gfx90a :2782 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>,2783 VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {2784 let DecoderNamespace = "GFX9";2785 }2786 }2787} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"2788 2789let SubtargetPredicate = HasFmacF64Inst, OtherPredicates = [isGFX9Only] in {2790 defm V_FMAC_F64 : VOP2_Real_e32e64_gfx90a <0x4>;2791} // End SubtargetPredicate = HasFmacF64Inst2792 2793let IsSingle = 1 in {2794 defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>;2795}2796 2797let SubtargetPredicate = HasFmaakFmamkF32Insts in {2798defm V_FMAMK_F32 : VOP2_Real_MADK_gfx940 <0x17>;2799defm V_FMAAK_F32 : VOP2_Real_MADK_gfx940 <0x18>;2800}2801 2802multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : Base_VOP2_Real_e32e64_vi<op> {2803 let SubtargetPredicate = isGFX9Only in2804 def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;2805}2806 2807multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> :2808 VOP2_Real_e32_gfx10<op>,2809 VOP2_Real_dpp_gfx10<op>,2810 VOP2_Real_dpp8_gfx10<op>;2811 2812multiclass VOP2Only_Real_DOT_ACC_gfx10<bits<6> op> : VOP2_Real_dpp_gfx10<op>,2813 VOP2_Real_dpp8_gfx10<op> {2814 let IsSingle = 1 in2815 defm NAME : VOP2_Real_e32_gfx10<op>;2816}2817 2818let OtherPredicates = [HasDot5Insts] in {2819 defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;2820 // NB: Opcode conflicts with V_DOT8C_I32_I42821 // This opcode exists in gfx 10.1* only2822 defm V_DOT2C_F32_F16 : VOP2Only_Real_DOT_ACC_gfx10<0x02>;2823}2824 2825let OtherPredicates = [HasDot6Insts] in {2826 defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx9<0x39>;2827 defm V_DOT4C_I32_I8 : VOP2Only_Real_DOT_ACC_gfx10<0x0d>;2828}2829 2830let OtherPredicates = [HasDot4Insts] in {2831 defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;2832}2833let OtherPredicates = [HasDot3Insts] in {2834 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx9<0x3a>;2835}2836 2837let SubtargetPredicate = HasPkFmacF16Inst in {2838defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;2839} // End SubtargetPredicate = HasPkFmacF16Inst2840 2841let SubtargetPredicate = HasDot3Insts in {2842 // NB: Opcode conflicts with V_DOT2C_F32_F162843 let DecoderNamespace = "GFX10_B" in2844 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>;2845}2846 2847let OtherPredicates = [HasDot13Insts] in {2848 let DecoderNamespace = "GFX950" in2849 defm V_DOT2C_F32_BF16 : VOP2_Real_DOT_ACC_gfx9<0x16>;2850}2851