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1//===-- VOPDInstructions.td - Vector Instruction Definitions --------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Encodings11//===----------------------------------------------------------------------===//12 13class VOPDe<bits<4> opX, bits<5> opY> : Enc64 {14 bits<9> src0X;15 bits<8> vsrc1X;16 bits<8> vdstX;17 bits<9> src0Y;18 bits<8> vsrc1Y;19 bits<8> vdstY;20 21 let Inst{8-0} = src0X;22 let Inst{16-9} = vsrc1X;23 let Inst{21-17} = opY;24 let Inst{25-22} = opX;25 let Inst{31-26} = 0x32; // encoding26 let Inst{40-32} = src0Y;27 let Inst{48-41} = vsrc1Y;28 let Inst{55-49} = vdstY{7-1};29 let Inst{63-56} = vdstX;30}31 32class VOPD_MADKe<bits<4> opX, bits<5> opY> : Enc96 {33 bits<9> src0X;34 bits<8> vsrc1X;35 bits<8> vdstX;36 bits<9> src0Y;37 bits<8> vsrc1Y;38 bits<8> vdstY;39 bits<32> imm;40 41 let Inst{8-0} = src0X;42 let Inst{16-9} = vsrc1X;43 let Inst{21-17} = opY;44 let Inst{25-22} = opX;45 let Inst{31-26} = 0x32; // encoding46 let Inst{40-32} = src0Y;47 let Inst{48-41} = vsrc1Y;48 let Inst{55-49} = vdstY{7-1};49 let Inst{63-56} = vdstX;50 let Inst{95-64} = imm;51}52 53class VOPD3e<bits<6> opX, bits<6> opY, VOP_Pseudo VDX, VOP_Pseudo VDY> : Enc96 {54 bits<9> src0X;55 bits<8> vsrc1X;56 bits<8> vsrc2X;57 bits<8> vdstX;58 bits<9> src0Y;59 bits<8> vsrc1Y;60 bits<8> vsrc2Y;61 bits<8> vdstY;62 // neg modifiers63 bit src0X_modifiers;64 bit src0Y_modifiers;65 bit vsrc1X_modifiers;66 bit vsrc1Y_modifiers;67 bit vsrc2X_modifiers;68 bit vsrc2Y_modifiers;69 bits<8> bitop3;70 71 let Inst{8-0} = src0X;72 let Inst{17-12} = opY;73 let Inst{23-18} = opX;74 let Inst{31-24} = 0xcf; // encoding75 let Inst{40-32} = src0Y;76 let Inst{41} = !if(VDX.Pfl.HasModifiers, src0X_modifiers, 0);77 let Inst{42} = !if(!and(VDX.Pfl.HasSrc1, VDX.Pfl.HasModifiers), vsrc1X_modifiers, 0);78 let Inst{43} = !if(!and(VDX.Pfl.HasVOPD3Src2, VDX.Pfl.HasModifiers), vsrc2X_modifiers, 0);79 let Inst{44} = !if(VDY.Pfl.HasModifiers, src0Y_modifiers, 0);80 let Inst{45} = !if(!and(VDY.Pfl.HasSrc1, VDY.Pfl.HasModifiers), vsrc1Y_modifiers, 0);81 let Inst{46} = !if(!and(VDY.Pfl.HasVOPD3Src2, VDY.Pfl.HasModifiers), vsrc2Y_modifiers, 0);82 let Inst{55-48} = !if(!eq(!find(VDX.Pfl.AsmVOPD3X, "$vsrc1X"), -1), 0, vsrc1X);83 84 // Despite the vsrc operand name, SGPRs can be used for vsrc2X for85 // V_DUAL_CNDMASK_B3286 let Inst{63-56} = !if(!eq(!find(VDX.Pfl.AsmVOPD3X, "$vsrc2X"), -1), 0, vsrc2X);87 let Inst{71-64} = vdstX;88 let Inst{79-72} = !if(!eq(!find(VDY.Pfl.AsmVOPD3Y, "$vsrc1Y"), -1), 0, vsrc1Y);89 let Inst{87-80} = !if(!ne(!find(VDY.Pfl.AsmVOPD3Y, "bitop"), -1), bitop3,90 !if(!eq(!find(VDY.Pfl.AsmVOPD3Y, "$vsrc2Y"), -1), 0, vsrc2Y));91 let Inst{95-88} = vdstY;92}93 94//===----------------------------------------------------------------------===//95// VOPD classes96//===----------------------------------------------------------------------===//97 98 99class GFXGenD<GFXGen Gen, list<string> DXPseudos, list<string> DYPseudos,100 Predicate subtargetPred = Gen.AssemblerPredicate> :101 GFXGen<Gen.AssemblerPredicate, Gen.DecoderNamespace, Gen.Suffix,102 Gen.Subtarget> {103 list<string> VOPDXPseudos = DXPseudos;104 list<string> VOPDYPseudos = DYPseudos;105 Predicate SubtargetPredicate = subtargetPred;106}107 108class VOPD_Base<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,109 VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>110 : VOPAnyCommon<outs, ins, asm, []>,111 VOP<NAME>,112 SIMCInstr<NAME, Gen.Subtarget> {113 // Fields for table indexing114 Instruction Opcode = !cast<Instruction>(NAME);115 bits<6> OpX = XasVC.VOPDOp;116 bits<6> OpY = YasVC.VOPDOp;117 bits<4> SubTgt = Gen.Subtarget;118 119 let VALU = 1;120 121 let DecoderNamespace = Gen.DecoderNamespace;122 let AssemblerPredicate = Gen.AssemblerPredicate;123 let WaveSizePredicate = isWave32;124 let isCodeGenOnly = 0;125 let SubtargetPredicate = Gen.SubtargetPredicate;126 let AsmMatchConverter = "cvtVOPD";127 let Size = 8;128 let ReadsModeReg = !or(VDX.ReadsModeReg, VDY.ReadsModeReg);129 let mayRaiseFPException = ReadsModeReg;130 131 // V_DUAL_FMAC and V_DUAL_DOT2ACC_F32_F16 and V_DUAL_DOT2ACC_F32_BF16 need a132 // dummy src2 tied to dst for passes to track its uses. Its presence does not133 // affect VOPD formation rules because the rules for src2 and dst are the134 // same. src2X and src2Y should not be encoded.135 bit hasSrc2AccX = !or(!eq(VDX.Mnemonic, "v_fmac_f32"), !eq(VDX.Mnemonic, "v_dot2c_f32_f16"), !eq(VDX.Mnemonic, "v_dot2c_f32_bf16"));136 bit hasSrc2AccY = !or(!eq(VDY.Mnemonic, "v_fmac_f32"), !eq(VDY.Mnemonic, "v_dot2c_f32_f16"), !eq(VDY.Mnemonic, "v_dot2c_f32_bf16"));137 string ConstraintsX = !if(hasSrc2AccX, "$src2X = $vdstX", "");138 string ConstraintsY = !if(hasSrc2AccY, "$src2Y = $vdstY", "");139 let Constraints =140 ConstraintsX # !if(!and(hasSrc2AccX, hasSrc2AccY), ", ", "") # ConstraintsY;141 142 let Uses = RegListUnion<VDX.Uses, VDY.Uses>.ret;143 let Defs = RegListUnion<VDX.Defs, VDY.Defs>.ret;144 let SchedRW = !listconcat(VDX.SchedRW, VDY.SchedRW);145}146 147class VOPD<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,148 VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>149 : VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC, Gen>,150 VOPDe<XasVC.VOPDOp{3-0}, YasVC.VOPDOp{4-0}> {151 let Inst{16-9} = !if (!eq(VDX.Mnemonic, "v_mov_b32"), 0x0, vsrc1X);152 let Inst{48-41} = !if (!eq(VDY.Mnemonic, "v_mov_b32"), 0x0, vsrc1Y);153}154 155class VOPD_MADK<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,156 VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>157 : VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC, Gen>,158 VOPD_MADKe<XasVC.VOPDOp{3-0}, YasVC.VOPDOp{4-0}> {159 let Inst{16-9} = !if (!eq(VDX.Mnemonic, "v_mov_b32"), 0x0, vsrc1X);160 let Inst{48-41} = !if (!eq(VDY.Mnemonic, "v_mov_b32"), 0x0, vsrc1Y);161 let Size = 12;162 let FixedSize = 1;163}164 165class VOPD3<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,166 VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>167 : VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC, Gen>,168 VOPD3e<XasVC.VOPDOp, YasVC.VOPDOp, VDX, VDY> {169 let VOPD3 = 1;170 let Size = 12;171 // VOPD3 uses promoted form of VOP2 instructions, so V_CNDMASK_B32 is not172 // limited to VCC src2 only, and a real SGPR will be used as an operand173 // instead.174 defvar UsesX = !if(!eq(VDX, V_CNDMASK_B32_e32), !filter(x, VDX.Uses, !ne(x, VCC)), VDX.Uses);175 defvar UsesY = !if(!eq(VDY, V_CNDMASK_B32_e32), !filter(x, VDY.Uses, !ne(x, VCC)), VDY.Uses);176 let Uses = RegListUnion<UsesX, UsesY>.ret;177}178 179defvar VOPDPseudosCommon = [180 "V_FMAC_F32_e32", "V_FMAAK_F32", "V_FMAMK_F32", "V_MUL_F32_e32",181 "V_ADD_F32_e32", "V_SUB_F32_e32", "V_SUBREV_F32_e32", "V_MUL_LEGACY_F32_e32",182 "V_MOV_B32_e32", "V_CNDMASK_B32_e32", "V_MAX_F32_e32", "V_MIN_F32_e32",183 "V_DOT2C_F32_F16_e32", "V_DOT2C_F32_BF16_e32"184];185defvar VOPDYOnlyPseudosCommon = ["V_ADD_U32_e32", "V_LSHLREV_B32_e32"];186defvar VOPDYOnlyPseudosGFX11_12 = ["V_AND_B32_e32"];187defvar VOPDYOnlyPseudosGFX1250 = ["V_MAX_I32_e32", "V_MIN_I32_e32",188 "V_SUB_U32_e32", "V_LSHRREV_B32_e32",189 "V_ASHRREV_I32_e32"];190 191defvar VOPDXPseudosGFX11 = VOPDPseudosCommon;192defvar VOPDXPseudosGFX12 = VOPDPseudosCommon;193defvar VOPDYPseudosGFX11 = !listconcat(VOPDXPseudosGFX11, VOPDYOnlyPseudosCommon, VOPDYOnlyPseudosGFX11_12);194defvar VOPDYPseudosGFX12 = !listconcat(VOPDXPseudosGFX12, VOPDYOnlyPseudosCommon, VOPDYOnlyPseudosGFX11_12);195defvar VOPDYPseudosGFX1250 = !listconcat(VOPDXPseudosGFX12, VOPDYOnlyPseudosCommon, VOPDYOnlyPseudosGFX1250);196 197def GFX11GenD : GFXGenD<GFX11Gen, VOPDXPseudosGFX11, VOPDYPseudosGFX11>;198def GFX12GenD : GFXGenD<GFX12Not12_50Gen, VOPDXPseudosGFX12, VOPDYPseudosGFX12>;199def GFX1250GenD : GFXGenD<GFX1250Gen, VOPDXPseudosGFX12, VOPDYPseudosGFX1250>;200 201 202def VOPDDstYOperand : RegisterOperand<VGPR_32, "printRegularOperand"> {203 let DecoderMethod = "decodeOperandVOPDDstY";204}205 206class getRenamed<string VOPDName, GFXGen Gen> {207 string ret = !cond(!eq(Gen.Subtarget, GFX11Gen.Subtarget) : VOPDName,208 !eq(VOPDName, "v_dual_max_f32") : "v_dual_max_num_f32",209 !eq(VOPDName, "v_dual_min_f32") : "v_dual_min_num_f32",210 true : VOPDName);211}212 213foreach Gen = [GFX11GenD, GFX12GenD, GFX1250GenD] in {214 foreach x = Gen.VOPDXPseudos in {215 foreach y = Gen.VOPDYPseudos in {216 defvar xInst = !cast<VOP_Pseudo>(x);217 defvar yInst = !cast<VOP_Pseudo>(y);218 defvar XasVC = !cast<VOPD_Component>(x);219 defvar YasVC = !cast<VOPD_Component>(y);220 defvar xAsmName = getRenamed<XasVC.VOPDName, Gen>.ret;221 defvar yAsmName = getRenamed<YasVC.VOPDName, Gen>.ret;222 defvar isMADK = !or(!eq(x, "V_FMAAK_F32"), !eq(x, "V_FMAMK_F32"),223 !eq(y, "V_FMAAK_F32"), !eq(y, "V_FMAMK_F32"));224 defvar isOpXMADK = !or(!eq(x, "V_FMAAK_F32"), !eq(x, "V_FMAMK_F32"));225 defvar isOpYMADK = !or(!eq(y, "V_FMAAK_F32"), !eq(y, "V_FMAMK_F32"));226 defvar OpName = "V_DUAL_" # !substr(x,2) # "_X_" # !substr(y,2) # Gen.Suffix;227 defvar outs = (outs VGPROp_32:$vdstX, VOPDDstYOperand:$vdstY);228 if !or(isOpXMADK, isOpYMADK) then {229 // If Both X and Y are MADK, the mandatory literal of X additionally must230 // use an alternate operand format which defers to the 'real' Y literal.231 defvar isOpXYMADK = !and(isOpXMADK, isOpYMADK);232 defvar X_MADK_Pfl = !cast<VOP_MADK_Base>(xInst.Pfl);233 defvar asm = xAsmName #" "#234 !if(isOpXYMADK, X_MADK_Pfl.AsmVOPDX_immX, xInst.Pfl.AsmVOPDX)#235 " :: "# yAsmName #" "# yInst.Pfl.AsmVOPDY;236 defvar ins = !con(!if(isOpXYMADK, xInst.Pfl.InsVOPDX_immX, xInst.Pfl.InsVOPDX),237 yInst.Pfl.InsVOPDY);238 def OpName : VOPD_MADK<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;239 } else {240 defvar ins = !con(xInst.Pfl.InsVOPDX, yInst.Pfl.InsVOPDY);241 defvar asm = xAsmName #" "# xInst.Pfl.AsmVOPDX #" :: "# yAsmName #" "# yInst.Pfl.AsmVOPDY;242 def OpName : VOPD<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;243 }244 }245 }246}247 248defvar VOPD3XPseudosExtra = ["V_ADD_U32_e32", "V_LSHLREV_B32_e32", "V_FMA_F32_e64", "V_SUB_U32_e32",249 "V_LSHRREV_B32_e32", "V_ASHRREV_I32_e32", "V_FMA_F64_e64", "V_ADD_F64_pseudo_e32",250 "V_MUL_F64_pseudo_e32", "V_MAX_NUM_F64_e32", "V_MIN_NUM_F64_e32"];251defvar VOPD3XPseudosGFX1250 = !listconcat(252 !filter(x, VOPDXPseudosGFX12, !and(!eq(!find(x, "FMAAK"), -1),253 !eq(!find(x, "FMAMK"), -1))),254 VOPD3XPseudosExtra);255defvar VOPD3YPseudosExtra = ["V_BITOP3_B32_e64", "V_FMA_F32_e64"];256defvar VOPD3YPseudosGFX1250 = !listconcat(257 !filter(x, VOPDYPseudosGFX1250, !and(!eq(!find(x, "FMAAK"), -1),258 !eq(!find(x, "FMAMK"), -1))),259 VOPD3YPseudosExtra);260 261def GFX1250GenD3 : GFXGenD<GFX1250Gen, VOPD3XPseudosGFX1250, VOPD3YPseudosGFX1250>;262 263class getOpcMap<string OPName> {264 defvar BaseName = !substr(OPName,2);265 string ret = !cond(!eq(BaseName, "BITOP3_B32_e64") : "BITOP2_B32_e64",266 1 : BaseName);267}268 269foreach Gen = [GFX1250GenD3] in {270 foreach x = Gen.VOPDXPseudos in {271 foreach y = Gen.VOPDYPseudos in {272 defvar xInst = !cast<VOP_Pseudo>(x);273 defvar yInst = !cast<VOP_Pseudo>(y);274 defvar XasVC = !cast<VOPD_Component>(x);275 defvar YasVC = !cast<VOPD_Component>(y);276 defvar xAsmName = getRenamed<XasVC.VOPDName, Gen>.ret;277 defvar yAsmName = getRenamed<YasVC.VOPDName, Gen>.ret;278 defvar OpName = "V_DUAL_" # getOpcMap<x>.ret # "_X_" # getOpcMap<y>.ret # "_e96" # Gen.Suffix;279 defvar asm = xAsmName # xInst.Pfl.AsmVOPD3X #" :: "# yAsmName #" "# yInst.Pfl.AsmVOPD3Y;280 defvar ins = !con(xInst.Pfl.InsVOPD3X, yInst.Pfl.InsVOPD3Y);281 defvar outs = (outs xInst.Pfl.DstRC:$vdstX, yInst.Pfl.DstRC:$vdstY);282 def OpName : VOPD3<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;283 }284 }285}286