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1//===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9include "llvm/Target/Target.td"10 11//===----------------------------------------------------------------------===//12// ARC Subtarget features13//===----------------------------------------------------------------------===//14 15def FeatureNORM16 : SubtargetFeature<"norm", "Xnorm", "true",17 "Enable support for norm instruction.">;18 19//===----------------------------------------------------------------------===//20// Registers, calling conventions, instruction descriptions21//===----------------------------------------------------------------------===//22 23include "ARCRegisterInfo.td"24include "ARCInstrInfo.td"25include "ARCCallingConv.td"26 27defm : RemapAllTargetPseudoPointerOperands<GPR32>;28 29def ARCInstrInfo : InstrInfo;30 31class Proc<string Name, list<SubtargetFeature> Features>32 : Processor<Name, NoItineraries, Features>;33 34def : Proc<"generic", []>;35 36def ARC : Target {37 let InstructionSet = ARCInstrInfo;38}39