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1//===- ARCISelLowering.h - ARC DAG Lowering Interface -----------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the interfaces that ARC uses to lower LLVM code into a10// selection DAG.11//12//===----------------------------------------------------------------------===//13 14#ifndef LLVM_LIB_TARGET_ARC_ARCISELLOWERING_H15#define LLVM_LIB_TARGET_ARC_ARCISELLOWERING_H16 17#include "ARC.h"18#include "llvm/CodeGen/SelectionDAG.h"19#include "llvm/CodeGen/TargetLowering.h"20 21namespace llvm {22 23// Forward delcarations24class ARCSubtarget;25class ARCTargetMachine;26 27//===--------------------------------------------------------------------===//28// TargetLowering Implementation29//===--------------------------------------------------------------------===//30class ARCTargetLowering : public TargetLowering {31public:32  explicit ARCTargetLowering(const TargetMachine &TM,33                             const ARCSubtarget &Subtarget);34 35  /// Provide custom lowering hooks for some operations.36  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;37 38  /// Return true if the addressing mode represented by AM is legal for this39  /// target, for a load/store of the specified type.40  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,41                             unsigned AS,42                             Instruction *I = nullptr) const override;43 44private:45  const ARCSubtarget &Subtarget;46 47  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,48                          SelectionDAG &DAG) const override;49 50  // Lower Operand helpers51  SDValue LowerCallArguments(SDValue Chain, CallingConv::ID CallConv,52                             bool isVarArg,53                             const SmallVectorImpl<ISD::InputArg> &Ins,54                             SDLoc dl, SelectionDAG &DAG,55                             SmallVectorImpl<SDValue> &InVals) const;56  // Lower Operand specifics57  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;58  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;59  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;60  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;61  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;62  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;63  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;64 65  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,66                               bool isVarArg,67                               const SmallVectorImpl<ISD::InputArg> &Ins,68                               const SDLoc &dl, SelectionDAG &DAG,69                               SmallVectorImpl<SDValue> &InVals) const override;70 71  SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,72                    SmallVectorImpl<SDValue> &InVals) const override;73 74  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,75                      const SmallVectorImpl<ISD::OutputArg> &Outs,76                      const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,77                      SelectionDAG &DAG) const override;78 79  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,80                      bool isVarArg,81                      const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,82                      LLVMContext &Context, const Type *RetTy) const override;83 84  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;85};86 87} // end namespace llvm88 89#endif // LLVM_LIB_TARGET_ARC_ARCISELLOWERING_H90