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1//===- ARCInstrInfo.h - ARC Instruction Information -------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the ARC implementation of the TargetInstrInfo class.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H14#define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H15 16#include "ARCRegisterInfo.h"17#include "llvm/CodeGen/TargetInstrInfo.h"18 19#define GET_INSTRINFO_HEADER20#include "ARCGenInstrInfo.inc"21 22namespace llvm {23 24class ARCSubtarget;25 26class ARCInstrInfo : public ARCGenInstrInfo {27 const ARCRegisterInfo RI;28 virtual void anchor();29 30public:31 ARCInstrInfo(const ARCSubtarget &);32 33 const ARCRegisterInfo &getRegisterInfo() const { return RI; }34 35 /// If the specified machine instruction is a direct36 /// load from a stack slot, return the virtual or physical register number of37 /// the destination along with the FrameIndex of the loaded stack slot. If38 /// not, return 0. This predicate must return 0 if the instruction has39 /// any side effects other than loading from the stack slot.40 Register isLoadFromStackSlot(const MachineInstr &MI,41 int &FrameIndex) const override;42 43 /// If the specified machine instruction is a direct44 /// store to a stack slot, return the virtual or physical register number of45 /// the source reg along with the FrameIndex of the loaded stack slot. If46 /// not, return 0. This predicate must return 0 if the instruction has47 /// any side effects other than storing to the stack slot.48 Register isStoreToStackSlot(const MachineInstr &MI,49 int &FrameIndex) const override;50 51 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;52 53 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,54 MachineBasicBlock *&FBB,55 SmallVectorImpl<MachineOperand> &Cond,56 bool AllowModify) const override;57 58 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,60 const DebugLoc &,61 int *BytesAdded = nullptr) const override;62 63 unsigned removeBranch(MachineBasicBlock &MBB,64 int *BytesRemoved = nullptr) const override;65 66 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,67 const DebugLoc &, Register DestReg, Register SrcReg,68 bool KillSrc, bool RenamableDest = false,69 bool RenamableSrc = false) const override;70 71 void storeRegToStackSlot(72 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,73 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,74 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;75 76 void loadRegFromStackSlot(77 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,78 int FrameIndex, const TargetRegisterClass *RC, Register VReg,79 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;80 81 bool82 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;83 84 85 bool isPostIncrement(const MachineInstr &MI) const override;86 87 // ARC-specific88 bool isPreIncrement(const MachineInstr &MI) const;89 90 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,91 unsigned &BasePos,92 unsigned &OffsetPos) const override;93 94 // Emit code before MBBI to load immediate value into physical register Reg.95 // Returns an iterator to the new instruction.96 MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,97 MachineBasicBlock::iterator MI,98 unsigned Reg, uint64_t Value) const;99};100 101} // end namespace llvm102 103#endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H104