80 lines · plain
1//===- ARCRegisterInfo.td - ARC Register defs --------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Declarations that describe the ARC register file11//===----------------------------------------------------------------------===//12 13class ARCReg<string n, list<string> altNames> : Register<n, altNames> {14 field bits<6> HwEncoding;15 let Namespace = "ARC";16}17 18// Registers are identified with 6-bit ID numbers.19// Core - 32-bit core registers20class Core<int num, string n, list<string>altNames=[]> : ARCReg<n, altNames> {21 let HWEncoding = num;22}23 24// Auxilary register25class Aux<int num, string n, list<string> altNames=[]> : ARCReg<n, altNames> {26 let HWEncoding = num;27}28 29// Integer registers30foreach i = 0 - 3 in31 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;32 33let CostPerUse=[1] in {34 foreach i = 4 - 11 in35 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;36}37 38foreach i = 12 - 15 in39 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;40 41let CostPerUse=[1] in {42 43 foreach i = 16 - 25 in44 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;45 46 def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>;47 def FP : Core<27, "%fp", ["%r27"]>, DwarfRegNum<[27]>;48 def SP : Core<28, "%sp", ["%r28"]>, DwarfRegNum<[28]>;49 def ILINK : Core<29, "%ilink">, DwarfRegNum<[29]>;50 def R30 : Core<30, "%r30">, DwarfRegNum<[30]>;51 def BLINK : Core<31, "%blink">, DwarfRegNum<[31]>;52 53 // Define extended core registers R32..R6354 foreach i = 32 - 63 in55 def R#i : Core<i, "%r"#i>, DwarfRegNum<[i]>;56}57 58// Auxilary registers59let CostPerUse=[1] in {60 def STATUS32 : Aux<10, "status32">; // No DwarfRegNum defined in the ARC ABI61}62 63def GPR32: RegisterClass<"ARC", [i32], 32,64 (add (sequence "R%u", 0, 25), GP, FP, SP, ILINK, R30, BLINK, (sequence "R%u", 32, 63))> {65 let AltOrders=[(add (sequence "R%u", 0, 25), GP, FP, SP, ILINK, R30, BLINK)];66 let AltOrderSelect = [{67 // When referenced in a C++ code block like this68 // 0 is all Core32 regs69 // 1 is AltOrders[0]70 // 2 is AltOrders[1] and so on71 return 1;72 }];73}74 75def SREG : RegisterClass<"ARC", [i32], 1, (add STATUS32)>;76 77def GPR_S : RegisterClass<"ARC", [i32], 8,78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;79 80