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1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9//10//===----------------------------------------------------------------------===//11 12//===----------------------------------------------------------------------===//13// Target-independent interfaces which we are implementing14//===----------------------------------------------------------------------===//15 16include "llvm/Target/Target.td"17 18include "ARMFeatures.td"19include "ARMArchitectures.td"20 21//===----------------------------------------------------------------------===//22// Register File Description23//===----------------------------------------------------------------------===//24 25include "ARMRegisterInfo.td"26include "ARMRegisterBanks.td"27include "ARMCallingConv.td"28 29//===----------------------------------------------------------------------===//30// ARM schedules.31//===----------------------------------------------------------------------===//32//33include "ARMPredicates.td"34include "ARMSchedule.td"35 36//===----------------------------------------------------------------------===//37// Instruction Descriptions38//===----------------------------------------------------------------------===//39 40include "ARMInstrInfo.td"41 42def Thumb1OnlyMode : HwMode<[IsThumb1Only]>;43def arm_ptr_rc : RegClassByHwMode<44 [DefaultMode, Thumb1OnlyMode],45 [GPR, tGPR]>;46 47defm : RemapAllTargetPseudoPointerOperands<arm_ptr_rc>;48 49def ARMInstrInfo : InstrInfo;50 51//===----------------------------------------------------------------------===//52// ARM schedules53//54include "ARMScheduleV6.td"55include "ARMScheduleA8.td"56include "ARMScheduleA9.td"57include "ARMScheduleSwift.td"58include "ARMScheduleR52.td"59include "ARMScheduleA57.td"60include "ARMScheduleM4.td"61include "ARMScheduleM55.td"62include "ARMScheduleM7.td"63include "ARMScheduleM85.td"64 65include "ARMProcessors.td"66 67//===----------------------------------------------------------------------===//68// Declare the target which we are implementing69//===----------------------------------------------------------------------===//70 71def ARMAsmWriter : AsmWriter {72 string AsmWriterClassName = "InstPrinter";73 int PassSubtarget = 1;74 int Variant = 0;75 bit isMCAsmWriter = 1;76}77 78def ARMAsmParser : AsmParser {79 bit ReportMultipleNearMisses = 1;80 let PreferSmallerInstructions = true;81}82 83def ARMAsmParserVariant : AsmParserVariant {84 int Variant = 0;85 string Name = "ARM";86 string BreakCharacters = ".";87}88 89def ARM : Target {90 // Pull in Instruction Info.91 let InstructionSet = ARMInstrInfo;92 let AssemblyWriters = [ARMAsmWriter];93 let AssemblyParsers = [ARMAsmParser];94 let AssemblyParserVariants = [ARMAsmParserVariant];95 let AllowRegisterRenaming = 1;96}97