963 lines · cpp
1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the base ARM implementation of TargetRegisterInfo class.10//11//===----------------------------------------------------------------------===//12 13#include "ARMBaseRegisterInfo.h"14#include "ARM.h"15#include "ARMBaseInstrInfo.h"16#include "ARMFrameLowering.h"17#include "ARMMachineFunctionInfo.h"18#include "ARMSubtarget.h"19#include "MCTargetDesc/ARMAddressingModes.h"20#include "MCTargetDesc/ARMBaseInfo.h"21#include "llvm/ADT/BitVector.h"22#include "llvm/ADT/STLExtras.h"23#include "llvm/ADT/SmallVector.h"24#include "llvm/CodeGen/MachineBasicBlock.h"25#include "llvm/CodeGen/MachineConstantPool.h"26#include "llvm/CodeGen/MachineFrameInfo.h"27#include "llvm/CodeGen/MachineFunction.h"28#include "llvm/CodeGen/MachineInstr.h"29#include "llvm/CodeGen/MachineInstrBuilder.h"30#include "llvm/CodeGen/MachineOperand.h"31#include "llvm/CodeGen/MachineRegisterInfo.h"32#include "llvm/CodeGen/RegisterScavenging.h"33#include "llvm/CodeGen/TargetInstrInfo.h"34#include "llvm/CodeGen/TargetRegisterInfo.h"35#include "llvm/CodeGen/VirtRegMap.h"36#include "llvm/IR/Attributes.h"37#include "llvm/IR/Constants.h"38#include "llvm/IR/DebugLoc.h"39#include "llvm/IR/Function.h"40#include "llvm/IR/Type.h"41#include "llvm/MC/MCInstrDesc.h"42#include "llvm/Support/Debug.h"43#include "llvm/Support/ErrorHandling.h"44#include "llvm/Support/raw_ostream.h"45#include "llvm/Target/TargetMachine.h"46#include "llvm/Target/TargetOptions.h"47#include <cassert>48#include <utility>49 50#define DEBUG_TYPE "arm-register-info"51 52#define GET_REGINFO_TARGET_DESC53#include "ARMGenRegisterInfo.inc"54 55using namespace llvm;56 57ARMBaseRegisterInfo::ARMBaseRegisterInfo()58 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {59 ARM_MC::initLLVMToCVRegMapping(this);60}61 62const MCPhysReg*63ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {64 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();65 ARMSubtarget::PushPopSplitVariation PushPopSplit =66 STI.getPushPopSplitVariation(*MF);67 const Function &F = MF->getFunction();68 69 if (F.getCallingConv() == CallingConv::GHC) {70 // GHC set of callee saved regs is empty as all those regs are71 // used for passing STG regs around72 return CSR_NoRegs_SaveList;73 } else if (PushPopSplit == ARMSubtarget::SplitR11WindowsSEH) {74 return CSR_Win_SplitFP_SaveList;75 } else if (F.getCallingConv() == CallingConv::CFGuard_Check) {76 return CSR_Win_AAPCS_CFGuard_Check_SaveList;77 } else if (F.getCallingConv() == CallingConv::SwiftTail) {78 return STI.isTargetDarwin() ? CSR_iOS_SwiftTail_SaveList79 : (PushPopSplit == ARMSubtarget::SplitR780 ? CSR_ATPCS_SplitPush_SwiftTail_SaveList81 : CSR_AAPCS_SwiftTail_SaveList);82 } else if (F.hasFnAttribute("interrupt")) {83 84 // Don't save the floating point registers if target does not have floating85 // point registers.86 if (STI.hasFPRegs() && F.hasFnAttribute("save-fp")) {87 bool HasNEON = STI.hasNEON();88 89 if (STI.isMClass()) {90 assert(!HasNEON && "NEON is only for Cortex-R/A");91 return PushPopSplit == ARMSubtarget::SplitR792 ? CSR_ATPCS_SplitPush_FP_SaveList93 : CSR_AAPCS_FP_SaveList;94 }95 if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {96 return HasNEON ? CSR_FIQ_FP_NEON_SaveList : CSR_FIQ_FP_SaveList;97 }98 return HasNEON ? CSR_GenericInt_FP_NEON_SaveList99 : CSR_GenericInt_FP_SaveList;100 }101 102 if (STI.isMClass()) {103 // M-class CPUs have hardware which saves the registers needed to allow a104 // function conforming to the AAPCS to function as a handler.105 return PushPopSplit == ARMSubtarget::SplitR7106 ? CSR_ATPCS_SplitPush_SaveList107 : CSR_AAPCS_SaveList;108 } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {109 // Fast interrupt mode gives the handler a private copy of R8-R14, so less110 // need to be saved to restore user-mode state.111 return CSR_FIQ_SaveList;112 } else {113 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by114 // exception handling.115 return CSR_GenericInt_SaveList;116 }117 }118 119 if (STI.getTargetLowering()->supportSwiftError() &&120 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {121 if (STI.isTargetDarwin())122 return CSR_iOS_SwiftError_SaveList;123 124 return PushPopSplit == ARMSubtarget::SplitR7125 ? CSR_ATPCS_SplitPush_SwiftError_SaveList126 : CSR_AAPCS_SwiftError_SaveList;127 }128 129 if (STI.isTargetDarwin() && F.getCallingConv() == CallingConv::CXX_FAST_TLS)130 return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()131 ? CSR_iOS_CXX_TLS_PE_SaveList132 : CSR_iOS_CXX_TLS_SaveList;133 134 if (STI.isTargetDarwin())135 return CSR_iOS_SaveList;136 137 if (PushPopSplit == ARMSubtarget::SplitR7)138 return STI.createAAPCSFrameChain() ? CSR_AAPCS_SplitPush_R7_SaveList139 : CSR_ATPCS_SplitPush_SaveList;140 141 if (PushPopSplit == ARMSubtarget::SplitR11AAPCSSignRA)142 return CSR_AAPCS_SplitPush_R11_SaveList;143 144 return CSR_AAPCS_SaveList;145}146 147const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(148 const MachineFunction *MF) const {149 assert(MF && "Invalid MachineFunction pointer.");150 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&151 MF->getInfo<ARMFunctionInfo>()->isSplitCSR())152 return CSR_iOS_CXX_TLS_ViaCopy_SaveList;153 return nullptr;154}155 156const uint32_t *157ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,158 CallingConv::ID CC) const {159 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();160 if (CC == CallingConv::GHC)161 // This is academic because all GHC calls are (supposed to be) tail calls162 return CSR_NoRegs_RegMask;163 if (CC == CallingConv::CFGuard_Check)164 return CSR_Win_AAPCS_CFGuard_Check_RegMask;165 if (CC == CallingConv::SwiftTail) {166 return STI.isTargetDarwin() ? CSR_iOS_SwiftTail_RegMask167 : CSR_AAPCS_SwiftTail_RegMask;168 }169 if (STI.getTargetLowering()->supportSwiftError() &&170 MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))171 return STI.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask172 : CSR_AAPCS_SwiftError_RegMask;173 174 if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)175 return CSR_iOS_CXX_TLS_RegMask;176 return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;177}178 179const uint32_t*180ARMBaseRegisterInfo::getNoPreservedMask() const {181 return CSR_NoRegs_RegMask;182}183 184const uint32_t *185ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const {186 assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&187 "only know about special TLS call on Darwin");188 return CSR_iOS_TLSCall_RegMask;189}190 191const uint32_t *192ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const {193 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();194 if (!STI.useSoftFloat() && STI.hasVFP2Base() && !STI.isThumb1Only())195 return CSR_NoRegs_RegMask;196 else197 return CSR_FPRegs_RegMask;198}199 200const uint32_t *201ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,202 CallingConv::ID CC) const {203 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();204 // This should return a register mask that is the same as that returned by205 // getCallPreservedMask but that additionally preserves the register used for206 // the first i32 argument (which must also be the register used to return a207 // single i32 return value)208 //209 // In case that the calling convention does not use the same register for210 // both or otherwise does not want to enable this optimization, the function211 // should return NULL212 if (CC == CallingConv::GHC)213 // This is academic because all GHC calls are (supposed to be) tail calls214 return nullptr;215 return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask216 : CSR_AAPCS_ThisReturn_RegMask;217}218 219ArrayRef<MCPhysReg> ARMBaseRegisterInfo::getIntraCallClobberedRegs(220 const MachineFunction *MF) const {221 static const MCPhysReg IntraCallClobberedRegs[] = {ARM::R12};222 return ArrayRef<MCPhysReg>(IntraCallClobberedRegs);223}224 225BitVector ARMBaseRegisterInfo::226getReservedRegs(const MachineFunction &MF) const {227 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();228 const ARMFrameLowering *TFI = getFrameLowering(MF);229 230 // FIXME: avoid re-calculating this every time.231 BitVector Reserved(getNumRegs());232 markSuperRegs(Reserved, ARM::SP);233 markSuperRegs(Reserved, ARM::PC);234 markSuperRegs(Reserved, ARM::FPSCR);235 markSuperRegs(Reserved, ARM::FPSCR_RM);236 markSuperRegs(Reserved, ARM::APSR_NZCV);237 if (TFI->isFPReserved(MF))238 markSuperRegs(Reserved, STI.getFramePointerReg());239 if (hasBasePointer(MF))240 markSuperRegs(Reserved, BasePtr);241 // Some targets reserve R9.242 if (STI.isR9Reserved())243 markSuperRegs(Reserved, ARM::R9);244 // Reserve D16-D31 if the subtarget doesn't support them.245 if (!STI.hasD32()) {246 static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");247 for (unsigned R = 0; R < 16; ++R)248 markSuperRegs(Reserved, ARM::D16 + R);249 }250 const TargetRegisterClass &RC = ARM::GPRPairRegClass;251 for (unsigned Reg : RC)252 for (MCPhysReg S : subregs(Reg))253 if (Reserved.test(S))254 markSuperRegs(Reserved, Reg);255 // For v8.1m architecture256 markSuperRegs(Reserved, ARM::ZR);257 258 assert(checkAllSuperRegsMarked(Reserved));259 return Reserved;260}261 262bool ARMBaseRegisterInfo::263isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const {264 return !getReservedRegs(MF).test(PhysReg);265}266 267bool ARMBaseRegisterInfo::isInlineAsmReadOnlyReg(const MachineFunction &MF,268 MCRegister PhysReg) const {269 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();270 const ARMFrameLowering *TFI = getFrameLowering(MF);271 272 BitVector Reserved(getNumRegs());273 markSuperRegs(Reserved, ARM::PC);274 if (TFI->isFPReserved(MF))275 markSuperRegs(Reserved, STI.getFramePointerReg());276 if (hasBasePointer(MF))277 markSuperRegs(Reserved, BasePtr);278 assert(checkAllSuperRegsMarked(Reserved));279 return Reserved.test(PhysReg.id());280}281 282const TargetRegisterClass *283ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,284 const MachineFunction &MF) const {285 unsigned SuperID = RC->getID();286 auto I = RC->superclasses().begin();287 auto E = RC->superclasses().end();288 do {289 switch (SuperID) {290 case ARM::GPRRegClassID:291 case ARM::SPRRegClassID:292 case ARM::DPRRegClassID:293 case ARM::GPRPairRegClassID:294 return getRegClass(SuperID);295 case ARM::QPRRegClassID:296 case ARM::QQPRRegClassID:297 case ARM::QQQQPRRegClassID:298 if (MF.getSubtarget<ARMSubtarget>().hasNEON())299 return getRegClass(SuperID);300 break;301 case ARM::MQPRRegClassID:302 case ARM::MQQPRRegClassID:303 case ARM::MQQQQPRRegClassID:304 if (MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps())305 return getRegClass(SuperID);306 break;307 }308 SuperID = (I != E) ? *I++ : ~0U;309 } while (SuperID != ~0U);310 return RC;311}312 313const TargetRegisterClass *314ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {315 return &ARM::GPRRegClass;316}317 318const TargetRegisterClass *319ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {320 if (RC == &ARM::CCRRegClass)321 return &ARM::rGPRRegClass; // Can't copy CCR registers.322 if (RC == &ARM::cl_FPSCR_NZCVRegClass)323 return &ARM::rGPRRegClass;324 return RC;325}326 327unsigned328ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,329 MachineFunction &MF) const {330 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();331 const ARMFrameLowering *TFI = getFrameLowering(MF);332 333 switch (RC->getID()) {334 default:335 return 0;336 case ARM::tGPRRegClassID: {337 // hasFP ends up calling getMaxCallFrameComputed() which may not be338 // available when getPressureLimit() is called as part of339 // ScheduleDAGRRList.340 bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()341 ? TFI->hasFP(MF) : true;342 return 5 - HasFP;343 }344 case ARM::GPRRegClassID: {345 bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()346 ? TFI->hasFP(MF) : true;347 return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);348 }349 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.350 case ARM::DPRRegClassID:351 return 32 - 10;352 }353}354 355// Get the other register in a GPRPair.356static MCRegister getPairedGPR(MCRegister Reg, bool Odd,357 const MCRegisterInfo *RI) {358 for (MCPhysReg Super : RI->superregs(Reg))359 if (ARM::GPRPairRegClass.contains(Super))360 return RI->getSubReg(Super, Odd ? ARM::gsub_1 : ARM::gsub_0);361 return MCRegister();362}363 364// Resolve the RegPairEven / RegPairOdd register allocator hints.365bool ARMBaseRegisterInfo::getRegAllocationHints(366 Register VirtReg, ArrayRef<MCPhysReg> Order,367 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,368 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {369 const MachineRegisterInfo &MRI = MF.getRegInfo();370 std::pair<unsigned, Register> Hint = MRI.getRegAllocationHint(VirtReg);371 372 unsigned Odd;373 switch (Hint.first) {374 case ARMRI::RegPairEven:375 Odd = 0;376 break;377 case ARMRI::RegPairOdd:378 Odd = 1;379 break;380 case ARMRI::RegLR:381 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);382 if (MRI.getRegClass(VirtReg)->contains(ARM::LR))383 Hints.push_back(ARM::LR);384 return false;385 default:386 return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);387 }388 389 // This register should preferably be even (Odd == 0) or odd (Odd == 1).390 // Check if the other part of the pair has already been assigned, and provide391 // the paired register as the first hint.392 Register Paired = Hint.second;393 if (!Paired)394 return false;395 396 Register PairedPhys;397 if (Paired.isPhysical()) {398 PairedPhys = Paired;399 } else if (VRM && VRM->hasPhys(Paired)) {400 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);401 }402 403 // First prefer the paired physreg.404 if (PairedPhys && is_contained(Order, PairedPhys))405 Hints.push_back(PairedPhys);406 407 // Then prefer even or odd registers.408 for (MCPhysReg Reg : Order) {409 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)410 continue;411 // Don't provide hints that are paired to a reserved register.412 MCRegister Paired = getPairedGPR(Reg, !Odd, this);413 if (!Paired || MRI.isReserved(Paired))414 continue;415 Hints.push_back(Reg);416 }417 return false;418}419 420void ARMBaseRegisterInfo::updateRegAllocHint(Register Reg, Register NewReg,421 MachineFunction &MF) const {422 MachineRegisterInfo *MRI = &MF.getRegInfo();423 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(Reg);424 if ((Hint.first == ARMRI::RegPairOdd || Hint.first == ARMRI::RegPairEven) &&425 Hint.second.isVirtual()) {426 // If 'Reg' is one of the even / odd register pair and it's now changed427 // (e.g. coalesced) into a different register. The other register of the428 // pair allocation hint must be updated to reflect the relationship429 // change.430 Register OtherReg = Hint.second;431 Hint = MRI->getRegAllocationHint(OtherReg);432 // Make sure the pair has not already divorced.433 if (Hint.second == Reg) {434 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);435 if (NewReg.isVirtual())436 MRI->setRegAllocationHint(NewReg,437 Hint.first == ARMRI::RegPairOdd438 ? ARMRI::RegPairEven439 : ARMRI::RegPairOdd,440 OtherReg);441 }442 }443}444 445bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {446 const MachineFrameInfo &MFI = MF.getFrameInfo();447 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();448 const ARMFrameLowering *TFI = getFrameLowering(MF);449 450 // If we have stack realignment and VLAs, we have no pointer to use to451 // access the stack. If we have stack realignment, and a large call frame,452 // we have no place to allocate the emergency spill slot.453 if (hasStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))454 return true;455 456 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited457 // negative range for ldr/str (255), and Thumb1 is positive offsets only.458 //459 // It's going to be better to use the SP or Base Pointer instead. When there460 // are variable sized objects, we can't reference off of the SP, so we461 // reserve a Base Pointer.462 //463 // For Thumb2, estimate whether a negative offset from the frame pointer464 // will be sufficient to reach the whole stack frame. If a function has a465 // smallish frame, it's less likely to have lots of spills and callee saved466 // space, so it's all more likely to be within range of the frame pointer.467 // If it's wrong, the scavenger will still enable access to work, it just468 // won't be optimal. (We should always be able to reach the emergency469 // spill slot from the frame pointer.)470 if (AFI->isThumb2Function() && MFI.hasVarSizedObjects() &&471 MFI.getLocalFrameSize() >= 128)472 return true;473 // For Thumb1, if sp moves, nothing is in range, so force a base pointer.474 // This is necessary for correctness in cases where we need an emergency475 // spill slot. (In Thumb1, we can't use a negative offset from the frame476 // pointer.)477 if (AFI->isThumb1OnlyFunction() && !TFI->hasReservedCallFrame(MF))478 return true;479 return false;480}481 482bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {483 const MachineRegisterInfo *MRI = &MF.getRegInfo();484 const ARMFrameLowering *TFI = getFrameLowering(MF);485 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();486 // We can't realign the stack if:487 // 1. Dynamic stack realignment is explicitly disabled,488 // 2. There are VLAs in the function and the base pointer is disabled.489 if (!TargetRegisterInfo::canRealignStack(MF))490 return false;491 // Stack realignment requires a frame pointer. If we already started492 // register allocation with frame pointer elimination, it is too late now.493 if (!MRI->canReserveReg(STI.getFramePointerReg()))494 return false;495 // We may also need a base pointer if there are dynamic allocas or stack496 // pointer adjustments around calls.497 if (TFI->hasReservedCallFrame(MF))498 return true;499 // A base pointer is required and allowed. Check that it isn't too late to500 // reserve it.501 return MRI->canReserveReg(BasePtr);502}503 504bool ARMBaseRegisterInfo::505cannotEliminateFrame(const MachineFunction &MF) const {506 const MachineFrameInfo &MFI = MF.getFrameInfo();507 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())508 return true;509 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||510 hasStackRealignment(MF);511}512 513Register514ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {515 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();516 const ARMFrameLowering *TFI = getFrameLowering(MF);517 518 if (TFI->hasFP(MF))519 return STI.getFramePointerReg();520 return ARM::SP;521}522 523/// emitLoadConstPool - Emits a load from constpool to materialize the524/// specified immediate.525void ARMBaseRegisterInfo::emitLoadConstPool(526 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,527 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val,528 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {529 MachineFunction &MF = *MBB.getParent();530 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();531 MachineConstantPool *ConstantPool = MF.getConstantPool();532 const Constant *C =533 ConstantInt::get(Type::getInt32Ty(MF.getFunction().getContext()), Val);534 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4));535 536 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))537 .addReg(DestReg, getDefRegState(true), SubIdx)538 .addConstantPoolIndex(Idx)539 .addImm(0)540 .add(predOps(Pred, PredReg))541 .setMIFlags(MIFlags);542}543 544bool ARMBaseRegisterInfo::545requiresRegisterScavenging(const MachineFunction &MF) const {546 return true;547}548 549bool ARMBaseRegisterInfo::550requiresFrameIndexScavenging(const MachineFunction &MF) const {551 return true;552}553 554bool ARMBaseRegisterInfo::555requiresVirtualBaseRegisters(const MachineFunction &MF) const {556 return true;557}558 559int64_t ARMBaseRegisterInfo::560getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {561 const MCInstrDesc &Desc = MI->getDesc();562 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);563 int64_t InstrOffs = 0;564 int Scale = 1;565 unsigned ImmIdx = 0;566 switch (AddrMode) {567 case ARMII::AddrModeT2_i8:568 case ARMII::AddrModeT2_i8neg:569 case ARMII::AddrModeT2_i8pos:570 case ARMII::AddrModeT2_i12:571 case ARMII::AddrMode_i12:572 InstrOffs = MI->getOperand(Idx+1).getImm();573 Scale = 1;574 break;575 case ARMII::AddrMode5: {576 // VFP address mode.577 const MachineOperand &OffOp = MI->getOperand(Idx+1);578 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());579 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)580 InstrOffs = -InstrOffs;581 Scale = 4;582 break;583 }584 case ARMII::AddrMode2:585 ImmIdx = Idx+2;586 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());587 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)588 InstrOffs = -InstrOffs;589 break;590 case ARMII::AddrMode3:591 ImmIdx = Idx+2;592 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());593 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)594 InstrOffs = -InstrOffs;595 break;596 case ARMII::AddrModeT1_s:597 ImmIdx = Idx+1;598 InstrOffs = MI->getOperand(ImmIdx).getImm();599 Scale = 4;600 break;601 default:602 llvm_unreachable("Unsupported addressing mode!");603 }604 605 return InstrOffs * Scale;606}607 608/// needsFrameBaseReg - Returns true if the instruction's frame index609/// reference would be better served by a base register other than FP610/// or SP. Used by LocalStackFrameAllocation to determine which frame index611/// references it should create new base registers for.612bool ARMBaseRegisterInfo::613needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {614 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {615 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");616 }617 618 // It's the load/store FI references that cause issues, as it can be difficult619 // to materialize the offset if it won't fit in the literal field. Estimate620 // based on the size of the local frame and some conservative assumptions621 // about the rest of the stack frame (note, this is pre-regalloc, so622 // we don't know everything for certain yet) whether this offset is likely623 // to be out of range of the immediate. Return true if so.624 625 // We only generate virtual base registers for loads and stores, so626 // return false for everything else.627 unsigned Opc = MI->getOpcode();628 switch (Opc) {629 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:630 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:631 case ARM::t2LDRi12: case ARM::t2LDRi8:632 case ARM::t2STRi12: case ARM::t2STRi8:633 case ARM::VLDRS: case ARM::VLDRD:634 case ARM::VSTRS: case ARM::VSTRD:635 case ARM::tSTRspi: case ARM::tLDRspi:636 break;637 default:638 return false;639 }640 641 // Without a virtual base register, if the function has variable sized642 // objects, all fixed-size local references will be via the frame pointer,643 // Approximate the offset and see if it's legal for the instruction.644 // Note that the incoming offset is based on the SP value at function entry,645 // so it'll be negative.646 MachineFunction &MF = *MI->getParent()->getParent();647 const ARMFrameLowering *TFI = getFrameLowering(MF);648 MachineFrameInfo &MFI = MF.getFrameInfo();649 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();650 651 // Estimate an offset from the frame pointer.652 // Conservatively assume all callee-saved registers get pushed. R4-R6653 // will be earlier than the FP, so we ignore those.654 // R7, LR655 int64_t FPOffset = Offset - 8;656 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15657 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())658 FPOffset -= 80;659 // Estimate an offset from the stack pointer.660 // The incoming offset is relating to the SP at the start of the function,661 // but when we access the local it'll be relative to the SP after local662 // allocation, so adjust our SP-relative offset by that allocation size.663 Offset += MFI.getLocalFrameSize();664 // Assume that we'll have at least some spill slots allocated.665 // FIXME: This is a total SWAG number. We should run some statistics666 // and pick a real one.667 Offset += 128; // 128 bytes of spill slots668 669 // If there's a frame pointer and the addressing mode allows it, try using it.670 // The FP is only available if there is no dynamic realignment. We671 // don't know for sure yet whether we'll need that, so we guess based672 // on whether there are any local variables that would trigger it.673 if (TFI->hasFP(MF) &&674 !((MFI.getLocalFrameMaxAlign() > TFI->getStackAlign()) &&675 canRealignStack(MF))) {676 if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))677 return false;678 }679 // If we can reference via the stack pointer, try that.680 // FIXME: This (and the code that resolves the references) can be improved681 // to only disallow SP relative references in the live range of682 // the VLA(s). In practice, it's unclear how much difference that683 // would make, but it may be worth doing.684 if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))685 return false;686 687 // The offset likely isn't legal, we want to allocate a virtual base register.688 return true;689}690 691/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to692/// be a pointer to FrameIdx at the beginning of the basic block.693Register694ARMBaseRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,695 int FrameIdx,696 int64_t Offset) const {697 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();698 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :699 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);700 701 MachineBasicBlock::iterator Ins = MBB->begin();702 DebugLoc DL; // Defaults to "unknown"703 if (Ins != MBB->end())704 DL = Ins->getDebugLoc();705 706 const MachineFunction &MF = *MBB->getParent();707 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();708 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();709 const MCInstrDesc &MCID = TII.get(ADDriOpc);710 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass);711 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0));712 713 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)714 .addFrameIndex(FrameIdx).addImm(Offset);715 716 if (!AFI->isThumb1OnlyFunction())717 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());718 719 return BaseReg;720}721 722void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,723 int64_t Offset) const {724 MachineBasicBlock &MBB = *MI.getParent();725 MachineFunction &MF = *MBB.getParent();726 const ARMBaseInstrInfo &TII =727 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());728 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();729 int Off = Offset; // ARM doesn't need the general 64-bit offsets730 unsigned i = 0;731 732 assert(!AFI->isThumb1OnlyFunction() &&733 "This resolveFrameIndex does not support Thumb1!");734 735 while (!MI.getOperand(i).isFI()) {736 ++i;737 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");738 }739 bool Done = false;740 if (!AFI->isThumbFunction())741 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);742 else {743 assert(AFI->isThumb2Function());744 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this);745 }746 assert(Done && "Unable to resolve frame index!");747 (void)Done;748}749 750bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,751 Register BaseReg,752 int64_t Offset) const {753 const MCInstrDesc &Desc = MI->getDesc();754 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);755 unsigned i = 0;756 for (; !MI->getOperand(i).isFI(); ++i)757 assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");758 759 // AddrMode4 and AddrMode6 cannot handle any offset.760 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)761 return Offset == 0;762 763 unsigned NumBits = 0;764 unsigned Scale = 1;765 bool isSigned = true;766 switch (AddrMode) {767 case ARMII::AddrModeT2_i8:768 case ARMII::AddrModeT2_i8pos:769 case ARMII::AddrModeT2_i8neg:770 case ARMII::AddrModeT2_i12:771 // i8 supports only negative, and i12 supports only positive, so772 // based on Offset sign, consider the appropriate instruction773 Scale = 1;774 if (Offset < 0) {775 NumBits = 8;776 Offset = -Offset;777 } else {778 NumBits = 12;779 }780 break;781 case ARMII::AddrMode5:782 // VFP address mode.783 NumBits = 8;784 Scale = 4;785 break;786 case ARMII::AddrMode_i12:787 case ARMII::AddrMode2:788 NumBits = 12;789 break;790 case ARMII::AddrMode3:791 NumBits = 8;792 break;793 case ARMII::AddrModeT1_s:794 NumBits = (BaseReg == ARM::SP ? 8 : 5);795 Scale = 4;796 isSigned = false;797 break;798 default:799 llvm_unreachable("Unsupported addressing mode!");800 }801 802 Offset += getFrameIndexInstrOffset(MI, i);803 // Make sure the offset is encodable for instructions that scale the804 // immediate.805 if ((Offset & (Scale-1)) != 0)806 return false;807 808 if (isSigned && Offset < 0)809 Offset = -Offset;810 811 unsigned Mask = (1 << NumBits) - 1;812 if ((unsigned)Offset <= Mask * Scale)813 return true;814 815 return false;816}817 818bool819ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,820 int SPAdj, unsigned FIOperandNum,821 RegScavenger *RS) const {822 MachineInstr &MI = *II;823 MachineBasicBlock &MBB = *MI.getParent();824 MachineFunction &MF = *MBB.getParent();825 const ARMBaseInstrInfo &TII =826 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());827 const ARMFrameLowering *TFI = getFrameLowering(MF);828 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();829 assert(!AFI->isThumb1OnlyFunction() &&830 "This eliminateFrameIndex does not support Thumb1!");831 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();832 Register FrameReg;833 834 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);835 836 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the837 // call frame setup/destroy instructions have already been eliminated. That838 // means the stack pointer cannot be used to access the emergency spill slot839 // when !hasReservedCallFrame().840#ifndef NDEBUG841 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){842 assert(TFI->hasReservedCallFrame(MF) &&843 "Cannot use SP to access the emergency spill slot in "844 "functions without a reserved call frame");845 assert(!MF.getFrameInfo().hasVarSizedObjects() &&846 "Cannot use SP to access the emergency spill slot in "847 "functions with variable sized frame objects");848 }849#endif // NDEBUG850 851 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");852 853 // Modify MI as necessary to handle as much of 'Offset' as possible854 bool Done = false;855 if (!AFI->isThumbFunction())856 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);857 else {858 assert(AFI->isThumb2Function());859 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII, this);860 }861 if (Done)862 return false;863 864 // If we get here, the immediate doesn't fit into the instruction. We folded865 // as much as possible above, handle the rest, providing a register that is866 // SP+LargeImm.867 assert(868 (Offset ||869 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||870 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6 ||871 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7 ||872 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7s2 ||873 (MI.getDesc().TSFlags & ARMII::AddrModeMask) ==874 ARMII::AddrModeT2_i7s4) &&875 "This code isn't needed if offset already handled!");876 877 unsigned ScratchReg = 0;878 int PIdx = MI.findFirstPredOperandIdx();879 ARMCC::CondCodes Pred = (PIdx == -1)880 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();881 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();882 883 const MCInstrDesc &MCID = MI.getDesc();884 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, FIOperandNum);885 886 if (Offset == 0 && (FrameReg.isVirtual() || RegClass->contains(FrameReg)))887 // Must be addrmode4/6.888 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);889 else {890 ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);891 if (!AFI->isThumbFunction())892 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,893 Offset, Pred, PredReg, TII);894 else {895 assert(AFI->isThumb2Function());896 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,897 Offset, Pred, PredReg, TII);898 }899 // Update the original instruction to use the scratch register.900 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);901 }902 return false;903}904 905bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,906 const TargetRegisterClass *SrcRC,907 unsigned SubReg,908 const TargetRegisterClass *DstRC,909 unsigned DstSubReg,910 const TargetRegisterClass *NewRC,911 LiveIntervals &LIS) const {912 auto MBB = MI->getParent();913 auto MF = MBB->getParent();914 const MachineRegisterInfo &MRI = MF->getRegInfo();915 // If not copying into a sub-register this should be ok because we shouldn't916 // need to split the reg.917 if (!DstSubReg)918 return true;919 // Small registers don't frequently cause a problem, so we can coalesce them.920 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&921 getRegSizeInBits(*SrcRC) < 256)922 return true;923 924 auto NewRCWeight =925 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);926 auto SrcRCWeight =927 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);928 auto DstRCWeight =929 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);930 // If the source register class is more expensive than the destination, the931 // coalescing is probably profitable.932 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)933 return true;934 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)935 return true;936 937 // If the register allocator isn't constrained, we can always allow coalescing938 // unfortunately we don't know yet if we will be constrained.939 // The goal of this heuristic is to restrict how many expensive registers940 // we allow to coalesce in a given basic block.941 auto AFI = MF->getInfo<ARMFunctionInfo>();942 auto It = AFI->getCoalescedWeight(MBB);943 944 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "945 << It->second << "\n");946 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "947 << NewRCWeight.RegWeight << "\n");948 949 // This number is the largest round number that which meets the criteria:950 // (1) addresses PR18825951 // (2) generates better code in some test cases (like vldm-shed-a9.ll)952 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)953 // In practice the SizeMultiplier will only factor in for straight line code954 // that uses a lot of NEON vectors, which isn't terribly common.955 unsigned SizeMultiplier = MBB->size()/100;956 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;957 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {958 It->second += NewRCWeight.RegWeight;959 return true;960 }961 return false;962}963