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1//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8// This describes the calling conventions for ARM architecture.9//===----------------------------------------------------------------------===//10 11/// CCIfAlign - Match of the original alignment of the arg12class CCIfAlign<string Align, CCAction A>:13 CCIf<!strconcat("ArgFlags.getNonZeroOrigAlign() == ", Align), A>;14 15//===----------------------------------------------------------------------===//16// ARM APCS Calling Convention17//===----------------------------------------------------------------------===//18let Entry = 1 in19def CC_ARM_APCS : CallingConv<[20 21 // Handles byval parameters.22 CCIfByVal<CCPassByVal<4, 4>>,23 24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,25 26 // Pass SwiftSelf in a callee saved register.27 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,28 29 // A SwiftError is passed in R8.30 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,31 32 // Handle all vector types as either f64 or v2f64.33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,35 36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack37 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,38 39 CCIfType<[f32], CCBitConvertToType<i32>>,40 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,41 42 CCIfType<[i32], CCAssignToStack<4, 4>>,43 CCIfType<[f64], CCAssignToStack<8, 4>>,44 CCIfType<[v2f64], CCAssignToStack<16, 4>>45]>;46 47let Entry = 1 in48def RetCC_ARM_APCS : CallingConv<[49 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,50 CCIfType<[f32], CCBitConvertToType<i32>>,51 52 // Pass SwiftSelf in a callee saved register.53 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,54 55 // A SwiftError is returned in R8.56 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,57 58 // Handle all vector types as either f64 or v2f64.59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,61 62 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,63 64 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,65 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>66]>;67 68//===----------------------------------------------------------------------===//69// ARM APCS Calling Convention for FastCC (when VFP2 or later is available)70//===----------------------------------------------------------------------===//71let Entry = 1 in72def FastCC_ARM_APCS : CallingConv<[73 // Handle all vector types as either f64 or v2f64.74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,76 77 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,78 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,79 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,80 S9, S10, S11, S12, S13, S14, S15]>>,81 82 // CPRCs may be allocated to co-processor registers or the stack - they83 // may never be allocated to core registers.84 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,85 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,86 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,87 88 CCDelegateTo<CC_ARM_APCS>89]>;90 91let Entry = 1 in92def RetFastCC_ARM_APCS : CallingConv<[93 // Handle all vector types as either f64 or v2f64.94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,96 97 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,98 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,99 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,100 S9, S10, S11, S12, S13, S14, S15]>>,101 CCDelegateTo<RetCC_ARM_APCS>102]>;103 104//===----------------------------------------------------------------------===//105// ARM APCS Calling Convention for GHC106//===----------------------------------------------------------------------===//107 108let Entry = 1 in109def CC_ARM_APCS_GHC : CallingConv<[110 // Handle all vector types as either f64 or v2f64.111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,113 114 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,115 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,116 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,117 118 // Promote i8/i16 arguments to i32.119 CCIfType<[i8, i16], CCPromoteToType<i32>>,120 121 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>123]>;124 125//===----------------------------------------------------------------------===//126// ARM AAPCS (EABI) Calling Convention, common parts127//===----------------------------------------------------------------------===//128 129def CC_ARM_AAPCS_Common : CallingConv<[130 131 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,132 133 // i64/f64 is passed in even pairs of GPRs134 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register135 // (and the same is true for f64 if VFP is not enabled)136 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,137 CCIfType<[i32], CCIf<"ArgFlags.getNonZeroOrigAlign() != Align(8)",138 CCAssignToReg<[R0, R1, R2, R3]>>>,139 140 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>,141 CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>,142 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,143 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_Common_Custom_f16_Stack">>,144 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,145 CCIfType<[v2f64], CCIfAlign<"16",146 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,147 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>148]>;149 150def RetCC_ARM_AAPCS_Common : CallingConv<[151 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,152 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,153 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>154]>;155 156//===----------------------------------------------------------------------===//157// ARM AAPCS (EABI) Calling Convention158//===----------------------------------------------------------------------===//159 160let Entry = 1 in161def CC_ARM_AAPCS : CallingConv<[162 // Handles byval parameters.163 CCIfByVal<CCPassByVal<4, 4>>,164 165 // The 'nest' parameter, if any, is passed in R12.166 CCIfNest<CCAssignToReg<[R12]>>,167 168 // Handle all vector types as either f64 or v2f64.169 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,170 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,171 172 // Pass SwiftSelf in a callee saved register.173 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,174 175 // A SwiftError is passed in R8.176 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,177 178 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,179 CCIfType<[f32], CCBitConvertToType<i32>>,180 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_Custom_f16">>,181 CCDelegateTo<CC_ARM_AAPCS_Common>182]>;183 184let Entry = 1 in185def RetCC_ARM_AAPCS : CallingConv<[186 // Handle all vector types as either f64 or v2f64.187 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,188 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,189 190 // Pass SwiftSelf in a callee saved register.191 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,192 193 // A SwiftError is returned in R8.194 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,195 196 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,197 CCIfType<[f32], CCBitConvertToType<i32>>,198 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_Custom_f16">>,199 200 CCDelegateTo<RetCC_ARM_AAPCS_Common>201]>;202 203//===----------------------------------------------------------------------===//204// ARM AAPCS-VFP (EABI) Calling Convention205// Also used for FastCC (when VFP2 or later is available)206//===----------------------------------------------------------------------===//207 208let Entry = 1 in209def CC_ARM_AAPCS_VFP : CallingConv<[210 // Handles byval parameters.211 CCIfByVal<CCPassByVal<4, 4>>,212 213 // Handle all vector types as either f64 or v2f64.214 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,215 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,216 217 // Pass SwiftSelf in a callee saved register.218 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,219 220 // A SwiftError is passed in R8.221 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,222 223 // HFAs are passed in a contiguous block of registers, or on the stack224 CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>,225 226 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,227 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,228 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,229 S9, S10, S11, S12, S13, S14, S15]>>,230 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_VFP_Custom_f16">>,231 CCDelegateTo<CC_ARM_AAPCS_Common>232]>;233 234let Entry = 1 in235def RetCC_ARM_AAPCS_VFP : CallingConv<[236 // Handle all vector types as either f64 or v2f64.237 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,238 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,239 240 // Pass SwiftSelf in a callee saved register.241 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,242 243 // A SwiftError is returned in R8.244 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,245 246 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,247 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,248 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,249 S9, S10, S11, S12, S13, S14, S15]>>,250 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_VFP_Custom_f16">>,251 CCDelegateTo<RetCC_ARM_AAPCS_Common>252]>;253 254 255// Windows Control Flow Guard checks take a single argument (the target function256// address) and have no return value.257let Entry = 1 in258def CC_ARM_Win32_CFGuard_Check : CallingConv<[259 CCIfType<[i32], CCAssignToReg<[R0]>>260]>;261 262 263 264//===----------------------------------------------------------------------===//265// Callee-saved register lists.266//===----------------------------------------------------------------------===//267 268def CSR_NoRegs : CalleeSavedRegs<(add)>;269def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>;270 271def CSR_FP_Interrupt_Regs : CalleeSavedRegs<(add FPSCR, FPEXC, (sequence "D%u", 15, 0))>;272def CSR_FP_NEON_Interrupt_Regs : CalleeSavedRegs<(add CSR_FP_Interrupt_Regs, 273 (sequence "D%u", 31, 16))>;274 275def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,276 (sequence "D%u", 15, 8))>;277 278def CSR_AAPCS_FP : CalleeSavedRegs<(add CSR_AAPCS, CSR_FP_Interrupt_Regs)>;279 280// The order of callee-saved registers needs to match the order we actually push281// them in FrameLowering, because this order is what's used by282// PrologEpilogInserter to allocate frame index slots. So when R7 is the frame283// pointer, we use this ATPCS alternative.284def CSR_ATPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,285 R11, R10, R9, R8,286 (sequence "D%u", 15, 8))>;287 288def CSR_Win_SplitFP : CalleeSavedRegs<(add R10, R9, R8, R7, R6, R5, R4,289 (sequence "D%u", 15, 8),290 LR, R11)>;291 292def CSR_ATPCS_SplitPush_FP : CalleeSavedRegs<(add CSR_ATPCS_SplitPush,293 CSR_FP_Interrupt_Regs)>;294 295// The Windows Control Flow Guard Check function preserves the same registers as296// AAPCS, and also preserves all floating point registers.297def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,298 R6, R5, R4, (sequence "D%u", 15, 0))>;299 300// R8 is used to pass swifterror, remove it from CSR.301def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>;302 303// R10 is used to pass swiftself, remove it from CSR.304def CSR_AAPCS_SwiftTail : CalleeSavedRegs<(sub CSR_AAPCS, R10)>;305 306 307// R8 is used to pass swifterror, remove it from CSR.308def CSR_ATPCS_SplitPush_SwiftError : CalleeSavedRegs<(sub CSR_ATPCS_SplitPush,309 R8)>;310 311// R10 is used to pass swifterror, remove it from CSR.312def CSR_ATPCS_SplitPush_SwiftTail : CalleeSavedRegs<(sub CSR_ATPCS_SplitPush,313 R10)>;314 315// Sometimes we need to split the push of the callee-saved GPRs into two316// regions, to ensure that the frame chain record is set up correctly. These317// list the callee-saved registers in the order they end up on the stack, which318// depends on whether the frame pointer is r7 or r11.319def CSR_AAPCS_SplitPush_R11 : CalleeSavedRegs<(add R10, R9, R8, R7, R6, R5, R4,320 LR, R11,321 (sequence "D%u", 15, 8))>;322def CSR_AAPCS_SplitPush_R7 : CalleeSavedRegs<(add LR, R11,323 R7, R6, R5, R4,324 R10, R9, R8,325 (sequence "D%u", 15, 8))>;326 327// Constructors and destructors return 'this' in the ARM C++ ABI; since 'this'328// and the pointer return value are both passed in R0 in these cases, this can329// be partially modelled by treating R0 as a callee-saved register330// Only the resulting RegMask is used; the SaveList is ignored331def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,332 R5, R4, (sequence "D%u", 15, 8),333 R0)>;334 335// iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.336// Also save R7-R4 first to match the stack frame fixed spill areas.337def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;338 339// R8 is used to pass swifterror, remove it from CSR.340def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>;341 342// R10 is used to pass swiftself, remove it from CSR.343def CSR_iOS_SwiftTail : CalleeSavedRegs<(sub CSR_iOS, R10)>;344 345def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,346 (sub CSR_AAPCS_ThisReturn, R9))>;347 348def CSR_iOS_TLSCall349 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),350 (sequence "D%u", 31, 0))>;351 352// C++ TLS access function saves all registers except SP. Try to match353// the order of CSRs in CSR_iOS.354def CSR_iOS_CXX_TLS : CalleeSavedRegs<(add CSR_iOS, (sequence "R%u", 12, 1),355 (sequence "D%u", 31, 0))>;356 357// CSRs that are handled by prologue, epilogue.358def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;359 360// CSRs that are handled explicitly via copies.361def CSR_iOS_CXX_TLS_ViaCopy : CalleeSavedRegs<(sub CSR_iOS_CXX_TLS,362 CSR_iOS_CXX_TLS_PE)>;363 364// The "interrupt" attribute is used to generate code that is acceptable in365// exception-handlers of various kinds. It makes us use a different return366// instruction (handled elsewhere) and affects which registers we must return to367// our "caller" in the same state as we receive them.368 369// For most interrupts, all registers except SP and LR are shared with370// user-space. We mark LR to be saved anyway, since this is what the ARM backend371// generally does rather than tracking its liveness as a normal register.372def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>;373 374def CSR_GenericInt_FP : CalleeSavedRegs<(add CSR_GenericInt, 375 CSR_FP_Interrupt_Regs)>;376 377def CSR_GenericInt_FP_NEON : CalleeSavedRegs<(add CSR_GenericInt_FP, 378 CSR_FP_NEON_Interrupt_Regs)>;379 380 381// The fast interrupt handlers have more private state and get their own copies382// of R8-R12, in addition to SP and LR. As before, mark LR for saving too.383 384// FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and385// current frame lowering expects to encounter it while processing callee-saved386// registers.387def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>;388 389def CSR_FIQ_FP : CalleeSavedRegs<(add CSR_FIQ, CSR_FP_Interrupt_Regs)>;390 391def CSR_FIQ_FP_NEON : CalleeSavedRegs<(add CSR_FIQ_FP, 392 CSR_FP_NEON_Interrupt_Regs)>;393 394 395