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1//===----------------------------------------------------------------------===//2// ARM Subtarget state.3//4 5// True if compiling for Thumb, false for ARM.6def ModeThumb : SubtargetFeature<"thumb-mode", "IsThumb",7 "true", "Thumb mode">;8 9// True if we're using software floating point features.10def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat",11 "true", "Use software floating "12 "point features.">;13 14//===----------------------------------------------------------------------===//15// ARM Subtarget features.16//17 18// This is currently only used by AArch64, but is required here because ARM and19// AArch64 share a tablegen backend for TargetParser.20class Extension<21 string TargetFeatureName, // String used for -target-feature.22 string Spelling, // The XYZ in HasXYZ and AEK_XYZ.23 string Desc, // Description.24 list<SubtargetFeature> Implies = [] // List of dependent features.25> : SubtargetFeature<TargetFeatureName, "Has" # Spelling, "true", Desc, Implies>26{27 string ArchExtKindSpelling = "AEK_" # Spelling; // ArchExtKind enum name.28}29 30// Floating Point, HW Division and Neon Support31 32// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only33// version).34def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true",35 "Enable FP registers">;36 37// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP1638// extension) and MVE (even in the integer-only version).39def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true",40 "Enable 16-bit FP registers",41 [FeatureFPRegs]>;42 43def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true",44 "Enable 64-bit FP registers",45 [FeatureFPRegs]>;46 47// True if the floating point unit supports double precision.48def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true",49 "Floating point unit supports "50 "double precision",51 [FeatureFPRegs64]>;52 53// True if subtarget has the full 32 double precision FP registers for VFPv3.54def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true",55 "Extend FP to 32 double registers">;56 57/// Versions of the VFP flags restricted to single precision, or to58/// 16 d-registers, or both.59multiclass VFPver<string name, string query, string description,60 list<SubtargetFeature> prev,61 list<SubtargetFeature> otherimplies,62 list<SubtargetFeature> vfp2prev = []> {63 def _D16_SP: SubtargetFeature<64 name#"d16sp", query#"D16SP", "true",65 description#" with only 16 d-registers and no double precision",66 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #67 !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #68 otherimplies>;69 def _SP: SubtargetFeature<70 name#"sp", query#"SP", "true",71 description#" with no double precision",72 !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) #73 otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;74 def _D16: SubtargetFeature<75 name#"d16", query#"D16", "true",76 description#" with only 16 d-registers",77 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) #78 vfp2prev #79 otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;80 def "": SubtargetFeature<81 name, query, "true", description,82 prev # otherimplies # [83 !cast<SubtargetFeature>(NAME # "_D16"),84 !cast<SubtargetFeature>(NAME # "_SP")]>;85}86 87def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",88 "Enable VFP2 instructions with "89 "no double precision",90 [FeatureFPRegs]>;91 92def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",93 "Enable VFP2 instructions",94 [FeatureFP64, FeatureVFP2_SP]>;95 96defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",97 [], [], [FeatureVFP2]>;98 99def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",100 "Enable NEON instructions",101 [FeatureVFP3]>;102 103// True if subtarget supports half-precision FP conversions.104def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",105 "Enable half-precision "106 "floating point">;107 108defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",109 [FeatureVFP3], [FeatureFP16]>;110 111defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",112 [FeatureVFP4], []>;113 114// True if subtarget supports half-precision FP operations.115def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",116 "Enable full half-precision "117 "floating point",118 [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>;119 120// True if subtarget supports half-precision FP fml operations.121def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",122 "Enable full half-precision "123 "floating point fml instructions",124 [FeatureFullFP16]>;125 126// True if subtarget supports [su]div in Thumb mode.127def FeatureHWDivThumb : SubtargetFeature<"hwdiv",128 "HasDivideInThumbMode", "true",129 "Enable divide instructions in Thumb">;130 131// True if subtarget supports [su]div in ARM mode.132def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",133 "HasDivideInARMMode", "true",134 "Enable divide instructions in ARM mode">;135 136// Atomic Support137 138// True if the subtarget supports DMB / DSB data barrier instructions.139def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",140 "Has data barrier (dmb/dsb) instructions">;141 142// True if the subtarget supports CLREX instructions.143def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",144 "Has v7 clrex instruction">;145 146// True if the subtarget supports DFB data barrier instruction.147def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",148 "Has full data barrier (dfb) instruction">;149 150// True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.151def FeatureAcquireRelease : SubtargetFeature<"acquire-release",152 "HasAcquireRelease", "true",153 "Has v8 acquire/release (lda/ldaex "154 " etc) instructions">;155 156 157// True if floating point compare + branch is slow.158def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "IsFPBrccSlow", "true",159 "FP compare + branch is slow">;160 161// True if the processor supports the Performance Monitor Extensions. These162// include a generic cycle-counter as well as more fine-grained (often163// implementation-specific) events.164def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",165 "Enable support for Performance "166 "Monitor extensions">;167 168 169// TrustZone Security Extensions170 171// True if processor supports TrustZone security extensions.172def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",173 "Enable support for TrustZone "174 "security extensions">;175 176// True if processor supports ARMv8-M Security Extensions.177def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",178 "Enable support for ARMv8-M "179 "Security Extensions">;180 181// True if processor supports SHA1 and SHA256.182def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true",183 "Enable SHA1 and SHA256 support", [FeatureNEON]>;184 185def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",186 "Enable AES support", [FeatureNEON]>;187 188// True if processor supports Cryptography extensions.189def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",190 "Enable support for "191 "Cryptography extensions",192 [FeatureNEON, FeatureSHA2, FeatureAES]>;193 194// True if processor supports CRC instructions.195def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",196 "Enable support for CRC instructions">;197 198// True if the ARMv8.2A dot product instructions are supported.199def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true",200 "Enable support for dot product instructions",201 [FeatureNEON]>;202 203// True if the processor supports RAS extensions.204// Not to be confused with FeatureHasRetAddrStack (return address stack).205def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",206 "Enable Reliability, Availability "207 "and Serviceability extensions">;208 209// Fast computation of non-negative address offsets.210// True if processor does positive address offset computation faster.211def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",212 "Enable fast computation of "213 "positive address offsets">;214 215// Fast execution of AES crypto operations.216// True if processor executes back to back AES instruction pairs faster.217def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",218 "CPU fuses AES crypto operations">;219 220// Fast execution of bottom and top halves of literal generation.221// True if processor executes back to back bottom and top halves of literal generation faster.222def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",223 "CPU fuses literal generation operations">;224 225// Choice of hardware register to use as the thread pointer, if any.226def FeatureReadTpTPIDRURW : SubtargetFeature<"read-tp-tpidrurw", "IsReadTPTPIDRURW", "true",227 "Reading thread pointer from TPIDRURW register">;228def FeatureReadTpTPIDRURO : SubtargetFeature<"read-tp-tpidruro", "IsReadTPTPIDRURO", "true",229 "Reading thread pointer from TPIDRURO register">;230def FeatureReadTpTPIDRPRW : SubtargetFeature<"read-tp-tpidrprw", "IsReadTPTPIDRPRW", "true",231 "Reading thread pointer from TPIDRPRW register">;232 233// Cyclone can zero VFP registers in 0 cycles.234// True if the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are235// particularly effective at zeroing a VFP register.236def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",237 "Has zero-cycle zeroing instructions">;238 239// Whether it is profitable to unpredicate certain instructions during if-conversion.240// True if if conversion may decide to leave some instructions unpredicated.241def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",242 "IsProfitableToUnpredicate", "true",243 "Is profitable to unpredicate">;244 245// Some targets (e.g. Swift) have microcoded VGETLNi32.246// True if VMOV will be favored over VGETLNi32.247def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",248 "HasSlowVGETLNi32", "true",249 "Has slow VGETLNi32 - prefer VMOV">;250 251// Some targets (e.g. Swift) have microcoded VDUP32.252// True if VMOV will be favored over VDUP.253def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",254 "true",255 "Has slow VDUP32 - prefer VMOV">;256 257// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON258// for scalar FP, as this allows more effective execution domain optimization.259// True if VMOVSR will be favored over VMOVDRR.260def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",261 "true", "Prefer VMOVSR">;262 263// Swift has ISHST barriers compatible with Atomic Release semantics but weaker264// than ISH.265// True if ISHST barriers will be used for Release semantics.266def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHSTBarriers",267 "true", "Prefer ISHST barriers">;268 269// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.270// True if the AGU and NEON/FPU units are multiplexed.271def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits",272 "true",273 "Has muxed AGU and NEON/FPU">;274 275// Whether VLDM/VSTM starting with odd register number need more microops276// than single VLDRS.277// True if a VLDM/VSTM starting with an odd register number is considered to278// take more microops than single VLDRS/VSTRS.279def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "HasSlowOddRegister",280 "true", "VLDM/VSTM starting "281 "with an odd register is slow">;282 283// Some targets have a renaming dependency when loading into D subregisters.284// True if loading into a D subregister will be penalized.285def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",286 "HasSlowLoadDSubregister", "true",287 "Loading into D subregs is slow">;288 289// True if use a wider stride when allocating VFP registers.290def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp",291 "UseWideStrideVFP", "true",292 "Use a wide stride when allocating VFP registers">;293 294// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.295// True if VMOVS will never be widened to VMOVD.296def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",297 "DontWidenVMOVS", "true",298 "Don't widen VMOVS to VMOVD">;299 300// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different301// VFP register widths.302// True if splat a register between VFP and NEON instructions.303def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",304 "UseSplatVFPToNeon", "true",305 "Splat register from VFP to NEON",306 [FeatureDontWidenVMOVS]>;307 308// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.309// True if run the MLx expansion pass.310def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx",311 "ExpandMLx", "true",312 "Expand VFP/NEON MLA/MLS instructions">;313 314// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.315// True if VFP/NEON VMLA/VMLS have special RAW hazards.316def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",317 "true", "Has VMLx hazards">;318 319// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from320// VFP to NEON, as an execution domain optimization.321// True if VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.322def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs",323 "UseNEONForFPMovs", "true",324 "Convert VMOVSR, VMOVRS, "325 "VMOVS to NEON">;326 327// Some processors benefit from using NEON instructions for scalar328// single-precision FP operations. This affects instruction selection and should329// only be enabled if the handling of denormals is not important.330// Use the method useNEONForSinglePrecisionFP() to determine if NEON should actually be used.331def FeatureNEONForFP : SubtargetFeature<"neonfp",332 "HasNEONForFP",333 "true",334 "Use NEON for single precision FP">;335 336// On some processors, VLDn instructions that access unaligned data take one337// extra cycle. Take that into account when computing operand latencies.338// True if VLDn instructions take an extra cycle for unaligned accesses.339def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAccessAlignment",340 "true",341 "Check for VLDn unaligned access">;342 343// Some processors have a nonpipelined VFP coprocessor.344// True if VFP instructions are not pipelined.345def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",346 "NonpipelinedVFP", "true",347 "VFP instructions are not pipelined">;348 349// Some processors have FP multiply-accumulate instructions that don't350// play nicely with other VFP / NEON instructions, and it's generally better351// to just not use them.352// If the VFP2 / NEON instructions are available, indicates353// whether the FP VML[AS] instructions are slow (if so, don't use them).354def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",355 "Disable VFP / NEON MAC instructions">;356 357// VFPv4 added VFMA instructions that can similarly be fast or slow.358// If the VFP4 / NEON instructions are available, indicates359// whether the FP VFM[AS] instructions are slow (if so, don't use them).360def FeatureHasSlowFPVFMx : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true",361 "Disable VFP / NEON FMA instructions">;362 363// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.364/// True if NEON has special multiplier accumulator365/// forwarding to allow mul + mla being issued back to back.366def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",367 "HasVMLxForwarding", "true",368 "Has multiplier accumulator forwarding">;369 370// Disable 32-bit to 16-bit narrowing for experimentation.371// True if codegen would prefer 32-bit Thumb instructions over 16-bit ones.372def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Prefers32BitThumb", "true",373 "Prefer 32-bit Thumb instrs">;374 375def FeaturePreferBranchAlign32 : SubtargetFeature<"loop-align", "PreferBranchLogAlignment","2",376 "Prefer 32-bit alignment for branch targets">;377 378def FeaturePreferBranchAlign64 : SubtargetFeature<"branch-align-64", "PreferBranchLogAlignment","3",379 "Prefer 64-bit alignment for branch targets">;380 381def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "4",382 "Model MVE instructions as a 1 beat per tick architecture">;383 384def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2",385 "Model MVE instructions as a 2 beats per tick architecture">;386 387def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "1",388 "Model MVE instructions as a 4 beats per tick architecture">;389 390/// Some instructions update CPSR partially, which can add false dependency for391/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is392/// mapped to a separate physical register. Avoid partial CPSR update for these393/// processors.394/// True if codegen would avoid using instructions395/// that partially update CPSR and add false dependency on the previous396/// CPSR setting instruction.397def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",398 "AvoidCPSRPartialUpdate", "true",399 "Avoid CPSR partial update for OOO execution">;400 401/// FeatureAvoidMULS - If true, codegen would avoid using the MULS instruction,402/// prefering the thumb2 MUL which doesn't set flags.403def FeatureAvoidMULS : SubtargetFeature<"avoid-muls",404 "AvoidMULS", "true",405 "Avoid MULS instructions for M class cores">;406 407 408/// Disable +1 predication cost for instructions updating CPSR.409/// Enabled for Cortex-A57.410/// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.411def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",412 "CheapPredicableCPSRDef",413 "true",414 "Disable +1 predication cost for instructions updating CPSR">;415 416// True if codegen should avoid using flag setting movs with shifter operand (i.e. asr, lsl, lsr).417def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",418 "AvoidMOVsShifterOperand", "true",419 "Avoid movs instructions with "420 "shifter operand">;421 422// Some processors perform return stack prediction. CodeGen should avoid issue423// "normal" call instructions to callees which do not return.424def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",425 "HasRetAddrStack", "true",426 "Has return address stack">;427 428// Some processors have no branch predictor, which changes the expected cost of429// taking a branch which affects the choice of whether to use predicated430// instructions.431// True if the subtarget has a branch predictor. Having432// a branch predictor or not changes the expected cost of taking a branch433// which affects the choice of whether to use predicated instructions.434def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",435 "HasBranchPredictor", "false",436 "Has no branch predictor">;437 438/// DSP extension.439/// True if the subtarget supports the DSP (saturating arith and such) instructions.440def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",441 "Supports DSP instructions in "442 "ARM and/or Thumb2">;443 444// True if the subtarget supports Multiprocessing extension (ARMv7 only).445def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",446 "Supports Multiprocessing extension">;447 448// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).449def FeatureVirtualization : SubtargetFeature<"virtualization",450 "HasVirtualization", "true",451 "Supports Virtualization extension",452 [FeatureHWDivThumb, FeatureHWDivARM]>;453 454// True if the subtarget disallows unaligned memory455// accesses for some types. For details, see456// ARMTargetLowering::allowsMisalignedMemoryAccesses().457def FeatureStrictAlign : SubtargetFeature<"strict-align",458 "StrictAlign", "true",459 "Disallow all unaligned memory "460 "access">;461 462// Generate calls via indirect call instructions.463def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",464 "Generate calls via indirect call "465 "instructions">;466 467// Generate code that does not contain data access to code sections.468def FeatureExecuteOnly : SubtargetFeature<"execute-only",469 "GenExecuteOnly", "true",470 "Enable the generation of "471 "execute only code.">;472 473// True if R9 is not available as a general purpose register.474def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",475 "Reserve R9, making it unavailable"476 " as GPR">;477 478// True if MOVT / MOVW pairs are not used for materialization of479// 32-bit imms (including global addresses).480def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",481 "Don't use movt/movw pairs for "482 "32-bit imms">;483 484/// Implicitly convert an instruction to a different one if its immediates485/// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.486def FeatureNoNegativeImmediates487 : SubtargetFeature<"no-neg-immediates",488 "NegativeImmediates", "false",489 "Convert immediates and instructions "490 "to their negated or complemented "491 "equivalent when the immediate does "492 "not fit in the encoding.">;493 494// Use the MachineScheduler for instruction scheduling for the subtarget.495def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",496 "Use the MachineScheduler">;497 498// Use the MachinePipeliner for instruction scheduling for the subtarget.499def FeatureUseMIPipeliner: SubtargetFeature<"use-mipipeliner", "UseMIPipeliner", "true",500 "Use the MachinePipeliner">;501 502// False if scheduling should happen again after register allocation.503def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",504 "DisablePostRAScheduler", "true",505 "Don't schedule again after register allocation">;506 507// Armv8.5-A extensions508 509// Has speculation barrier.510def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",511 "Enable v8.5a Speculation Barrier" >;512 513// Armv8.6-A extensions514 515// True if subtarget supports BFloat16 floating point operations.516def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", "true",517 "Enable support for BFloat16 instructions", [FeatureNEON]>;518 519// True if subtarget supports 8-bit integer matrix multiply.520def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",521 "true", "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>;522 523// Armv8.1-M extensions524 525// True if the processor supports the Low Overhead Branch extension.526def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true",527 "Enable Low Overhead Branch "528 "extensions">;529 530// Mitigate against the cve-2021-35465 security vulnurability.531def FeatureFixCMSE_CVE_2021_35465 : SubtargetFeature<"fix-cmse-cve-2021-35465",532 "FixCMSE_CVE_2021_35465", "true",533 "Mitigate against the cve-2021-35465 "534 "security vulnurability">;535 536def FeaturePACBTI : SubtargetFeature<"pacbti", "HasPACBTI", "true",537 "Enable Pointer Authentication and Branch "538 "Target Identification">;539 540/// Don't place a BTI instruction after return-twice constructs (setjmp).541def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",542 "NoBTIAtReturnTwice", "true",543 "Don't place a BTI instruction "544 "after a return-twice">;545 546// Armv8.9-A/Armv9.4-A 2022 Architecture Extensions547def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB", "true",548 "Enable Clear BHB instruction">;549 550 551def FeatureFixCortexA57AES1742098 : SubtargetFeature<"fix-cortex-a57-aes-1742098",552 "FixCortexA57AES1742098", "true",553 "Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES)">;554 555// If frame pointers are in use, they must follow the AAPCS definition, which556// always uses R11 as the frame pointer. If this is not set, we can use R7 as557// the frame pointer for Thumb1-only code, which is more efficient, but less558// compatible. Note that this feature does not control whether frame pointers559// are emitted, that is controlled by the "frame-pointer" function attribute.560def FeatureAAPCSFrameChain : SubtargetFeature<"aapcs-frame-chain",561 "CreateAAPCSFrameChain", "true",562 "Create an AAPCS compliant frame chain">;563 564// Assume that lock-free 32-bit atomics are available, even if the target565// and operating system combination would not usually provide them. The user566// is responsible for providing any necessary __sync implementations. Code567// built with this feature is not ABI-compatible with code built without this568// feature, if atomic variables are exposed across the ABI boundary.569def FeatureAtomics32 : SubtargetFeature<570 "atomics-32", "HasForced32BitAtomics", "true",571 "Assume that lock-free 32-bit atomics are available">;572 573//===----------------------------------------------------------------------===//574// ARM architecture class575//576 577// A-series ISA578def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",579 "Is application profile ('A' series)">;580 581// R-series ISA582def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",583 "Is realtime profile ('R' series)">;584 585// M-series ISA586def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",587 "Is microcontroller profile ('M' series)">;588 589// True if Thumb2 instructions are supported.590def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",591 "Enable Thumb2 instructions">;592 593// True if subtarget does not support ARM mode execution.594def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",595 "Does not support ARM mode execution">;596 597//===----------------------------------------------------------------------===//598// ARM ISAa.599//600// Specify whether target support specific ARM ISA variants.601 602def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",603 "Support ARM v4T instructions">;604 605def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",606 "Support ARM v5T instructions",607 [HasV4TOps]>;608 609def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",610 "Support ARM v5TE, v5TEj, and "611 "v5TExp instructions",612 [HasV5TOps]>;613 614def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",615 "Support ARM v6 instructions",616 [HasV5TEOps]>;617 618def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",619 "Support ARM v6M instructions",620 [HasV6Ops]>;621 622def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",623 "Support ARM v8M Baseline instructions",624 [HasV6MOps]>;625 626def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",627 "Support ARM v6k instructions",628 [HasV6Ops]>;629 630def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",631 "Support ARM v6t2 instructions",632 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;633 634def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",635 "Support ARM v7 instructions",636 [HasV6T2Ops, FeatureV7Clrex]>;637 638def HasV8MMainlineOps :639 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",640 "Support ARM v8M Mainline instructions",641 [HasV7Ops]>;642 643def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",644 "Support ARM v8 instructions",645 [HasV7Ops, FeaturePerfMon, FeatureAcquireRelease]>;646 647def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",648 "Support ARM v8.1a instructions",649 [HasV8Ops]>;650 651def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",652 "Support ARM v8.2a instructions",653 [HasV8_1aOps]>;654 655def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",656 "Support ARM v8.3a instructions",657 [HasV8_2aOps]>;658 659def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",660 "Support ARM v8.4a instructions",661 [HasV8_3aOps, FeatureDotProd]>;662 663def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",664 "Support ARM v8.5a instructions",665 [HasV8_4aOps, FeatureSB]>;666 667def HasV8_6aOps : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true",668 "Support ARM v8.6a instructions",669 [HasV8_5aOps, FeatureBF16,670 FeatureMatMulInt8]>;671 672def HasV8_7aOps : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true",673 "Support ARM v8.7a instructions",674 [HasV8_6aOps]>;675 676def HasV8_8aOps : SubtargetFeature<"v8.8a", "HasV8_8aOps", "true",677 "Support ARM v8.8a instructions",678 [HasV8_7aOps]>;679 680def HasV8_9aOps : SubtargetFeature<"v8.9a", "HasV8_9aOps", "true",681 "Support ARM v8.9a instructions",682 [HasV8_8aOps, FeatureCLRBHB]>;683 684def HasV9_0aOps : SubtargetFeature<"v9a", "HasV9_0aOps", "true",685 "Support ARM v9a instructions",686 [HasV8_5aOps]>;687 688def HasV9_1aOps : SubtargetFeature<"v9.1a", "HasV9_1aOps", "true",689 "Support ARM v9.1a instructions",690 [HasV8_6aOps, HasV9_0aOps]>;691 692def HasV9_2aOps : SubtargetFeature<"v9.2a", "HasV9_2aOps", "true",693 "Support ARM v9.2a instructions",694 [HasV8_7aOps, HasV9_1aOps]>;695 696def HasV9_3aOps : SubtargetFeature<"v9.3a", "HasV9_3aOps", "true",697 "Support ARM v9.3a instructions",698 [HasV8_8aOps, HasV9_2aOps]>;699 700def HasV9_4aOps : SubtargetFeature<"v9.4a", "HasV9_4aOps", "true",701 "Support ARM v9.4a instructions",702 [HasV8_9aOps, HasV9_3aOps]>;703 704// Armv9.5-A is a v9-only architecture. From v9.5-A onwards there's no mapping705// to an equivalent v8.x version.706def HasV9_5aOps : SubtargetFeature<"v9.5a", "HasV9_5aOps", "true",707 "Support ARM v9.5a instructions",708 [HasV9_4aOps]>;709 710// Armv9.6-A is a v9-only architecture.711def HasV9_6aOps : SubtargetFeature<"v9.6a", "HasV9_6aOps", "true",712 "Support ARM v9.6a instructions",713 [HasV9_5aOps]>;714 715// Armv9.7-A is a v9-only architecture.716def HasV9_7aOps : SubtargetFeature<"v9.7a", "HasV9_7aOps", "true",717 "Support ARM v9.7a instructions",718 [HasV9_6aOps]>;719 720def HasV8_1MMainlineOps : SubtargetFeature<721 "v8.1m.main", "HasV8_1MMainlineOps", "true",722 "Support ARM v8-1M Mainline instructions",723 [HasV8MMainlineOps]>;724def HasMVEIntegerOps : SubtargetFeature<725 "mve", "HasMVEIntegerOps", "true",726 "Support M-Class Vector Extension with integer ops",727 [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>;728def HasMVEFloatOps : SubtargetFeature<729 "mve.fp", "HasMVEFloatOps", "true",730 "Support M-Class Vector Extension with integer and floating ops",731 [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>;732 733def HasCDEOps : SubtargetFeature<"cde", "HasCDEOps", "true",734 "Support CDE instructions",735 [HasV8MMainlineOps]>;736 737foreach i = {0-7} in738 def FeatureCoprocCDE#i : SubtargetFeature<"cdecp"#i,739 "CoprocCDE["#i#"]", "true",740 "Coprocessor "#i#" ISA is CDEv1",741 [HasCDEOps]>;742 743//===----------------------------------------------------------------------===//744// Control codegen mitigation against Straight Line Speculation vulnerability.745//===----------------------------------------------------------------------===//746 747/// Harden against Straight Line Speculation for Returns and Indirect Branches.748def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",749 "HardenSlsRetBr", "true",750 "Harden against straight line speculation across RETurn and BranchRegister "751 "instructions">;752/// Harden against Straight Line Speculation for indirect calls.753def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",754 "HardenSlsBlr", "true",755 "Harden against straight line speculation across indirect calls">;756/// Generate thunk code for SLS mitigation in the normal text section.757def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",758 "HardenSlsNoComdat", "true",759 "Generate thunk code for SLS mitigation in the normal text section">;760 761//===----------------------------------------------------------------------===//762// Endianness of instruction encodings in memory.763//764// In the current Arm architecture, this is usually little-endian regardless of765// data endianness. But before Armv7 it was typical for instruction endianness766// to match data endianness, so that a big-endian system was consistently big-767// endian. And Armv7-R can be configured to use big-endian instructions.768//769// Additionally, even when targeting Armv7-A, big-endian instructions can be770// found in relocatable object files, because the Arm ABI specifies that the771// linker byte-reverses them depending on the target architecture.772//773// So we have a feature here to indicate that instructions are stored big-774// endian, which you can set when instantiating an MCDisassembler.775def ModeBigEndianInstructions : SubtargetFeature<"big-endian-instructions",776 "BigEndianInstructions", "true",777 "Expect instructions to be stored big-endian.">;778 779