3706 lines · cpp
1//===- ARMFrameLowering.cpp - ARM Frame Information -----------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the ARM implementation of TargetFrameLowering class.10//11//===----------------------------------------------------------------------===//12//13// This file contains the ARM implementation of TargetFrameLowering class.14//15// On ARM, stack frames are structured as follows:16//17// The stack grows downward.18//19// All of the individual frame areas on the frame below are optional, i.e. it's20// possible to create a function so that the particular area isn't present21// in the frame.22//23// At function entry, the "frame" looks as follows:24//25// | | Higher address26// |-----------------------------------|27// | |28// | arguments passed on the stack |29// | |30// |-----------------------------------| <- sp31// | | Lower address32//33//34// After the prologue has run, the frame has the following general structure.35// Technically the last frame area (VLAs) doesn't get created until in the36// main function body, after the prologue is run. However, it's depicted here37// for completeness.38//39// | | Higher address40// |-----------------------------------|41// | |42// | arguments passed on the stack |43// | |44// |-----------------------------------| <- (sp at function entry)45// | |46// | varargs from registers |47// | |48// |-----------------------------------|49// | |50// | prev_lr |51// | prev_fp |52// | (a.k.a. "frame record") |53// | |54// |- - - - - - - - - - - - - - - - - -| <- fp (r7 or r11)55// | |56// | callee-saved gpr registers |57// | |58// |-----------------------------------|59// | |60// | callee-saved fp/simd regs |61// | |62// |-----------------------------------|63// |.empty.space.to.make.part.below....|64// |.aligned.in.case.it.needs.more.than| (size of this area is unknown at65// |.the.standard.8-byte.alignment.....| compile time; if present)66// |-----------------------------------|67// | |68// | local variables of fixed size |69// | including spill slots |70// |-----------------------------------| <- base pointer (not defined by ABI,71// |.variable-sized.local.variables....| LLVM chooses r6)72// |.(VLAs)............................| (size of this area is unknown at73// |...................................| compile time)74// |-----------------------------------| <- sp75// | | Lower address76//77//78// To access the data in a frame, at-compile time, a constant offset must be79// computable from one of the pointers (fp, bp, sp) to access it. The size80// of the areas with a dotted background cannot be computed at compile-time81// if they are present, making it required to have all three of fp, bp and82// sp to be set up to be able to access all contents in the frame areas,83// assuming all of the frame areas are non-empty.84//85// For most functions, some of the frame areas are empty. For those functions,86// it may not be necessary to set up fp or bp:87// * A base pointer is definitely needed when there are both VLAs and local88// variables with more-than-default alignment requirements.89// * A frame pointer is definitely needed when there are local variables with90// more-than-default alignment requirements.91//92// In some cases when a base pointer is not strictly needed, it is generated93// anyway when offsets from the frame pointer to access local variables become94// so large that the offset can't be encoded in the immediate fields of loads95// or stores.96//97// The frame pointer might be chosen to be r7 or r11, depending on the target98// architecture and operating system. See ARMSubtarget::getFramePointerReg for99// details.100//101// Outgoing function arguments must be at the bottom of the stack frame when102// calling another function. If we do not have variable-sized stack objects, we103// can allocate a "reserved call frame" area at the bottom of the local104// variable area, large enough for all outgoing calls. If we do have VLAs, then105// the stack pointer must be decremented and incremented around each call to106// make space for the arguments below the VLAs.107//108//===----------------------------------------------------------------------===//109 110#include "ARMFrameLowering.h"111#include "ARMBaseInstrInfo.h"112#include "ARMBaseRegisterInfo.h"113#include "ARMConstantPoolValue.h"114#include "ARMMachineFunctionInfo.h"115#include "ARMSubtarget.h"116#include "MCTargetDesc/ARMAddressingModes.h"117#include "MCTargetDesc/ARMBaseInfo.h"118#include "Utils/ARMBaseInfo.h"119#include "llvm/ADT/BitVector.h"120#include "llvm/ADT/STLExtras.h"121#include "llvm/ADT/SmallPtrSet.h"122#include "llvm/ADT/SmallVector.h"123#include "llvm/CodeGen/CFIInstBuilder.h"124#include "llvm/CodeGen/MachineBasicBlock.h"125#include "llvm/CodeGen/MachineConstantPool.h"126#include "llvm/CodeGen/MachineFrameInfo.h"127#include "llvm/CodeGen/MachineFunction.h"128#include "llvm/CodeGen/MachineInstr.h"129#include "llvm/CodeGen/MachineInstrBuilder.h"130#include "llvm/CodeGen/MachineJumpTableInfo.h"131#include "llvm/CodeGen/MachineModuleInfo.h"132#include "llvm/CodeGen/MachineOperand.h"133#include "llvm/CodeGen/MachineRegisterInfo.h"134#include "llvm/CodeGen/RegisterScavenging.h"135#include "llvm/CodeGen/TargetInstrInfo.h"136#include "llvm/CodeGen/TargetRegisterInfo.h"137#include "llvm/CodeGen/TargetSubtargetInfo.h"138#include "llvm/IR/Attributes.h"139#include "llvm/IR/CallingConv.h"140#include "llvm/IR/DebugLoc.h"141#include "llvm/IR/Function.h"142#include "llvm/MC/MCAsmInfo.h"143#include "llvm/MC/MCInstrDesc.h"144#include "llvm/Support/CodeGen.h"145#include "llvm/Support/CommandLine.h"146#include "llvm/Support/Compiler.h"147#include "llvm/Support/Debug.h"148#include "llvm/Support/ErrorHandling.h"149#include "llvm/Support/raw_ostream.h"150#include "llvm/Target/TargetMachine.h"151#include "llvm/Target/TargetOptions.h"152#include <algorithm>153#include <cassert>154#include <cstddef>155#include <cstdint>156#include <iterator>157#include <utility>158#include <vector>159 160#define DEBUG_TYPE "arm-frame-lowering"161 162using namespace llvm;163 164static cl::opt<bool>165SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),166 cl::desc("Align ARM NEON spills in prolog and epilog"));167 168static MachineBasicBlock::iterator169skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,170 unsigned NumAlignedDPRCS2Regs);171 172enum class SpillArea {173 GPRCS1,174 GPRCS2,175 FPStatus,176 DPRCS1,177 DPRCS2,178 GPRCS3,179 FPCXT,180};181 182/// Get the spill area that Reg should be saved into in the prologue.183SpillArea getSpillArea(Register Reg,184 ARMSubtarget::PushPopSplitVariation Variation,185 unsigned NumAlignedDPRCS2Regs,186 const ARMBaseRegisterInfo *RegInfo) {187 // NoSplit:188 // push {r0-r12, lr} GPRCS1189 // vpush {r8-d15} DPRCS1190 //191 // SplitR7:192 // push {r0-r7, lr} GPRCS1193 // push {r8-r12} GPRCS2194 // vpush {r8-d15} DPRCS1195 //196 // SplitR11WindowsSEH:197 // push {r0-r10, r12} GPRCS1198 // vpush {r8-d15} DPRCS1199 // push {r11, lr} GPRCS3200 //201 // SplitR11AAPCSSignRA:202 // push {r0-r10, r12} GPRSC1203 // push {r11, lr} GPRCS2204 // vpush {r8-d15} DPRCS1205 206 // If FPCXTNS is spilled (for CMSE secure entryfunctions), it is always at207 // the top of the stack frame.208 // The DPRCS2 region is used for ABIs which only guarantee 4-byte alignment209 // of SP. If used, it will be below the other save areas, after the stack has210 // been re-aligned.211 212 switch (Reg) {213 default:214 dbgs() << "Don't know where to spill " << printReg(Reg, RegInfo) << "\n";215 llvm_unreachable("Don't know where to spill this register");216 break;217 218 case ARM::FPCXTNS:219 return SpillArea::FPCXT;220 221 case ARM::FPSCR:222 case ARM::FPEXC:223 return SpillArea::FPStatus;224 225 case ARM::R0:226 case ARM::R1:227 case ARM::R2:228 case ARM::R3:229 case ARM::R4:230 case ARM::R5:231 case ARM::R6:232 case ARM::R7:233 return SpillArea::GPRCS1;234 235 case ARM::R8:236 case ARM::R9:237 case ARM::R10:238 if (Variation == ARMSubtarget::SplitR7)239 return SpillArea::GPRCS2;240 else241 return SpillArea::GPRCS1;242 243 case ARM::R11:244 if (Variation == ARMSubtarget::SplitR7 ||245 Variation == ARMSubtarget::SplitR11AAPCSSignRA)246 return SpillArea::GPRCS2;247 if (Variation == ARMSubtarget::SplitR11WindowsSEH)248 return SpillArea::GPRCS3;249 250 return SpillArea::GPRCS1;251 252 case ARM::R12:253 if (Variation == ARMSubtarget::SplitR7)254 return SpillArea::GPRCS2;255 else256 return SpillArea::GPRCS1;257 258 case ARM::LR:259 if (Variation == ARMSubtarget::SplitR11AAPCSSignRA)260 return SpillArea::GPRCS2;261 if (Variation == ARMSubtarget::SplitR11WindowsSEH)262 return SpillArea::GPRCS3;263 264 return SpillArea::GPRCS1;265 266 case ARM::D0:267 case ARM::D1:268 case ARM::D2:269 case ARM::D3:270 case ARM::D4:271 case ARM::D5:272 case ARM::D6:273 case ARM::D7:274 return SpillArea::DPRCS1;275 276 case ARM::D8:277 case ARM::D9:278 case ARM::D10:279 case ARM::D11:280 case ARM::D12:281 case ARM::D13:282 case ARM::D14:283 case ARM::D15:284 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)285 return SpillArea::DPRCS2;286 else287 return SpillArea::DPRCS1;288 289 case ARM::D16:290 case ARM::D17:291 case ARM::D18:292 case ARM::D19:293 case ARM::D20:294 case ARM::D21:295 case ARM::D22:296 case ARM::D23:297 case ARM::D24:298 case ARM::D25:299 case ARM::D26:300 case ARM::D27:301 case ARM::D28:302 case ARM::D29:303 case ARM::D30:304 case ARM::D31:305 return SpillArea::DPRCS1;306 }307}308 309ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)310 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, Align(4)),311 STI(sti) {}312 313bool ARMFrameLowering::keepFramePointer(const MachineFunction &MF) const {314 // iOS always has a FP for backtracking, force other targets to keep their FP315 // when doing FastISel. The emitted code is currently superior, and in cases316 // like test-suite's lencod FastISel isn't quite correct when FP is eliminated.317 return MF.getSubtarget<ARMSubtarget>().useFastISel();318}319 320/// Returns true if the target can safely skip saving callee-saved registers321/// for noreturn nounwind functions.322bool ARMFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const {323 assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&324 MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&325 !MF.getFunction().hasFnAttribute(Attribute::UWTable));326 327 // Frame pointer and link register are not treated as normal CSR, thus we328 // can always skip CSR saves for nonreturning functions.329 return true;330}331 332/// hasFPImpl - Return true if the specified function should have a dedicated333/// frame pointer register. This is true if the function has variable sized334/// allocas or if frame pointer elimination is disabled.335bool ARMFrameLowering::hasFPImpl(const MachineFunction &MF) const {336 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();337 const MachineFrameInfo &MFI = MF.getFrameInfo();338 339 // Check to see if the target want to forcibly keep frame pointer.340 if (keepFramePointer(MF))341 return true;342 343 // ABI-required frame pointer.344 if (MF.getTarget().Options.DisableFramePointerElim(MF))345 return true;346 347 // Frame pointer required for use within this function.348 return (RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||349 MFI.isFrameAddressTaken());350}351 352/// isFPReserved - Return true if the frame pointer register should be353/// considered a reserved register on the scope of the specified function.354bool ARMFrameLowering::isFPReserved(const MachineFunction &MF) const {355 return hasFP(MF) || MF.getTarget().Options.FramePointerIsReserved(MF);356}357 358/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is359/// not required, we reserve argument space for call sites in the function360/// immediately on entry to the current function. This eliminates the need for361/// add/sub sp brackets around call sites. Returns true if the call frame is362/// included as part of the stack frame.363bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {364 const MachineFrameInfo &MFI = MF.getFrameInfo();365 unsigned CFSize = MFI.getMaxCallFrameSize();366 // It's not always a good idea to include the call frame as part of the367 // stack frame. ARM (especially Thumb) has small immediate offset to368 // address the stack frame. So a large call frame can cause poor codegen369 // and may even makes it impossible to scavenge a register.370 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12371 return false;372 373 return !MFI.hasVarSizedObjects();374}375 376/// canSimplifyCallFramePseudos - If there is a reserved call frame, the377/// call frame pseudos can be simplified. Unlike most targets, having a FP378/// is not sufficient here since we still may reference some objects via SP379/// even when FP is available in Thumb2 mode.380bool381ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {382 return hasReservedCallFrame(MF) || MF.getFrameInfo().hasVarSizedObjects();383}384 385// Returns how much of the incoming argument stack area we should clean up in an386// epilogue. For the C calling convention this will be 0, for guaranteed tail387// call conventions it can be positive (a normal return or a tail call to a388// function that uses less stack space for arguments) or negative (for a tail389// call to a function that needs more stack space than us for arguments).390static int getArgumentStackToRestore(MachineFunction &MF,391 MachineBasicBlock &MBB) {392 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();393 bool IsTailCallReturn = false;394 if (MBB.end() != MBBI) {395 unsigned RetOpcode = MBBI->getOpcode();396 IsTailCallReturn = RetOpcode == ARM::TCRETURNdi ||397 RetOpcode == ARM::TCRETURNri ||398 RetOpcode == ARM::TCRETURNrinotr12;399 }400 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();401 402 int ArgumentPopSize = 0;403 if (IsTailCallReturn) {404 MachineOperand &StackAdjust = MBBI->getOperand(1);405 406 // For a tail-call in a callee-pops-arguments environment, some or all of407 // the stack may actually be in use for the call's arguments, this is408 // calculated during LowerCall and consumed here...409 ArgumentPopSize = StackAdjust.getImm();410 } else {411 // ... otherwise the amount to pop is *all* of the argument space,412 // conveniently stored in the MachineFunctionInfo by413 // LowerFormalArguments. This will, of course, be zero for the C calling414 // convention.415 ArgumentPopSize = AFI->getArgumentStackToRestore();416 }417 418 return ArgumentPopSize;419}420 421static bool needsWinCFI(const MachineFunction &MF) {422 const Function &F = MF.getFunction();423 return MF.getTarget().getMCAsmInfo()->usesWindowsCFI() &&424 F.needsUnwindTableEntry();425}426 427// Given a load or a store instruction, generate an appropriate unwinding SEH428// code on Windows.429static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,430 const TargetInstrInfo &TII,431 unsigned Flags) {432 unsigned Opc = MBBI->getOpcode();433 MachineBasicBlock *MBB = MBBI->getParent();434 MachineFunction &MF = *MBB->getParent();435 DebugLoc DL = MBBI->getDebugLoc();436 MachineInstrBuilder MIB;437 const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();438 const ARMBaseRegisterInfo *RegInfo = Subtarget.getRegisterInfo();439 440 Flags |= MachineInstr::NoMerge;441 442 switch (Opc) {443 default:444 report_fatal_error("No SEH Opcode for instruction " + TII.getName(Opc));445 break;446 case ARM::t2ADDri: // add.w r11, sp, #xx447 case ARM::t2ADDri12: // add.w r11, sp, #xx448 case ARM::t2MOVTi16: // movt r4, #xx449 case ARM::tBL: // bl __chkstk450 // These are harmless if used for just setting up a frame pointer,451 // but that frame pointer can't be relied upon for unwinding, unless452 // set up with SEH_SaveSP.453 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))454 .addImm(/*Wide=*/1)455 .setMIFlags(Flags);456 break;457 458 case ARM::t2MOVi16: { // mov(w) r4, #xx459 bool Wide = MBBI->getOperand(1).getImm() >= 256;460 if (!Wide) {461 MachineInstrBuilder NewInstr =462 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags());463 NewInstr.add(MBBI->getOperand(0));464 NewInstr.add(t1CondCodeOp(/*isDead=*/true));465 for (MachineOperand &MO : llvm::drop_begin(MBBI->operands()))466 NewInstr.add(MO);467 MachineBasicBlock::iterator NewMBBI = MBB->insertAfter(MBBI, NewInstr);468 MBB->erase(MBBI);469 MBBI = NewMBBI;470 }471 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags);472 break;473 }474 475 case ARM::tBLXr: // blx r12 (__chkstk)476 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))477 .addImm(/*Wide=*/0)478 .setMIFlags(Flags);479 break;480 481 case ARM::t2MOVi32imm: // movw+movt482 // This pseudo instruction expands into two mov instructions. If the483 // second operand is a symbol reference, this will stay as two wide484 // instructions, movw+movt. If they're immediates, the first one can485 // end up as a narrow mov though.486 // As two SEH instructions are appended here, they won't get interleaved487 // between the two final movw/movt instructions, but it doesn't make any488 // practical difference.489 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))490 .addImm(/*Wide=*/1)491 .setMIFlags(Flags);492 MBB->insertAfter(MBBI, MIB);493 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))494 .addImm(/*Wide=*/1)495 .setMIFlags(Flags);496 break;497 498 case ARM::t2STR_PRE:499 if (MBBI->getOperand(0).getReg() == ARM::SP &&500 MBBI->getOperand(2).getReg() == ARM::SP &&501 MBBI->getOperand(3).getImm() == -4) {502 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());503 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))504 .addImm(1ULL << Reg)505 .addImm(/*Wide=*/1)506 .setMIFlags(Flags);507 } else {508 report_fatal_error("No matching SEH Opcode for t2STR_PRE");509 }510 break;511 512 case ARM::t2LDR_POST:513 if (MBBI->getOperand(1).getReg() == ARM::SP &&514 MBBI->getOperand(2).getReg() == ARM::SP &&515 MBBI->getOperand(3).getImm() == 4) {516 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());517 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))518 .addImm(1ULL << Reg)519 .addImm(/*Wide=*/1)520 .setMIFlags(Flags);521 } else {522 report_fatal_error("No matching SEH Opcode for t2LDR_POST");523 }524 break;525 526 case ARM::t2LDMIA_RET:527 case ARM::t2LDMIA_UPD:528 case ARM::t2STMDB_UPD: {529 unsigned Mask = 0;530 bool Wide = false;531 for (unsigned i = 4, NumOps = MBBI->getNumOperands(); i != NumOps; ++i) {532 const MachineOperand &MO = MBBI->getOperand(i);533 if (!MO.isReg() || MO.isImplicit())534 continue;535 unsigned Reg = RegInfo->getSEHRegNum(MO.getReg());536 if (Reg == 15)537 Reg = 14;538 if (Reg >= 8 && Reg <= 13)539 Wide = true;540 else if (Opc == ARM::t2LDMIA_UPD && Reg == 14)541 Wide = true;542 Mask |= 1 << Reg;543 }544 if (!Wide) {545 unsigned NewOpc;546 switch (Opc) {547 case ARM::t2LDMIA_RET:548 NewOpc = ARM::tPOP_RET;549 break;550 case ARM::t2LDMIA_UPD:551 NewOpc = ARM::tPOP;552 break;553 case ARM::t2STMDB_UPD:554 NewOpc = ARM::tPUSH;555 break;556 default:557 llvm_unreachable("");558 }559 MachineInstrBuilder NewInstr =560 BuildMI(MF, DL, TII.get(NewOpc)).setMIFlags(MBBI->getFlags());561 for (unsigned i = 2, NumOps = MBBI->getNumOperands(); i != NumOps; ++i)562 NewInstr.add(MBBI->getOperand(i));563 MachineBasicBlock::iterator NewMBBI = MBB->insertAfter(MBBI, NewInstr);564 MBB->erase(MBBI);565 MBBI = NewMBBI;566 }567 unsigned SEHOpc =568 (Opc == ARM::t2LDMIA_RET) ? ARM::SEH_SaveRegs_Ret : ARM::SEH_SaveRegs;569 MIB = BuildMI(MF, DL, TII.get(SEHOpc))570 .addImm(Mask)571 .addImm(Wide ? 1 : 0)572 .setMIFlags(Flags);573 break;574 }575 case ARM::VSTMDDB_UPD:576 case ARM::VLDMDIA_UPD: {577 int First = -1, Last = 0;578 for (const MachineOperand &MO : llvm::drop_begin(MBBI->operands(), 4)) {579 unsigned Reg = RegInfo->getSEHRegNum(MO.getReg());580 if (First == -1)581 First = Reg;582 Last = Reg;583 }584 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveFRegs))585 .addImm(First)586 .addImm(Last)587 .setMIFlags(Flags);588 break;589 }590 case ARM::tSUBspi:591 case ARM::tADDspi:592 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc))593 .addImm(MBBI->getOperand(2).getImm() * 4)594 .addImm(/*Wide=*/0)595 .setMIFlags(Flags);596 break;597 case ARM::t2SUBspImm:598 case ARM::t2SUBspImm12:599 case ARM::t2ADDspImm:600 case ARM::t2ADDspImm12:601 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc))602 .addImm(MBBI->getOperand(2).getImm())603 .addImm(/*Wide=*/1)604 .setMIFlags(Flags);605 break;606 607 case ARM::tMOVr:608 if (MBBI->getOperand(1).getReg() == ARM::SP &&609 (Flags & MachineInstr::FrameSetup)) {610 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());611 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP))612 .addImm(Reg)613 .setMIFlags(Flags);614 } else if (MBBI->getOperand(0).getReg() == ARM::SP &&615 (Flags & MachineInstr::FrameDestroy)) {616 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());617 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP))618 .addImm(Reg)619 .setMIFlags(Flags);620 } else {621 report_fatal_error("No SEH Opcode for MOV");622 }623 break;624 625 case ARM::tBX_RET:626 case ARM::TCRETURNri:627 case ARM::TCRETURNrinotr12:628 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret))629 .addImm(/*Wide=*/0)630 .setMIFlags(Flags);631 break;632 633 case ARM::TCRETURNdi:634 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret))635 .addImm(/*Wide=*/1)636 .setMIFlags(Flags);637 break;638 }639 return MBB->insertAfter(MBBI, MIB);640}641 642static MachineBasicBlock::iterator643initMBBRange(MachineBasicBlock &MBB, const MachineBasicBlock::iterator &MBBI) {644 if (MBBI == MBB.begin())645 return MachineBasicBlock::iterator();646 return std::prev(MBBI);647}648 649static void insertSEHRange(MachineBasicBlock &MBB,650 MachineBasicBlock::iterator Start,651 const MachineBasicBlock::iterator &End,652 const ARMBaseInstrInfo &TII, unsigned MIFlags) {653 if (Start.isValid())654 Start = std::next(Start);655 else656 Start = MBB.begin();657 658 for (auto MI = Start; MI != End;) {659 auto Next = std::next(MI);660 // Check if this instruction already has got a SEH opcode added. In that661 // case, don't do this generic mapping.662 if (Next != End && isSEHInstruction(*Next)) {663 MI = std::next(Next);664 while (MI != End && isSEHInstruction(*MI))665 ++MI;666 continue;667 }668 insertSEH(MI, TII, MIFlags);669 MI = Next;670 }671}672 673static void emitRegPlusImmediate(674 bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,675 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,676 unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags,677 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {678 if (isARM)679 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,680 Pred, PredReg, TII, MIFlags);681 else682 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,683 Pred, PredReg, TII, MIFlags);684}685 686static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,687 MachineBasicBlock::iterator &MBBI, const DebugLoc &dl,688 const ARMBaseInstrInfo &TII, int NumBytes,689 unsigned MIFlags = MachineInstr::NoFlags,690 ARMCC::CondCodes Pred = ARMCC::AL,691 unsigned PredReg = 0) {692 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,693 MIFlags, Pred, PredReg);694}695 696static int sizeOfSPAdjustment(const MachineInstr &MI) {697 int RegSize;698 switch (MI.getOpcode()) {699 case ARM::VSTMDDB_UPD:700 RegSize = 8;701 break;702 case ARM::STMDB_UPD:703 case ARM::t2STMDB_UPD:704 RegSize = 4;705 break;706 case ARM::t2STR_PRE:707 case ARM::STR_PRE_IMM:708 return 4;709 default:710 llvm_unreachable("Unknown push or pop like instruction");711 }712 713 int count = 0;714 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+715 // pred) so the list starts at 4.716 for (int i = MI.getNumOperands() - 1; i >= 4; --i)717 count += RegSize;718 return count;719}720 721static bool WindowsRequiresStackProbe(const MachineFunction &MF,722 size_t StackSizeInBytes) {723 const MachineFrameInfo &MFI = MF.getFrameInfo();724 const Function &F = MF.getFunction();725 unsigned StackProbeSize = (MFI.getStackProtectorIndex() > 0) ? 4080 : 4096;726 727 StackProbeSize =728 F.getFnAttributeAsParsedInteger("stack-probe-size", StackProbeSize);729 return (StackSizeInBytes >= StackProbeSize) &&730 !F.hasFnAttribute("no-stack-arg-probe");731}732 733namespace {734 735struct StackAdjustingInsts {736 struct InstInfo {737 MachineBasicBlock::iterator I;738 unsigned SPAdjust;739 bool BeforeFPSet;740 741#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)742 void dump() {743 dbgs() << " " << (BeforeFPSet ? "before-fp " : " ")744 << "sp-adjust=" << SPAdjust;745 I->dump();746 }747#endif748 };749 750 SmallVector<InstInfo, 4> Insts;751 752 void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust,753 bool BeforeFPSet = false) {754 InstInfo Info = {I, SPAdjust, BeforeFPSet};755 Insts.push_back(Info);756 }757 758 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {759 auto Info =760 llvm::find_if(Insts, [&](InstInfo &Info) { return Info.I == I; });761 assert(Info != Insts.end() && "invalid sp adjusting instruction");762 Info->SPAdjust += ExtraBytes;763 }764 765 void emitDefCFAOffsets(MachineBasicBlock &MBB, bool HasFP) {766 CFIInstBuilder CFIBuilder(MBB, MBB.end(), MachineInstr::FrameSetup);767 unsigned CFAOffset = 0;768 for (auto &Info : Insts) {769 if (HasFP && !Info.BeforeFPSet)770 return;771 772 CFAOffset += Info.SPAdjust;773 CFIBuilder.setInsertPoint(std::next(Info.I));774 CFIBuilder.buildDefCFAOffset(CFAOffset);775 }776 }777 778#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)779 void dump() {780 dbgs() << "StackAdjustingInsts:\n";781 for (auto &Info : Insts)782 Info.dump();783 }784#endif785};786 787} // end anonymous namespace788 789/// Emit an instruction sequence that will align the address in790/// register Reg by zero-ing out the lower bits. For versions of the791/// architecture that support Neon, this must be done in a single792/// instruction, since skipAlignedDPRCS2Spills assumes it is done in a793/// single instruction. That function only gets called when optimizing794/// spilling of D registers on a core with the Neon instruction set795/// present.796static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,797 const TargetInstrInfo &TII,798 MachineBasicBlock &MBB,799 MachineBasicBlock::iterator MBBI,800 const DebugLoc &DL, const unsigned Reg,801 const Align Alignment,802 const bool MustBeSingleInstruction) {803 const ARMSubtarget &AST = MF.getSubtarget<ARMSubtarget>();804 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();805 const unsigned AlignMask = Alignment.value() - 1U;806 const unsigned NrBitsToZero = Log2(Alignment);807 assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");808 if (!AFI->isThumbFunction()) {809 // if the BFC instruction is available, use that to zero the lower810 // bits:811 // bfc Reg, #0, log2(Alignment)812 // otherwise use BIC, if the mask to zero the required number of bits813 // can be encoded in the bic immediate field814 // bic Reg, Reg, Alignment-1815 // otherwise, emit816 // lsr Reg, Reg, log2(Alignment)817 // lsl Reg, Reg, log2(Alignment)818 if (CanUseBFC) {819 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)820 .addReg(Reg, RegState::Kill)821 .addImm(~AlignMask)822 .add(predOps(ARMCC::AL));823 } else if (AlignMask <= 255) {824 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)825 .addReg(Reg, RegState::Kill)826 .addImm(AlignMask)827 .add(predOps(ARMCC::AL))828 .add(condCodeOp());829 } else {830 assert(!MustBeSingleInstruction &&831 "Shouldn't call emitAligningInstructions demanding a single "832 "instruction to be emitted for large stack alignment for a target "833 "without BFC.");834 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)835 .addReg(Reg, RegState::Kill)836 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))837 .add(predOps(ARMCC::AL))838 .add(condCodeOp());839 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)840 .addReg(Reg, RegState::Kill)841 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))842 .add(predOps(ARMCC::AL))843 .add(condCodeOp());844 }845 } else {846 // Since this is only reached for Thumb-2 targets, the BFC instruction847 // should always be available.848 assert(CanUseBFC);849 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)850 .addReg(Reg, RegState::Kill)851 .addImm(~AlignMask)852 .add(predOps(ARMCC::AL));853 }854}855 856/// We need the offset of the frame pointer relative to other MachineFrameInfo857/// offsets which are encoded relative to SP at function begin.858/// See also emitPrologue() for how the FP is set up.859/// Unfortunately we cannot determine this value in determineCalleeSaves() yet860/// as assignCalleeSavedSpillSlots() hasn't run at this point. Instead we use861/// this to produce a conservative estimate that we check in an assert() later.862static int getMaxFPOffset(const ARMSubtarget &STI, const ARMFunctionInfo &AFI,863 const MachineFunction &MF) {864 ARMSubtarget::PushPopSplitVariation PushPopSplit =865 STI.getPushPopSplitVariation(MF);866 // For Thumb1, push.w isn't available, so the first push will always push867 // r7 and lr onto the stack first.868 if (AFI.isThumb1OnlyFunction())869 return -AFI.getArgRegsSaveSize() - (2 * 4);870 // This is a conservative estimation: Assume the frame pointer being r7 and871 // pc("r15") up to r8 getting spilled before (= 8 registers).872 int MaxRegBytes = 8 * 4;873 if (PushPopSplit == ARMSubtarget::SplitR11AAPCSSignRA)874 // Here, r11 can be stored below all of r4-r15.875 MaxRegBytes = 11 * 4;876 if (PushPopSplit == ARMSubtarget::SplitR11WindowsSEH) {877 // Here, r11 can be stored below all of r4-r15 plus d8-d15.878 MaxRegBytes = 11 * 4 + 8 * 8;879 }880 int FPCXTSaveSize =881 (STI.hasV8_1MMainlineOps() && AFI.isCmseNSEntryFunction()) ? 4 : 0;882 return -FPCXTSaveSize - AFI.getArgRegsSaveSize() - MaxRegBytes;883}884 885void ARMFrameLowering::emitPrologue(MachineFunction &MF,886 MachineBasicBlock &MBB) const {887 MachineBasicBlock::iterator MBBI = MBB.begin();888 MachineFrameInfo &MFI = MF.getFrameInfo();889 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();890 const TargetMachine &TM = MF.getTarget();891 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();892 const ARMBaseInstrInfo &TII = *STI.getInstrInfo();893 assert(!AFI->isThumb1OnlyFunction() &&894 "This emitPrologue does not support Thumb1!");895 bool isARM = !AFI->isThumbFunction();896 Align Alignment = STI.getFrameLowering()->getStackAlign();897 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();898 unsigned NumBytes = MFI.getStackSize();899 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();900 int FPCXTSaveSize = 0;901 bool NeedsWinCFI = needsWinCFI(MF);902 ARMSubtarget::PushPopSplitVariation PushPopSplit =903 STI.getPushPopSplitVariation(MF);904 905 LLVM_DEBUG(dbgs() << "Emitting prologue for " << MF.getName() << "\n");906 907 // Debug location must be unknown since the first debug location is used908 // to determine the end of the prologue.909 DebugLoc dl;910 911 Register FramePtr = RegInfo->getFrameRegister(MF);912 913 // Determine the sizes of each callee-save spill areas and record which frame914 // belongs to which callee-save spill areas.915 unsigned GPRCS1Size = 0, GPRCS2Size = 0, FPStatusSize = 0,916 DPRCS1Size = 0, GPRCS3Size = 0, DPRCS2Size = 0;917 int FramePtrSpillFI = 0;918 int D8SpillFI = 0;919 920 // All calls are tail calls in GHC calling conv, and functions have no921 // prologue/epilogue.922 if (MF.getFunction().getCallingConv() == CallingConv::GHC)923 return;924 925 StackAdjustingInsts DefCFAOffsetCandidates;926 bool HasFP = hasFP(MF);927 928 if (!AFI->hasStackFrame() &&929 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {930 if (NumBytes != 0) {931 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,932 MachineInstr::FrameSetup);933 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes, true);934 }935 if (!NeedsWinCFI)936 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, HasFP);937 if (NeedsWinCFI && MBBI != MBB.begin()) {938 insertSEHRange(MBB, {}, MBBI, TII, MachineInstr::FrameSetup);939 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_PrologEnd))940 .setMIFlag(MachineInstr::FrameSetup);941 MF.setHasWinCFI(true);942 }943 return;944 }945 946 // Determine spill area sizes, and some important frame indices.947 SpillArea FramePtrSpillArea = SpillArea::GPRCS1;948 bool BeforeFPPush = true;949 for (const CalleeSavedInfo &I : CSI) {950 MCRegister Reg = I.getReg();951 int FI = I.getFrameIdx();952 953 SpillArea Area = getSpillArea(Reg, PushPopSplit,954 AFI->getNumAlignedDPRCS2Regs(), RegInfo);955 956 if (Reg == FramePtr.asMCReg()) {957 FramePtrSpillFI = FI;958 FramePtrSpillArea = Area;959 }960 if (Reg == ARM::D8)961 D8SpillFI = FI;962 963 switch (Area) {964 case SpillArea::FPCXT:965 FPCXTSaveSize += 4;966 break;967 case SpillArea::GPRCS1:968 GPRCS1Size += 4;969 break;970 case SpillArea::GPRCS2:971 GPRCS2Size += 4;972 break;973 case SpillArea::FPStatus:974 FPStatusSize += 4;975 break;976 case SpillArea::DPRCS1:977 DPRCS1Size += 8;978 break;979 case SpillArea::GPRCS3:980 GPRCS3Size += 4;981 break;982 case SpillArea::DPRCS2:983 DPRCS2Size += 8;984 break;985 }986 }987 988 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push,989 DPRCS1Push, GPRCS3Push;990 991 // Move past the PAC computation.992 if (AFI->shouldSignReturnAddress())993 LastPush = MBBI++;994 995 // Move past FPCXT area.996 if (FPCXTSaveSize > 0) {997 LastPush = MBBI++;998 DefCFAOffsetCandidates.addInst(LastPush, FPCXTSaveSize, BeforeFPPush);999 }1000 1001 // Allocate the vararg register save area.1002 if (ArgRegsSaveSize) {1003 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,1004 MachineInstr::FrameSetup);1005 LastPush = std::prev(MBBI);1006 DefCFAOffsetCandidates.addInst(LastPush, ArgRegsSaveSize, BeforeFPPush);1007 }1008 1009 // Move past area 1.1010 if (GPRCS1Size > 0) {1011 GPRCS1Push = LastPush = MBBI++;1012 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, BeforeFPPush);1013 if (FramePtrSpillArea == SpillArea::GPRCS1)1014 BeforeFPPush = false;1015 }1016 1017 // Determine starting offsets of spill areas. These offsets are all positive1018 // offsets from the bottom of the lowest-addressed callee-save area1019 // (excluding DPRCS2, which is th the re-aligned stack region) to the bottom1020 // of the spill area in question.1021 unsigned FPCXTOffset = NumBytes - ArgRegsSaveSize - FPCXTSaveSize;1022 unsigned GPRCS1Offset = FPCXTOffset - GPRCS1Size;1023 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;1024 unsigned FPStatusOffset = GPRCS2Offset - FPStatusSize;1025 1026 Align DPRAlign = DPRCS1Size ? std::min(Align(8), Alignment) : Align(4);1027 unsigned DPRGapSize = (ArgRegsSaveSize + FPCXTSaveSize + GPRCS1Size +1028 GPRCS2Size + FPStatusSize) %1029 DPRAlign.value();1030 1031 unsigned DPRCS1Offset = FPStatusOffset - DPRGapSize - DPRCS1Size;1032 1033 if (HasFP) {1034 // Offset from the CFA to the saved frame pointer, will be negative.1035 [[maybe_unused]] int FPOffset = MFI.getObjectOffset(FramePtrSpillFI);1036 LLVM_DEBUG(dbgs() << "FramePtrSpillFI: " << FramePtrSpillFI1037 << ", FPOffset: " << FPOffset << "\n");1038 assert(getMaxFPOffset(STI, *AFI, MF) <= FPOffset &&1039 "Max FP estimation is wrong");1040 AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +1041 NumBytes);1042 }1043 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);1044 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);1045 AFI->setDPRCalleeSavedArea1Offset(DPRCS1Offset);1046 1047 // Move past area 2.1048 if (GPRCS2Size > 0) {1049 assert(PushPopSplit != ARMSubtarget::SplitR11WindowsSEH);1050 GPRCS2Push = LastPush = MBBI++;1051 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size, BeforeFPPush);1052 if (FramePtrSpillArea == SpillArea::GPRCS2)1053 BeforeFPPush = false;1054 }1055 1056 // Move past FP status save area.1057 if (FPStatusSize > 0) {1058 while (MBBI != MBB.end()) {1059 unsigned Opc = MBBI->getOpcode();1060 if (Opc == ARM::VMRS || Opc == ARM::VMRS_FPEXC)1061 MBBI++;1062 else1063 break;1064 }1065 LastPush = MBBI++;1066 DefCFAOffsetCandidates.addInst(LastPush, FPStatusSize);1067 }1068 1069 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our1070 // .cfi_offset operations will reflect that.1071 if (DPRGapSize) {1072 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");1073 if (LastPush != MBB.end() &&1074 tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, DPRGapSize))1075 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);1076 else {1077 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,1078 MachineInstr::FrameSetup);1079 DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize, BeforeFPPush);1080 }1081 }1082 1083 // Move past DPRCS1Size.1084 if (DPRCS1Size > 0) {1085 // Since vpush register list cannot have gaps, there may be multiple vpush1086 // instructions in the prologue.1087 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {1088 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI),1089 BeforeFPPush);1090 DPRCS1Push = LastPush = MBBI++;1091 }1092 }1093 1094 // Move past the aligned DPRCS2 area.1095 if (DPRCS2Size > 0) {1096 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());1097 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and1098 // leaves the stack pointer pointing to the DPRCS2 area.1099 //1100 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.1101 NumBytes += MFI.getObjectOffset(D8SpillFI);1102 } else1103 NumBytes = DPRCS1Offset;1104 1105 // Move GPRCS3, if using using SplitR11WindowsSEH.1106 if (GPRCS3Size > 0) {1107 assert(PushPopSplit == ARMSubtarget::SplitR11WindowsSEH);1108 GPRCS3Push = LastPush = MBBI++;1109 DefCFAOffsetCandidates.addInst(LastPush, GPRCS3Size, BeforeFPPush);1110 if (FramePtrSpillArea == SpillArea::GPRCS3)1111 BeforeFPPush = false;1112 }1113 1114 bool NeedsWinCFIStackAlloc = NeedsWinCFI;1115 if (PushPopSplit == ARMSubtarget::SplitR11WindowsSEH && HasFP)1116 NeedsWinCFIStackAlloc = false;1117 1118 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {1119 uint32_t NumWords = NumBytes >> 2;1120 1121 if (NumWords < 65536) {1122 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)1123 .addImm(NumWords)1124 .setMIFlags(MachineInstr::FrameSetup)1125 .add(predOps(ARMCC::AL));1126 } else {1127 // Split into two instructions here, instead of using t2MOVi32imm,1128 // to allow inserting accurate SEH instructions (including accurate1129 // instruction size for each of them).1130 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)1131 .addImm(NumWords & 0xffff)1132 .setMIFlags(MachineInstr::FrameSetup)1133 .add(predOps(ARMCC::AL));1134 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), ARM::R4)1135 .addReg(ARM::R4)1136 .addImm(NumWords >> 16)1137 .setMIFlags(MachineInstr::FrameSetup)1138 .add(predOps(ARMCC::AL));1139 }1140 1141 switch (TM.getCodeModel()) {1142 case CodeModel::Tiny:1143 llvm_unreachable("Tiny code model not available on ARM.");1144 case CodeModel::Small:1145 case CodeModel::Medium:1146 case CodeModel::Kernel:1147 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))1148 .add(predOps(ARMCC::AL))1149 .addExternalSymbol("__chkstk")1150 .addReg(ARM::R4, RegState::Implicit)1151 .setMIFlags(MachineInstr::FrameSetup);1152 break;1153 case CodeModel::Large:1154 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)1155 .addExternalSymbol("__chkstk")1156 .setMIFlags(MachineInstr::FrameSetup);1157 1158 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))1159 .add(predOps(ARMCC::AL))1160 .addReg(ARM::R12, RegState::Kill)1161 .addReg(ARM::R4, RegState::Implicit)1162 .setMIFlags(MachineInstr::FrameSetup);1163 break;1164 }1165 1166 MachineInstrBuilder Instr, SEH;1167 Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)1168 .addReg(ARM::SP, RegState::Kill)1169 .addReg(ARM::R4, RegState::Kill)1170 .setMIFlags(MachineInstr::FrameSetup)1171 .add(predOps(ARMCC::AL))1172 .add(condCodeOp());1173 if (NeedsWinCFIStackAlloc) {1174 SEH = BuildMI(MF, dl, TII.get(ARM::SEH_StackAlloc))1175 .addImm(NumBytes)1176 .addImm(/*Wide=*/1)1177 .setMIFlags(MachineInstr::FrameSetup);1178 MBB.insertAfter(Instr, SEH);1179 }1180 NumBytes = 0;1181 }1182 1183 if (NumBytes) {1184 // Adjust SP after all the callee-save spills.1185 if (AFI->getNumAlignedDPRCS2Regs() == 0 &&1186 tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes))1187 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);1188 else {1189 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,1190 MachineInstr::FrameSetup);1191 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes);1192 }1193 1194 if (HasFP && isARM)1195 // Restore from fp only in ARM mode: e.g. sub sp, r7, #241196 // Note it's not safe to do this in Thumb2 mode because it would have1197 // taken two instructions:1198 // mov sp, r71199 // sub sp, #241200 // If an interrupt is taken between the two instructions, then sp is in1201 // an inconsistent state (pointing to the middle of callee-saved area).1202 // The interrupt handler can end up clobbering the registers.1203 AFI->setShouldRestoreSPFromFP(true);1204 }1205 1206 // Set FP to point to the stack slot that contains the previous FP.1207 // For iOS, FP is R7, which has now been stored in spill area 1.1208 // Otherwise, if this is not iOS, all the callee-saved registers go1209 // into spill area 1, including the FP in R11. In either case, it1210 // is in area one and the adjustment needs to take place just after1211 // that push.1212 MachineBasicBlock::iterator AfterPush;1213 if (HasFP) {1214 MachineBasicBlock::iterator FPPushInst;1215 // Offset from SP immediately after the push which saved the FP to the FP1216 // save slot.1217 int64_t FPOffsetAfterPush;1218 switch (FramePtrSpillArea) {1219 case SpillArea::GPRCS1:1220 FPPushInst = GPRCS1Push;1221 FPOffsetAfterPush = MFI.getObjectOffset(FramePtrSpillFI) +1222 ArgRegsSaveSize + FPCXTSaveSize +1223 sizeOfSPAdjustment(*FPPushInst);1224 LLVM_DEBUG(dbgs() << "Frame pointer in GPRCS1, offset "1225 << FPOffsetAfterPush << " after that push\n");1226 break;1227 case SpillArea::GPRCS2:1228 FPPushInst = GPRCS2Push;1229 FPOffsetAfterPush = MFI.getObjectOffset(FramePtrSpillFI) +1230 ArgRegsSaveSize + FPCXTSaveSize + GPRCS1Size +1231 sizeOfSPAdjustment(*FPPushInst);1232 LLVM_DEBUG(dbgs() << "Frame pointer in GPRCS2, offset "1233 << FPOffsetAfterPush << " after that push\n");1234 break;1235 case SpillArea::GPRCS3:1236 FPPushInst = GPRCS3Push;1237 FPOffsetAfterPush = MFI.getObjectOffset(FramePtrSpillFI) +1238 ArgRegsSaveSize + FPCXTSaveSize + GPRCS1Size +1239 FPStatusSize + GPRCS2Size + DPRCS1Size + DPRGapSize +1240 sizeOfSPAdjustment(*FPPushInst);1241 LLVM_DEBUG(dbgs() << "Frame pointer in GPRCS3, offset "1242 << FPOffsetAfterPush << " after that push\n");1243 break;1244 default:1245 llvm_unreachable("frame pointer in unknown spill area");1246 break;1247 }1248 AfterPush = std::next(FPPushInst);1249 if (PushPopSplit == ARMSubtarget::SplitR11WindowsSEH)1250 assert(FPOffsetAfterPush == 0);1251 1252 // Emit the MOV or ADD to set up the frame pointer register.1253 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII,1254 FramePtr, ARM::SP, FPOffsetAfterPush,1255 MachineInstr::FrameSetup);1256 1257 if (!NeedsWinCFI) {1258 // Emit DWARF info to find the CFA using the frame pointer from this1259 // point onward.1260 CFIInstBuilder CFIBuilder(MBB, AfterPush, MachineInstr::FrameSetup);1261 if (FPOffsetAfterPush != 0)1262 CFIBuilder.buildDefCFA(FramePtr, -MFI.getObjectOffset(FramePtrSpillFI));1263 else1264 CFIBuilder.buildDefCFARegister(FramePtr);1265 }1266 }1267 1268 // Emit a SEH opcode indicating the prologue end. The rest of the prologue1269 // instructions below don't need to be replayed to unwind the stack.1270 if (NeedsWinCFI && MBBI != MBB.begin()) {1271 MachineBasicBlock::iterator End = MBBI;1272 if (HasFP && PushPopSplit == ARMSubtarget::SplitR11WindowsSEH)1273 End = AfterPush;1274 insertSEHRange(MBB, {}, End, TII, MachineInstr::FrameSetup);1275 BuildMI(MBB, End, dl, TII.get(ARM::SEH_PrologEnd))1276 .setMIFlag(MachineInstr::FrameSetup);1277 MF.setHasWinCFI(true);1278 }1279 1280 // Now that the prologue's actual instructions are finalised, we can insert1281 // the necessary DWARF cf instructions to describe the situation. Start by1282 // recording where each register ended up:1283 if (!NeedsWinCFI) {1284 for (const auto &Entry : reverse(CSI)) {1285 MCRegister Reg = Entry.getReg();1286 int FI = Entry.getFrameIdx();1287 MachineBasicBlock::iterator CFIPos;1288 switch (getSpillArea(Reg, PushPopSplit, AFI->getNumAlignedDPRCS2Regs(),1289 RegInfo)) {1290 case SpillArea::GPRCS1:1291 CFIPos = std::next(GPRCS1Push);1292 break;1293 case SpillArea::GPRCS2:1294 CFIPos = std::next(GPRCS2Push);1295 break;1296 case SpillArea::DPRCS1:1297 CFIPos = std::next(DPRCS1Push);1298 break;1299 case SpillArea::GPRCS3:1300 CFIPos = std::next(GPRCS3Push);1301 break;1302 case SpillArea::FPStatus:1303 case SpillArea::FPCXT:1304 case SpillArea::DPRCS2:1305 // FPCXT and DPRCS2 are not represented in the DWARF info.1306 break;1307 }1308 1309 if (CFIPos.isValid()) {1310 CFIInstBuilder(MBB, CFIPos, MachineInstr::FrameSetup)1311 .buildOffset(Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg,1312 MFI.getObjectOffset(FI));1313 }1314 }1315 }1316 1317 // Now we can emit descriptions of where the canonical frame address was1318 // throughout the process. If we have a frame pointer, it takes over the job1319 // half-way through, so only the first few .cfi_def_cfa_offset instructions1320 // actually get emitted.1321 if (!NeedsWinCFI) {1322 LLVM_DEBUG(DefCFAOffsetCandidates.dump());1323 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, HasFP);1324 }1325 1326 if (STI.isTargetELF() && hasFP(MF))1327 MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -1328 AFI->getFramePtrSpillOffset());1329 1330 AFI->setFPCXTSaveAreaSize(FPCXTSaveSize);1331 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);1332 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);1333 AFI->setFPStatusSavesSize(FPStatusSize);1334 AFI->setDPRCalleeSavedGapSize(DPRGapSize);1335 AFI->setDPRCalleeSavedArea1Size(DPRCS1Size);1336 AFI->setGPRCalleeSavedArea3Size(GPRCS3Size);1337 1338 // If we need dynamic stack realignment, do it here. Be paranoid and make1339 // sure if we also have VLAs, we have a base pointer for frame access.1340 // If aligned NEON registers were spilled, the stack has already been1341 // realigned.1342 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->hasStackRealignment(MF)) {1343 Align MaxAlign = MFI.getMaxAlign();1344 assert(!AFI->isThumb1OnlyFunction());1345 if (!AFI->isThumbFunction()) {1346 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,1347 false);1348 } else {1349 // We cannot use sp as source/dest register here, thus we're using r4 to1350 // perform the calculations. We're emitting the following sequence:1351 // mov r4, sp1352 // -- use emitAligningInstructions to produce best sequence to zero1353 // -- out lower bits in r41354 // mov sp, r41355 // FIXME: It will be better just to find spare register here.1356 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)1357 .addReg(ARM::SP, RegState::Kill)1358 .add(predOps(ARMCC::AL));1359 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,1360 false);1361 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)1362 .addReg(ARM::R4, RegState::Kill)1363 .add(predOps(ARMCC::AL));1364 }1365 1366 AFI->setShouldRestoreSPFromFP(true);1367 }1368 1369 // If we need a base pointer, set it up here. It's whatever the value1370 // of the stack pointer is at this point. Any variable size objects1371 // will be allocated after this, so we can still use the base pointer1372 // to reference locals.1373 // FIXME: Clarify FrameSetup flags here.1374 if (RegInfo->hasBasePointer(MF)) {1375 if (isARM)1376 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister())1377 .addReg(ARM::SP)1378 .add(predOps(ARMCC::AL))1379 .add(condCodeOp());1380 else1381 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister())1382 .addReg(ARM::SP)1383 .add(predOps(ARMCC::AL));1384 }1385 1386 // If the frame has variable sized objects then the epilogue must restore1387 // the sp from fp. We can assume there's an FP here since hasFP already1388 // checks for hasVarSizedObjects.1389 if (MFI.hasVarSizedObjects())1390 AFI->setShouldRestoreSPFromFP(true);1391}1392 1393void ARMFrameLowering::emitEpilogue(MachineFunction &MF,1394 MachineBasicBlock &MBB) const {1395 MachineFrameInfo &MFI = MF.getFrameInfo();1396 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();1397 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();1398 const ARMBaseInstrInfo &TII =1399 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());1400 assert(!AFI->isThumb1OnlyFunction() &&1401 "This emitEpilogue does not support Thumb1!");1402 bool isARM = !AFI->isThumbFunction();1403 ARMSubtarget::PushPopSplitVariation PushPopSplit =1404 STI.getPushPopSplitVariation(MF);1405 1406 LLVM_DEBUG(dbgs() << "Emitting epilogue for " << MF.getName() << "\n");1407 1408 // Amount of stack space we reserved next to incoming args for either1409 // varargs registers or stack arguments in tail calls made by this function.1410 unsigned ReservedArgStack = AFI->getArgRegsSaveSize();1411 1412 // How much of the stack used by incoming arguments this function is expected1413 // to restore in this particular epilogue.1414 int IncomingArgStackToRestore = getArgumentStackToRestore(MF, MBB);1415 int NumBytes = (int)MFI.getStackSize();1416 Register FramePtr = RegInfo->getFrameRegister(MF);1417 1418 // All calls are tail calls in GHC calling conv, and functions have no1419 // prologue/epilogue.1420 if (MF.getFunction().getCallingConv() == CallingConv::GHC)1421 return;1422 1423 // First put ourselves on the first (from top) terminator instructions.1424 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();1425 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();1426 1427 MachineBasicBlock::iterator RangeStart;1428 if (!AFI->hasStackFrame()) {1429 if (MF.hasWinCFI()) {1430 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart))1431 .setMIFlag(MachineInstr::FrameDestroy);1432 RangeStart = initMBBRange(MBB, MBBI);1433 }1434 1435 if (NumBytes + IncomingArgStackToRestore != 0)1436 emitSPUpdate(isARM, MBB, MBBI, dl, TII,1437 NumBytes + IncomingArgStackToRestore,1438 MachineInstr::FrameDestroy);1439 } else {1440 // Unwind MBBI to point to first LDR / VLDRD.1441 if (MBBI != MBB.begin()) {1442 do {1443 --MBBI;1444 } while (MBBI != MBB.begin() &&1445 MBBI->getFlag(MachineInstr::FrameDestroy));1446 if (!MBBI->getFlag(MachineInstr::FrameDestroy))1447 ++MBBI;1448 }1449 1450 if (MF.hasWinCFI()) {1451 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart))1452 .setMIFlag(MachineInstr::FrameDestroy);1453 RangeStart = initMBBRange(MBB, MBBI);1454 }1455 1456 // Move SP to start of FP callee save spill area.1457 NumBytes -=1458 (ReservedArgStack + AFI->getFPCXTSaveAreaSize() +1459 AFI->getGPRCalleeSavedArea1Size() + AFI->getGPRCalleeSavedArea2Size() +1460 AFI->getFPStatusSavesSize() + AFI->getDPRCalleeSavedGapSize() +1461 AFI->getDPRCalleeSavedArea1Size() + AFI->getGPRCalleeSavedArea3Size());1462 1463 // Reset SP based on frame pointer only if the stack frame extends beyond1464 // frame pointer stack slot or target is ELF and the function has FP.1465 if (AFI->shouldRestoreSPFromFP()) {1466 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;1467 if (NumBytes) {1468 if (isARM)1469 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,1470 ARMCC::AL, 0, TII,1471 MachineInstr::FrameDestroy);1472 else {1473 // It's not possible to restore SP from FP in a single instruction.1474 // For iOS, this looks like:1475 // mov sp, r71476 // sub sp, #241477 // This is bad, if an interrupt is taken after the mov, sp is in an1478 // inconsistent state.1479 // Use the first callee-saved register as a scratch register.1480 assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&1481 "No scratch register to restore SP from FP!");1482 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,1483 ARMCC::AL, 0, TII, MachineInstr::FrameDestroy);1484 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)1485 .addReg(ARM::R4)1486 .add(predOps(ARMCC::AL))1487 .setMIFlag(MachineInstr::FrameDestroy);1488 }1489 } else {1490 // Thumb2 or ARM.1491 if (isARM)1492 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)1493 .addReg(FramePtr)1494 .add(predOps(ARMCC::AL))1495 .add(condCodeOp())1496 .setMIFlag(MachineInstr::FrameDestroy);1497 else1498 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)1499 .addReg(FramePtr)1500 .add(predOps(ARMCC::AL))1501 .setMIFlag(MachineInstr::FrameDestroy);1502 }1503 } else if (NumBytes &&1504 !tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))1505 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes,1506 MachineInstr::FrameDestroy);1507 1508 // Increment past our save areas.1509 if (AFI->getGPRCalleeSavedArea3Size()) {1510 assert(PushPopSplit == ARMSubtarget::SplitR11WindowsSEH);1511 (void)PushPopSplit;1512 MBBI++;1513 }1514 1515 if (MBBI != MBB.end() && AFI->getDPRCalleeSavedArea1Size()) {1516 MBBI++;1517 // Since vpop register list cannot have gaps, there may be multiple vpop1518 // instructions in the epilogue.1519 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD)1520 MBBI++;1521 }1522 if (AFI->getDPRCalleeSavedGapSize()) {1523 assert(AFI->getDPRCalleeSavedGapSize() == 4 &&1524 "unexpected DPR alignment gap");1525 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize(),1526 MachineInstr::FrameDestroy);1527 }1528 1529 if (AFI->getGPRCalleeSavedArea2Size()) {1530 assert(PushPopSplit != ARMSubtarget::SplitR11WindowsSEH);1531 (void)PushPopSplit;1532 MBBI++;1533 }1534 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;1535 1536 if (ReservedArgStack || IncomingArgStackToRestore) {1537 assert((int)ReservedArgStack + IncomingArgStackToRestore >= 0 &&1538 "attempting to restore negative stack amount");1539 emitSPUpdate(isARM, MBB, MBBI, dl, TII,1540 ReservedArgStack + IncomingArgStackToRestore,1541 MachineInstr::FrameDestroy);1542 }1543 1544 // Validate PAC, It should have been already popped into R12. For CMSE entry1545 // function, the validation instruction is emitted during expansion of the1546 // tBXNS_RET, since the validation must use the value of SP at function1547 // entry, before saving, resp. after restoring, FPCXTNS.1548 if (AFI->shouldSignReturnAddress() && !AFI->isCmseNSEntryFunction())1549 BuildMI(MBB, MBBI, DebugLoc(), STI.getInstrInfo()->get(ARM::t2AUT));1550 }1551 1552 if (MF.hasWinCFI()) {1553 insertSEHRange(MBB, RangeStart, MBB.end(), TII, MachineInstr::FrameDestroy);1554 BuildMI(MBB, MBB.end(), dl, TII.get(ARM::SEH_EpilogEnd))1555 .setMIFlag(MachineInstr::FrameDestroy);1556 }1557}1558 1559/// getFrameIndexReference - Provide a base+offset reference to an FI slot for1560/// debug info. It's the same as what we use for resolving the code-gen1561/// references for now. FIXME: This can go wrong when references are1562/// SP-relative and simple call frames aren't used.1563StackOffset ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF,1564 int FI,1565 Register &FrameReg) const {1566 return StackOffset::getFixed(ResolveFrameIndexReference(MF, FI, FrameReg, 0));1567}1568 1569int ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,1570 int FI, Register &FrameReg,1571 int SPAdj) const {1572 const MachineFrameInfo &MFI = MF.getFrameInfo();1573 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(1574 MF.getSubtarget().getRegisterInfo());1575 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();1576 int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize();1577 int FPOffset = Offset - AFI->getFramePtrSpillOffset();1578 bool isFixed = MFI.isFixedObjectIndex(FI);1579 1580 FrameReg = ARM::SP;1581 Offset += SPAdj;1582 1583 // SP can move around if there are allocas. We may also lose track of SP1584 // when emergency spilling inside a non-reserved call frame setup.1585 bool hasMovingSP = !hasReservedCallFrame(MF);1586 1587 // When dynamically realigning the stack, use the frame pointer for1588 // parameters, and the stack/base pointer for locals.1589 if (RegInfo->hasStackRealignment(MF)) {1590 assert(hasFP(MF) && "dynamic stack realignment without a FP!");1591 if (isFixed) {1592 FrameReg = RegInfo->getFrameRegister(MF);1593 Offset = FPOffset;1594 } else if (hasMovingSP) {1595 assert(RegInfo->hasBasePointer(MF) &&1596 "VLAs and dynamic stack alignment, but missing base pointer!");1597 FrameReg = RegInfo->getBaseRegister();1598 Offset -= SPAdj;1599 }1600 return Offset;1601 }1602 1603 // If there is a frame pointer, use it when we can.1604 if (hasFP(MF) && AFI->hasStackFrame()) {1605 // Use frame pointer to reference fixed objects. Use it for locals if1606 // there are VLAs (and thus the SP isn't reliable as a base).1607 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {1608 FrameReg = RegInfo->getFrameRegister(MF);1609 return FPOffset;1610 } else if (hasMovingSP) {1611 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");1612 if (AFI->isThumb2Function()) {1613 // Try to use the frame pointer if we can, else use the base pointer1614 // since it's available. This is handy for the emergency spill slot, in1615 // particular.1616 if (FPOffset >= -255 && FPOffset < 0) {1617 FrameReg = RegInfo->getFrameRegister(MF);1618 return FPOffset;1619 }1620 }1621 } else if (AFI->isThumbFunction()) {1622 // Prefer SP to base pointer, if the offset is suitably aligned and in1623 // range as the effective range of the immediate offset is bigger when1624 // basing off SP.1625 // Use add <rd>, sp, #<imm8>1626 // ldr <rd>, [sp, #<imm8>]1627 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)1628 return Offset;1629 // In Thumb2 mode, the negative offset is very limited. Try to avoid1630 // out of range references. ldr <rt>,[<rn>, #-<imm8>]1631 if (AFI->isThumb2Function() && FPOffset >= -255 && FPOffset < 0) {1632 FrameReg = RegInfo->getFrameRegister(MF);1633 return FPOffset;1634 }1635 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {1636 // Otherwise, use SP or FP, whichever is closer to the stack slot.1637 FrameReg = RegInfo->getFrameRegister(MF);1638 return FPOffset;1639 }1640 }1641 // Use the base pointer if we have one.1642 // FIXME: Maybe prefer sp on Thumb1 if it's legal and the offset is cheaper?1643 // That can happen if we forced a base pointer for a large call frame.1644 if (RegInfo->hasBasePointer(MF)) {1645 FrameReg = RegInfo->getBaseRegister();1646 Offset -= SPAdj;1647 }1648 return Offset;1649}1650 1651void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,1652 MachineBasicBlock::iterator MI,1653 ArrayRef<CalleeSavedInfo> CSI,1654 unsigned StmOpc, unsigned StrOpc,1655 bool NoGap,1656 function_ref<bool(unsigned)> Func) const {1657 MachineFunction &MF = *MBB.getParent();1658 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();1659 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();1660 1661 DebugLoc DL;1662 1663 using RegAndKill = std::pair<unsigned, bool>;1664 1665 SmallVector<RegAndKill, 4> Regs;1666 unsigned i = CSI.size();1667 while (i != 0) {1668 unsigned LastReg = 0;1669 for (; i != 0; --i) {1670 MCRegister Reg = CSI[i-1].getReg();1671 if (!Func(Reg))1672 continue;1673 1674 const MachineRegisterInfo &MRI = MF.getRegInfo();1675 bool isLiveIn = MRI.isLiveIn(Reg);1676 if (!isLiveIn && !MRI.isReserved(Reg))1677 MBB.addLiveIn(Reg);1678 // If NoGap is true, push consecutive registers and then leave the rest1679 // for other instructions. e.g.1680 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}1681 if (NoGap && LastReg && LastReg != Reg-1)1682 break;1683 LastReg = Reg;1684 // Do not set a kill flag on values that are also marked as live-in. This1685 // happens with the @llvm-returnaddress intrinsic and with arguments1686 // passed in callee saved registers.1687 // Omitting the kill flags is conservatively correct even if the live-in1688 // is not used after all.1689 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));1690 }1691 1692 if (Regs.empty())1693 continue;1694 1695 llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) {1696 return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);1697 });1698 1699 if (Regs.size() > 1 || StrOpc== 0) {1700 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)1701 .addReg(ARM::SP)1702 .setMIFlags(MachineInstr::FrameSetup)1703 .add(predOps(ARMCC::AL));1704 for (const auto &[Reg, Kill] : Regs)1705 MIB.addReg(Reg, getKillRegState(Kill));1706 } else if (Regs.size() == 1) {1707 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP)1708 .addReg(Regs[0].first, getKillRegState(Regs[0].second))1709 .addReg(ARM::SP)1710 .setMIFlags(MachineInstr::FrameSetup)1711 .addImm(-4)1712 .add(predOps(ARMCC::AL));1713 }1714 Regs.clear();1715 1716 // Put any subsequent vpush instructions before this one: they will refer to1717 // higher register numbers so need to be pushed first in order to preserve1718 // monotonicity.1719 if (MI != MBB.begin())1720 --MI;1721 }1722}1723 1724void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,1725 MachineBasicBlock::iterator MI,1726 MutableArrayRef<CalleeSavedInfo> CSI,1727 unsigned LdmOpc, unsigned LdrOpc,1728 bool isVarArg, bool NoGap,1729 function_ref<bool(unsigned)> Func) const {1730 MachineFunction &MF = *MBB.getParent();1731 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();1732 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();1733 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();1734 bool hasPAC = AFI->shouldSignReturnAddress();1735 DebugLoc DL;1736 bool isTailCall = false;1737 bool isInterrupt = false;1738 bool isTrap = false;1739 bool isCmseEntry = false;1740 ARMSubtarget::PushPopSplitVariation PushPopSplit =1741 STI.getPushPopSplitVariation(MF);1742 if (MBB.end() != MI) {1743 DL = MI->getDebugLoc();1744 unsigned RetOpcode = MI->getOpcode();1745 isTailCall =1746 (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri ||1747 RetOpcode == ARM::TCRETURNrinotr12);1748 isInterrupt =1749 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;1750 isTrap = RetOpcode == ARM::TRAP || RetOpcode == ARM::tTRAP;1751 isCmseEntry = (RetOpcode == ARM::tBXNS || RetOpcode == ARM::tBXNS_RET);1752 }1753 1754 SmallVector<unsigned, 4> Regs;1755 unsigned i = CSI.size();1756 while (i != 0) {1757 unsigned LastReg = 0;1758 bool DeleteRet = false;1759 for (; i != 0; --i) {1760 CalleeSavedInfo &Info = CSI[i-1];1761 MCRegister Reg = Info.getReg();1762 if (!Func(Reg))1763 continue;1764 1765 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&1766 !isCmseEntry && !isTrap && AFI->getArgumentStackToRestore() == 0 &&1767 STI.hasV5TOps() && MBB.succ_empty() && !hasPAC &&1768 (PushPopSplit != ARMSubtarget::SplitR11WindowsSEH &&1769 PushPopSplit != ARMSubtarget::SplitR11AAPCSSignRA)) {1770 Reg = ARM::PC;1771 // Fold the return instruction into the LDM.1772 DeleteRet = true;1773 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;1774 }1775 1776 // If NoGap is true, pop consecutive registers and then leave the rest1777 // for other instructions. e.g.1778 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}1779 if (NoGap && LastReg && LastReg != Reg-1)1780 break;1781 1782 LastReg = Reg;1783 Regs.push_back(Reg);1784 }1785 1786 if (Regs.empty())1787 continue;1788 1789 llvm::sort(Regs, [&](unsigned LHS, unsigned RHS) {1790 return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);1791 });1792 1793 if (Regs.size() > 1 || LdrOpc == 0) {1794 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)1795 .addReg(ARM::SP)1796 .add(predOps(ARMCC::AL))1797 .setMIFlags(MachineInstr::FrameDestroy);1798 for (unsigned Reg : Regs)1799 MIB.addReg(Reg, getDefRegState(true));1800 if (DeleteRet) {1801 if (MI != MBB.end()) {1802 MIB.copyImplicitOps(*MI);1803 MI->eraseFromParent();1804 }1805 }1806 MI = MIB;1807 } else if (Regs.size() == 1) {1808 // If we adjusted the reg to PC from LR above, switch it back here. We1809 // only do that for LDM.1810 if (Regs[0] == ARM::PC)1811 Regs[0] = ARM::LR;1812 MachineInstrBuilder MIB =1813 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])1814 .addReg(ARM::SP, RegState::Define)1815 .addReg(ARM::SP)1816 .setMIFlags(MachineInstr::FrameDestroy);1817 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once1818 // that refactoring is complete (eventually).1819 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {1820 MIB.addReg(0);1821 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));1822 } else1823 MIB.addImm(4);1824 MIB.add(predOps(ARMCC::AL));1825 }1826 Regs.clear();1827 1828 // Put any subsequent vpop instructions after this one: they will refer to1829 // higher register numbers so need to be popped afterwards.1830 if (MI != MBB.end())1831 ++MI;1832 }1833}1834 1835void ARMFrameLowering::emitFPStatusSaves(MachineBasicBlock &MBB,1836 MachineBasicBlock::iterator MI,1837 ArrayRef<CalleeSavedInfo> CSI,1838 unsigned PushOpc) const {1839 MachineFunction &MF = *MBB.getParent();1840 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();1841 1842 SmallVector<MCRegister> Regs;1843 auto RegPresent = [&CSI](MCRegister Reg) {1844 return llvm::any_of(CSI, [Reg](const CalleeSavedInfo &C) {1845 return C.getReg() == Reg;1846 });1847 };1848 1849 // If we need to save FPSCR, then we must move FPSCR into R4 with the VMRS1850 // instruction.1851 if (RegPresent(ARM::FPSCR)) {1852 BuildMI(MBB, MI, DebugLoc(), TII.get(ARM::VMRS), ARM::R4)1853 .add(predOps(ARMCC::AL))1854 .setMIFlags(MachineInstr::FrameSetup);1855 1856 Regs.push_back(ARM::R4);1857 }1858 1859 // If we need to save FPEXC, then we must move FPEXC into R5 with the1860 // VMRS_FPEXC instruction.1861 if (RegPresent(ARM::FPEXC)) {1862 BuildMI(MBB, MI, DebugLoc(), TII.get(ARM::VMRS_FPEXC), ARM::R5)1863 .add(predOps(ARMCC::AL))1864 .setMIFlags(MachineInstr::FrameSetup);1865 1866 Regs.push_back(ARM::R5);1867 }1868 1869 // If neither FPSCR and FPEXC are present, then do nothing.1870 if (Regs.size() == 0)1871 return;1872 1873 // Push both R4 and R5 onto the stack, if present.1874 MachineInstrBuilder MIB =1875 BuildMI(MBB, MI, DebugLoc(), TII.get(PushOpc), ARM::SP)1876 .addReg(ARM::SP)1877 .add(predOps(ARMCC::AL))1878 .setMIFlags(MachineInstr::FrameSetup);1879 1880 for (Register Reg : Regs) {1881 MIB.addReg(Reg);1882 }1883}1884 1885void ARMFrameLowering::emitFPStatusRestores(1886 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,1887 MutableArrayRef<CalleeSavedInfo> CSI, unsigned LdmOpc) const {1888 MachineFunction &MF = *MBB.getParent();1889 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();1890 1891 auto RegPresent = [&CSI](MCRegister Reg) {1892 return llvm::any_of(CSI, [Reg](const CalleeSavedInfo &C) {1893 return C.getReg() == Reg;1894 });1895 };1896 1897 // Do nothing if we don't need to restore any FP status registers.1898 if (!RegPresent(ARM::FPSCR) && !RegPresent(ARM::FPEXC))1899 return;1900 1901 // Pop registers off of the stack.1902 MachineInstrBuilder MIB =1903 BuildMI(MBB, MI, DebugLoc(), TII.get(LdmOpc), ARM::SP)1904 .addReg(ARM::SP)1905 .add(predOps(ARMCC::AL))1906 .setMIFlags(MachineInstr::FrameDestroy);1907 1908 // If FPSCR was saved, it will be popped into R4.1909 if (RegPresent(ARM::FPSCR)) {1910 MIB.addReg(ARM::R4, RegState::Define);1911 }1912 1913 // If FPEXC was saved, it will be popped into R5.1914 if (RegPresent(ARM::FPEXC)) {1915 MIB.addReg(ARM::R5, RegState::Define);1916 }1917 1918 // Move the FPSCR value back into the register with the VMSR instruction.1919 if (RegPresent(ARM::FPSCR)) {1920 BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::VMSR))1921 .addReg(ARM::R4)1922 .add(predOps(ARMCC::AL))1923 .setMIFlags(MachineInstr::FrameDestroy);1924 }1925 1926 // Move the FPEXC value back into the register with the VMSR_FPEXC1927 // instruction.1928 if (RegPresent(ARM::FPEXC)) {1929 BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::VMSR_FPEXC))1930 .addReg(ARM::R5)1931 .add(predOps(ARMCC::AL))1932 .setMIFlags(MachineInstr::FrameDestroy);1933 }1934}1935 1936/// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers1937/// starting from d8. Also insert stack realignment code and leave the stack1938/// pointer pointing to the d8 spill slot.1939static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,1940 MachineBasicBlock::iterator MI,1941 unsigned NumAlignedDPRCS2Regs,1942 ArrayRef<CalleeSavedInfo> CSI,1943 const TargetRegisterInfo *TRI) {1944 MachineFunction &MF = *MBB.getParent();1945 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();1946 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();1947 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();1948 MachineFrameInfo &MFI = MF.getFrameInfo();1949 1950 // Mark the D-register spill slots as properly aligned. Since MFI computes1951 // stack slot layout backwards, this can actually mean that the d-reg stack1952 // slot offsets can be wrong. The offset for d8 will always be correct.1953 for (const CalleeSavedInfo &I : CSI) {1954 unsigned DNum = I.getReg() - ARM::D8;1955 if (DNum > NumAlignedDPRCS2Regs - 1)1956 continue;1957 int FI = I.getFrameIdx();1958 // The even-numbered registers will be 16-byte aligned, the odd-numbered1959 // registers will be 8-byte aligned.1960 MFI.setObjectAlignment(FI, DNum % 2 ? Align(8) : Align(16));1961 1962 // The stack slot for D8 needs to be maximally aligned because this is1963 // actually the point where we align the stack pointer. MachineFrameInfo1964 // computes all offsets relative to the incoming stack pointer which is a1965 // bit weird when realigning the stack. Any extra padding for this1966 // over-alignment is not realized because the code inserted below adjusts1967 // the stack pointer by numregs * 8 before aligning the stack pointer.1968 if (DNum == 0)1969 MFI.setObjectAlignment(FI, MFI.getMaxAlign());1970 }1971 1972 // Move the stack pointer to the d8 spill slot, and align it at the same1973 // time. Leave the stack slot address in the scratch register r4.1974 //1975 // sub r4, sp, #numregs * 81976 // bic r4, r4, #align - 11977 // mov sp, r41978 //1979 bool isThumb = AFI->isThumbFunction();1980 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");1981 AFI->setShouldRestoreSPFromFP(true);1982 1983 // sub r4, sp, #numregs * 81984 // The immediate is <= 64, so it doesn't need any special encoding.1985 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;1986 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)1987 .addReg(ARM::SP)1988 .addImm(8 * NumAlignedDPRCS2Regs)1989 .add(predOps(ARMCC::AL))1990 .add(condCodeOp());1991 1992 Align MaxAlign = MF.getFrameInfo().getMaxAlign();1993 // We must set parameter MustBeSingleInstruction to true, since1994 // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform1995 // stack alignment. Luckily, this can always be done since all ARM1996 // architecture versions that support Neon also support the BFC1997 // instruction.1998 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);1999 2000 // mov sp, r42001 // The stack pointer must be adjusted before spilling anything, otherwise2002 // the stack slots could be clobbered by an interrupt handler.2003 // Leave r4 live, it is used below.2004 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;2005 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)2006 .addReg(ARM::R4)2007 .add(predOps(ARMCC::AL));2008 if (!isThumb)2009 MIB.add(condCodeOp());2010 2011 // Now spill NumAlignedDPRCS2Regs registers starting from d8.2012 // r4 holds the stack slot address.2013 unsigned NextReg = ARM::D8;2014 2015 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.2016 // The writeback is only needed when emitting two vst1.64 instructions.2017 if (NumAlignedDPRCS2Regs >= 6) {2018 MCRegister SupReg =2019 TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);2020 MBB.addLiveIn(SupReg);2021 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)2022 .addReg(ARM::R4, RegState::Kill)2023 .addImm(16)2024 .addReg(NextReg)2025 .addReg(SupReg, RegState::ImplicitKill)2026 .add(predOps(ARMCC::AL));2027 NextReg += 4;2028 NumAlignedDPRCS2Regs -= 4;2029 }2030 2031 // We won't modify r4 beyond this point. It currently points to the next2032 // register to be spilled.2033 unsigned R4BaseReg = NextReg;2034 2035 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.2036 if (NumAlignedDPRCS2Regs >= 4) {2037 MCRegister SupReg =2038 TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);2039 MBB.addLiveIn(SupReg);2040 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))2041 .addReg(ARM::R4)2042 .addImm(16)2043 .addReg(NextReg)2044 .addReg(SupReg, RegState::ImplicitKill)2045 .add(predOps(ARMCC::AL));2046 NextReg += 4;2047 NumAlignedDPRCS2Regs -= 4;2048 }2049 2050 // 16-byte aligned vst1.64 with 2 d-regs.2051 if (NumAlignedDPRCS2Regs >= 2) {2052 MCRegister SupReg =2053 TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QPRRegClass);2054 MBB.addLiveIn(SupReg);2055 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))2056 .addReg(ARM::R4)2057 .addImm(16)2058 .addReg(SupReg)2059 .add(predOps(ARMCC::AL));2060 NextReg += 2;2061 NumAlignedDPRCS2Regs -= 2;2062 }2063 2064 // Finally, use a vanilla vstr.64 for the odd last register.2065 if (NumAlignedDPRCS2Regs) {2066 MBB.addLiveIn(NextReg);2067 // vstr.64 uses addrmode5 which has an offset scale of 4.2068 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))2069 .addReg(NextReg)2070 .addReg(ARM::R4)2071 .addImm((NextReg - R4BaseReg) * 2)2072 .add(predOps(ARMCC::AL));2073 }2074 2075 // The last spill instruction inserted should kill the scratch register r4.2076 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);2077}2078 2079/// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an2080/// iterator to the following instruction.2081static MachineBasicBlock::iterator2082skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,2083 unsigned NumAlignedDPRCS2Regs) {2084 // sub r4, sp, #numregs * 82085 // bic r4, r4, #align - 12086 // mov sp, r42087 ++MI; ++MI; ++MI;2088 assert(MI->mayStore() && "Expecting spill instruction");2089 2090 // These switches all fall through.2091 switch(NumAlignedDPRCS2Regs) {2092 case 7:2093 ++MI;2094 assert(MI->mayStore() && "Expecting spill instruction");2095 [[fallthrough]];2096 default:2097 ++MI;2098 assert(MI->mayStore() && "Expecting spill instruction");2099 [[fallthrough]];2100 case 1:2101 case 2:2102 case 4:2103 assert(MI->killsRegister(ARM::R4, /*TRI=*/nullptr) && "Missed kill flag");2104 ++MI;2105 }2106 return MI;2107}2108 2109/// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers2110/// starting from d8. These instructions are assumed to execute while the2111/// stack is still aligned, unlike the code inserted by emitPopInst.2112static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,2113 MachineBasicBlock::iterator MI,2114 unsigned NumAlignedDPRCS2Regs,2115 ArrayRef<CalleeSavedInfo> CSI,2116 const TargetRegisterInfo *TRI) {2117 MachineFunction &MF = *MBB.getParent();2118 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();2119 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();2120 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();2121 2122 // Find the frame index assigned to d8.2123 int D8SpillFI = 0;2124 for (const CalleeSavedInfo &I : CSI)2125 if (I.getReg() == ARM::D8) {2126 D8SpillFI = I.getFrameIdx();2127 break;2128 }2129 2130 // Materialize the address of the d8 spill slot into the scratch register r4.2131 // This can be fairly complicated if the stack frame is large, so just use2132 // the normal frame index elimination mechanism to do it. This code runs as2133 // the initial part of the epilog where the stack and base pointers haven't2134 // been changed yet.2135 bool isThumb = AFI->isThumbFunction();2136 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");2137 2138 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;2139 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)2140 .addFrameIndex(D8SpillFI)2141 .addImm(0)2142 .add(predOps(ARMCC::AL))2143 .add(condCodeOp());2144 2145 // Now restore NumAlignedDPRCS2Regs registers starting from d8.2146 unsigned NextReg = ARM::D8;2147 2148 // 16-byte aligned vld1.64 with 4 d-regs and writeback.2149 if (NumAlignedDPRCS2Regs >= 6) {2150 MCRegister SupReg =2151 TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);2152 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)2153 .addReg(ARM::R4, RegState::Define)2154 .addReg(ARM::R4, RegState::Kill)2155 .addImm(16)2156 .addReg(SupReg, RegState::ImplicitDefine)2157 .add(predOps(ARMCC::AL));2158 NextReg += 4;2159 NumAlignedDPRCS2Regs -= 4;2160 }2161 2162 // We won't modify r4 beyond this point. It currently points to the next2163 // register to be spilled.2164 unsigned R4BaseReg = NextReg;2165 2166 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.2167 if (NumAlignedDPRCS2Regs >= 4) {2168 MCRegister SupReg =2169 TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QQPRRegClass);2170 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)2171 .addReg(ARM::R4)2172 .addImm(16)2173 .addReg(SupReg, RegState::ImplicitDefine)2174 .add(predOps(ARMCC::AL));2175 NextReg += 4;2176 NumAlignedDPRCS2Regs -= 4;2177 }2178 2179 // 16-byte aligned vld1.64 with 2 d-regs.2180 if (NumAlignedDPRCS2Regs >= 2) {2181 MCRegister SupReg =2182 TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, &ARM::QPRRegClass);2183 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)2184 .addReg(ARM::R4)2185 .addImm(16)2186 .add(predOps(ARMCC::AL));2187 NextReg += 2;2188 NumAlignedDPRCS2Regs -= 2;2189 }2190 2191 // Finally, use a vanilla vldr.64 for the remaining odd register.2192 if (NumAlignedDPRCS2Regs)2193 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)2194 .addReg(ARM::R4)2195 .addImm(2 * (NextReg - R4BaseReg))2196 .add(predOps(ARMCC::AL));2197 2198 // Last store kills r4.2199 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);2200}2201 2202bool ARMFrameLowering::spillCalleeSavedRegisters(2203 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,2204 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {2205 if (CSI.empty())2206 return false;2207 2208 MachineFunction &MF = *MBB.getParent();2209 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();2210 ARMSubtarget::PushPopSplitVariation PushPopSplit =2211 STI.getPushPopSplitVariation(MF);2212 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();2213 2214 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;2215 unsigned PushOneOpc = AFI->isThumbFunction() ?2216 ARM::t2STR_PRE : ARM::STR_PRE_IMM;2217 unsigned FltOpc = ARM::VSTMDDB_UPD;2218 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();2219 // Compute PAC in R12.2220 if (AFI->shouldSignReturnAddress()) {2221 BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::t2PAC))2222 .setMIFlags(MachineInstr::FrameSetup);2223 }2224 // Save the non-secure floating point context.2225 if (llvm::any_of(CSI, [](const CalleeSavedInfo &C) {2226 return C.getReg() == ARM::FPCXTNS;2227 })) {2228 BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::VSTR_FPCXTNS_pre),2229 ARM::SP)2230 .addReg(ARM::SP)2231 .addImm(-4)2232 .add(predOps(ARMCC::AL));2233 }2234 2235 auto CheckRegArea = [PushPopSplit, NumAlignedDPRCS2Regs,2236 RegInfo](unsigned Reg, SpillArea TestArea) {2237 return getSpillArea(Reg, PushPopSplit, NumAlignedDPRCS2Regs, RegInfo) ==2238 TestArea;2239 };2240 auto IsGPRCS1 = [&CheckRegArea](unsigned Reg) {2241 return CheckRegArea(Reg, SpillArea::GPRCS1);2242 };2243 auto IsGPRCS2 = [&CheckRegArea](unsigned Reg) {2244 return CheckRegArea(Reg, SpillArea::GPRCS2);2245 };2246 auto IsDPRCS1 = [&CheckRegArea](unsigned Reg) {2247 return CheckRegArea(Reg, SpillArea::DPRCS1);2248 };2249 auto IsGPRCS3 = [&CheckRegArea](unsigned Reg) {2250 return CheckRegArea(Reg, SpillArea::GPRCS3);2251 };2252 2253 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, IsGPRCS1);2254 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, IsGPRCS2);2255 emitFPStatusSaves(MBB, MI, CSI, PushOpc);2256 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, IsDPRCS1);2257 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, IsGPRCS3);2258 2259 // The code above does not insert spill code for the aligned DPRCS2 registers.2260 // The stack realignment code will be inserted between the push instructions2261 // and these spills.2262 if (NumAlignedDPRCS2Regs)2263 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);2264 2265 return true;2266}2267 2268bool ARMFrameLowering::restoreCalleeSavedRegisters(2269 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,2270 MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {2271 if (CSI.empty())2272 return false;2273 2274 MachineFunction &MF = *MBB.getParent();2275 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();2276 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();2277 2278 bool isVarArg = AFI->getArgRegsSaveSize() > 0;2279 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();2280 ARMSubtarget::PushPopSplitVariation PushPopSplit =2281 STI.getPushPopSplitVariation(MF);2282 2283 // The emitPopInst calls below do not insert reloads for the aligned DPRCS22284 // registers. Do that here instead.2285 if (NumAlignedDPRCS2Regs)2286 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);2287 2288 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;2289 unsigned LdrOpc =2290 AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;2291 unsigned FltOpc = ARM::VLDMDIA_UPD;2292 2293 auto CheckRegArea = [PushPopSplit, NumAlignedDPRCS2Regs,2294 RegInfo](unsigned Reg, SpillArea TestArea) {2295 return getSpillArea(Reg, PushPopSplit, NumAlignedDPRCS2Regs, RegInfo) ==2296 TestArea;2297 };2298 auto IsGPRCS1 = [&CheckRegArea](unsigned Reg) {2299 return CheckRegArea(Reg, SpillArea::GPRCS1);2300 };2301 auto IsGPRCS2 = [&CheckRegArea](unsigned Reg) {2302 return CheckRegArea(Reg, SpillArea::GPRCS2);2303 };2304 auto IsDPRCS1 = [&CheckRegArea](unsigned Reg) {2305 return CheckRegArea(Reg, SpillArea::DPRCS1);2306 };2307 auto IsGPRCS3 = [&CheckRegArea](unsigned Reg) {2308 return CheckRegArea(Reg, SpillArea::GPRCS3);2309 };2310 2311 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, IsGPRCS3);2312 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, IsDPRCS1);2313 emitFPStatusRestores(MBB, MI, CSI, PopOpc);2314 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, IsGPRCS2);2315 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, IsGPRCS1);2316 2317 return true;2318}2319 2320// FIXME: Make generic?2321static unsigned EstimateFunctionSizeInBytes(const MachineFunction &MF,2322 const ARMBaseInstrInfo &TII) {2323 unsigned FnSize = 0;2324 for (auto &MBB : MF) {2325 for (auto &MI : MBB)2326 FnSize += TII.getInstSizeInBytes(MI);2327 }2328 if (MF.getJumpTableInfo())2329 for (auto &Table: MF.getJumpTableInfo()->getJumpTables())2330 FnSize += Table.MBBs.size() * 4;2331 FnSize += MF.getConstantPool()->getConstants().size() * 4;2332 return FnSize;2333}2334 2335/// estimateRSStackSizeLimit - Look at each instruction that references stack2336/// frames and return the stack size limit beyond which some of these2337/// instructions will require a scratch register during their expansion later.2338// FIXME: Move to TII?2339static unsigned estimateRSStackSizeLimit(MachineFunction &MF,2340 const TargetFrameLowering *TFI,2341 bool &HasNonSPFrameIndex) {2342 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();2343 const ARMBaseInstrInfo &TII =2344 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());2345 unsigned Limit = (1 << 12) - 1;2346 for (auto &MBB : MF) {2347 for (auto &MI : MBB) {2348 if (MI.isDebugInstr())2349 continue;2350 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {2351 if (!MI.getOperand(i).isFI())2352 continue;2353 2354 // When using ADDri to get the address of a stack object, 255 is the2355 // largest offset guaranteed to fit in the immediate offset.2356 if (MI.getOpcode() == ARM::ADDri) {2357 Limit = std::min(Limit, (1U << 8) - 1);2358 break;2359 }2360 // t2ADDri will not require an extra register, it can reuse the2361 // destination.2362 if (MI.getOpcode() == ARM::t2ADDri || MI.getOpcode() == ARM::t2ADDri12)2363 break;2364 2365 const MCInstrDesc &MCID = MI.getDesc();2366 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i);2367 if (RegClass && !RegClass->contains(ARM::SP))2368 HasNonSPFrameIndex = true;2369 2370 // Otherwise check the addressing mode.2371 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {2372 case ARMII::AddrMode_i12:2373 case ARMII::AddrMode2:2374 // Default 12 bit limit.2375 break;2376 case ARMII::AddrMode3:2377 case ARMII::AddrModeT2_i8neg:2378 Limit = std::min(Limit, (1U << 8) - 1);2379 break;2380 case ARMII::AddrMode5FP16:2381 Limit = std::min(Limit, ((1U << 8) - 1) * 2);2382 break;2383 case ARMII::AddrMode5:2384 case ARMII::AddrModeT2_i8s4:2385 case ARMII::AddrModeT2_ldrex:2386 Limit = std::min(Limit, ((1U << 8) - 1) * 4);2387 break;2388 case ARMII::AddrModeT2_i12:2389 // i12 supports only positive offset so these will be converted to2390 // i8 opcodes. See llvm::rewriteT2FrameIndex.2391 if (TFI->hasFP(MF) && AFI->hasStackFrame())2392 Limit = std::min(Limit, (1U << 8) - 1);2393 break;2394 case ARMII::AddrMode4:2395 case ARMII::AddrMode6:2396 // Addressing modes 4 & 6 (load/store) instructions can't encode an2397 // immediate offset for stack references.2398 return 0;2399 case ARMII::AddrModeT2_i7:2400 Limit = std::min(Limit, ((1U << 7) - 1) * 1);2401 break;2402 case ARMII::AddrModeT2_i7s2:2403 Limit = std::min(Limit, ((1U << 7) - 1) * 2);2404 break;2405 case ARMII::AddrModeT2_i7s4:2406 Limit = std::min(Limit, ((1U << 7) - 1) * 4);2407 break;2408 default:2409 llvm_unreachable("Unhandled addressing mode in stack size limit calculation");2410 }2411 break; // At most one FI per instruction2412 }2413 }2414 }2415 2416 return Limit;2417}2418 2419// In functions that realign the stack, it can be an advantage to spill the2420// callee-saved vector registers after realigning the stack. The vst1 and vld12421// instructions take alignment hints that can improve performance.2422static void2423checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {2424 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);2425 if (!SpillAlignedNEONRegs)2426 return;2427 2428 // Naked functions don't spill callee-saved registers.2429 if (MF.getFunction().hasFnAttribute(Attribute::Naked))2430 return;2431 2432 // We are planning to use NEON instructions vst1 / vld1.2433 if (!MF.getSubtarget<ARMSubtarget>().hasNEON())2434 return;2435 2436 // Don't bother if the default stack alignment is sufficiently high.2437 if (MF.getSubtarget().getFrameLowering()->getStackAlign() >= Align(8))2438 return;2439 2440 // Aligned spills require stack realignment.2441 if (!static_cast<const ARMBaseRegisterInfo *>(2442 MF.getSubtarget().getRegisterInfo())->canRealignStack(MF))2443 return;2444 2445 // We always spill contiguous d-registers starting from d8. Count how many2446 // needs spilling. The register allocator will almost always use the2447 // callee-saved registers in order, but it can happen that there are holes in2448 // the range. Registers above the hole will be spilled to the standard DPRCS2449 // area.2450 unsigned NumSpills = 0;2451 for (; NumSpills < 8; ++NumSpills)2452 if (!SavedRegs.test(ARM::D8 + NumSpills))2453 break;2454 2455 // Don't do this for just one d-register. It's not worth it.2456 if (NumSpills < 2)2457 return;2458 2459 // Spill the first NumSpills D-registers after realigning the stack.2460 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);2461 2462 // A scratch register is required for the vst1 / vld1 instructions.2463 SavedRegs.set(ARM::R4);2464}2465 2466bool ARMFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {2467 // For CMSE entry functions, we want to save the FPCXT_NS immediately2468 // upon function entry (resp. restore it immmediately before return)2469 if (STI.hasV8_1MMainlineOps() &&2470 MF.getInfo<ARMFunctionInfo>()->isCmseNSEntryFunction())2471 return false;2472 2473 // We are disabling shrinkwrapping for now when PAC is enabled, as2474 // shrinkwrapping can cause clobbering of r12 when the PAC code is2475 // generated. A follow-up patch will fix this in a more performant manner.2476 if (MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(2477 true /* SpillsLR */))2478 return false;2479 2480 return true;2481}2482 2483bool ARMFrameLowering::requiresAAPCSFrameRecord(2484 const MachineFunction &MF) const {2485 const auto &Subtarget = MF.getSubtarget<ARMSubtarget>();2486 return Subtarget.createAAPCSFrameChain() && hasFP(MF);2487}2488 2489// Thumb1 may require a spill when storing to a frame index through FP (or any2490// access with execute-only), for cases where FP is a high register (R11). This2491// scans the function for cases where this may happen.2492static bool canSpillOnFrameIndexAccess(const MachineFunction &MF,2493 const TargetFrameLowering &TFI) {2494 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();2495 if (!AFI->isThumb1OnlyFunction())2496 return false;2497 2498 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();2499 for (const auto &MBB : MF)2500 for (const auto &MI : MBB)2501 if (MI.getOpcode() == ARM::tSTRspi || MI.getOpcode() == ARM::tSTRi ||2502 STI.genExecuteOnly())2503 for (const auto &Op : MI.operands())2504 if (Op.isFI()) {2505 Register Reg;2506 TFI.getFrameIndexReference(MF, Op.getIndex(), Reg);2507 if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::SP)2508 return true;2509 }2510 return false;2511}2512 2513void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,2514 BitVector &SavedRegs,2515 RegScavenger *RS) const {2516 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);2517 // This tells PEI to spill the FP as if it is any other callee-save register2518 // to take advantage the eliminateFrameIndex machinery. This also ensures it2519 // is spilled in the order specified by getCalleeSavedRegs() to make it easier2520 // to combine multiple loads / stores.2521 bool CanEliminateFrame = !(requiresAAPCSFrameRecord(MF) && hasFP(MF)) &&2522 !MF.getTarget().Options.DisableFramePointerElim(MF);2523 bool CS1Spilled = false;2524 bool LRSpilled = false;2525 unsigned NumGPRSpills = 0;2526 unsigned NumFPRSpills = 0;2527 SmallVector<unsigned, 4> UnspilledCS1GPRs;2528 SmallVector<unsigned, 4> UnspilledCS2GPRs;2529 const Function &F = MF.getFunction();2530 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(2531 MF.getSubtarget().getRegisterInfo());2532 const ARMBaseInstrInfo &TII =2533 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());2534 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();2535 MachineFrameInfo &MFI = MF.getFrameInfo();2536 MachineRegisterInfo &MRI = MF.getRegInfo();2537 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();2538 (void)TRI; // Silence unused warning in non-assert builds.2539 Register FramePtr = STI.getFramePointerReg();2540 ARMSubtarget::PushPopSplitVariation PushPopSplit =2541 STI.getPushPopSplitVariation(MF);2542 2543 // For a floating point interrupt, save these registers always, since LLVM2544 // currently doesn't model reads/writes to these registers.2545 if (F.hasFnAttribute("interrupt") && F.hasFnAttribute("save-fp")) {2546 SavedRegs.set(ARM::FPSCR);2547 SavedRegs.set(ARM::R4);2548 2549 // This register will only be present on non-MClass registers.2550 if (STI.isMClass()) {2551 SavedRegs.reset(ARM::FPEXC);2552 } else {2553 SavedRegs.set(ARM::FPEXC);2554 SavedRegs.set(ARM::R5);2555 }2556 }2557 2558 // Spill R4 if Thumb2 function requires stack realignment - it will be used as2559 // scratch register. Also spill R4 if Thumb2 function has varsized objects,2560 // since it's not always possible to restore sp from fp in a single2561 // instruction.2562 // FIXME: It will be better just to find spare register here.2563 if (AFI->isThumb2Function() &&2564 (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF)))2565 SavedRegs.set(ARM::R4);2566 2567 // If a stack probe will be emitted, spill R4 and LR, since they are2568 // clobbered by the stack probe call.2569 // This estimate should be a safe, conservative estimate. The actual2570 // stack probe is enabled based on the size of the local objects;2571 // this estimate also includes the varargs store size.2572 if (STI.isTargetWindows() &&2573 WindowsRequiresStackProbe(MF, MFI.estimateStackSize(MF))) {2574 SavedRegs.set(ARM::R4);2575 SavedRegs.set(ARM::LR);2576 }2577 2578 if (AFI->isThumb1OnlyFunction()) {2579 // Spill LR if Thumb1 function uses variable length argument lists.2580 if (AFI->getArgRegsSaveSize() > 0)2581 SavedRegs.set(ARM::LR);2582 2583 // Spill R4 if Thumb1 epilogue has to restore SP from FP or the function2584 // requires stack alignment. We don't know for sure what the stack size2585 // will be, but for this, an estimate is good enough. If there anything2586 // changes it, it'll be a spill, which implies we've used all the registers2587 // and so R4 is already used, so not marking it here will be OK.2588 // FIXME: It will be better just to find spare register here.2589 if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF) ||2590 MFI.estimateStackSize(MF) > 508)2591 SavedRegs.set(ARM::R4);2592 }2593 2594 // See if we can spill vector registers to aligned stack.2595 checkNumAlignedDPRCS2Regs(MF, SavedRegs);2596 2597 // Spill the BasePtr if it's used.2598 if (RegInfo->hasBasePointer(MF))2599 SavedRegs.set(RegInfo->getBaseRegister());2600 2601 // On v8.1-M.Main CMSE entry functions save/restore FPCXT.2602 if (STI.hasV8_1MMainlineOps() && AFI->isCmseNSEntryFunction())2603 CanEliminateFrame = false;2604 2605 // When return address signing is enabled R12 is treated as callee-saved.2606 if (AFI->shouldSignReturnAddress())2607 CanEliminateFrame = false;2608 2609 // Don't spill FP if the frame can be eliminated. This is determined2610 // by scanning the callee-save registers to see if any is modified.2611 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);2612 for (unsigned i = 0; CSRegs[i]; ++i) {2613 unsigned Reg = CSRegs[i];2614 bool Spilled = false;2615 if (SavedRegs.test(Reg)) {2616 Spilled = true;2617 CanEliminateFrame = false;2618 }2619 2620 if (!ARM::GPRRegClass.contains(Reg)) {2621 if (Spilled) {2622 if (ARM::SPRRegClass.contains(Reg))2623 NumFPRSpills++;2624 else if (ARM::DPRRegClass.contains(Reg))2625 NumFPRSpills += 2;2626 else if (ARM::QPRRegClass.contains(Reg))2627 NumFPRSpills += 4;2628 }2629 continue;2630 }2631 2632 if (Spilled) {2633 NumGPRSpills++;2634 2635 if (PushPopSplit != ARMSubtarget::SplitR7) {2636 if (Reg == ARM::LR)2637 LRSpilled = true;2638 CS1Spilled = true;2639 continue;2640 }2641 2642 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.2643 switch (Reg) {2644 case ARM::LR:2645 LRSpilled = true;2646 [[fallthrough]];2647 case ARM::R0: case ARM::R1:2648 case ARM::R2: case ARM::R3:2649 case ARM::R4: case ARM::R5:2650 case ARM::R6: case ARM::R7:2651 CS1Spilled = true;2652 break;2653 default:2654 break;2655 }2656 } else {2657 if (PushPopSplit != ARMSubtarget::SplitR7) {2658 UnspilledCS1GPRs.push_back(Reg);2659 continue;2660 }2661 2662 switch (Reg) {2663 case ARM::R0: case ARM::R1:2664 case ARM::R2: case ARM::R3:2665 case ARM::R4: case ARM::R5:2666 case ARM::R6: case ARM::R7:2667 case ARM::LR:2668 UnspilledCS1GPRs.push_back(Reg);2669 break;2670 default:2671 UnspilledCS2GPRs.push_back(Reg);2672 break;2673 }2674 }2675 }2676 2677 bool ForceLRSpill = false;2678 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {2679 unsigned FnSize = EstimateFunctionSizeInBytes(MF, TII);2680 // Force LR to be spilled if the Thumb function size is > 2048. This enables2681 // use of BL to implement far jump.2682 if (FnSize >= (1 << 11)) {2683 CanEliminateFrame = false;2684 ForceLRSpill = true;2685 }2686 }2687 2688 // If any of the stack slot references may be out of range of an immediate2689 // offset, make sure a register (or a spill slot) is available for the2690 // register scavenger. Note that if we're indexing off the frame pointer, the2691 // effective stack size is 4 bytes larger since the FP points to the stack2692 // slot of the previous FP. Also, if we have variable sized objects in the2693 // function, stack slot references will often be negative, and some of2694 // our instructions are positive-offset only, so conservatively consider2695 // that case to want a spill slot (or register) as well. Similarly, if2696 // the function adjusts the stack pointer during execution and the2697 // adjustments aren't already part of our stack size estimate, our offset2698 // calculations may be off, so be conservative.2699 // FIXME: We could add logic to be more precise about negative offsets2700 // and which instructions will need a scratch register for them. Is it2701 // worth the effort and added fragility?2702 unsigned EstimatedStackSize =2703 MFI.estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills);2704 2705 // Determine biggest (positive) SP offset in MachineFrameInfo.2706 int MaxFixedOffset = 0;2707 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {2708 int MaxObjectOffset = MFI.getObjectOffset(I) + MFI.getObjectSize(I);2709 MaxFixedOffset = std::max(MaxFixedOffset, MaxObjectOffset);2710 }2711 2712 bool HasFP = hasFP(MF);2713 if (HasFP) {2714 if (AFI->hasStackFrame())2715 EstimatedStackSize += 4;2716 } else {2717 // If FP is not used, SP will be used to access arguments, so count the2718 // size of arguments into the estimation.2719 EstimatedStackSize += MaxFixedOffset;2720 }2721 EstimatedStackSize += 16; // For possible paddings.2722 2723 unsigned EstimatedRSStackSizeLimit, EstimatedRSFixedSizeLimit;2724 bool HasNonSPFrameIndex = false;2725 if (AFI->isThumb1OnlyFunction()) {2726 // For Thumb1, don't bother to iterate over the function. The only2727 // instruction that requires an emergency spill slot is a store to a2728 // frame index.2729 //2730 // tSTRspi, which is used for sp-relative accesses, has an 8-bit unsigned2731 // immediate. tSTRi, which is used for bp- and fp-relative accesses, has2732 // a 5-bit unsigned immediate.2733 //2734 // We could try to check if the function actually contains a tSTRspi2735 // that might need the spill slot, but it's not really important.2736 // Functions with VLAs or extremely large call frames are rare, and2737 // if a function is allocating more than 1KB of stack, an extra 4-byte2738 // slot probably isn't relevant.2739 //2740 // A special case is the scenario where r11 is used as FP, where accesses2741 // to a frame index will require its value to be moved into a low reg.2742 // This is handled later on, once we are able to determine if we have any2743 // fp-relative accesses.2744 if (RegInfo->hasBasePointer(MF))2745 EstimatedRSStackSizeLimit = (1U << 5) * 4;2746 else2747 EstimatedRSStackSizeLimit = (1U << 8) * 4;2748 EstimatedRSFixedSizeLimit = (1U << 5) * 4;2749 } else {2750 EstimatedRSStackSizeLimit =2751 estimateRSStackSizeLimit(MF, this, HasNonSPFrameIndex);2752 EstimatedRSFixedSizeLimit = EstimatedRSStackSizeLimit;2753 }2754 // Final estimate of whether sp or bp-relative accesses might require2755 // scavenging.2756 bool HasLargeStack = EstimatedStackSize > EstimatedRSStackSizeLimit;2757 2758 // If the stack pointer moves and we don't have a base pointer, the2759 // estimate logic doesn't work. The actual offsets might be larger when2760 // we're constructing a call frame, or we might need to use negative2761 // offsets from fp.2762 bool HasMovingSP = MFI.hasVarSizedObjects() ||2763 (MFI.adjustsStack() && !canSimplifyCallFramePseudos(MF));2764 bool HasBPOrFixedSP = RegInfo->hasBasePointer(MF) || !HasMovingSP;2765 2766 // If we have a frame pointer, we assume arguments will be accessed2767 // relative to the frame pointer. Check whether fp-relative accesses to2768 // arguments require scavenging.2769 //2770 // We could do slightly better on Thumb1; in some cases, an sp-relative2771 // offset would be legal even though an fp-relative offset is not.2772 int MaxFPOffset = getMaxFPOffset(STI, *AFI, MF);2773 bool HasLargeArgumentList =2774 HasFP && (MaxFixedOffset - MaxFPOffset) > (int)EstimatedRSFixedSizeLimit;2775 2776 bool BigFrameOffsets = HasLargeStack || !HasBPOrFixedSP ||2777 HasLargeArgumentList || HasNonSPFrameIndex;2778 LLVM_DEBUG(dbgs() << "EstimatedLimit: " << EstimatedRSStackSizeLimit2779 << "; EstimatedStack: " << EstimatedStackSize2780 << "; EstimatedFPStack: " << MaxFixedOffset - MaxFPOffset2781 << "; BigFrameOffsets: " << BigFrameOffsets << "\n");2782 if (BigFrameOffsets ||2783 !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {2784 AFI->setHasStackFrame(true);2785 2786 // Save the FP if:2787 // 1. We currently need it (HasFP), OR2788 // 2. We might need it later due to stack realignment from aligned DPRCS22789 // saves (which will make hasFP() become true in emitPrologue).2790 if (HasFP || (isFPReserved(MF) && AFI->getNumAlignedDPRCS2Regs() > 0)) {2791 SavedRegs.set(FramePtr);2792 // If the frame pointer is required by the ABI, also spill LR so that we2793 // emit a complete frame record.2794 if ((requiresAAPCSFrameRecord(MF) ||2795 MF.getTarget().Options.DisableFramePointerElim(MF)) &&2796 !LRSpilled) {2797 SavedRegs.set(ARM::LR);2798 LRSpilled = true;2799 NumGPRSpills++;2800 auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR);2801 if (LRPos != UnspilledCS1GPRs.end())2802 UnspilledCS1GPRs.erase(LRPos);2803 }2804 auto FPPos = llvm::find(UnspilledCS1GPRs, FramePtr);2805 if (FPPos != UnspilledCS1GPRs.end())2806 UnspilledCS1GPRs.erase(FPPos);2807 NumGPRSpills++;2808 if (FramePtr == ARM::R7)2809 CS1Spilled = true;2810 }2811 2812 // This is the number of extra spills inserted for callee-save GPRs which2813 // would not otherwise be used by the function. When greater than zero it2814 // guaranteees that it is possible to scavenge a register to hold the2815 // address of a stack slot. On Thumb1, the register must be a valid operand2816 // to tSTRi, i.e. r4-r7. For other subtargets, this is any GPR, i.e. r4-r112817 // or lr.2818 //2819 // If we don't insert a spill, we instead allocate an emergency spill2820 // slot, which can be used by scavenging to spill an arbitrary register.2821 //2822 // We currently don't try to figure out whether any specific instruction2823 // requires scavening an additional register.2824 unsigned NumExtraCSSpill = 0;2825 2826 if (AFI->isThumb1OnlyFunction()) {2827 // For Thumb1-only targets, we need some low registers when we save and2828 // restore the high registers (which aren't allocatable, but could be2829 // used by inline assembly) because the push/pop instructions can not2830 // access high registers. If necessary, we might need to push more low2831 // registers to ensure that there is at least one free that can be used2832 // for the saving & restoring, and preferably we should ensure that as2833 // many as are needed are available so that fewer push/pop instructions2834 // are required.2835 2836 // Low registers which are not currently pushed, but could be (r4-r7).2837 SmallVector<unsigned, 4> AvailableRegs;2838 2839 // Unused argument registers (r0-r3) can be clobbered in the prologue for2840 // free.2841 int EntryRegDeficit = 0;2842 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {2843 if (!MF.getRegInfo().isLiveIn(Reg)) {2844 --EntryRegDeficit;2845 LLVM_DEBUG(dbgs()2846 << printReg(Reg, TRI)2847 << " is unused argument register, EntryRegDeficit = "2848 << EntryRegDeficit << "\n");2849 }2850 }2851 2852 // Unused return registers can be clobbered in the epilogue for free.2853 int ExitRegDeficit = AFI->getReturnRegsCount() - 4;2854 LLVM_DEBUG(dbgs() << AFI->getReturnRegsCount()2855 << " return regs used, ExitRegDeficit = "2856 << ExitRegDeficit << "\n");2857 2858 int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit);2859 LLVM_DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n");2860 2861 // r4-r6 can be used in the prologue if they are pushed by the first push2862 // instruction.2863 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {2864 if (SavedRegs.test(Reg)) {2865 --RegDeficit;2866 LLVM_DEBUG(dbgs() << printReg(Reg, TRI)2867 << " is saved low register, RegDeficit = "2868 << RegDeficit << "\n");2869 } else {2870 AvailableRegs.push_back(Reg);2871 LLVM_DEBUG(2872 dbgs()2873 << printReg(Reg, TRI)2874 << " is non-saved low register, adding to AvailableRegs\n");2875 }2876 }2877 2878 // r7 can be used if it is not being used as the frame pointer.2879 if (!HasFP || FramePtr != ARM::R7) {2880 if (SavedRegs.test(ARM::R7)) {2881 --RegDeficit;2882 LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "2883 << RegDeficit << "\n");2884 } else {2885 AvailableRegs.push_back(ARM::R7);2886 LLVM_DEBUG(2887 dbgs()2888 << "%r7 is non-saved low register, adding to AvailableRegs\n");2889 }2890 }2891 2892 // Each of r8-r11 needs to be copied to a low register, then pushed.2893 for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) {2894 if (SavedRegs.test(Reg)) {2895 ++RegDeficit;2896 LLVM_DEBUG(dbgs() << printReg(Reg, TRI)2897 << " is saved high register, RegDeficit = "2898 << RegDeficit << "\n");2899 }2900 }2901 2902 // LR can only be used by PUSH, not POP, and can't be used at all if the2903 // llvm.returnaddress intrinsic is used. This is only worth doing if we2904 // are more limited at function entry than exit.2905 if ((EntryRegDeficit > ExitRegDeficit) &&2906 !(MF.getRegInfo().isLiveIn(ARM::LR) &&2907 MF.getFrameInfo().isReturnAddressTaken())) {2908 if (SavedRegs.test(ARM::LR)) {2909 --RegDeficit;2910 LLVM_DEBUG(dbgs() << "%lr is saved register, RegDeficit = "2911 << RegDeficit << "\n");2912 } else {2913 AvailableRegs.push_back(ARM::LR);2914 LLVM_DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n");2915 }2916 }2917 2918 // If there are more high registers that need pushing than low registers2919 // available, push some more low registers so that we can use fewer push2920 // instructions. This might not reduce RegDeficit all the way to zero,2921 // because we can only guarantee that r4-r6 are available, but r8-r11 may2922 // need saving.2923 LLVM_DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n");2924 for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) {2925 unsigned Reg = AvailableRegs.pop_back_val();2926 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)2927 << " to make up reg deficit\n");2928 SavedRegs.set(Reg);2929 NumGPRSpills++;2930 CS1Spilled = true;2931 assert(!MRI.isReserved(Reg) && "Should not be reserved");2932 if (Reg != ARM::LR && !MRI.isPhysRegUsed(Reg))2933 NumExtraCSSpill++;2934 UnspilledCS1GPRs.erase(llvm::find(UnspilledCS1GPRs, Reg));2935 if (Reg == ARM::LR)2936 LRSpilled = true;2937 }2938 LLVM_DEBUG(dbgs() << "After adding spills, RegDeficit = " << RegDeficit2939 << "\n");2940 }2941 2942 // Avoid spilling LR in Thumb1 if there's a tail call: it's expensive to2943 // restore LR in that case.2944 bool ExpensiveLRRestore = AFI->isThumb1OnlyFunction() && MFI.hasTailCall();2945 2946 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.2947 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).2948 if (!LRSpilled && CS1Spilled && !ExpensiveLRRestore) {2949 SavedRegs.set(ARM::LR);2950 NumGPRSpills++;2951 SmallVectorImpl<unsigned>::iterator LRPos;2952 LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR);2953 if (LRPos != UnspilledCS1GPRs.end())2954 UnspilledCS1GPRs.erase(LRPos);2955 2956 ForceLRSpill = false;2957 if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR) &&2958 !AFI->isThumb1OnlyFunction())2959 NumExtraCSSpill++;2960 }2961 2962 // If stack and double are 8-byte aligned and we are spilling an odd number2963 // of GPRs, spill one extra callee save GPR so we won't have to pad between2964 // the integer and double callee save areas.2965 LLVM_DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n");2966 const Align TargetAlign = getStackAlign();2967 if (TargetAlign >= Align(8) && (NumGPRSpills & 1)) {2968 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {2969 for (unsigned Reg : UnspilledCS1GPRs) {2970 // Don't spill high register if the function is thumb. In the case of2971 // Windows on ARM, accept R11 (frame pointer)2972 if (!AFI->isThumbFunction() ||2973 (STI.isTargetWindows() && Reg == ARM::R11) ||2974 isARMLowRegister(Reg) ||2975 (Reg == ARM::LR && !ExpensiveLRRestore)) {2976 SavedRegs.set(Reg);2977 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)2978 << " to make up alignment\n");2979 if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg) &&2980 !(Reg == ARM::LR && AFI->isThumb1OnlyFunction()))2981 NumExtraCSSpill++;2982 break;2983 }2984 }2985 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {2986 unsigned Reg = UnspilledCS2GPRs.front();2987 SavedRegs.set(Reg);2988 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)2989 << " to make up alignment\n");2990 if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))2991 NumExtraCSSpill++;2992 }2993 }2994 2995 // Estimate if we might need to scavenge registers at some point in order2996 // to materialize a stack offset. If so, either spill one additional2997 // callee-saved register or reserve a special spill slot to facilitate2998 // register scavenging. Thumb1 needs a spill slot for stack pointer2999 // adjustments and for frame index accesses when FP is high register,3000 // even when the frame itself is small.3001 unsigned RegsNeeded = 0;3002 if (BigFrameOffsets || canSpillOnFrameIndexAccess(MF, *this)) {3003 RegsNeeded++;3004 // With thumb1 execute-only we may need an additional register for saving3005 // and restoring the CPSR.3006 if (AFI->isThumb1OnlyFunction() && STI.genExecuteOnly() && !STI.useMovt())3007 RegsNeeded++;3008 }3009 3010 if (RegsNeeded > NumExtraCSSpill) {3011 // If any non-reserved CS register isn't spilled, just spill one or two3012 // extra. That should take care of it!3013 unsigned NumExtras = TargetAlign.value() / 4;3014 SmallVector<unsigned, 2> Extras;3015 while (NumExtras && !UnspilledCS1GPRs.empty()) {3016 unsigned Reg = UnspilledCS1GPRs.pop_back_val();3017 if (!MRI.isReserved(Reg) &&3018 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg))) {3019 Extras.push_back(Reg);3020 NumExtras--;3021 }3022 }3023 // For non-Thumb1 functions, also check for hi-reg CS registers3024 if (!AFI->isThumb1OnlyFunction()) {3025 while (NumExtras && !UnspilledCS2GPRs.empty()) {3026 unsigned Reg = UnspilledCS2GPRs.pop_back_val();3027 if (!MRI.isReserved(Reg)) {3028 Extras.push_back(Reg);3029 NumExtras--;3030 }3031 }3032 }3033 if (NumExtras == 0) {3034 for (unsigned Reg : Extras) {3035 SavedRegs.set(Reg);3036 if (!MRI.isPhysRegUsed(Reg))3037 NumExtraCSSpill++;3038 }3039 }3040 while ((RegsNeeded > NumExtraCSSpill) && RS) {3041 // Reserve a slot closest to SP or frame pointer.3042 LLVM_DEBUG(dbgs() << "Reserving emergency spill slot\n");3043 const TargetRegisterClass &RC = ARM::GPRRegClass;3044 unsigned Size = TRI->getSpillSize(RC);3045 Align Alignment = TRI->getSpillAlign(RC);3046 RS->addScavengingFrameIndex(3047 MFI.CreateSpillStackObject(Size, Alignment));3048 --RegsNeeded;3049 }3050 }3051 }3052 3053 if (ForceLRSpill)3054 SavedRegs.set(ARM::LR);3055 AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));3056}3057 3058void ARMFrameLowering::updateLRRestored(MachineFunction &MF) {3059 MachineFrameInfo &MFI = MF.getFrameInfo();3060 if (!MFI.isCalleeSavedInfoValid())3061 return;3062 3063 // Check if all terminators do not implicitly use LR. Then we can 'restore' LR3064 // into PC so it is not live out of the return block: Clear the Restored bit3065 // in that case.3066 for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {3067 if (Info.getReg() != ARM::LR)3068 continue;3069 if (all_of(MF, [](const MachineBasicBlock &MBB) {3070 return all_of(MBB.terminators(), [](const MachineInstr &Term) {3071 return !Term.isReturn() || Term.getOpcode() == ARM::LDMIA_RET ||3072 Term.getOpcode() == ARM::t2LDMIA_RET ||3073 Term.getOpcode() == ARM::tPOP_RET;3074 });3075 })) {3076 Info.setRestored(false);3077 break;3078 }3079 }3080}3081 3082void ARMFrameLowering::processFunctionBeforeFrameFinalized(3083 MachineFunction &MF, RegScavenger *RS) const {3084 TargetFrameLowering::processFunctionBeforeFrameFinalized(MF, RS);3085 updateLRRestored(MF);3086}3087 3088void ARMFrameLowering::getCalleeSaves(const MachineFunction &MF,3089 BitVector &SavedRegs) const {3090 TargetFrameLowering::getCalleeSaves(MF, SavedRegs);3091 3092 // If we have the "returned" parameter attribute which guarantees that we3093 // return the value which was passed in r0 unmodified (e.g. C++ 'structors),3094 // record that fact for IPRA.3095 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();3096 if (AFI->getPreservesR0())3097 SavedRegs.set(ARM::R0);3098}3099 3100bool ARMFrameLowering::assignCalleeSavedSpillSlots(3101 MachineFunction &MF, const TargetRegisterInfo *TRI,3102 std::vector<CalleeSavedInfo> &CSI) const {3103 // For CMSE entry functions, handle floating-point context as if it was a3104 // callee-saved register.3105 if (STI.hasV8_1MMainlineOps() &&3106 MF.getInfo<ARMFunctionInfo>()->isCmseNSEntryFunction()) {3107 CSI.emplace_back(ARM::FPCXTNS);3108 CSI.back().setRestored(false);3109 }3110 3111 // For functions, which sign their return address, upon function entry, the3112 // return address PAC is computed in R12. Treat R12 as a callee-saved register3113 // in this case.3114 const auto &AFI = *MF.getInfo<ARMFunctionInfo>();3115 if (AFI.shouldSignReturnAddress()) {3116 // The order of register must match the order we push them, because the3117 // PEI assigns frame indices in that order. That order depends on the3118 // PushPopSplitVariation, there are only two cases which we use with return3119 // address signing:3120 switch (STI.getPushPopSplitVariation(MF)) {3121 case ARMSubtarget::SplitR7:3122 // LR, R7, R6, R5, R4, <R12>, R11, R10, R9, R8, D15-D83123 CSI.insert(find_if(CSI,3124 [=](const auto &CS) {3125 MCRegister Reg = CS.getReg();3126 return Reg == ARM::R10 || Reg == ARM::R11 ||3127 Reg == ARM::R8 || Reg == ARM::R9 ||3128 ARM::DPRRegClass.contains(Reg);3129 }),3130 CalleeSavedInfo(ARM::R12));3131 break;3132 case ARMSubtarget::SplitR11AAPCSSignRA:3133 // With SplitR11AAPCSSignRA, R12 will always be the highest-addressed CSR3134 // on the stack.3135 CSI.insert(CSI.begin(), CalleeSavedInfo(ARM::R12));3136 break;3137 case ARMSubtarget::NoSplit:3138 assert(!MF.getTarget().Options.DisableFramePointerElim(MF) &&3139 "ABI-required frame pointers need a CSR split when signing return "3140 "address.");3141 CSI.insert(find_if(CSI,3142 [=](const auto &CS) {3143 MCRegister Reg = CS.getReg();3144 return Reg != ARM::LR;3145 }),3146 CalleeSavedInfo(ARM::R12));3147 break;3148 default:3149 llvm_unreachable("Unexpected CSR split with return address signing");3150 }3151 }3152 3153 return false;3154}3155 3156const TargetFrameLowering::SpillSlot *3157ARMFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {3158 static const SpillSlot FixedSpillOffsets[] = {{ARM::FPCXTNS, -4}};3159 NumEntries = std::size(FixedSpillOffsets);3160 return FixedSpillOffsets;3161}3162 3163MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr(3164 MachineFunction &MF, MachineBasicBlock &MBB,3165 MachineBasicBlock::iterator I) const {3166 const ARMBaseInstrInfo &TII =3167 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());3168 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();3169 bool isARM = !AFI->isThumbFunction();3170 DebugLoc dl = I->getDebugLoc();3171 unsigned Opc = I->getOpcode();3172 bool IsDestroy = Opc == TII.getCallFrameDestroyOpcode();3173 unsigned CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;3174 3175 assert(!AFI->isThumb1OnlyFunction() &&3176 "This eliminateCallFramePseudoInstr does not support Thumb1!");3177 3178 int PIdx = I->findFirstPredOperandIdx();3179 ARMCC::CondCodes Pred = (PIdx == -1)3180 ? ARMCC::AL3181 : (ARMCC::CondCodes)I->getOperand(PIdx).getImm();3182 unsigned PredReg = TII.getFramePred(*I);3183 3184 if (!hasReservedCallFrame(MF)) {3185 // Bail early if the callee is expected to do the adjustment.3186 if (IsDestroy && CalleePopAmount != -1U)3187 return MBB.erase(I);3188 3189 // If we have alloca, convert as follows:3190 // ADJCALLSTACKDOWN -> sub, sp, sp, amount3191 // ADJCALLSTACKUP -> add, sp, sp, amount3192 unsigned Amount = TII.getFrameSize(*I);3193 if (Amount != 0) {3194 // We need to keep the stack aligned properly. To do this, we round the3195 // amount of space needed for the outgoing arguments up to the next3196 // alignment boundary.3197 Amount = alignSPAdjust(Amount);3198 3199 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {3200 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,3201 Pred, PredReg);3202 } else {3203 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);3204 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,3205 Pred, PredReg);3206 }3207 }3208 } else if (CalleePopAmount != -1U) {3209 // If the calling convention demands that the callee pops arguments from the3210 // stack, we want to add it back if we have a reserved call frame.3211 emitSPUpdate(isARM, MBB, I, dl, TII, -CalleePopAmount,3212 MachineInstr::NoFlags, Pred, PredReg);3213 }3214 return MBB.erase(I);3215}3216 3217/// Get the minimum constant for ARM that is greater than or equal to the3218/// argument. In ARM, constants can have any value that can be produced by3219/// rotating an 8-bit value to the right by an even number of bits within a3220/// 32-bit word.3221static uint32_t alignToARMConstant(uint32_t Value) {3222 unsigned Shifted = 0;3223 3224 if (Value == 0)3225 return 0;3226 3227 while (!(Value & 0xC0000000)) {3228 Value = Value << 2;3229 Shifted += 2;3230 }3231 3232 bool Carry = (Value & 0x00FFFFFF);3233 Value = ((Value & 0xFF000000) >> 24) + Carry;3234 3235 if (Value & 0x0000100)3236 Value = Value & 0x000001FC;3237 3238 if (Shifted > 24)3239 Value = Value >> (Shifted - 24);3240 else3241 Value = Value << (24 - Shifted);3242 3243 return Value;3244}3245 3246// The stack limit in the TCB is set to this many bytes above the actual3247// stack limit.3248static const uint64_t kSplitStackAvailable = 256;3249 3250// Adjust the function prologue to enable split stacks. This currently only3251// supports android and linux.3252//3253// The ABI of the segmented stack prologue is a little arbitrarily chosen, but3254// must be well defined in order to allow for consistent implementations of the3255// __morestack helper function. The ABI is also not a normal ABI in that it3256// doesn't follow the normal calling conventions because this allows the3257// prologue of each function to be optimized further.3258//3259// Currently, the ABI looks like (when calling __morestack)3260//3261// * r4 holds the minimum stack size requested for this function call3262// * r5 holds the stack size of the arguments to the function3263// * the beginning of the function is 3 instructions after the call to3264// __morestack3265//3266// Implementations of __morestack should use r4 to allocate a new stack, r5 to3267// place the arguments on to the new stack, and the 3-instruction knowledge to3268// jump directly to the body of the function when working on the new stack.3269//3270// An old (and possibly no longer compatible) implementation of __morestack for3271// ARM can be found at [1].3272//3273// [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S3274void ARMFrameLowering::adjustForSegmentedStacks(3275 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {3276 unsigned Opcode;3277 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();3278 bool Thumb = ST->isThumb();3279 bool Thumb2 = ST->isThumb2();3280 3281 // Sadly, this currently doesn't support varargs, platforms other than3282 // android/linux. Note that thumb1/thumb2 are support for android/linux.3283 if (MF.getFunction().isVarArg())3284 report_fatal_error("Segmented stacks do not support vararg functions.");3285 if (!ST->isTargetAndroid() && !ST->isTargetLinux())3286 report_fatal_error("Segmented stacks not supported on this platform.");3287 3288 MachineFrameInfo &MFI = MF.getFrameInfo();3289 const ARMBaseInstrInfo &TII =3290 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());3291 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();3292 DebugLoc DL;3293 3294 if (!MFI.needsSplitStackProlog())3295 return;3296 3297 uint64_t StackSize = MFI.getStackSize();3298 3299 // Use R4 and R5 as scratch registers.3300 // We save R4 and R5 before use and restore them before leaving the function.3301 unsigned ScratchReg0 = ARM::R4;3302 unsigned ScratchReg1 = ARM::R5;3303 unsigned MovOp = ST->useMovt() ? ARM::t2MOVi32imm : ARM::tMOVi32imm;3304 uint64_t AlignedStackSize;3305 3306 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();3307 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();3308 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();3309 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();3310 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();3311 3312 // Grab everything that reaches PrologueMBB to update there liveness as well.3313 SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion;3314 SmallVector<MachineBasicBlock *, 2> WalkList;3315 WalkList.push_back(&PrologueMBB);3316 3317 do {3318 MachineBasicBlock *CurMBB = WalkList.pop_back_val();3319 for (MachineBasicBlock *PredBB : CurMBB->predecessors()) {3320 if (BeforePrologueRegion.insert(PredBB).second)3321 WalkList.push_back(PredBB);3322 }3323 } while (!WalkList.empty());3324 3325 // The order in that list is important.3326 // The blocks will all be inserted before PrologueMBB using that order.3327 // Therefore the block that should appear first in the CFG should appear3328 // first in the list.3329 MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB,3330 PostStackMBB};3331 3332 BeforePrologueRegion.insert_range(AddedBlocks);3333 3334 for (const auto &LI : PrologueMBB.liveins()) {3335 for (MachineBasicBlock *PredBB : BeforePrologueRegion)3336 PredBB->addLiveIn(LI);3337 }3338 3339 // Remove the newly added blocks from the list, since we know3340 // we do not have to do the following updates for them.3341 for (MachineBasicBlock *B : AddedBlocks) {3342 BeforePrologueRegion.erase(B);3343 MF.insert(PrologueMBB.getIterator(), B);3344 }3345 3346 for (MachineBasicBlock *MBB : BeforePrologueRegion) {3347 // Make sure the LiveIns are still sorted and unique.3348 MBB->sortUniqueLiveIns();3349 // Replace the edges to PrologueMBB by edges to the sequences3350 // we are about to add, but only update for immediate predecessors.3351 if (MBB->isSuccessor(&PrologueMBB))3352 MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]);3353 }3354 3355 // The required stack size that is aligned to ARM constant criterion.3356 AlignedStackSize = alignToARMConstant(StackSize);3357 3358 // When the frame size is less than 256 we just compare the stack3359 // boundary directly to the value of the stack pointer, per gcc.3360 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;3361 3362 // We will use two of the callee save registers as scratch registers so we3363 // need to save those registers onto the stack.3364 // We will use SR0 to hold stack limit and SR1 to hold the stack size3365 // requested and arguments for __morestack().3366 // SR0: Scratch Register #03367 // SR1: Scratch Register #13368 // push {SR0, SR1}3369 if (Thumb) {3370 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))3371 .add(predOps(ARMCC::AL))3372 .addReg(ScratchReg0)3373 .addReg(ScratchReg1);3374 } else {3375 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))3376 .addReg(ARM::SP, RegState::Define)3377 .addReg(ARM::SP)3378 .add(predOps(ARMCC::AL))3379 .addReg(ScratchReg0)3380 .addReg(ScratchReg1);3381 }3382 3383 // Emit the relevant DWARF information about the change in stack pointer as3384 // well as where to find both r4 and r5 (the callee-save registers)3385 if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {3386 CFIInstBuilder CFIBuilder(PrevStackMBB, MachineInstr::NoFlags);3387 CFIBuilder.buildDefCFAOffset(8);3388 CFIBuilder.buildOffset(ScratchReg1, -4);3389 CFIBuilder.buildOffset(ScratchReg0, -8);3390 }3391 3392 // mov SR1, sp3393 if (Thumb) {3394 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)3395 .addReg(ARM::SP)3396 .add(predOps(ARMCC::AL));3397 } else if (CompareStackPointer) {3398 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)3399 .addReg(ARM::SP)3400 .add(predOps(ARMCC::AL))3401 .add(condCodeOp());3402 }3403 3404 // sub SR1, sp, #StackSize3405 if (!CompareStackPointer && Thumb) {3406 if (AlignedStackSize < 256) {3407 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)3408 .add(condCodeOp())3409 .addReg(ScratchReg1)3410 .addImm(AlignedStackSize)3411 .add(predOps(ARMCC::AL));3412 } else {3413 if (Thumb2 || ST->genExecuteOnly()) {3414 BuildMI(McrMBB, DL, TII.get(MovOp), ScratchReg0)3415 .addImm(AlignedStackSize);3416 } else {3417 auto MBBI = McrMBB->end();3418 auto RegInfo = STI.getRegisterInfo();3419 RegInfo->emitLoadConstPool(*McrMBB, MBBI, DL, ScratchReg0, 0,3420 AlignedStackSize);3421 }3422 BuildMI(McrMBB, DL, TII.get(ARM::tSUBrr), ScratchReg1)3423 .add(condCodeOp())3424 .addReg(ScratchReg1)3425 .addReg(ScratchReg0)3426 .add(predOps(ARMCC::AL));3427 }3428 } else if (!CompareStackPointer) {3429 if (AlignedStackSize < 256) {3430 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)3431 .addReg(ARM::SP)3432 .addImm(AlignedStackSize)3433 .add(predOps(ARMCC::AL))3434 .add(condCodeOp());3435 } else {3436 auto MBBI = McrMBB->end();3437 auto RegInfo = STI.getRegisterInfo();3438 RegInfo->emitLoadConstPool(*McrMBB, MBBI, DL, ScratchReg0, 0,3439 AlignedStackSize);3440 BuildMI(McrMBB, DL, TII.get(ARM::SUBrr), ScratchReg1)3441 .addReg(ARM::SP)3442 .addReg(ScratchReg0)3443 .add(predOps(ARMCC::AL))3444 .add(condCodeOp());3445 }3446 }3447 3448 if (Thumb && ST->isThumb1Only()) {3449 if (ST->genExecuteOnly()) {3450 BuildMI(GetMBB, DL, TII.get(MovOp), ScratchReg0)3451 .addExternalSymbol("__STACK_LIMIT");3452 } else {3453 unsigned PCLabelId = ARMFI->createPICLabelUId();3454 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(3455 MF.getFunction().getContext(), "__STACK_LIMIT", PCLabelId, 0);3456 MachineConstantPool *MCP = MF.getConstantPool();3457 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, Align(4));3458 3459 // ldr SR0, [pc, offset(STACK_LIMIT)]3460 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)3461 .addConstantPoolIndex(CPI)3462 .add(predOps(ARMCC::AL));3463 }3464 3465 // ldr SR0, [SR0]3466 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)3467 .addReg(ScratchReg0)3468 .addImm(0)3469 .add(predOps(ARMCC::AL));3470 } else {3471 // Get TLS base address from the coprocessor3472 // mrc p15, #0, SR0, c13, c0, #33473 BuildMI(McrMBB, DL, TII.get(Thumb ? ARM::t2MRC : ARM::MRC),3474 ScratchReg0)3475 .addImm(15)3476 .addImm(0)3477 .addImm(13)3478 .addImm(0)3479 .addImm(3)3480 .add(predOps(ARMCC::AL));3481 3482 // Use the last tls slot on android and a private field of the TCP on linux.3483 assert(ST->isTargetAndroid() || ST->isTargetLinux());3484 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;3485 3486 // Get the stack limit from the right offset3487 // ldr SR0, [sr0, #4 * TlsOffset]3488 BuildMI(GetMBB, DL, TII.get(Thumb ? ARM::t2LDRi12 : ARM::LDRi12),3489 ScratchReg0)3490 .addReg(ScratchReg0)3491 .addImm(4 * TlsOffset)3492 .add(predOps(ARMCC::AL));3493 }3494 3495 // Compare stack limit with stack size requested.3496 // cmp SR0, SR13497 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;3498 BuildMI(GetMBB, DL, TII.get(Opcode))3499 .addReg(ScratchReg0)3500 .addReg(ScratchReg1)3501 .add(predOps(ARMCC::AL));3502 3503 // This jump is taken if StackLimit <= SP - stack required.3504 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;3505 BuildMI(GetMBB, DL, TII.get(Opcode))3506 .addMBB(PostStackMBB)3507 .addImm(ARMCC::LS)3508 .addReg(ARM::CPSR);3509 3510 // Calling __morestack(StackSize, Size of stack arguments).3511 // __morestack knows that the stack size requested is in SR0(r4)3512 // and amount size of stack arguments is in SR1(r5).3513 3514 // Pass first argument for the __morestack by Scratch Register #0.3515 // The amount size of stack required3516 if (Thumb) {3517 if (AlignedStackSize < 256) {3518 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)3519 .add(condCodeOp())3520 .addImm(AlignedStackSize)3521 .add(predOps(ARMCC::AL));3522 } else {3523 if (Thumb2 || ST->genExecuteOnly()) {3524 BuildMI(AllocMBB, DL, TII.get(MovOp), ScratchReg0)3525 .addImm(AlignedStackSize);3526 } else {3527 auto MBBI = AllocMBB->end();3528 auto RegInfo = STI.getRegisterInfo();3529 RegInfo->emitLoadConstPool(*AllocMBB, MBBI, DL, ScratchReg0, 0,3530 AlignedStackSize);3531 }3532 }3533 } else {3534 if (AlignedStackSize < 256) {3535 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)3536 .addImm(AlignedStackSize)3537 .add(predOps(ARMCC::AL))3538 .add(condCodeOp());3539 } else {3540 auto MBBI = AllocMBB->end();3541 auto RegInfo = STI.getRegisterInfo();3542 RegInfo->emitLoadConstPool(*AllocMBB, MBBI, DL, ScratchReg0, 0,3543 AlignedStackSize);3544 }3545 }3546 3547 // Pass second argument for the __morestack by Scratch Register #1.3548 // The amount size of stack consumed to save function arguments.3549 if (Thumb) {3550 if (ARMFI->getArgumentStackSize() < 256) {3551 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)3552 .add(condCodeOp())3553 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))3554 .add(predOps(ARMCC::AL));3555 } else {3556 if (Thumb2 || ST->genExecuteOnly()) {3557 BuildMI(AllocMBB, DL, TII.get(MovOp), ScratchReg1)3558 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()));3559 } else {3560 auto MBBI = AllocMBB->end();3561 auto RegInfo = STI.getRegisterInfo();3562 RegInfo->emitLoadConstPool(3563 *AllocMBB, MBBI, DL, ScratchReg1, 0,3564 alignToARMConstant(ARMFI->getArgumentStackSize()));3565 }3566 }3567 } else {3568 if (alignToARMConstant(ARMFI->getArgumentStackSize()) < 256) {3569 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)3570 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))3571 .add(predOps(ARMCC::AL))3572 .add(condCodeOp());3573 } else {3574 auto MBBI = AllocMBB->end();3575 auto RegInfo = STI.getRegisterInfo();3576 RegInfo->emitLoadConstPool(3577 *AllocMBB, MBBI, DL, ScratchReg1, 0,3578 alignToARMConstant(ARMFI->getArgumentStackSize()));3579 }3580 }3581 3582 // push {lr} - Save return address of this function.3583 if (Thumb) {3584 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))3585 .add(predOps(ARMCC::AL))3586 .addReg(ARM::LR);3587 } else {3588 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))3589 .addReg(ARM::SP, RegState::Define)3590 .addReg(ARM::SP)3591 .add(predOps(ARMCC::AL))3592 .addReg(ARM::LR);3593 }3594 3595 // Emit the DWARF info about the change in stack as well as where to find the3596 // previous link register3597 if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {3598 CFIInstBuilder CFIBuilder(AllocMBB, MachineInstr::NoFlags);3599 CFIBuilder.buildDefCFAOffset(12);3600 CFIBuilder.buildOffset(ARM::LR, -12);3601 }3602 3603 // Call __morestack().3604 if (Thumb) {3605 BuildMI(AllocMBB, DL, TII.get(ARM::tBL))3606 .add(predOps(ARMCC::AL))3607 .addExternalSymbol("__morestack");3608 } else {3609 BuildMI(AllocMBB, DL, TII.get(ARM::BL))3610 .addExternalSymbol("__morestack");3611 }3612 3613 // pop {lr} - Restore return address of this original function.3614 if (Thumb) {3615 if (ST->isThumb1Only()) {3616 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))3617 .add(predOps(ARMCC::AL))3618 .addReg(ScratchReg0);3619 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)3620 .addReg(ScratchReg0)3621 .add(predOps(ARMCC::AL));3622 } else {3623 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))3624 .addReg(ARM::LR, RegState::Define)3625 .addReg(ARM::SP, RegState::Define)3626 .addReg(ARM::SP)3627 .addImm(4)3628 .add(predOps(ARMCC::AL));3629 }3630 } else {3631 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))3632 .addReg(ARM::SP, RegState::Define)3633 .addReg(ARM::SP)3634 .add(predOps(ARMCC::AL))3635 .addReg(ARM::LR);3636 }3637 3638 // Restore SR0 and SR1 in case of __morestack() was called.3639 // __morestack() will skip PostStackMBB block so we need to restore3640 // scratch registers from here.3641 // pop {SR0, SR1}3642 if (Thumb) {3643 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))3644 .add(predOps(ARMCC::AL))3645 .addReg(ScratchReg0)3646 .addReg(ScratchReg1);3647 } else {3648 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))3649 .addReg(ARM::SP, RegState::Define)3650 .addReg(ARM::SP)3651 .add(predOps(ARMCC::AL))3652 .addReg(ScratchReg0)3653 .addReg(ScratchReg1);3654 }3655 3656 // Update the CFA offset now that we've popped3657 if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI())3658 CFIInstBuilder(AllocMBB, MachineInstr::NoFlags).buildDefCFAOffset(0);3659 3660 // Return from this function.3661 BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));3662 3663 // Restore SR0 and SR1 in case of __morestack() was not called.3664 // pop {SR0, SR1}3665 if (Thumb) {3666 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))3667 .add(predOps(ARMCC::AL))3668 .addReg(ScratchReg0)3669 .addReg(ScratchReg1);3670 } else {3671 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))3672 .addReg(ARM::SP, RegState::Define)3673 .addReg(ARM::SP)3674 .add(predOps(ARMCC::AL))3675 .addReg(ScratchReg0)3676 .addReg(ScratchReg1);3677 }3678 3679 // Update the CFA offset now that we've popped3680 if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {3681 CFIInstBuilder CFIBuilder(PostStackMBB, MachineInstr::NoFlags);3682 CFIBuilder.buildDefCFAOffset(0);3683 3684 // Tell debuggers that r4 and r5 are now the same as they were in the3685 // previous function, that they're the "Same Value".3686 CFIBuilder.buildSameValue(ScratchReg0);3687 CFIBuilder.buildSameValue(ScratchReg1);3688 }3689 3690 // Organizing MBB lists3691 PostStackMBB->addSuccessor(&PrologueMBB);3692 3693 AllocMBB->addSuccessor(PostStackMBB);3694 3695 GetMBB->addSuccessor(PostStackMBB);3696 GetMBB->addSuccessor(AllocMBB);3697 3698 McrMBB->addSuccessor(GetMBB);3699 3700 PrevStackMBB->addSuccessor(McrMBB);3701 3702#ifdef EXPENSIVE_CHECKS3703 MF.verify();3704#endif3705}3706