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1//===-- ARMInstrCDE.td - CDE support for ARM ---------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the Arm CDE (Custom Datapath Extension) instruction set.10//11//===----------------------------------------------------------------------===//12 13// Immediate operand of arbitrary bit width14class BitWidthImmOperand<int width>15 : ImmAsmOperand<0, !add(!shl(1, width), -1)> {16 let Name = "Imm"#width#"b";17}18 19class BitWidthImm<int width>20 : Operand<i32>,21 ImmLeaf<i32, "{ return Imm >= 0 && Imm < (1 << "#width#"); }"> {22 let ParserMatchClass = BitWidthImmOperand<width>;23}24 25def CDEDualRegOp : RegisterOperand<GPRPairnosp, "printGPRPairOperand">;26 27// Used by VCX3 FP28def imm_3b : BitWidthImm<3>;29 30// Used by VCX3 vector31def imm_4b : BitWidthImm<4>;32 33// Used by VCX2 FP and CX334def imm_6b : BitWidthImm<6>;35 36// Used by VCX2 vector37def imm_7b : BitWidthImm<7>;38 39// Used by CX240def imm_9b : BitWidthImm<9>;41 42// Used by VCX1 FP43def imm_11b : BitWidthImm<11>;44 45// Used by VCX1 vector46def imm_12b : BitWidthImm<12>;47 48// Used by CX149def imm_13b : BitWidthImm<13>;50 51// Base class for all CDE instructions52class CDE_Instr<bit acc, dag oops, dag iops, string asm, string cstr>53 : Thumb2XI<oops, !con((ins p_imm:$coproc), iops),54 AddrModeNone, /*sz=*/4, NoItinerary,55 asm, cstr, /*pattern=*/[]>,56 Sched<[]> {57 bits<3> coproc;58 59 let Inst{31-29} = 0b111; // 15:1360 let Inst{28} = acc;61 let Inst{27-26} = 0b11;62 let Inst{11} = 0b0;63 let Inst{10-8} = coproc{2-0};64 65 let isPredicable = 0;66 let DecoderNamespace = "Thumb2CDE";67}68 69// Base class for CX* CDE instructions70class CDE_GPR_Instr<bit dual, bit acc, dag oops, dag iops,71 string asm, string cstr>72 : CDE_Instr<acc, oops, iops, asm, cstr>,73 Requires<[HasCDE]> {74 75 let Inst{25-24} = 0b10;76 let Inst{6} = dual;77 let isPredicable = acc;78}79 80// Set of registers used by the CDE instructions.81class CDE_RegisterOperands {82 dag Rd;83 dag Rd_src;84 dag Rn;85 dag Rm;86}87 88// CX* CDE instruction parameter set89class CX_Params {90 dag Oops; // Output operands for CX* instructions91 dag Iops1; // Input operands for CX1* instructions92 dag Iops2; // Input operands for CX2* instructions93 dag Iops3; // Input operands for CX3* instructions94 dag PredOp; // Input predicate operand95 string PAsm; // Predicate assembly string96 string Cstr; // asm constraint string97 bit Dual; // "dual" field for encoding98 bit Acc; // "acc" field for encoding99}100 101// VCX* CDE instruction parameter set102class VCX_Params {103 dag Oops; // Output operands for VCX* instructions104 dag Iops1; // Input operands for VCX1* instructions105 dag Iops2; // Input operands for VCX2* instructions106 dag Iops3; // Input operands for VCX3* instructions107 string Cstr; // asm constraint string108 bit Acc; // "acc" field for encoding109 vpred_ops Vpred; // Predication type for VCX* vector instructions110}111 112// CX1, CX1A, CX1D, CX1DA113class CDE_CX1_Instr<string iname, CX_Params params>114 : CDE_GPR_Instr<params.Dual, params.Acc, params.Oops,115 !con(params.Iops1, (ins imm_13b:$imm), params.PredOp),116 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),117 params.Cstr> {118 bits<0> p;119 bits<13> imm;120 bits<4> Rd;121 122 let Inst{23-22} = 0b00;123 let Inst{21-16} = imm{12-7};124 let Inst{15-12} = Rd{3-0};125 let Inst{7} = imm{6};126 let Inst{5-0} = imm{5-0};127}128 129// CX2, CX2A, CX2D, CX2DA130class CDE_CX2_Instr<string iname, CX_Params params>131 : CDE_GPR_Instr<params.Dual, params.Acc, params.Oops,132 !con(params.Iops2, (ins imm_9b:$imm), params.PredOp),133 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),134 params.Cstr> {135 bits<0> p;136 bits<9> imm;137 bits<4> Rd;138 bits<4> Rn;139 140 let Inst{23-22} = 0b01;141 let Inst{21-20} = imm{8-7};142 let Inst{19-16} = Rn{3-0};143 let Inst{15-12} = Rd{3-0};144 let Inst{7} = imm{6};145 let Inst{5-0} = imm{5-0};146}147 148// CX3, CX3A, CX3D, CX3DA149class CDE_CX3_Instr<string iname, CX_Params params>150 : CDE_GPR_Instr<params.Dual, params.Acc, params.Oops,151 !con(params.Iops3, (ins imm_6b:$imm), params.PredOp),152 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),153 params.Cstr> {154 bits<0> p;155 bits<6> imm;156 bits<4> Rd;157 bits<4> Rn;158 bits<4> Rm;159 160 let Inst{23} = 0b1;161 let Inst{22-20} = imm{5-3};162 let Inst{19-16} = Rn{3-0};163 let Inst{15-12} = Rm{3-0};164 let Inst{7} = imm{2};165 let Inst{5-4} = imm{1-0};166 let Inst{3-0} = Rd{3-0};167}168 169// Registers for single-register variants of CX* instructions170def cde_cx_single_regs : CDE_RegisterOperands {171 let Rd = (outs GPRwithAPSR_NZCVnosp:$Rd);172 let Rd_src = (ins GPRwithAPSR_NZCVnosp:$Rd_src);173 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);174 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);175}176 177// Registers for single-register variants of CX* instructions178def cde_cx_dual_regs : CDE_RegisterOperands {179 let Rd = (outs CDEDualRegOp:$Rd);180 let Rd_src = (ins CDEDualRegOp:$Rd_src);181 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);182 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);183}184 185class CDE_CX_ParamsTemplate<bit dual, bit acc, CDE_RegisterOperands ops>186 : CX_Params {187 188 dag IOpsPrefix = !if(acc, ops.Rd_src, (ins));189 190 let Oops = ops.Rd;191 let Iops1 = IOpsPrefix;192 let Iops2 = !con(IOpsPrefix, ops.Rn);193 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);194 let PredOp = !if(acc, (ins pred:$p), (ins));195 let PAsm = !if(acc, "${p}", "");196 let Cstr = !if(acc, "$Rd = $Rd_src", "");197 let Dual = dual;198 let Acc = acc;199}200 201def cde_cx_params_single_noacc : CDE_CX_ParamsTemplate<0b0, 0b0, cde_cx_single_regs>;202def cde_cx_params_single_acc : CDE_CX_ParamsTemplate<0b0, 0b1, cde_cx_single_regs>;203def cde_cx_params_dual_noacc : CDE_CX_ParamsTemplate<0b1, 0b0, cde_cx_dual_regs>;204def cde_cx_params_dual_acc : CDE_CX_ParamsTemplate<0b1, 0b1, cde_cx_dual_regs>;205 206def CDE_CX1 : CDE_CX1_Instr<"cx1", cde_cx_params_single_noacc>;207def CDE_CX1A : CDE_CX1_Instr<"cx1a", cde_cx_params_single_acc>;208def CDE_CX1D : CDE_CX1_Instr<"cx1d", cde_cx_params_dual_noacc>;209def CDE_CX1DA : CDE_CX1_Instr<"cx1da", cde_cx_params_dual_acc>;210 211def CDE_CX2 : CDE_CX2_Instr<"cx2", cde_cx_params_single_noacc>;212def CDE_CX2A : CDE_CX2_Instr<"cx2a", cde_cx_params_single_acc>;213def CDE_CX2D : CDE_CX2_Instr<"cx2d", cde_cx_params_dual_noacc>;214def CDE_CX2DA : CDE_CX2_Instr<"cx2da", cde_cx_params_dual_acc>;215 216def CDE_CX3 : CDE_CX3_Instr<"cx3", cde_cx_params_single_noacc>;217def CDE_CX3A : CDE_CX3_Instr<"cx3a", cde_cx_params_single_acc>;218def CDE_CX3D : CDE_CX3_Instr<"cx3d", cde_cx_params_dual_noacc>;219def CDE_CX3DA : CDE_CX3_Instr<"cx3da", cde_cx_params_dual_acc>;220 221let Predicates = [HasCDE] in {222 def : Pat<(i32 (int_arm_cde_cx1 timm:$coproc, timm:$imm)),223 (i32 (CDE_CX1 p_imm:$coproc, imm_13b:$imm))>;224 def : Pat<(i32 (int_arm_cde_cx1a timm:$coproc, GPRwithAPSR_NZCVnosp:$acc,225 timm:$imm)),226 (i32 (CDE_CX1A p_imm:$coproc, GPRwithAPSR_NZCVnosp:$acc,227 imm_13b:$imm))>;228 def : Pat<(i32 (int_arm_cde_cx2 timm:$coproc, GPRwithAPSR_NZCVnosp:$n,229 timm:$imm)),230 (i32 (CDE_CX2 p_imm:$coproc, GPRwithAPSR_NZCVnosp:$n,231 imm_9b:$imm))>;232 def : Pat<(i32 (int_arm_cde_cx2a timm:$coproc, GPRwithAPSR_NZCVnosp:$acc,233 GPRwithAPSR_NZCVnosp:$n, timm:$imm)),234 (i32 (CDE_CX2A p_imm:$coproc, GPRwithAPSR_NZCVnosp:$acc,235 GPRwithAPSR_NZCVnosp:$n, imm_9b:$imm))>;236 def : Pat<(i32 (int_arm_cde_cx3 timm:$coproc, GPRwithAPSR_NZCVnosp:$n,237 GPRwithAPSR_NZCVnosp:$m, timm:$imm)),238 (i32 (CDE_CX3 p_imm:$coproc, GPRwithAPSR_NZCVnosp:$n,239 GPRwithAPSR_NZCVnosp:$m, imm_6b:$imm))>;240 def : Pat<(i32 (int_arm_cde_cx3a timm:$coproc,241 GPRwithAPSR_NZCVnosp:$acc,242 GPRwithAPSR_NZCVnosp:$n,243 GPRwithAPSR_NZCVnosp:$m, timm:$imm)),244 (i32 (CDE_CX3A p_imm:$coproc,245 GPRwithAPSR_NZCVnosp:$acc,246 GPRwithAPSR_NZCVnosp:$n,247 GPRwithAPSR_NZCVnosp:$m, imm_6b:$imm))>;248}249 250class CDE_RequiresSReg : Requires<[HasCDE, HasFPRegs]>;251class CDE_RequiresDReg : Requires<[HasCDE, HasFPRegs]>;252class CDE_RequiresQReg : Requires<[HasCDE, HasMVEInt]>;253 254// Base class for CDE VCX* instructions255class CDE_FP_Vec_Instr<bit vec, bit acc, dag oops, dag iops, string asm, string cstr>256 : CDE_Instr<acc, oops, iops, asm, cstr> {257 let Inst{25} = 0b0;258 let Inst{6} = vec;259}260 261// Base class for floating-point variants of CDE VCX* instructions262class CDE_FP_Instr<bit acc, bit sz, dag oops, dag iops, string asm, string cstr>263 : CDE_FP_Vec_Instr<0b0, acc, oops, iops, asm, cstr> {264 let Inst{24} = sz;265}266 267// Base class for vector variants of CDE VCX* instruction268class CDE_Vec_Instr<bit acc, dag oops, dag iops, string asm, string cstr,269 vpred_ops vpred>270 : CDE_FP_Vec_Instr<0b1, acc, oops,271 !con(iops, (ins vpred:$vp)), asm,272 !strconcat(cstr, vpred.vpred_constraint)>,273 CDE_RequiresQReg {274 bits<0> vp;275}276 277 278// VCX1/VCX1A, vector variant279class CDE_VCX1_Vec_Instr<string iname, VCX_Params params>280 : CDE_Vec_Instr<params.Acc, params.Oops,281 !con(params.Iops1, (ins imm_12b:$imm)),282 iname#"${vp}\t$coproc, $Qd, $imm", params.Cstr, params.Vpred> {283 bits<12> imm;284 bits<3> Qd;285 286 let Inst{24} = imm{11};287 let Inst{23} = 0b0;288 let Inst{22} = 0b0;289 let Inst{21-20} = 0b10;290 let Inst{19-16} = imm{10-7};291 let Inst{15-13} = Qd{2-0};292 let Inst{12} = 0b0;293 let Inst{7} = imm{6};294 let Inst{5-0} = imm{5-0};295 296 let Unpredictable{22} = 0b1;297}298 299// VCX1/VCX1A, base class for FP variants300class CDE_VCX1_FP_Instr<bit sz, string iname, VCX_Params params>301 : CDE_FP_Instr<params.Acc, sz, params.Oops,302 !con(params.Iops1, (ins imm_11b:$imm)),303 iname#"\t$coproc, $Vd, $imm", params.Cstr> {304 bits<11> imm;305 306 let Inst{23} = 0b0;307 let Inst{21-20} = 0b10;308 let Inst{19-16} = imm{10-7};309 let Inst{7} = imm{6};310 let Inst{5-0} = imm{5-0};311}312 313// VCX1/VCX1A, S registers314class CDE_VCX1_FP_Instr_S<string iname, VCX_Params params>315 : CDE_VCX1_FP_Instr<0b0, iname, params>,316 CDE_RequiresSReg {317 bits<5> Vd;318 319 let Inst{22} = Vd{0};320 let Inst{15-12} = Vd{4-1};321}322 323// VCX1/VCX1A, D registers324class CDE_VCX1_FP_Instr_D<string iname, VCX_Params params>325 : CDE_VCX1_FP_Instr<0b1, iname, params>,326 CDE_RequiresDReg {327 bits<5> Vd;328 329 let Inst{22} = Vd{4};330 let Inst{15-12} = Vd{3-0};331}332 333// VCX2/VCX2A, vector variant334class CDE_VCX2_Vec_Instr<string iname, VCX_Params params>335 : CDE_Vec_Instr<params.Acc, params.Oops,336 !con(params.Iops2, (ins imm_7b:$imm)),337 iname#"${vp}\t$coproc, $Qd, $Qm, $imm", params.Cstr,338 params.Vpred> {339 bits<7> imm;340 bits<3> Qd;341 bits<3> Qm;342 343 let Inst{24} = imm{6};344 let Inst{23} = 0b0;345 let Inst{22} = 0b0;346 let Inst{21-20} = 0b11;347 let Inst{19-16} = imm{5-2};348 let Inst{15-13} = Qd{2-0};349 let Inst{12} = 0b0;350 let Inst{7} = imm{1};351 let Inst{5} = 0b0;352 let Inst{4} = imm{0};353 let Inst{3-1} = Qm{2-0};354 let Inst{0} = 0b0;355 356 let Unpredictable{22} = 0b1;357 let Unpredictable{5} = 0b1;358}359 360// VCX2/VCX2A, base class for FP variants361class CDE_VCX2_FP_Instr<bit sz, string iname, VCX_Params params>362 : CDE_FP_Instr<params.Acc, sz, params.Oops,363 !con(params.Iops2, (ins imm_6b:$imm)),364 iname#"\t$coproc, $Vd, $Vm, $imm", params.Cstr> {365 bits<6> imm;366 367 let Inst{23} = 0b0;368 let Inst{21-20} = 0b11;369 let Inst{19-16} = imm{5-2};370 let Inst{7} = imm{1};371 let Inst{4} = imm{0};372}373 374// VCX2/VCX2A, S registers375class CDE_VCX2_FP_Instr_S<string iname, VCX_Params params>376 : CDE_VCX2_FP_Instr<0b0, iname, params>,377 CDE_RequiresSReg {378 bits<5> Vd;379 bits<5> Vm;380 381 let Inst{15-12} = Vd{4-1};382 let Inst{22} = Vd{0};383 let Inst{3-0} = Vm{4-1};384 let Inst{5} = Vm{0};385}386 387// VCX2/VCX2A, D registers388class CDE_VCX2_FP_Instr_D<string iname, VCX_Params params>389 : CDE_VCX2_FP_Instr<0b1, iname, params>,390 CDE_RequiresDReg {391 bits<5> Vd;392 bits<5> Vm;393 394 let Inst{15-12} = Vd{3-0};395 let Inst{22} = Vd{4};396 let Inst{3-0} = Vm{3-0};397 let Inst{5} = Vm{4};398}399 400// VCX3/VCX3A, vector variant401class CDE_VCX3_Vec_Instr<string iname, VCX_Params params>402 : CDE_Vec_Instr<params.Acc, params.Oops,403 !con(params.Iops3, (ins imm_4b:$imm)),404 iname#"${vp}\t$coproc, $Qd, $Qn, $Qm, $imm", params.Cstr,405 params.Vpred> {406 bits<4> imm;407 bits<3> Qd;408 bits<3> Qm;409 bits<3> Qn;410 411 let Inst{24} = imm{3};412 let Inst{23} = 0b1;413 let Inst{22} = 0b0;414 let Inst{21-20} = imm{2-1};415 let Inst{19-17} = Qn{2-0};416 let Inst{16} = 0b0;417 let Inst{15-13} = Qd{2-0};418 let Inst{12} = 0b0;419 let Inst{7} = 0b0;420 let Inst{5} = 0b0;421 let Inst{4} = imm{0};422 let Inst{3-1} = Qm{2-0};423 let Inst{0} = 0b0;424 425 let Unpredictable{22} = 0b1;426 let Unpredictable{7} = 0b1;427 let Unpredictable{5} = 0b1;428}429 430// VCX3/VCX3A, base class for FP variants431class CDE_VCX3_FP_Instr<bit sz, string iname, VCX_Params params>432 : CDE_FP_Instr<params.Acc, sz, params.Oops,433 !con(params.Iops3, (ins imm_3b:$imm)),434 iname#"\t$coproc, $Vd, $Vn, $Vm, $imm", params.Cstr> {435 bits<3> imm;436 437 let Inst{23} = 0b1;438 let Inst{21-20} = imm{2-1};439 let Inst{4} = imm{0};440}441 442// VCX3/VCX3A, S registers443class CDE_VCX3_FP_Instr_S<string iname, VCX_Params params>444 : CDE_VCX3_FP_Instr<0b0, iname, params>,445 CDE_RequiresSReg {446 bits<5> Vd;447 bits<5> Vm;448 bits<5> Vn;449 450 let Inst{22} = Vd{0};451 let Inst{19-16} = Vn{4-1};452 let Inst{15-12} = Vd{4-1};453 let Inst{7} = Vn{0};454 let Inst{5} = Vm{0};455 let Inst{3-0} = Vm{4-1};456}457 458// VCX3/VCX3A, D registers459class CDE_VCX3_FP_Instr_D<string iname, VCX_Params params>460 : CDE_VCX3_FP_Instr<0b1, iname, params>,461 CDE_RequiresDReg {462 bits<5> Vd;463 bits<5> Vm;464 bits<5> Vn;465 466 let Inst{22} = Vd{4};467 let Inst{19-16} = Vn{3-0};468 let Inst{15-12} = Vd{3-0};469 let Inst{7} = Vn{4};470 let Inst{5} = Vm{4};471 let Inst{3-0} = Vm{3-0};472}473 474// Register operands for VCX* instructions475class CDE_VCX_RegisterOperandsTemplate<RegisterClass regclass>476 : CDE_RegisterOperands {477 let Rd = (outs regclass:$Vd);478 let Rd_src = (ins regclass:$Vd_src);479 let Rn = (ins regclass:$Vn);480 let Rm = (ins regclass:$Vm);481}482 483class CDE_VCXQ_RegisterOperandsTemplate<RegisterClass regclass>484 : CDE_RegisterOperands {485 let Rd = (outs regclass:$Qd);486 let Rd_src = (ins regclass:$Qd_src);487 let Rn = (ins regclass:$Qn);488 let Rm = (ins regclass:$Qm);489}490 491def cde_vcx_s_regs : CDE_VCX_RegisterOperandsTemplate<SPR>;492def cde_vcx_d_regs : CDE_VCX_RegisterOperandsTemplate<DPR_VFP2>;493def cde_vcx_q_regs : CDE_VCXQ_RegisterOperandsTemplate<MQPR>;494 495class CDE_VCX_ParamsTemplate<bit acc, CDE_RegisterOperands ops>496 : VCX_Params {497 498 dag IOpsPrefix = !if(acc, ops.Rd_src, (ins));499 500 let Oops = ops.Rd;501 let Iops1 = IOpsPrefix;502 let Iops2 = !con(IOpsPrefix, ops.Rm);503 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);504 let Cstr = !if(acc, "$Vd = $Vd_src", "");505 let Acc = acc;506}507 508class CDE_VCXQ_ParamsTemplate<bit acc, CDE_RegisterOperands ops>509 : VCX_Params {510 511 dag IOpsPrefix = !if(acc, ops.Rd_src, (ins));512 513 let Oops = ops.Rd;514 let Iops1 = IOpsPrefix;515 let Iops2 = !con(IOpsPrefix, ops.Rm);516 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);517 let Cstr = !if(acc, "$Qd = $Qd_src", "");518 let Acc = acc;519 let Vpred = !if(acc, vpred_n, vpred_r);520}521 522def cde_vcx_params_s_noacc : CDE_VCX_ParamsTemplate<0b0, cde_vcx_s_regs>;523def cde_vcx_params_s_acc : CDE_VCX_ParamsTemplate<0b1, cde_vcx_s_regs>;524def cde_vcx_params_d_noacc : CDE_VCX_ParamsTemplate<0b0, cde_vcx_d_regs>;525def cde_vcx_params_d_acc : CDE_VCX_ParamsTemplate<0b1, cde_vcx_d_regs>;526def cde_vcx_params_q_noacc : CDE_VCXQ_ParamsTemplate<0b0, cde_vcx_q_regs>;527def cde_vcx_params_q_acc : CDE_VCXQ_ParamsTemplate<0b1, cde_vcx_q_regs>;528 529def CDE_VCX1_fpsp : CDE_VCX1_FP_Instr_S<"vcx1", cde_vcx_params_s_noacc>;530def CDE_VCX1A_fpsp : CDE_VCX1_FP_Instr_S<"vcx1a", cde_vcx_params_s_acc>;531def CDE_VCX1_fpdp : CDE_VCX1_FP_Instr_D<"vcx1", cde_vcx_params_d_noacc>;532def CDE_VCX1A_fpdp : CDE_VCX1_FP_Instr_D<"vcx1a", cde_vcx_params_d_acc>;533def CDE_VCX1_vec : CDE_VCX1_Vec_Instr<"vcx1", cde_vcx_params_q_noacc>;534def CDE_VCX1A_vec : CDE_VCX1_Vec_Instr<"vcx1a", cde_vcx_params_q_acc>;535 536def CDE_VCX2_fpsp : CDE_VCX2_FP_Instr_S<"vcx2", cde_vcx_params_s_noacc>;537def CDE_VCX2A_fpsp : CDE_VCX2_FP_Instr_S<"vcx2a", cde_vcx_params_s_acc>;538def CDE_VCX2_fpdp : CDE_VCX2_FP_Instr_D<"vcx2", cde_vcx_params_d_noacc>;539def CDE_VCX2A_fpdp : CDE_VCX2_FP_Instr_D<"vcx2a", cde_vcx_params_d_acc>;540def CDE_VCX2_vec : CDE_VCX2_Vec_Instr<"vcx2", cde_vcx_params_q_noacc>;541def CDE_VCX2A_vec : CDE_VCX2_Vec_Instr<"vcx2a", cde_vcx_params_q_acc>;542 543def CDE_VCX3_fpsp : CDE_VCX3_FP_Instr_S<"vcx3", cde_vcx_params_s_noacc>;544def CDE_VCX3A_fpsp : CDE_VCX3_FP_Instr_S<"vcx3a", cde_vcx_params_s_acc>;545def CDE_VCX3_fpdp : CDE_VCX3_FP_Instr_D<"vcx3", cde_vcx_params_d_noacc>;546def CDE_VCX3A_fpdp : CDE_VCX3_FP_Instr_D<"vcx3a", cde_vcx_params_d_acc>;547def CDE_VCX3_vec : CDE_VCX3_Vec_Instr<"vcx3", cde_vcx_params_q_noacc>;548def CDE_VCX3A_vec : CDE_VCX3_Vec_Instr<"vcx3a", cde_vcx_params_q_acc>;549 550 551let Predicates = [HasCDE, HasFPRegs] in {552 def : Pat<(f32 (int_arm_cde_vcx1 timm:$coproc, timm:$imm)),553 (f32 (CDE_VCX1_fpsp p_imm:$coproc, imm_11b:$imm))>;554 def : Pat<(f32 (int_arm_cde_vcx1a timm:$coproc, (f32 SPR:$acc), timm:$imm)),555 (f32 (CDE_VCX1A_fpsp p_imm:$coproc, SPR:$acc, imm_11b:$imm))>;556 def : Pat<(f64 (int_arm_cde_vcx1 timm:$coproc, timm:$imm)),557 (f64 (CDE_VCX1_fpdp p_imm:$coproc, imm_11b:$imm))>;558 def : Pat<(f64 (int_arm_cde_vcx1a timm:$coproc, (f64 DPR:$acc), timm:$imm)),559 (f64 (CDE_VCX1A_fpdp p_imm:$coproc, DPR:$acc, imm_11b:$imm))>;560 561 def : Pat<(f32 (int_arm_cde_vcx2 timm:$coproc, (f32 SPR:$n), timm:$imm)),562 (f32 (CDE_VCX2_fpsp p_imm:$coproc, SPR:$n, imm_6b:$imm))>;563 def : Pat<(f32 (int_arm_cde_vcx2a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),564 timm:$imm)),565 (f32 (CDE_VCX2A_fpsp p_imm:$coproc, SPR:$acc, SPR:$n, imm_6b:$imm))>;566 def : Pat<(f64 (int_arm_cde_vcx2 timm:$coproc, (f64 DPR:$n), timm:$imm)),567 (f64 (CDE_VCX2_fpdp p_imm:$coproc, DPR:$n, imm_6b:$imm))>;568 def : Pat<(f64 (int_arm_cde_vcx2a timm:$coproc, (f64 DPR:$acc), (f64 DPR:$n),569 timm:$imm)),570 (f64 (CDE_VCX2A_fpdp p_imm:$coproc, DPR:$acc, DPR:$n, imm_6b:$imm))>;571 572 def : Pat<(f32 (int_arm_cde_vcx3 timm:$coproc, (f32 SPR:$n), (f32 SPR:$m),573 timm:$imm)),574 (f32 (CDE_VCX3_fpsp p_imm:$coproc, (f32 SPR:$n), (f32 SPR:$m),575 imm_3b:$imm))>;576 def : Pat<(f32 (int_arm_cde_vcx3a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),577 (f32 SPR:$m), timm:$imm)),578 (f32 (CDE_VCX3A_fpsp p_imm:$coproc, SPR:$acc, SPR:$n, SPR:$m,579 imm_3b:$imm))>;580 def : Pat<(f64 (int_arm_cde_vcx3 timm:$coproc, (f64 DPR:$n), (f64 DPR:$m),581 timm:$imm)),582 (f64 (CDE_VCX3_fpdp p_imm:$coproc, DPR:$n, DPR:$m, imm_3b:$imm))>;583 def : Pat<(f64 (int_arm_cde_vcx3a timm:$coproc, (f64 DPR:$acc), (f64 DPR:$n),584 (f64 DPR:$m), timm:$imm)),585 (f64 (CDE_VCX3A_fpdp p_imm:$coproc, DPR:$acc, DPR:$n, DPR:$m,586 imm_3b:$imm))>;587}588 589let Predicates = [HasCDE, HasMVEInt] in {590 def : Pat<(v16i8 (int_arm_cde_vcx1q timm:$coproc, timm:$imm)),591 (v16i8 (CDE_VCX1_vec p_imm:$coproc, imm_12b:$imm))>;592 def : Pat<(v16i8 (int_arm_cde_vcx1qa timm:$coproc, (v16i8 MQPR:$acc),593 timm:$imm)),594 (v16i8 (CDE_VCX1A_vec p_imm:$coproc, MQPR:$acc, imm_12b:$imm))>;595 596 def : Pat<(v16i8 (int_arm_cde_vcx2q timm:$coproc, (v16i8 MQPR:$n), timm:$imm)),597 (v16i8 (CDE_VCX2_vec p_imm:$coproc, MQPR:$n, imm_7b:$imm))>;598 def : Pat<(v16i8 (int_arm_cde_vcx2qa timm:$coproc, (v16i8 MQPR:$acc),599 (v16i8 MQPR:$n), timm:$imm)),600 (v16i8 (CDE_VCX2A_vec p_imm:$coproc, MQPR:$acc, MQPR:$n,601 imm_7b:$imm))>;602 603 def : Pat<(v16i8 (int_arm_cde_vcx3q timm:$coproc, (v16i8 MQPR:$n),604 (v16i8 MQPR:$m), timm:$imm)),605 (v16i8 (CDE_VCX3_vec p_imm:$coproc, MQPR:$n, MQPR:$m,606 imm_4b:$imm))>;607 def : Pat<(v16i8 (int_arm_cde_vcx3qa timm:$coproc, (v16i8 MQPR:$acc),608 (v16i8 MQPR:$n), (v16i8 MQPR:$m),609 timm:$imm)),610 (v16i8 (CDE_VCX3A_vec p_imm:$coproc, MQPR:$acc, MQPR:$n, MQPR:$m,611 imm_4b:$imm))>;612}613 614multiclass VCXPredicatedPat_m<MVEVectorVTInfo VTI> {615 def : Pat<(VTI.Vec (int_arm_cde_vcx1q_predicated timm:$coproc,616 (VTI.Vec MQPR:$inactive), timm:$imm,617 (VTI.Pred VCCR:$pred))),618 (VTI.Vec (CDE_VCX1_vec p_imm:$coproc, imm_12b:$imm, ARMVCCThen,619 (VTI.Pred VCCR:$pred), zero_reg,620 (VTI.Vec MQPR:$inactive)))>;621 def : Pat<(VTI.Vec (int_arm_cde_vcx1qa_predicated timm:$coproc,622 (VTI.Vec MQPR:$acc), timm:$imm,623 (VTI.Pred VCCR:$pred))),624 (VTI.Vec (CDE_VCX1A_vec p_imm:$coproc, (VTI.Vec MQPR:$acc),625 imm_12b:$imm, ARMVCCThen,626 (VTI.Pred VCCR:$pred), zero_reg))>;627 628 def : Pat<(VTI.Vec (int_arm_cde_vcx2q_predicated timm:$coproc,629 (VTI.Vec MQPR:$inactive),630 (v16i8 MQPR:$n), timm:$imm,631 (VTI.Pred VCCR:$pred))),632 (VTI.Vec (CDE_VCX2_vec p_imm:$coproc, (v16i8 MQPR:$n),633 imm_7b:$imm, ARMVCCThen,634 (VTI.Pred VCCR:$pred), zero_reg,635 (VTI.Vec MQPR:$inactive)))>;636 def : Pat<(VTI.Vec (int_arm_cde_vcx2qa_predicated timm:$coproc,637 (VTI.Vec MQPR:$acc),638 (v16i8 MQPR:$n), timm:$imm,639 (VTI.Pred VCCR:$pred))),640 (VTI.Vec (CDE_VCX2A_vec p_imm:$coproc, (VTI.Vec MQPR:$acc),641 (v16i8 MQPR:$n), timm:$imm, ARMVCCThen,642 (VTI.Pred VCCR:$pred), zero_reg))>;643 644 def : Pat<(VTI.Vec (int_arm_cde_vcx3q_predicated timm:$coproc,645 (VTI.Vec MQPR:$inactive),646 (v16i8 MQPR:$n), (v16i8 MQPR:$m),647 timm:$imm,648 (VTI.Pred VCCR:$pred))),649 (VTI.Vec (CDE_VCX3_vec p_imm:$coproc, (v16i8 MQPR:$n),650 (v16i8 MQPR:$m),651 imm_4b:$imm, ARMVCCThen,652 (VTI.Pred VCCR:$pred), zero_reg,653 (VTI.Vec MQPR:$inactive)))>;654 def : Pat<(VTI.Vec (int_arm_cde_vcx3qa_predicated timm:$coproc,655 (VTI.Vec MQPR:$acc),656 (v16i8 MQPR:$n), (v16i8 MQPR:$m), timm:$imm,657 (VTI.Pred VCCR:$pred))),658 (VTI.Vec (CDE_VCX3A_vec p_imm:$coproc, (VTI.Vec MQPR:$acc),659 (v16i8 MQPR:$n), (v16i8 MQPR:$m),660 imm_4b:$imm, ARMVCCThen,661 (VTI.Pred VCCR:$pred), zero_reg))>;662}663 664let Predicates = [HasCDE, HasMVEInt] in665 foreach VTI = [ MVE_v16i8, MVE_v8i16, MVE_v4i32, MVE_v2i64 ] in666 defm : VCXPredicatedPat_m<VTI>;667 668let Predicates = [HasCDE, HasMVEFloat] in669 foreach VTI = [ MVE_v8f16, MVE_v4f32 ] in670 defm : VCXPredicatedPat_m<VTI>;671