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1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the Thumb instruction set.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// Thumb specific DAG Nodes.15//16 17// CMSE non-secure function call.18def ARMtsecall : SDNode<"ARMISD::tSECALL", SDT_ARMcall,19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,20 SDNPVariadic]>;21 22def imm_sr_XFORM: SDNodeXForm<imm, [{23 unsigned Imm = N->getZExtValue();24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);25}]>;26def ThumbSRImmAsmOperand: ImmAsmOperand<1,32> { let Name = "ImmThumbSR"; }27def imm_sr : Operand<i32>, ImmLeaf<i32, [{28 return Imm > 0 && Imm <= 32;29}], imm_sr_XFORM> {30 let PrintMethod = "printThumbSRImm";31 let ParserMatchClass = ThumbSRImmAsmOperand;32}33 34def imm0_7_neg : PatLeaf<(i32 imm), [{35 return (uint32_t)-N->getZExtValue() < 8;36}], imm_neg_XFORM>;37 38def ThumbModImmNeg1_7AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg1_7"; }39def mod_imm1_7_neg : Operand<i32>, PatLeaf<(imm), [{40 unsigned Value = -(unsigned)N->getZExtValue();41 return 0 < Value && Value < 8;42 }], imm_neg_XFORM> {43 let ParserMatchClass = ThumbModImmNeg1_7AsmOperand;44}45 46def ThumbModImmNeg8_255AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg8_255"; }47def mod_imm8_255_neg : Operand<i32>, PatLeaf<(imm), [{48 unsigned Value = -(unsigned)N->getZExtValue();49 return 7 < Value && Value < 256;50 }], imm_neg_XFORM> {51 let ParserMatchClass = ThumbModImmNeg8_255AsmOperand;52}53 54 55def imm0_255_comp : PatLeaf<(i32 imm), [{56 return ~((uint32_t)N->getZExtValue()) < 256;57}]>;58 59def imm8_255_neg : PatLeaf<(i32 imm), [{60 unsigned Val = -N->getZExtValue();61 return Val >= 8 && Val < 256;62}], imm_neg_XFORM>;63 64// Break imm's up into two pieces: an immediate + a left shift. This uses65// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt66// to get the val/shift pieces.67def thumb_immshifted : PatLeaf<(imm), [{68 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());69}]>;70 71def thumb_immshifted_val : SDNodeXForm<imm, [{72 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());73 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);74}]>;75 76def thumb_immshifted_shamt : SDNodeXForm<imm, [{77 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());78 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);79}]>;80 81def imm256_510 : ImmLeaf<i32, [{82 return Imm >= 256 && Imm < 511;83}]>;84 85def thumb_imm256_510_addend : SDNodeXForm<imm, [{86 return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32);87}]>;88 89// Scaled 4 immediate.90def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }91def t_imm0_1020s4 : Operand<i32> {92 let PrintMethod = "printThumbS4ImmOperand";93 let ParserMatchClass = t_imm0_1020s4_asmoperand;94 let OperandType = "OPERAND_IMMEDIATE";95}96 97def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }98def t_imm0_508s4 : Operand<i32> {99 let PrintMethod = "printThumbS4ImmOperand";100 let ParserMatchClass = t_imm0_508s4_asmoperand;101 let OperandType = "OPERAND_IMMEDIATE";102}103// Alias use only, so no printer is necessary.104def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }105def t_imm0_508s4_neg : Operand<i32> {106 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;107 let OperandType = "OPERAND_IMMEDIATE";108}109 110// Define Thumb specific addressing modes.111 112// unsigned 8-bit, 2-scaled memory offset113class OperandUnsignedOffset_b8s2 : AsmOperandClass {114 let Name = "UnsignedOffset_b8s2";115 let PredicateMethod = "isUnsignedOffset<8, 2>";116}117 118def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;119 120// thumb style PC relative operand. signed, 8 bits magnitude,121// two bits shift. can be represented as either [pc, #imm], #imm,122// or relocatable expression...123def ThumbMemPC : AsmOperandClass {124 let Name = "ThumbMemPC";125}126 127let OperandType = "OPERAND_PCREL" in {128def t_brtarget : Operand<OtherVT> {129 let EncoderMethod = "getThumbBRTargetOpValue";130 let DecoderMethod = "DecodeThumbBROperand";131}132 133// ADR instruction labels.134def t_adrlabel : Operand<i32> {135 let EncoderMethod = "getThumbAdrLabelOpValue";136 let PrintMethod = "printAdrLabelOperand<2>";137 let ParserMatchClass = UnsignedOffset_b8s2;138}139 140 141def thumb_br_target : Operand<OtherVT> {142 let ParserMatchClass = ThumbBranchTarget;143 let EncoderMethod = "getThumbBranchTargetOpValue";144 let OperandType = "OPERAND_PCREL";145}146 147def thumb_bl_target : Operand<i32> {148 let ParserMatchClass = ThumbBranchTarget;149 let EncoderMethod = "getThumbBLTargetOpValue";150 let DecoderMethod = "DecodeThumbBLTargetOperand";151}152 153// Target for BLX *from* thumb mode.154def thumb_blx_target : Operand<i32> {155 let ParserMatchClass = ARMBranchTarget;156 let EncoderMethod = "getThumbBLXTargetOpValue";157 let DecoderMethod = "DecodeThumbBLXOffset";158}159 160def thumb_bcc_target : Operand<OtherVT> {161 let ParserMatchClass = ThumbBranchTarget;162 let EncoderMethod = "getThumbBCCTargetOpValue";163 let DecoderMethod = "DecodeThumbBCCTargetOperand";164}165 166def thumb_cb_target : Operand<OtherVT> {167 let ParserMatchClass = ThumbBranchTarget;168 let EncoderMethod = "getThumbCBTargetOpValue";169 let DecoderMethod = "DecodeThumbCmpBROperand";170}171} // OperandType = "OPERAND_PCREL"172 173// t_addrmode_pc := <label> => pc + imm8 * 4174//175def t_addrmode_pc : MemOperand {176 let EncoderMethod = "getAddrModePCOpValue";177 let DecoderMethod = "DecodeThumbAddrModePC";178 let PrintMethod = "printThumbLdrLabelOperand";179 let ParserMatchClass = ThumbMemPC;180}181 182// t_addrmode_rr := reg + reg183//184def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }185def t_addrmode_rr : MemOperand,186 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {187 let EncoderMethod = "getThumbAddrModeRegRegOpValue";188 let PrintMethod = "printThumbAddrModeRROperand";189 let DecoderMethod = "DecodeThumbAddrModeRR";190 let ParserMatchClass = t_addrmode_rr_asm_operand;191 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);192}193 194// t_addrmode_rr_sext := reg + reg195//196// This is similar to t_addrmode_rr, but uses different heuristics for197// ldrsb/ldrsh.198def t_addrmode_rr_sext : MemOperand,199 ComplexPattern<i32, 2, "SelectThumbAddrModeRRSext", []> {200 let EncoderMethod = "getThumbAddrModeRegRegOpValue";201 let PrintMethod = "printThumbAddrModeRROperand";202 let DecoderMethod = "DecodeThumbAddrModeRR";203 let ParserMatchClass = t_addrmode_rr_asm_operand;204 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);205}206 207// t_addrmode_rrs := reg + reg208//209// We use separate scaled versions because the Select* functions need210// to explicitly check for a matching constant and return false here so that211// the reg+imm forms will match instead. This is a horrible way to do that,212// as it forces tight coupling between the methods, but it's how selectiondag213// currently works.214def t_addrmode_rrs1 : MemOperand,215 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {216 let EncoderMethod = "getThumbAddrModeRegRegOpValue";217 let PrintMethod = "printThumbAddrModeRROperand";218 let DecoderMethod = "DecodeThumbAddrModeRR";219 let ParserMatchClass = t_addrmode_rr_asm_operand;220 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);221}222def t_addrmode_rrs2 : MemOperand,223 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {224 let EncoderMethod = "getThumbAddrModeRegRegOpValue";225 let DecoderMethod = "DecodeThumbAddrModeRR";226 let PrintMethod = "printThumbAddrModeRROperand";227 let ParserMatchClass = t_addrmode_rr_asm_operand;228 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);229}230def t_addrmode_rrs4 : MemOperand,231 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {232 let EncoderMethod = "getThumbAddrModeRegRegOpValue";233 let DecoderMethod = "DecodeThumbAddrModeRR";234 let PrintMethod = "printThumbAddrModeRROperand";235 let ParserMatchClass = t_addrmode_rr_asm_operand;236 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);237}238 239// t_addrmode_is4 := reg + imm5 * 4240//241def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }242def t_addrmode_is4 : MemOperand,243 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {244 let EncoderMethod = "getAddrModeISOpValue";245 let DecoderMethod = "DecodeThumbAddrModeIS";246 let PrintMethod = "printThumbAddrModeImm5S4Operand";247 let ParserMatchClass = t_addrmode_is4_asm_operand;248 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);249}250 251// t_addrmode_is2 := reg + imm5 * 2252//253def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }254def t_addrmode_is2 : MemOperand,255 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {256 let EncoderMethod = "getAddrModeISOpValue";257 let DecoderMethod = "DecodeThumbAddrModeIS";258 let PrintMethod = "printThumbAddrModeImm5S2Operand";259 let ParserMatchClass = t_addrmode_is2_asm_operand;260 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);261}262 263// t_addrmode_is1 := reg + imm5264//265def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }266def t_addrmode_is1 : MemOperand,267 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {268 let EncoderMethod = "getAddrModeISOpValue";269 let DecoderMethod = "DecodeThumbAddrModeIS";270 let PrintMethod = "printThumbAddrModeImm5S1Operand";271 let ParserMatchClass = t_addrmode_is1_asm_operand;272 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);273}274 275// t_addrmode_sp := sp + imm8 * 4276//277// FIXME: This really shouldn't have an explicit SP operand at all. It should278// be implicit, just like in the instruction encoding itself.279def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }280def t_addrmode_sp : MemOperand,281 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {282 let EncoderMethod = "getAddrModeThumbSPOpValue";283 let DecoderMethod = "DecodeThumbAddrModeSP";284 let PrintMethod = "printThumbAddrModeSPOperand";285 let ParserMatchClass = t_addrmode_sp_asm_operand;286 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);287}288 289// Inspects parent to determine whether an or instruction can be implemented as290// an add (i.e. whether we know overflow won't occur in the add).291let WantsParent = true in292def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr">;293 294// Pattern to exclude immediates from matching295def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>;296 297//===----------------------------------------------------------------------===//298// Miscellaneous Instructions.299//300 301// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE302// from removing one half of the matched pairs. That breaks PEI, which assumes303// these will always be in pairs, and asserts if it finds otherwise. Better way?304let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {305def tADJCALLSTACKUP :306 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,307 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,308 Requires<[IsThumb, IsThumb1Only]>;309 310def tADJCALLSTACKDOWN :311 PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2), NoItinerary,312 [(ARMcallseq_start imm:$amt, imm:$amt2)]>,313 Requires<[IsThumb, IsThumb1Only]>;314}315 316class T1SystemEncoding<bits<8> opc>317 : T1Encoding<0b101111> {318 let Inst{9-8} = 0b11;319 let Inst{7-0} = opc;320}321 322def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",323 [(int_arm_hint imm0_15:$imm)]>,324 T1SystemEncoding<0x00>,325 Requires<[IsThumb, HasV6M]> {326 bits<4> imm;327 let Inst{7-4} = imm;328}329 330// Note: When EmitPriority == 1, the alias will be used for printing331class tHintAlias<string Asm, dag Result, bit EmitPriority = 0> : tInstAlias<Asm, Result, EmitPriority> {332 let Predicates = [IsThumb, HasV6M];333}334 335def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110336def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410337def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408338def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409339def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157340def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> {341 let Predicates = [IsThumb2, HasV8];342}343 344// The imm operand $val can be used by a debugger to store more information345// about the breakpoint.346def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",347 []>,348 T1Encoding<0b101111> {349 let Inst{9-8} = 0b10;350 // A8.6.22351 bits<8> val;352 let Inst{7-0} = val;353}354// default immediate for breakpoint mnemonic355def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>;356 357def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",358 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {359 let Inst{9-6} = 0b1010;360 bits<6> val;361 let Inst{5-0} = val;362}363 364def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",365 []>, T1Encoding<0b101101>, Requires<[IsThumb, IsNotMClass]>, Deprecated<HasV8Ops> {366 bits<1> end;367 // A8.6.156368 let Inst{9-5} = 0b10010;369 let Inst{4} = 1;370 let Inst{3} = end;371 let Inst{2-0} = 0b000;372}373 374// Change Processor State is a system instruction -- for disassembly only.375def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),376 NoItinerary, "cps$imod $iflags", []>,377 T1Misc<0b0110011> {378 // A8.6.38 & B6.1.1379 bit imod;380 bits<3> iflags;381 382 let Inst{4} = imod;383 let Inst{3} = 0;384 let Inst{2-0} = iflags;385 let DecoderMethod = "DecodeThumbCPS";386}387 388// For both thumb1 and thumb2.389let isNotDuplicable = 1, isCodeGenOnly = 1 in390def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",391 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,392 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {393 // A8.6.6394 bits<3> dst;395 let Inst{6-3} = 0b1111; // Rm = pc396 let Inst{2-0} = dst;397}398 399// ADD <Rd>, sp, #<imm8>400// FIXME: This should not be marked as having side effects, and it should be401// rematerializable. Clearing the side effect bit causes miscompilations,402// probably because the instruction can be moved around.403def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),404 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,405 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {406 // A6.2 & A8.6.8407 bits<3> dst;408 bits<8> imm;409 let Inst{10-8} = dst;410 let Inst{7-0} = imm;411 let DecoderMethod = "DecodeThumbAddSpecialReg";412}413 414// Thumb1 frame lowering is rather fragile, we hope to be able to use415// tADDrSPi, but we may need to insert a sequence that clobbers CPSR.416def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset),417 NoItinerary, []>,418 Requires<[IsThumb, IsThumb1Only]> {419 let Defs = [CPSR];420}421 422// ADD sp, sp, #<imm7>423def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),424 IIC_iALUi, "add", "\t$Rdn, $imm", []>,425 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {426 // A6.2.5 & A8.6.8427 bits<7> imm;428 let Inst{6-0} = imm;429 let DecoderMethod = "DecodeThumbAddSPImm";430}431 432// SUB sp, sp, #<imm7>433// FIXME: The encoding and the ASM string don't match up.434def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),435 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,436 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {437 // A6.2.5 & A8.6.214438 bits<7> imm;439 let Inst{6-0} = imm;440 let DecoderMethod = "DecodeThumbAddSPImm";441}442 443def : tInstSubst<"add${p} sp, $imm",444 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;445def : tInstSubst<"add${p} sp, sp, $imm",446 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;447 448// Can optionally specify SP as a three operand instruction.449def : tInstAlias<"add${p} sp, sp, $imm",450 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;451def : tInstAlias<"sub${p} sp, sp, $imm",452 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;453 454// ADD <Rm>, sp455def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,456 "add", "\t$Rdn, $sp, $Rn", []>,457 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {458 // A8.6.9 Encoding T1459 bits<4> Rdn;460 let Inst{7} = Rdn{3};461 let Inst{6-3} = 0b1101;462 let Inst{2-0} = Rdn{2-0};463 let DecoderMethod = "DecodeThumbAddSPReg";464}465 466// ADD sp, <Rm>467def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,468 "add", "\t$Rdn, $Rm", []>,469 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {470 // A8.6.9 Encoding T2471 bits<4> Rm;472 let Inst{7} = 1;473 let Inst{6-3} = Rm;474 let Inst{2-0} = 0b101;475 let DecoderMethod = "DecodeThumbAddSPReg";476}477 478//===----------------------------------------------------------------------===//479// Control Flow Instructions.480//481 482// Indirect branches483let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {484 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,485 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {486 // A6.2.3 & A8.6.25487 bits<0> p;488 bits<4> Rm;489 let Inst{6-3} = Rm;490 let Inst{2-0} = 0b000;491 let Unpredictable{2-0} = 0b111;492 }493 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,494 Requires<[IsThumb, Has8MSecExt]>,495 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {496 bits<0> p;497 bits<4> Rm;498 let Inst{6-3} = Rm;499 let Inst{2-0} = 0b100;500 let Unpredictable{1-0} = 0b11;501 }502}503 504let isReturn = 1, isTerminator = 1, isBarrier = 1 in {505 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,506 [(ARMretglue)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;507 508 // alternative return for CMSE entry functions509 def tBXNS_RET : tPseudoInst<(outs), (ins), 2, IIC_Br,510 [(ARMseretglue)]>, Sched<[WriteBr]>;511 512 // Alternative return instruction used by vararg functions.513 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),514 2, IIC_Br, [],515 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;516}517 518// All calls clobber the non-callee saved registers. SP is marked as a use to519// prevent stack-pointer assignments that appear immediately before calls from520// potentially appearing dead.521let isCall = 1,522 Defs = [LR], Uses = [SP] in {523 // Also used for Thumb2524 def tBL : TIx2<0b11110, 0b11, 1,525 (outs), (ins pred:$p, thumb_bl_target:$func), IIC_Br,526 "bl${p}\t$func",527 [(ARMcall tglobaladdr:$func)]>,528 Requires<[IsThumb]>, Sched<[WriteBrL]> {529 bits<0> p;530 bits<24> func;531 let Inst{26} = func{23};532 let Inst{25-16} = func{20-11};533 let Inst{13} = func{22};534 let Inst{11} = func{21};535 let Inst{10-0} = func{10-0};536 }537 538 // ARMv5T and above, also used for Thumb2539 def tBLXi : TIx2<0b11110, 0b11, 0,540 (outs), (ins pred:$p, thumb_blx_target:$func), IIC_Br,541 "blx${p}\t$func", []>,542 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {543 bits<0> p;544 bits<24> func;545 let Inst{26} = func{23};546 let Inst{25-16} = func{20-11};547 let Inst{13} = func{22};548 let Inst{11} = func{21};549 let Inst{10-1} = func{10-1};550 let Inst{0} = 0; // func{0} is assumed zero551 }552 553 // Also used for Thumb2554 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,555 "blx${p}\t$func", []>,556 Requires<[IsThumb, HasV5T]>,557 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;558 bits<0> p;559 bits<4> func;560 let Inst{6-3} = func;561 let Inst{2-0} = 0b000;562 }563 def tBLXr_noip : ARMPseudoExpand<(outs), (ins pred:$p, GPRnoip:$func),564 2, IIC_Br, [], (tBLXr pred:$p, GPR:$func)>,565 Requires<[IsThumb, HasV5T]>,566 Sched<[WriteBrL]>;567 568 569 // ARMv8-M Security Extensions570 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br,571 "blxns${p}\t$func", []>,572 Requires<[IsThumb, Has8MSecExt]>,573 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {574 bits<0> p;575 bits<4> func;576 let Inst{6-3} = func;577 let Inst{2-0} = 0b100;578 let Unpredictable{1-0} = 0b11;579 }580 581 def tBLXNS_CALL : PseudoInst<(outs), (ins GPRnopc:$func), IIC_Br,582 [(ARMtsecall GPRnopc:$func)]>,583 Requires<[IsThumb, Has8MSecExt]>, Sched<[WriteBr]>;584 585 // ARMv4T586 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),587 4, IIC_Br,588 [(ARMcall_nolink tGPR:$func)]>,589 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;590 591 // Also used for Thumb2592 // push lr before the call593 def tBL_PUSHLR : tPseudoInst<(outs), (ins GPRlr:$ra, pred:$p, thumb_bl_target:$func),594 4, IIC_Br,595 []>,596 Requires<[IsThumb]>, Sched<[WriteBr]>;597}598 599def : ARMPat<(ARMcall GPR:$func), (tBLXr $func)>,600 Requires<[IsThumb, HasV5T, NoSLSBLRMitigation]>;601def : ARMPat<(ARMcall GPRnoip:$func), (tBLXr_noip $func)>,602 Requires<[IsThumb, HasV5T, SLSBLRMitigation]>;603 604let isBranch = 1, isTerminator = 1, isBarrier = 1 in {605 let isPredicable = 1 in606 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,607 "b", "\t$target", [(br bb:$target)]>,608 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {609 bits<11> target;610 let Inst{10-0} = target;611 let AsmMatchConverter = "cvtThumbBranches";612 }613 614 // Far jump615 // Just a pseudo for a tBL instruction. Needed to let regalloc know about616 // the clobber of LR.617 let Defs = [LR] in618 def tBfar : tPseudoExpand<(outs), (ins thumb_bl_target:$target, pred:$p),619 4, IIC_Br, [],620 (tBL pred:$p, thumb_bl_target:$target)>,621 Sched<[WriteBrTbl]>;622 623 def tBR_JTr : tPseudoInst<(outs),624 (ins tGPR:$target, i32imm:$jt),625 0, IIC_Br,626 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>,627 Sched<[WriteBrTbl]> {628 let Size = 2;629 let isNotDuplicable = 1;630 list<Predicate> Predicates = [IsThumb, IsThumb1Only];631 }632}633 634// FIXME: should be able to write a pattern for ARMBrcond, but can't use635// a two-value operand where a dag node expects two operands. :(636let isBranch = 1, isTerminator = 1 in637 def tBcc : T1I<(outs), (ins thumb_bcc_target:$target, pred:$p), IIC_Br,638 "b${p}\t$target",639 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,640 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {641 bits<4> p;642 bits<8> target;643 let Inst{11-8} = p;644 let Inst{7-0} = target;645 let AsmMatchConverter = "cvtThumbBranches";646}647 648 649// Tail calls650let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {651 // IOS versions.652 let Uses = [SP] in {653 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),654 4, IIC_Br, [],655 (tBX GPR:$dst, (ops 14, zero_reg))>,656 Requires<[IsThumb]>, Sched<[WriteBr]>;657 }658 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls659 // on MachO), so it's in ARMInstrThumb2.td.660 // Non-MachO version:661 let Uses = [SP] in {662 def tTAILJMPdND : tPseudoExpand<(outs),663 (ins t_brtarget:$dst, pred:$p),664 4, IIC_Br, [],665 (tB t_brtarget:$dst, pred:$p)>,666 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;667 }668}669 670 671// A8.6.218 Supervisor Call (Software Interrupt)672// A8.6.16 B: Encoding T1673// If Inst{11-8} == 0b1111 then SEE SVC674let isCall = 1, Uses = [SP] in675def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,676 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {677 bits<8> imm;678 let Inst{15-12} = 0b1101;679 let Inst{11-8} = 0b1111;680 let Inst{7-0} = imm;681}682 683// The assembler uses 0xDEFE for a trap instruction.684let isTrap = 1 in685def tTRAP : TI<(outs), (ins), IIC_Br,686 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {687 let Inst = 0xdefe;688}689 690//===----------------------------------------------------------------------===//691// Load Store Instructions.692//693 694// PC-relative loads need to be matched first as constant pool accesses need to695// always be PC-relative. We do this using AddedComplexity, as the pattern is696// simpler than the patterns of the other load instructions.697let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in698def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,699 "ldr", "\t$Rt, $addr",700 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,701 T1Encoding<{0,1,0,0,1,?}>, Sched<[WriteLd]> {702 // A6.2 & A8.6.59703 bits<3> Rt;704 bits<8> addr;705 let Inst{10-8} = Rt;706 let Inst{7-0} = addr;707}708 709// SP-relative loads should be matched before standard immediate-offset loads as710// it means we avoid having to move SP to another register.711let canFoldAsLoad = 1 in712def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,713 "ldr", "\t$Rt, $addr",714 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,715 T1LdStSP<{1,?,?}>, Sched<[WriteLd]> {716 bits<3> Rt;717 bits<8> addr;718 let Inst{10-8} = Rt;719 let Inst{7-0} = addr;720}721 722// Loads: reg/reg and reg/imm5723let canFoldAsLoad = 1, isReMaterializable = 1 in724multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,725 Operand AddrMode_r, Operand AddrMode_i,726 AddrMode am, InstrItinClass itin_r,727 InstrItinClass itin_i, string asm,728 PatFrag opnode> {729 // Immediate-offset loads should be matched before register-offset loads as730 // when the offset is a constant it's simpler to first check if it fits in the731 // immediate offset field then fall back to register-offset if it doesn't.732 def i : // reg/imm5733 T1pILdStEncodeImm<imm_opc, 1 /* Load */,734 (outs tGPR:$Rt), (ins AddrMode_i:$addr),735 am, itin_i, asm, "\t$Rt, $addr",736 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;737 // Register-offset loads are matched last.738 def r : // reg/reg739 T1pILdStEncode<reg_opc,740 (outs tGPR:$Rt), (ins AddrMode_r:$addr),741 am, itin_r, asm, "\t$Rt, $addr",742 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;743}744// Stores: reg/reg and reg/imm5745multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,746 Operand AddrMode_r, Operand AddrMode_i,747 AddrMode am, InstrItinClass itin_r,748 InstrItinClass itin_i, string asm,749 PatFrag opnode> {750 def i : // reg/imm5751 T1pILdStEncodeImm<imm_opc, 0 /* Store */,752 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),753 am, itin_i, asm, "\t$Rt, $addr",754 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;755 def r : // reg/reg756 T1pILdStEncode<reg_opc,757 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),758 am, itin_r, asm, "\t$Rt, $addr",759 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;760}761 762// A8.6.57 & A8.6.60763defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr,764 t_addrmode_is4, AddrModeT1_4,765 IIC_iLoad_r, IIC_iLoad_i, "ldr",766 load>, Sched<[WriteLd]>;767 768// A8.6.64 & A8.6.61769defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr,770 t_addrmode_is1, AddrModeT1_1,771 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",772 zextloadi8>, Sched<[WriteLd]>;773 774// A8.6.76 & A8.6.73775defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr,776 t_addrmode_is2, AddrModeT1_2,777 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",778 zextloadi16>, Sched<[WriteLd]>;779 780let AddedComplexity = 10 in781def tLDRSB : // A8.6.80782 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr_sext:$addr),783 AddrModeT1_1, IIC_iLoad_bh_r,784 "ldrsb", "\t$Rt, $addr",785 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>;786 787let AddedComplexity = 10 in788def tLDRSH : // A8.6.84789 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr_sext:$addr),790 AddrModeT1_2, IIC_iLoad_bh_r,791 "ldrsh", "\t$Rt, $addr",792 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>;793 794 795def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,796 "str", "\t$Rt, $addr",797 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,798 T1LdStSP<{0,?,?}>, Sched<[WriteST]> {799 bits<3> Rt;800 bits<8> addr;801 let Inst{10-8} = Rt;802 let Inst{7-0} = addr;803}804 805// A8.6.194 & A8.6.192806defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr,807 t_addrmode_is4, AddrModeT1_4,808 IIC_iStore_r, IIC_iStore_i, "str",809 store>, Sched<[WriteST]>;810 811// A8.6.197 & A8.6.195812defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr,813 t_addrmode_is1, AddrModeT1_1,814 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",815 truncstorei8>, Sched<[WriteST]>;816 817// A8.6.207 & A8.6.205818defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr,819 t_addrmode_is2, AddrModeT1_2,820 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",821 truncstorei16>, Sched<[WriteST]>;822 823 824//===----------------------------------------------------------------------===//825// Load / store multiple Instructions.826//827 828// These require base address to be written back or one of the loaded regs.829let hasSideEffects = 0 in {830 831let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in832def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),833 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {834 bits<0> p;835 bits<3> Rn;836 bits<8> regs;837 let Inst{10-8} = Rn;838 let Inst{7-0} = regs;839}840 841// Writeback version is just a pseudo, as there's no encoding difference.842// Writeback happens iff the base register is not in the destination register843// list.844let mayLoad = 1, hasExtraDefRegAllocReq = 1 in845def tLDMIA_UPD :846 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,847 "$Rn = $wb", IIC_iLoad_mu>,848 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {849 let Size = 2;850 let OutOperandList = (outs tGPR:$wb);851 let InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops);852 let Pattern = [];853 let isCodeGenOnly = 1;854 let isPseudo = 1;855 list<Predicate> Predicates = [IsThumb];856}857 858// There is no non-writeback version of STM for Thumb.859let mayStore = 1, hasExtraSrcRegAllocReq = 1 in860def tSTMIA_UPD : Thumb1I<(outs tGPR:$wb),861 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),862 AddrModeNone, 2, IIC_iStore_mu,863 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,864 T1Encoding<{1,1,0,0,0,?}> {865 bits<0> p;866 bits<3> Rn;867 bits<8> regs;868 let Inst{10-8} = Rn;869 let Inst{7-0} = regs;870}871 872} // hasSideEffects873 874def : InstAlias<"ldm${p} $Rn!, $regs",875 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,876 Requires<[IsThumb, IsThumb1Only]>;877 878let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1,879 variadicOpsAreDefs = 1 in880def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),881 IIC_iPop,882 "pop${p}\t$regs", []>,883 T1Misc<{1,1,0,?,?,?,?}>, Sched<[WriteLd]> {884 bits<0> p;885 bits<16> regs;886 let Inst{8} = regs{15};887 let Inst{7-0} = regs{7-0};888}889 890let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in891def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),892 IIC_iStore_m,893 "push${p}\t$regs", []>,894 T1Misc<{0,1,0,?,?,?,?}>, Sched<[WriteST]> {895 bits<0> p;896 bits<16> regs;897 let Inst{8} = regs{14};898 let Inst{7-0} = regs{7-0};899}900 901//===----------------------------------------------------------------------===//902// Arithmetic Instructions.903//904 905// Helper classes for encoding T1pI patterns:906class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,907 string opc, string asm, list<dag> pattern>908 : T1pI<oops, iops, itin, opc, asm, pattern>,909 T1DataProcessing<opA> {910 bits<3> Rm;911 bits<3> Rn;912 let Inst{5-3} = Rm;913 let Inst{2-0} = Rn;914}915class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,916 string opc, string asm, list<dag> pattern>917 : T1pI<oops, iops, itin, opc, asm, pattern>,918 T1Misc<opA> {919 bits<3> Rm;920 bits<3> Rd;921 let Inst{5-3} = Rm;922 let Inst{2-0} = Rd;923}924 925// Helper classes for encoding T1sI patterns:926class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,927 string opc, string asm, list<dag> pattern>928 : T1sI<oops, iops, itin, opc, asm, pattern>,929 T1DataProcessing<opA> {930 bits<3> Rd;931 bits<3> Rn;932 let Inst{5-3} = Rn;933 let Inst{2-0} = Rd;934}935class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,936 string opc, string asm, list<dag> pattern>937 : T1sI<oops, iops, itin, opc, asm, pattern>,938 T1General<opA> {939 bits<3> Rm;940 bits<3> Rn;941 bits<3> Rd;942 let Inst{8-6} = Rm;943 let Inst{5-3} = Rn;944 let Inst{2-0} = Rd;945}946class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,947 string opc, string asm, list<dag> pattern>948 : T1sI<oops, iops, itin, opc, asm, pattern>,949 T1General<opA> {950 bits<3> Rd;951 bits<3> Rm;952 let Inst{5-3} = Rm;953 let Inst{2-0} = Rd;954}955 956// Helper classes for encoding T1sIt patterns:957class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,958 string opc, string asm, list<dag> pattern>959 : T1sIt<oops, iops, itin, opc, asm, pattern>,960 T1DataProcessing<opA> {961 bits<3> Rdn;962 bits<3> Rm;963 let Inst{5-3} = Rm;964 let Inst{2-0} = Rdn;965}966class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,967 string opc, string asm, list<dag> pattern>968 : T1sIt<oops, iops, itin, opc, asm, pattern>,969 T1General<opA> {970 bits<3> Rdn;971 bits<8> imm8;972 let Inst{10-8} = Rdn;973 let Inst{7-0} = imm8;974}975 976let isAdd = 1 in {977 // Add with carry register978 let isCommutable = 1, Uses = [CPSR] in979 def tADC : // A8.6.2980 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,981 "adc", "\t$Rdn, $Rm",982 []>, Sched<[WriteALU]>;983 984 // Add immediate985 def tADDi3 : // A8.6.4 T1986 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),987 IIC_iALUi,988 "add", "\t$Rd, $Rm, $imm3",989 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,990 Sched<[WriteALU]> {991 bits<3> imm3;992 let Inst{8-6} = imm3;993 }994 995 def tADDi8 : // A8.6.4 T2996 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),997 (ins tGPR:$Rn, imm0_255_expr:$imm8), IIC_iALUi,998 "add", "\t$Rdn, $imm8",999 [(set tGPR:$Rdn, (add tGPR:$Rn, imm0_255_expr:$imm8))]>,1000 Sched<[WriteALU]>;1001 1002 // Add register1003 let isCommutable = 1 in1004 def tADDrr : // A8.6.6 T11005 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),1006 IIC_iALUr,1007 "add", "\t$Rd, $Rn, $Rm",1008 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>,1009 Sched<[WriteALU]>;1010 1011 /// Similar to the above except these set the 's' bit so the1012 /// instruction modifies the CPSR register.1013 ///1014 /// These opcodes will be converted to the real non-S opcodes by1015 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.1016 let hasPostISelHook = 1, Defs = [CPSR] in {1017 let isCommutable = 1, Uses = [CPSR] in1018 def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1019 2, IIC_iALUr,1020 [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,1021 CPSR))]>,1022 Requires<[IsThumb1Only]>,1023 Sched<[WriteALU]>;1024 1025 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),1026 2, IIC_iALUi,1027 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,1028 imm0_7:$imm3))]>,1029 Requires<[IsThumb1Only]>,1030 Sched<[WriteALU]>;1031 1032 def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255_expr:$imm8),1033 2, IIC_iALUi,1034 [(set tGPR:$Rdn, CPSR, (ARMaddc tGPR:$Rn,1035 imm0_255_expr:$imm8))]>,1036 Requires<[IsThumb1Only]>,1037 Sched<[WriteALU]>;1038 1039 let isCommutable = 1 in1040 def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),1041 2, IIC_iALUr,1042 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn,1043 tGPR:$Rm))]>,1044 Requires<[IsThumb1Only]>,1045 Sched<[WriteALU]>;1046 }1047 1048 let hasSideEffects = 0 in1049 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,1050 "add", "\t$Rdn, $Rm", []>,1051 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {1052 // A8.6.6 T21053 bits<4> Rdn;1054 bits<4> Rm;1055 let Inst{7} = Rdn{3};1056 let Inst{6-3} = Rm;1057 let Inst{2-0} = Rdn{2-0};1058 }1059}1060 1061// Thumb has more flexible short encodings for ADD than ORR, so use those where1062// possible.1063def : T1Pat<(or AddLikeOrOp:$Rn, imm0_7:$imm), (tADDi3 $Rn, imm0_7:$imm)>;1064 1065def : T1Pat<(or AddLikeOrOp:$Rn, imm8_255:$imm), (tADDi8 $Rn, imm8_255:$imm)>;1066 1067def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;1068 1069 1070def : tInstAlias <"add${s}${p} $Rdn, $Rm",1071 (tADDrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;1072 1073def : tInstSubst<"sub${s}${p} $rd, $rn, $imm",1074 (tADDi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>;1075def : tInstSubst<"sub${s}${p} $rdn, $imm",1076 (tADDi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p)>;1077 1078 1079// AND register1080let isCommutable = 1 in1081def tAND : // A8.6.121082 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1083 IIC_iBITr,1084 "and", "\t$Rdn, $Rm",1085 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;1086 1087// ASR immediate1088def tASRri : // A8.6.141089 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),1090 IIC_iMOVsi,1091 "asr", "\t$Rd, $Rm, $imm5",1092 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,1093 Sched<[WriteALU]> {1094 bits<5> imm5;1095 let Inst{10-6} = imm5;1096}1097 1098// ASR register1099def tASRrr : // A8.6.151100 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1101 IIC_iMOVsr,1102 "asr", "\t$Rdn, $Rm",1103 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;1104 1105// BIC register1106def tBIC : // A8.6.201107 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1108 IIC_iBITr,1109 "bic", "\t$Rdn, $Rm",1110 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,1111 Sched<[WriteALU]>;1112 1113// CMN register1114let isCompare = 1, Defs = [CPSR] in {1115//FIXME: Disable CMN, as CCodes are backwards from compare expectations1116// Compare-to-zero still works out, just not the relationals1117//def tCMN : // A8.6.331118// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),1119// IIC_iCMPr,1120// "cmn", "\t$lhs, $rhs",1121// [(set CPSR, (ARMcmp tGPR:$lhs, (ineg tGPR:$rhs)))]>;1122 1123def tCMNz : // A8.6.331124 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),1125 IIC_iCMPr,1126 "cmn", "\t$Rn, $Rm",1127 [(set CPSR, (ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm)))]>,1128 Sched<[WriteCMP]>;1129 1130} // isCompare = 1, Defs = [CPSR]1131 1132// CMP immediate1133let isCompare = 1, Defs = [CPSR] in {1134def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,1135 "cmp", "\t$Rn, $imm8",1136 [(set CPSR, (ARMcmp tGPR:$Rn, imm0_255:$imm8))]>,1137 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {1138 // A8.6.351139 bits<3> Rn;1140 bits<8> imm8;1141 let Inst{10-8} = Rn;1142 let Inst{7-0} = imm8;1143}1144 1145// CMP register1146def tCMPr : // A8.6.36 T11147 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),1148 IIC_iCMPr,1149 "cmp", "\t$Rn, $Rm",1150 [(set CPSR, (ARMcmp tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteCMP]>;1151 1152def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,1153 "cmp", "\t$Rn, $Rm", []>,1154 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {1155 // A8.6.36 T21156 bits<4> Rm;1157 bits<4> Rn;1158 let Inst{7} = Rn{3};1159 let Inst{6-3} = Rm;1160 let Inst{2-0} = Rn{2-0};1161}1162} // isCompare = 1, Defs = [CPSR]1163 1164 1165// XOR register1166let isCommutable = 1 in1167def tEOR : // A8.6.451168 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1169 IIC_iBITr,1170 "eor", "\t$Rdn, $Rm",1171 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;1172 1173// LSL immediate1174def tLSLri : // A8.6.881175 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),1176 IIC_iMOVsi,1177 "lsl", "\t$Rd, $Rm, $imm5",1178 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,1179 Sched<[WriteALU]> {1180 bits<5> imm5;1181 let Inst{10-6} = imm5;1182}1183 1184// LSL register1185def tLSLrr : // A8.6.891186 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1187 IIC_iMOVsr,1188 "lsl", "\t$Rdn, $Rm",1189 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;1190 1191// LSR immediate1192def tLSRri : // A8.6.901193 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),1194 IIC_iMOVsi,1195 "lsr", "\t$Rd, $Rm, $imm5",1196 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,1197 Sched<[WriteALU]> {1198 bits<5> imm5;1199 let Inst{10-6} = imm5;1200}1201 1202// LSR register1203def tLSRrr : // A8.6.911204 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1205 IIC_iMOVsr,1206 "lsr", "\t$Rdn, $Rm",1207 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;1208 1209// Move register1210let isMoveImm = 1 in1211def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255_expr:$imm8), IIC_iMOVi,1212 "mov", "\t$Rd, $imm8",1213 [(set tGPR:$Rd, imm0_255_expr:$imm8)]>,1214 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {1215 // A8.6.961216 bits<3> Rd;1217 bits<8> imm8;1218 let Inst{10-8} = Rd;1219 let Inst{7-0} = imm8;1220}1221// Because we have an explicit tMOVSr below, we need an alias to handle1222// the immediate "movs" form here. Blech.1223def : tInstAlias<"movs $Rdn, $imm8",1224 (tMOVi8 tGPR:$Rdn, (s_cc_out CPSR),1225 imm0_255_expr:$imm8, (pred 14, zero_reg))>;1226 1227// A7-73: MOV(2) - mov setting flag.1228 1229let hasSideEffects = 0, isMoveReg = 1 in {1230def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,1231 2, IIC_iMOVr,1232 "mov", "\t$Rd, $Rm", "", []>,1233 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {1234 // A8.6.971235 bits<4> Rd;1236 bits<4> Rm;1237 let Inst{7} = Rd{3};1238 let Inst{6-3} = Rm;1239 let Inst{2-0} = Rd{2-0};1240}1241let Defs = [CPSR] in1242def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,1243 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {1244 // A8.6.971245 bits<3> Rd;1246 bits<3> Rm;1247 let Inst{15-6} = 0b0000000000;1248 let Inst{5-3} = Rm;1249 let Inst{2-0} = Rd;1250}1251} // hasSideEffects1252 1253// Multiply register1254let isCommutable = 1 in1255def tMUL : // A8.6.105 T11256 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,1257 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",1258 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,1259 T1DataProcessing<0b1101>, Sched<[WriteMUL32, ReadMUL, ReadMUL]> {1260 bits<3> Rd;1261 bits<3> Rn;1262 let Inst{5-3} = Rn;1263 let Inst{2-0} = Rd;1264 let AsmMatchConverter = "cvtThumbMultiply";1265}1266 1267def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,1268 pred:$p)>;1269 1270// Move inverse register1271def tMVN : // A8.6.1071272 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,1273 "mvn", "\t$Rd, $Rn",1274 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;1275 1276// Bitwise or register1277let isCommutable = 1 in1278def tORR : // A8.6.1141279 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1280 IIC_iBITr,1281 "orr", "\t$Rdn, $Rm",1282 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;1283 1284// Swaps1285def tREV : // A8.6.1341286 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),1287 IIC_iUNAr,1288 "rev", "\t$Rd, $Rm",1289 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,1290 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;1291 1292def tREV16 : // A8.6.1351293 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),1294 IIC_iUNAr,1295 "rev16", "\t$Rd, $Rm",1296 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,1297 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;1298 1299def tREVSH : // A8.6.1361300 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),1301 IIC_iUNAr,1302 "revsh", "\t$Rd, $Rm",1303 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,1304 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;1305 1306// Rotate right register1307def tROR : // A8.6.1391308 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1309 IIC_iMOVsr,1310 "ror", "\t$Rdn, $Rm",1311 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,1312 Sched<[WriteALU]>;1313 1314// Negate register1315def tRSB : // A8.6.1411316 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),1317 IIC_iALUi,1318 "rsb", "\t$Rd, $Rn, #0",1319 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;1320 1321// Subtract with carry register1322let Uses = [CPSR] in1323def tSBC : // A8.6.1511324 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1325 IIC_iALUr,1326 "sbc", "\t$Rdn, $Rm",1327 []>,1328 Sched<[WriteALU]>;1329 1330// Subtract immediate1331def tSUBi3 : // A8.6.210 T11332 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),1333 IIC_iALUi,1334 "sub", "\t$Rd, $Rm, $imm3",1335 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,1336 Sched<[WriteALU]> {1337 bits<3> imm3;1338 let Inst{8-6} = imm3;1339}1340 1341def tSUBi8 : // A8.6.210 T21342 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),1343 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,1344 "sub", "\t$Rdn, $imm8",1345 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,1346 Sched<[WriteALU]>;1347 1348def : tInstSubst<"add${s}${p} $rd, $rn, $imm",1349 (tSUBi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>;1350 1351 1352def : tInstSubst<"add${s}${p} $rdn, $imm",1353 (tSUBi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p)>;1354 1355 1356// Subtract register1357def tSUBrr : // A8.6.2121358 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),1359 IIC_iALUr,1360 "sub", "\t$Rd, $Rn, $Rm",1361 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,1362 Sched<[WriteALU]>;1363 1364def : tInstAlias <"sub${s}${p} $Rdn, $Rm",1365 (tSUBrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;1366 1367/// Similar to the above except these set the 's' bit so the1368/// instruction modifies the CPSR register.1369///1370/// These opcodes will be converted to the real non-S opcodes by1371/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.1372let hasPostISelHook = 1, Defs = [CPSR] in {1373 let Uses = [CPSR] in1374 def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),1375 2, IIC_iALUr,1376 [(set tGPR:$Rdn, CPSR, (ARMsube tGPR:$Rn, tGPR:$Rm,1377 CPSR))]>,1378 Requires<[IsThumb1Only]>,1379 Sched<[WriteALU]>;1380 1381 def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),1382 2, IIC_iALUi,1383 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rm,1384 imm0_7:$imm3))]>,1385 Requires<[IsThumb1Only]>,1386 Sched<[WriteALU]>;1387 1388 def tSUBSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),1389 2, IIC_iALUi,1390 [(set tGPR:$Rdn, CPSR, (ARMsubc tGPR:$Rn,1391 imm8_255:$imm8))]>,1392 Requires<[IsThumb1Only]>,1393 Sched<[WriteALU]>;1394 1395 def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),1396 2, IIC_iALUr,1397 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn,1398 tGPR:$Rm))]>,1399 Requires<[IsThumb1Only]>,1400 Sched<[WriteALU]>;1401 1402 def tRSBS : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn),1403 2, IIC_iALUr,1404 [(set tGPR:$Rd, CPSR, (ARMsubc 0, tGPR:$Rn))]>,1405 Requires<[IsThumb1Only]>,1406 Sched<[WriteALU]>;1407 1408 def tLSLSri : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, imm0_31:$imm5),1409 2, IIC_iALUr,1410 [(set tGPR:$Rd, CPSR, (ARMlsls tGPR:$Rn, imm0_31:$imm5))]>,1411 Requires<[IsThumb1Only]>,1412 Sched<[WriteALU]>;1413}1414 1415// Sign-extend byte1416def tSXTB : // A8.6.2221417 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),1418 IIC_iUNAr,1419 "sxtb", "\t$Rd, $Rm",1420 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,1421 Requires<[IsThumb, IsThumb1Only, HasV6]>,1422 Sched<[WriteALU]>;1423 1424// Sign-extend short1425def tSXTH : // A8.6.2241426 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),1427 IIC_iUNAr,1428 "sxth", "\t$Rd, $Rm",1429 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,1430 Requires<[IsThumb, IsThumb1Only, HasV6]>,1431 Sched<[WriteALU]>;1432 1433// Test1434let isCompare = 1, isCommutable = 1, Defs = [CPSR] in1435def tTST : // A8.6.2301436 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,1437 "tst", "\t$Rn, $Rm",1438 [(set CPSR, (ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0))]>,1439 Sched<[WriteALU]>;1440 1441// A8.8.247 UDF - Undefined (Encoding T1)1442def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8",1443 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 {1444 bits<8> imm8;1445 let Inst{15-12} = 0b1101;1446 let Inst{11-8} = 0b1110;1447 let Inst{7-0} = imm8;1448}1449 1450def : Pat<(debugtrap), (tBKPT 0)>, Requires<[IsThumb, HasV5T]>;1451def : Pat<(debugtrap), (tUDF 254)>, Requires<[IsThumb, NoV5T]>;1452 1453def t__brkdiv0 : TI<(outs), (ins), IIC_Br, "__brkdiv0",1454 [(int_arm_undefined 249)]>, Encoding16,1455 Requires<[IsThumb, IsWindows]> {1456 let Inst = 0xdef9;1457 let isTerminator = 1;1458}1459 1460// Zero-extend byte1461def tUXTB : // A8.6.2621462 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),1463 IIC_iUNAr,1464 "uxtb", "\t$Rd, $Rm",1465 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,1466 Requires<[IsThumb, IsThumb1Only, HasV6]>,1467 Sched<[WriteALU]>;1468 1469// Zero-extend short1470def tUXTH : // A8.6.2641471 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),1472 IIC_iUNAr,1473 "uxth", "\t$Rd, $Rm",1474 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,1475 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;1476 1477// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.1478// Expanded after instruction selection into a branch sequence.1479let usesCustomInserter = 1 in // Expanded after instruction selection.1480 def tMOVCCr_pseudo :1481 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$p),1482 NoItinerary, []>;1483 1484def : Pat<(ARMcmov tGPR:$false, tGPR:$true, imm:$cc, CPSR),1485 (tMOVCCr_pseudo $false, $true, imm:$cc, CPSR)>;1486 1487// tLEApcrel - Load a pc-relative address into a register without offending the1488// assembler.1489 1490def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),1491 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,1492 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {1493 bits<3> Rd;1494 bits<8> addr;1495 let Inst{10-8} = Rd;1496 let Inst{7-0} = addr;1497 let DecoderMethod = "DecodeThumbAddSpecialReg";1498}1499 1500let hasSideEffects = 0, isReMaterializable = 1 in1501def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),1502 2, IIC_iALUi, []>, Sched<[WriteALU]>;1503 1504let hasSideEffects = 1 in1505def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),1506 (ins i32imm:$label, pred:$p),1507 2, IIC_iALUi, []>, Sched<[WriteALU]>;1508 1509// Thumb-1 doesn't have the TBB or TBH instructions, but we can synthesize them1510// and make use of the same compressed jump table format as Thumb-2.1511let Size = 2, isBranch = 1, isTerminator = 1, isBarrier = 1,1512 isIndirectBranch = 1, isNotDuplicable = 1 in {1513def tTBB_JT : tPseudoInst<(outs),1514 (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0,1515 IIC_Br, []>, Sched<[WriteBr]>;1516 1517def tTBH_JT : tPseudoInst<(outs),1518 (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0,1519 IIC_Br, []>, Sched<[WriteBr]>;1520}1521 1522//===----------------------------------------------------------------------===//1523// TLS Instructions1524//1525 1526// __aeabi_read_tp preserves the registers r1-r3.1527// This is a pseudo inst so that we can get the encoding right,1528// complete with fixup for the aeabi_read_tp function.1529let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in1530def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,1531 [(set R0, ARMthread_pointer)]>,1532 Requires<[IsThumb, IsReadTPSoft]>,1533 Sched<[WriteBr]>;1534 1535//===----------------------------------------------------------------------===//1536// SJLJ Exception handling intrinsics1537//1538 1539// eh_sjlj_setjmp() is an instruction sequence to store the return address and1540// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming1541// from some other function to get here, and we're using the stack frame for the1542// containing function to save/restore registers, we can't keep anything live in1543// regs across the eh_sjlj_setjmp(), else it will almost certainly have been1544// tromped upon when we get here from a longjmp(). We force everything out of1545// registers except for our own input by listing the relevant registers in1546// Defs. By doing so, we also cause the prologue/epilogue code to actively1547// preserve all of the callee-saved registers, which is exactly what we want.1548// $val is a scratch register for our use.1549// This gets lowered to an instruction sequence of 12 bytes1550let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],1551 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, Size = 12,1552 usesCustomInserter = 1 in1553def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),1554 AddrModeNone, 0, NoItinerary, "","",1555 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;1556 1557// This gets lowered to an instruction sequence of 10 bytes1558// FIXME: Non-IOS version(s)1559let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,1560 Size = 10, Defs = [ R7, LR, SP ] in1561def tInt_eh_sjlj_longjmp : XI<(outs), (ins tGPR:$src, tGPR:$scratch),1562 AddrModeNone, 0, IndexModeNone,1563 Pseudo, NoItinerary, "", "",1564 [(ARMeh_sjlj_longjmp tGPR:$src, tGPR:$scratch)]>,1565 Requires<[IsThumb,IsNotWindows]>;1566 1567// This gets lowered to an instruction sequence of 12 bytes1568// (Windows is Thumb2-only)1569let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,1570 Size = 12, Defs = [ R11, LR, SP ] in1571def tInt_WIN_eh_sjlj_longjmp1572 : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone,1573 Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,1574 Requires<[IsThumb,IsWindows]>;1575 1576//===----------------------------------------------------------------------===//1577// Non-Instruction Patterns1578//1579 1580// Comparisons1581def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),1582 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;1583def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),1584 (tCMPr tGPR:$Rn, tGPR:$Rm)>;1585 1586// Bswap 16 with load/store1587def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),1588 (tREV16 (tLDRHi t_addrmode_is2:$addr))>;1589def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)),1590 (tREV16 (tLDRHr t_addrmode_rr:$addr))>;1591def : T1Pat<(srl (bswap top16Zero:$Rn), (i32 16)),1592 (tREV16 tGPR:$Rn)>;1593def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),1594 t_addrmode_is2:$addr),1595 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>;1596def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),1597 t_addrmode_rr:$addr),1598 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>;1599 1600// ConstantPool1601def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;1602 1603// GlobalAddress1604def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr),1605 IIC_iLoadiALU,1606 [(set tGPR:$dst,1607 (ARMWrapperPIC tglobaladdr:$addr))]>,1608 Requires<[IsThumb, DontUseMovtInPic]>;1609 1610def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),1611 IIC_iLoad_i,1612 [(set tGPR:$dst,1613 (ARMWrapper tglobaladdr:$src))]>,1614 Requires<[IsThumb, DontUseMovt, DontGenExecuteOnly]>;1615 1616// 32-bit immediate using mov/add with the 4 :lower0_7: to :upper8_15:1617// relocations.1618// This is a single pseudo instruction to make it re-materializable.1619// FIXME: Remove this when we can do generalized remat.1620let Defs = [CPSR], isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in1621def tMOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), NoItinerary,1622 [(set rGPR:$dst, (i32 imm:$src))]>,1623 Requires<[IsThumb1Only, GenExecuteOnly, DontUseMovt]>;1624 1625def : ARMPat<(ARMWrapper tglobaladdr :$dst), (tMOVi32imm tglobaladdr :$dst)>,1626 Requires<[GenT1ExecuteOnly]>;1627def : ARMPat<(ARMWrapper texternalsym :$dst), (tMOVi32imm texternalsym :$dst)>,1628 Requires<[GenT1ExecuteOnly]>;1629 1630 1631// TLS globals1632def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),1633 (tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,1634 Requires<[IsThumb, DontUseMovtInPic]>;1635def : Pat<(ARMWrapper tglobaltlsaddr:$addr),1636 (tLDRLIT_ga_abs tglobaltlsaddr:$addr)>,1637 Requires<[IsThumb, DontUseMovt]>;1638 1639 1640// JumpTable1641def : T1Pat<(ARMWrapperJT tjumptable:$dst),1642 (tLEApcrelJT tjumptable:$dst)>;1643 1644// Direct calls1645def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>,1646 Requires<[IsThumb]>;1647 1648// zextload i1 -> zextload i81649def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),1650 (tLDRBi t_addrmode_is1:$addr)>;1651def : T1Pat<(zextloadi1 t_addrmode_rr:$addr),1652 (tLDRBr t_addrmode_rr:$addr)>;1653 1654// extload from the stack -> word load from the stack, as it avoids having to1655// materialize the base in a separate register. This only works when a word1656// load puts the byte/halfword value in the same place in the register that the1657// byte/halfword load would, i.e. when little-endian.1658def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,1659 Requires<[IsThumb, IsThumb1Only, IsLE]>;1660def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,1661 Requires<[IsThumb, IsThumb1Only, IsLE]>;1662def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,1663 Requires<[IsThumb, IsThumb1Only, IsLE]>;1664 1665// extload -> zextload1666def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;1667def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;1668def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;1669def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;1670def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;1671def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>;1672 1673// post-inc loads and stores1674 1675// post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is1676// different to how ISel expects them for a post-inc load, so use a pseudo1677// and expand it just after ISel.1678let usesCustomInserter = 1, mayLoad =1,1679 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in1680 def tLDR_postidx: tPseudoInst<(outs tGPR:$Rt, tGPR:$Rn_wb),1681 (ins tGPR:$Rn, pred:$p),1682 4, IIC_iStore_ru,1683 []>;1684 1685// post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def1686// multiple registers) is the same in ISel as MachineInstr, so there's no need1687// for a pseudo.1688def : T1Pat<(post_store tGPR:$Rt, tGPR:$Rn, 4),1689 (tSTMIA_UPD tGPR:$Rn, tGPR:$Rt)>;1690 1691// If it's impossible to use [r,r] address mode for sextload, select to1692// ldsr{b|h} r, 0 instead, in a hope that the mov 0 will be more likely to be1693// commoned out than a sxth.1694let AddedComplexity = 10 in {1695def : T1Pat<(sextloadi8 tGPR:$Rn),1696 (tLDRSB tGPR:$Rn, (tMOVi8 0))>,1697 Requires<[IsThumb, IsThumb1Only, HasV6]>;1698def : T1Pat<(sextloadi16 tGPR:$Rn),1699 (tLDRSH tGPR:$Rn, (tMOVi8 0))>,1700 Requires<[IsThumb, IsThumb1Only, HasV6]>;1701}1702 1703def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),1704 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;1705def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),1706 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>;1707def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),1708 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;1709def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),1710 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>;1711 1712def : T1Pat<(atomic_load_azext_8 t_addrmode_is1:$src),1713 (tLDRBi t_addrmode_is1:$src)>;1714def : T1Pat<(atomic_load_azext_8 t_addrmode_rr:$src),1715 (tLDRBr t_addrmode_rr:$src)>;1716def : T1Pat<(atomic_load_azext_16 t_addrmode_is2:$src),1717 (tLDRHi t_addrmode_is2:$src)>;1718def : T1Pat<(atomic_load_azext_16 t_addrmode_rr:$src),1719 (tLDRHr t_addrmode_rr:$src)>;1720def : T1Pat<(atomic_load_nonext_32 t_addrmode_is4:$src),1721 (tLDRi t_addrmode_is4:$src)>;1722def : T1Pat<(atomic_load_nonext_32 t_addrmode_rr:$src),1723 (tLDRr t_addrmode_rr:$src)>;1724def : T1Pat<(atomic_store_8 tGPR:$val, t_addrmode_is1:$ptr),1725 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;1726def : T1Pat<(atomic_store_8 tGPR:$val, t_addrmode_rr:$ptr),1727 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>;1728def : T1Pat<(atomic_store_16 tGPR:$val, t_addrmode_is2:$ptr),1729 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;1730def : T1Pat<(atomic_store_16 tGPR:$val, t_addrmode_rr:$ptr),1731 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>;1732def : T1Pat<(atomic_store_32 tGPR:$val, t_addrmode_is4:$ptr),1733 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;1734def : T1Pat<(atomic_store_32 tGPR:$val, t_addrmode_rr:$ptr),1735 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>;1736 1737// Large immediate handling.1738 1739// Two piece imms.1740def : T1Pat<(i32 thumb_immshifted:$src),1741 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),1742 (thumb_immshifted_shamt imm:$src))>;1743 1744def : T1Pat<(i32 imm0_255_comp:$src),1745 (tMVN (tMOVi8 (imm_not_XFORM imm:$src)))>;1746 1747def : T1Pat<(i32 imm256_510:$src),1748 (tADDi8 (tMOVi8 255),1749 (thumb_imm256_510_addend imm:$src))>;1750 1751// Pseudo instruction that combines ldr from constpool and add pc. This should1752// be expanded into two instructions late to allow if-conversion and1753// scheduling.1754let isReMaterializable = 1 in1755def tLDRpci_pic : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr, pclabel:$cp),1756 NoItinerary,1757 [(set tGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),1758 imm:$cp))]>,1759 Requires<[IsThumb, IsThumb1Only]>;1760 1761// Pseudo-instruction for merged POP and return.1762// FIXME: remove when we have a way to marking a MI with these properties.1763let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,1764 hasExtraDefRegAllocReq = 1 in1765def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),1766 2, IIC_iPop_Br, [],1767 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;1768 1769// Indirect branch using "mov pc, $Rm"1770let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {1771 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),1772 2, IIC_Br, [(brind GPR:$Rm)],1773 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;1774}1775 1776 1777// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf001778// encoding is available on ARMv6K, but we don't differentiate that finely.1779def : InstAlias<"nop", (tMOVr R8, R8, (pred 14, zero_reg)), 0>,1780 Requires<[IsThumb, IsThumb1Only]>;1781 1782 1783// "neg" is and alias for "rsb rd, rn, #0"1784def : tInstAlias<"neg${s}${p} $Rd, $Rm",1785 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;1786 1787 1788// Implied destination operand forms for shifts.1789def : tInstAlias<"lsl${s}${p} $Rdm, $imm",1790 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;1791def : tInstAlias<"lsr${s}${p} $Rdm, $imm",1792 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;1793def : tInstAlias<"asr${s}${p} $Rdm, $imm",1794 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;1795 1796// Pseudo instruction ldr Rt, =immediate1797def tLDRConstPool1798 : tAsmPseudo<"ldr${p} $Rt, $immediate",1799 (ins tGPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;1800 1801//===----------------------------------1802// Atomic cmpxchg for -O01803//===----------------------------------1804 1805// See ARMInstrInfo.td. These two thumb specific pseudos are required to1806// restrict the register class for the UXTB/UXTH ops used in the expansion.1807 1808let Constraints = "@earlyclobber $Rd,@earlyclobber $temp",1809 mayLoad = 1, mayStore = 1 in {1810def tCMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),1811 (ins GPR:$addr, tGPR:$desired, GPR:$new),1812 NoItinerary, []>, Sched<[]>;1813 1814def tCMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),1815 (ins GPR:$addr, tGPR:$desired, GPR:$new),1816 NoItinerary, []>, Sched<[]>;1817 1818def tCMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),1819 (ins GPR:$addr, GPR:$desired, GPR:$new),1820 NoItinerary, []>, Sched<[]>;1821}1822