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1//===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the Thumb2 instruction set.10//11//===----------------------------------------------------------------------===//12 13// IT block predicate field14def it_pred_asmoperand : AsmOperandClass {15 let Name = "ITCondCode";16 let ParserMethod = "parseITCondCode";17}18def it_pred : Operand<i32> {19 let PrintMethod = "printMandatoryPredicateOperand";20 let ParserMatchClass = it_pred_asmoperand;21}22 23// IT block condition mask24def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }25def it_mask : Operand<i32> {26 let PrintMethod = "printThumbITMask";27 let ParserMatchClass = it_mask_asmoperand;28 let EncoderMethod = "getITMaskOpValue";29}30 31// t2_shift_imm: An integer that encodes a shift amount and the type of shift32// (asr or lsl). The 6-bit immediate encodes as:33// {5} 0 ==> lsl34// 1 asr35// {4-0} imm5 shift amount.36// asr #32 not allowed37def t2_shift_imm : Operand<i32> {38 let PrintMethod = "printShiftImmOperand";39 let ParserMatchClass = ShifterImmAsmOperand;40 let DecoderMethod = "DecodeT2ShifterImmOperand";41}42 43def mve_shift_imm : AsmOperandClass {44 let Name = "MVELongShift";45 let RenderMethod = "addImmOperands";46 let DiagnosticString = "operand must be an immediate in the range [1,32]";47}48def long_shift : Operand<i32>,49 ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> {50 let ParserMatchClass = mve_shift_imm;51 let DecoderMethod = "DecodeLongShiftOperand";52}53 54// Shifted operands. No register controlled shifts for Thumb2.55// Note: We do not support rrx shifted operands yet.56def t2_so_reg : Operand<i32>, // reg imm57 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",58 [shl,srl,sra,rotr]> {59 let EncoderMethod = "getT2SORegOpValue";60 let PrintMethod = "printT2SOOperand";61 let DecoderMethod = "DecodeSORegImmOperand";62 let ParserMatchClass = ShiftedImmAsmOperand;63 let MIOperandInfo = (ops rGPR, i32imm);64}65 66// Same as above, but only matching on a single use node.67def t2_so_reg_oneuse : Operand<i32>,68 ComplexPattern<i32, 2,69 "SelectShiftImmShifterOperandOneUse",70 [shl,srl,sra,rotr]>;71 72// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value73def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{74 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),75 MVT::i32);76}]>;77 78// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value79def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{80 return CurDAG->getSignedTargetConstant(-((int)N->getZExtValue()), SDLoc(N),81 MVT::i32);82}]>;83 84// so_imm_notSext_XFORM - Return a so_imm value packed into the format85// described for so_imm_notSext def below, with sign extension from 1686// bits.87def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{88 APInt apIntN = N->getAPIntValue();89 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();90 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);91}]>;92 93// t2_so_imm - Match a 32-bit immediate operand, which is an94// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit95// immediate splatted into multiple bytes of the word.96def t2_so_imm_asmoperand : AsmOperandClass {97 let Name = "T2SOImm";98 let RenderMethod = "addImmOperands";99 100}101def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{102 return ARM_AM::getT2SOImmVal(Imm) != -1;103 }]> {104 let ParserMatchClass = t2_so_imm_asmoperand;105 let EncoderMethod = "getT2SOImmOpValue";106 let DecoderMethod = "DecodeT2SOImm";107}108 109// t2_so_imm_not - Match an immediate that is a complement110// of a t2_so_imm.111// Note: this pattern doesn't require an encoder method and such, as it's112// only used on aliases (Pat<> and InstAlias<>). The actual encoding113// is handled by the destination instructions, which use t2_so_imm.114def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }115def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{116 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;117}], t2_so_imm_not_XFORM> {118 let ParserMatchClass = t2_so_imm_not_asmoperand;119}120 121// t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm122// if the upper 16 bits are zero.123def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{124 APInt apIntN = N->getAPIntValue();125 if (!apIntN.isIntN(16)) return false;126 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();127 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;128 }], t2_so_imm_notSext16_XFORM> {129 let ParserMatchClass = t2_so_imm_not_asmoperand;130}131 132// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.133def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }134def t2_so_imm_neg : Operand<i32>, ImmLeaf<i32, [{135 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;136}], t2_so_imm_neg_XFORM> {137 let ParserMatchClass = t2_so_imm_neg_asmoperand;138}139 140/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095].141def imm0_4095_asmoperand: ImmAsmOperand<0,4095> { let Name = "Imm0_4095"; }142def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{143 return Imm >= 0 && Imm < 4096;144}]> {145 let ParserMatchClass = imm0_4095_asmoperand;146}147 148def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }149def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{150 return (uint32_t)(-N->getZExtValue()) < 4096;151}], imm_neg_XFORM> {152 let ParserMatchClass = imm0_4095_neg_asmoperand;153}154 155def imm1_255_neg : PatLeaf<(i32 imm), [{156 uint32_t Val = -N->getZExtValue();157 return (Val > 0 && Val < 255);158}], imm_neg_XFORM>;159 160def imm0_255_not : PatLeaf<(i32 imm), [{161 return (uint32_t)(~N->getZExtValue()) < 255;162}], imm_not_XFORM>;163 164def lo5AllOne : PatLeaf<(i32 imm), [{165 // Returns true if all low 5-bits are 1.166 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;167}]>;168 169// Define Thumb2 specific addressing modes.170 171// t2_addr_offset_none := reg172def MemNoOffsetT2AsmOperand173 : AsmOperandClass { let Name = "MemNoOffsetT2"; }174def t2_addr_offset_none : MemOperand {175 let PrintMethod = "printAddrMode7Operand";176 let DecoderMethod = "DecodeGPRnopcRegisterClass";177 let ParserMatchClass = MemNoOffsetT2AsmOperand;178 let MIOperandInfo = (ops GPRnopc:$base);179}180 181// t2_nosp_addr_offset_none := reg182def MemNoOffsetT2NoSpAsmOperand183 : AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; }184def t2_nosp_addr_offset_none : MemOperand {185 let PrintMethod = "printAddrMode7Operand";186 let DecoderMethod = "DecoderGPRRegisterClass";187 let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand;188 let MIOperandInfo = (ops rGPR:$base);189}190 191// t2addrmode_imm12 := reg + imm12192def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}193def t2addrmode_imm12 : MemOperand,194 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {195 let PrintMethod = "printAddrModeImm12Operand<false>";196 let EncoderMethod = "getAddrModeImm12OpValue";197 let DecoderMethod = "DecodeT2AddrModeImm12";198 let ParserMatchClass = t2addrmode_imm12_asmoperand;199 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);200}201 202// t2ldrlabel := imm12203def t2ldrlabel : MemOperand {204 let EncoderMethod = "getAddrModeImm12OpValue";205 let PrintMethod = "printThumbLdrLabelOperand";206}207 208def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}209def t2ldr_pcrel_imm12 : Operand<i32> {210 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;211 // used for assembler pseudo instruction and maps to t2ldrlabel, so212 // doesn't need encoder or print methods of its own.213}214 215// ADR instruction labels.216def t2adrlabel : Operand<i32> {217 let EncoderMethod = "getT2AdrLabelOpValue";218 let PrintMethod = "printAdrLabelOperand<0>";219}220 221// t2addrmode_posimm8 := reg + imm8222def MemPosImm8OffsetAsmOperand : AsmOperandClass {223 let Name="MemPosImm8Offset";224 let RenderMethod = "addMemImmOffsetOperands";225}226def t2addrmode_posimm8 : MemOperand {227 let PrintMethod = "printT2AddrModeImm8Operand<false>";228 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";229 let DecoderMethod = "DecodeT2AddrModeImm8";230 let ParserMatchClass = MemPosImm8OffsetAsmOperand;231 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);232}233 234// t2addrmode_negimm8 := reg - imm8235def MemNegImm8OffsetAsmOperand : AsmOperandClass {236 let Name="MemNegImm8Offset";237 let RenderMethod = "addMemImmOffsetOperands";238}239def t2addrmode_negimm8 : MemOperand,240 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {241 let PrintMethod = "printT2AddrModeImm8Operand<false>";242 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";243 let DecoderMethod = "DecodeT2AddrModeImm8";244 let ParserMatchClass = MemNegImm8OffsetAsmOperand;245 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);246}247 248// t2addrmode_imm8 := reg +/- imm8249def MemImm8OffsetAsmOperand : AsmOperandClass {250 let Name = "MemImm8Offset";251 let RenderMethod = "addMemImmOffsetOperands";252}253class T2AddrMode_Imm8 : MemOperand,254 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {255 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";256 let DecoderMethod = "DecodeT2AddrModeImm8";257 let ParserMatchClass = MemImm8OffsetAsmOperand;258 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);259}260 261def t2addrmode_imm8 : T2AddrMode_Imm8 {262 let PrintMethod = "printT2AddrModeImm8Operand<false>";263}264 265def t2addrmode_imm8_pre : T2AddrMode_Imm8 {266 let PrintMethod = "printT2AddrModeImm8Operand<true>";267}268 269def t2am_imm8_offset : MemOperand,270 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset"> {271 let PrintMethod = "printT2AddrModeImm8OffsetOperand";272 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";273 let DecoderMethod = "DecodeT2Imm8";274 let WantsRoot = true;275}276 277// t2addrmode_imm8s4 := reg +/- (imm8 << 2)278def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}279class T2AddrMode_Imm8s4 : MemOperand,280 ComplexPattern<i32, 2, "SelectT2AddrModeImm8<2>", []> {281 let EncoderMethod = "getT2AddrModeImm8s4OpValue";282 let DecoderMethod = "DecodeT2AddrModeImm8s4";283 let ParserMatchClass = MemImm8s4OffsetAsmOperand;284 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);285}286 287def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {288 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";289}290 291def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {292 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";293}294 295def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }296def t2am_imm8s4_offset : MemOperand {297 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";298 let EncoderMethod = "getT2ScaledImmOpValue<8,2>";299 let DecoderMethod = "DecodeT2Imm8S4";300}301 302// t2addrmode_imm7s4 := reg +/- (imm7 << 2)303def MemImm7s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm7s4Offset";}304class T2AddrMode_Imm7s4 : MemOperand {305 let EncoderMethod = "getT2AddrModeImm7s4OpValue";306 let DecoderMethod = "DecodeT2AddrModeImm7<2,0>";307 let ParserMatchClass = MemImm7s4OffsetAsmOperand;308 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);309}310 311def t2addrmode_imm7s4 : T2AddrMode_Imm7s4 {312 // They are printed the same way as the imm8 version313 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";314}315 316def t2addrmode_imm7s4_pre : T2AddrMode_Imm7s4 {317 // They are printed the same way as the imm8 version318 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";319}320 321def t2am_imm7s4_offset_asmoperand : AsmOperandClass { let Name = "Imm7s4"; }322def t2am_imm7s4_offset : MemOperand {323 // They are printed the same way as the imm8 version324 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";325 let ParserMatchClass = t2am_imm7s4_offset_asmoperand;326 let EncoderMethod = "getT2ScaledImmOpValue<7,2>";327 let DecoderMethod = "DecodeT2Imm7S4";328}329 330// t2addrmode_imm0_1020s4 := reg + (imm8 << 2)331def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {332 let Name = "MemImm0_1020s4Offset";333}334def t2addrmode_imm0_1020s4 : MemOperand,335 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {336 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";337 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";338 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";339 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;340 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);341}342 343// t2addrmode_so_reg := reg + (reg << imm2)344def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}345def t2addrmode_so_reg : MemOperand,346 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {347 let PrintMethod = "printT2AddrModeSoRegOperand";348 let EncoderMethod = "getT2AddrModeSORegOpValue";349 let DecoderMethod = "DecodeT2AddrModeSOReg";350 let ParserMatchClass = t2addrmode_so_reg_asmoperand;351 let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);352}353 354// Addresses for the TBB/TBH instructions.355def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }356def addrmode_tbb : MemOperand {357 let PrintMethod = "printAddrModeTBB";358 let ParserMatchClass = addrmode_tbb_asmoperand;359 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);360}361def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }362def addrmode_tbh : MemOperand {363 let PrintMethod = "printAddrModeTBH";364 let ParserMatchClass = addrmode_tbh_asmoperand;365 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);366}367 368// Define ARMv8.1-M specific addressing modes.369 370// Label operands for BF/BFL/WLS/DLS/LE371class BFLabelOp<string signed, string isNeg, string zeroPermitted, string size,372 string fixup>373 : Operand<OtherVT> {374 let EncoderMethod = !strconcat("getBFTargetOpValue<", isNeg, ", ",375 fixup, ">");376 let OperandType = "OPERAND_PCREL";377 let DecoderMethod = !strconcat("DecodeBFLabelOperand<", signed, ", ",378 isNeg, ", ", zeroPermitted, ", ", size, ">");379}380def bflabel_u4 : BFLabelOp<"false", "false", "false", "4", "ARM::fixup_bf_branch">;381def bflabel_s12 : BFLabelOp<"true", "false", "true", "12", "ARM::fixup_bfc_target">;382def bflabel_s16 : BFLabelOp<"true", "false", "true", "16", "ARM::fixup_bf_target">;383def bflabel_s18 : BFLabelOp<"true", "false", "true", "18", "ARM::fixup_bfl_target">;384 385def wlslabel_u11_asmoperand : AsmOperandClass {386 let Name = "WLSLabel";387 let RenderMethod = "addImmOperands";388 let PredicateMethod = "isUnsignedOffset<11, 1>";389 let DiagnosticString =390 "loop end is out of range or not a positive multiple of 2";391}392def wlslabel_u11 : BFLabelOp<"false", "false", "true", "11", "ARM::fixup_wls"> {393 let ParserMatchClass = wlslabel_u11_asmoperand;394}395def lelabel_u11_asmoperand : AsmOperandClass {396 let Name = "LELabel";397 let RenderMethod = "addImmOperands";398 let PredicateMethod = "isLEOffset";399 let DiagnosticString =400 "loop start is out of range or not a negative multiple of 2";401}402def lelabel_u11 : BFLabelOp<"false", "true", "true", "11", "ARM::fixup_le"> {403 let ParserMatchClass = lelabel_u11_asmoperand;404}405 406def bfafter_target : Operand<OtherVT> {407 let EncoderMethod = "getBFAfterTargetOpValue";408 let OperandType = "OPERAND_PCREL";409 let DecoderMethod = "DecodeBFAfterTargetOperand";410}411 412// pred operand excluding AL413def pred_noal_asmoperand : AsmOperandClass {414 let Name = "CondCodeNoAL";415 let RenderMethod = "addITCondCodeOperands";416 let PredicateMethod = "isITCondCodeNoAL";417 let ParserMethod = "parseITCondCode";418}419def pred_noal : Operand<i32> {420 let PrintMethod = "printMandatoryPredicateOperand";421 let ParserMatchClass = pred_noal_asmoperand;422 let DecoderMethod = "DecodePredNoALOperand";423}424 425 426// CSEL aliases inverted predicate427def pred_noal_inv_asmoperand : AsmOperandClass {428 let Name = "CondCodeNoALInv";429 let RenderMethod = "addITCondCodeInvOperands";430 let PredicateMethod = "isITCondCodeNoAL";431 let ParserMethod = "parseITCondCode";432}433def pred_noal_inv : Operand<i32> {434 let PrintMethod = "printMandatoryInvertedPredicateOperand";435 let ParserMatchClass = pred_noal_inv_asmoperand;436}437//===----------------------------------------------------------------------===//438// Multiclass helpers...439//440 441 442class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,443 string opc, string asm, list<dag> pattern>444 : T2I<oops, iops, itin, opc, asm, pattern> {445 bits<4> Rd;446 bits<12> imm;447 448 let Inst{11-8} = Rd;449 let Inst{26} = imm{11};450 let Inst{14-12} = imm{10-8};451 let Inst{7-0} = imm{7-0};452}453 454 455class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,456 string opc, string asm, list<dag> pattern>457 : T2sI<oops, iops, itin, opc, asm, pattern> {458 bits<4> Rd;459 bits<4> Rn;460 bits<12> imm;461 462 let Inst{11-8} = Rd;463 let Inst{26} = imm{11};464 let Inst{14-12} = imm{10-8};465 let Inst{7-0} = imm{7-0};466}467 468class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,469 string opc, string asm, list<dag> pattern>470 : T2I<oops, iops, itin, opc, asm, pattern> {471 bits<4> Rn;472 bits<12> imm;473 474 let Inst{19-16} = Rn;475 let Inst{26} = imm{11};476 let Inst{14-12} = imm{10-8};477 let Inst{7-0} = imm{7-0};478}479 480 481class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,482 string opc, string asm, list<dag> pattern>483 : T2I<oops, iops, itin, opc, asm, pattern> {484 bits<4> Rd;485 bits<12> ShiftedRm;486 487 let Inst{11-8} = Rd;488 let Inst{3-0} = ShiftedRm{3-0};489 let Inst{5-4} = ShiftedRm{6-5};490 let Inst{14-12} = ShiftedRm{11-9};491 let Inst{7-6} = ShiftedRm{8-7};492}493 494class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,495 string opc, string asm, list<dag> pattern>496 : T2sI<oops, iops, itin, opc, asm, pattern> {497 bits<4> Rd;498 bits<12> ShiftedRm;499 500 let Inst{11-8} = Rd;501 let Inst{3-0} = ShiftedRm{3-0};502 let Inst{5-4} = ShiftedRm{6-5};503 let Inst{14-12} = ShiftedRm{11-9};504 let Inst{7-6} = ShiftedRm{8-7};505}506 507class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,508 string opc, string asm, list<dag> pattern>509 : T2I<oops, iops, itin, opc, asm, pattern> {510 bits<4> Rn;511 bits<12> ShiftedRm;512 513 let Inst{19-16} = Rn;514 let Inst{3-0} = ShiftedRm{3-0};515 let Inst{5-4} = ShiftedRm{6-5};516 let Inst{14-12} = ShiftedRm{11-9};517 let Inst{7-6} = ShiftedRm{8-7};518}519 520class T2TwoReg<dag oops, dag iops, InstrItinClass itin,521 string opc, string asm, list<dag> pattern>522 : T2I<oops, iops, itin, opc, asm, pattern> {523 bits<4> Rd;524 bits<4> Rm;525 526 let Inst{11-8} = Rd;527 let Inst{3-0} = Rm;528}529 530class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,531 string opc, string asm, list<dag> pattern>532 : T2sI<oops, iops, itin, opc, asm, pattern> {533 bits<4> Rd;534 bits<4> Rm;535 536 let Inst{11-8} = Rd;537 let Inst{3-0} = Rm;538}539 540class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,541 string opc, string asm, list<dag> pattern>542 : T2I<oops, iops, itin, opc, asm, pattern> {543 bits<4> Rn;544 bits<4> Rm;545 546 let Inst{19-16} = Rn;547 let Inst{3-0} = Rm;548}549 550 551class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,552 string opc, string asm, list<dag> pattern>553 : T2I<oops, iops, itin, opc, asm, pattern> {554 bits<4> Rd;555 bits<4> Rn;556 bits<12> imm;557 558 let Inst{11-8} = Rd;559 let Inst{19-16} = Rn;560 let Inst{26} = imm{11};561 let Inst{14-12} = imm{10-8};562 let Inst{7-0} = imm{7-0};563}564 565class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,566 string opc, string asm, list<dag> pattern>567 : T2sI<oops, iops, itin, opc, asm, pattern> {568 bits<4> Rd;569 bits<4> Rn;570 bits<12> imm;571 572 let Inst{11-8} = Rd;573 let Inst{19-16} = Rn;574 let Inst{26} = imm{11};575 let Inst{14-12} = imm{10-8};576 let Inst{7-0} = imm{7-0};577}578 579class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,580 string opc, string asm, list<dag> pattern>581 : T2I<oops, iops, itin, opc, asm, pattern> {582 bits<4> Rd;583 bits<4> Rm;584 bits<5> imm;585 586 let Inst{11-8} = Rd;587 let Inst{3-0} = Rm;588 let Inst{14-12} = imm{4-2};589 let Inst{7-6} = imm{1-0};590}591 592class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,593 string opc, string asm, list<dag> pattern>594 : T2sI<oops, iops, itin, opc, asm, pattern> {595 bits<4> Rd;596 bits<4> Rm;597 bits<5> imm;598 599 let Inst{11-8} = Rd;600 let Inst{3-0} = Rm;601 let Inst{14-12} = imm{4-2};602 let Inst{7-6} = imm{1-0};603}604 605class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,606 string opc, string asm, list<dag> pattern>607 : T2I<oops, iops, itin, opc, asm, pattern> {608 bits<4> Rd;609 bits<4> Rn;610 bits<4> Rm;611 612 let Inst{11-8} = Rd;613 let Inst{19-16} = Rn;614 let Inst{3-0} = Rm;615}616 617class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin,618 string asm, list<dag> pattern>619 : T2XI<oops, iops, itin, asm, pattern> {620 bits<4> Rd;621 bits<4> Rn;622 bits<4> Rm;623 624 let Inst{11-8} = Rd;625 let Inst{19-16} = Rn;626 let Inst{3-0} = Rm;627}628 629class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,630 string opc, string asm, list<dag> pattern>631 : T2sI<oops, iops, itin, opc, asm, pattern> {632 bits<4> Rd;633 bits<4> Rn;634 bits<4> Rm;635 636 let Inst{11-8} = Rd;637 let Inst{19-16} = Rn;638 let Inst{3-0} = Rm;639}640 641class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,642 string opc, string asm, list<dag> pattern>643 : T2I<oops, iops, itin, opc, asm, pattern> {644 bits<4> Rd;645 bits<4> Rn;646 bits<12> ShiftedRm;647 648 let Inst{11-8} = Rd;649 let Inst{19-16} = Rn;650 let Inst{3-0} = ShiftedRm{3-0};651 let Inst{5-4} = ShiftedRm{6-5};652 let Inst{14-12} = ShiftedRm{11-9};653 let Inst{7-6} = ShiftedRm{8-7};654}655 656class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,657 string opc, string asm, list<dag> pattern>658 : T2sI<oops, iops, itin, opc, asm, pattern> {659 bits<4> Rd;660 bits<4> Rn;661 bits<12> ShiftedRm;662 663 let Inst{11-8} = Rd;664 let Inst{19-16} = Rn;665 let Inst{3-0} = ShiftedRm{3-0};666 let Inst{5-4} = ShiftedRm{6-5};667 let Inst{14-12} = ShiftedRm{11-9};668 let Inst{7-6} = ShiftedRm{8-7};669}670 671class T2FourReg<dag oops, dag iops, InstrItinClass itin,672 string opc, string asm, list<dag> pattern>673 : T2I<oops, iops, itin, opc, asm, pattern> {674 bits<4> Rd;675 bits<4> Rn;676 bits<4> Rm;677 bits<4> Ra;678 679 let Inst{19-16} = Rn;680 let Inst{15-12} = Ra;681 let Inst{11-8} = Rd;682 let Inst{3-0} = Rm;683}684 685class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,686 string opc, list<dag> pattern>687 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,688 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,689 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]> {690 bits<4> RdLo;691 bits<4> RdHi;692 bits<4> Rn;693 bits<4> Rm;694 695 let Inst{31-23} = 0b111110111;696 let Inst{22-20} = opc22_20;697 let Inst{19-16} = Rn;698 let Inst{15-12} = RdLo;699 let Inst{11-8} = RdHi;700 let Inst{7-4} = opc7_4;701 let Inst{3-0} = Rm;702}703class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>704 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),705 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,706 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,707 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,708 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {709 bits<4> RdLo;710 bits<4> RdHi;711 bits<4> Rn;712 bits<4> Rm;713 714 let Inst{31-23} = 0b111110111;715 let Inst{22-20} = opc22_20;716 let Inst{19-16} = Rn;717 let Inst{15-12} = RdLo;718 let Inst{11-8} = RdHi;719 let Inst{7-4} = opc7_4;720 let Inst{3-0} = Rm;721}722 723 724/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a725/// binary operation that produces a value. These are predicable and can be726/// changed to modify CPSR.727multiclass T2I_bin_irs<bits<4> opcod, string opc,728 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,729 SDPatternOperator opnode, bit Commutable = 0,730 string wide = ""> {731 // shifted imm732 def ri : T2sTwoRegImm<733 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,734 opc, "\t$Rd, $Rn, $imm",735 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,736 Sched<[WriteALU, ReadALU]> {737 let Inst{31-27} = 0b11110;738 let Inst{25} = 0;739 let Inst{24-21} = opcod;740 let Inst{15} = 0;741 }742 // register743 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,744 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),745 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,746 Sched<[WriteALU, ReadALU, ReadALU]> {747 let isCommutable = Commutable;748 let Inst{31-27} = 0b11101;749 let Inst{26-25} = 0b01;750 let Inst{24-21} = opcod;751 let Inst{15} = 0b0;752 // In most of these instructions, and most versions of the Arm753 // architecture, bit 15 of this encoding is listed as (0) rather754 // than 0, i.e. setting it to 1 is UNPREDICTABLE or a soft-fail755 // rather than a hard failure. In v8.1-M, this requirement is756 // upgraded to a hard one for ORR, so that the encodings with 1757 // in this bit can be reused for other instructions (such as758 // CSEL). Setting Unpredictable{15} = 1 here would reintroduce759 // that encoding clash in the auto- generated MC decoder, so I760 // comment it out.761 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1);762 let Inst{14-12} = 0b000; // imm3763 let Inst{7-6} = 0b00; // imm2764 let Inst{5-4} = 0b00; // type765 }766 // shifted register767 def rs : T2sTwoRegShiftedReg<768 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,769 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),770 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,771 Sched<[WriteALUsi, ReadALU]> {772 let Inst{31-27} = 0b11101;773 let Inst{26-25} = 0b01;774 let Inst{24-21} = opcod;775 let Inst{15} = 0;776 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); // see above777 }778 // Assembly aliases for optional destination operand when it's the same779 // as the source operand.780 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),781 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,782 t2_so_imm:$imm, pred:$p,783 cc_out:$s)>;784 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),785 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,786 rGPR:$Rm, pred:$p,787 cc_out:$s)>;788 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),789 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,790 t2_so_reg:$shift, pred:$p,791 cc_out:$s)>;792}793 794/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need795// the ".w" suffix to indicate that they are wide.796multiclass T2I_bin_w_irs<bits<4> opcod, string opc,797 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,798 SDPatternOperator opnode, bit Commutable = 0> :799 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {800 // Assembler aliases w/ the ".w" suffix.801 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),802 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,803 cc_out:$s)>;804 // Assembler aliases w/o the ".w" suffix.805 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),806 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,807 cc_out:$s)>;808 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),809 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,810 pred:$p, cc_out:$s)>;811 812 // and with the optional destination operand, too.813 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),814 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,815 pred:$p, cc_out:$s)>;816 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),817 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,818 cc_out:$s)>;819 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),820 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,821 pred:$p, cc_out:$s)>;822}823 824/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are825/// reversed. The 'rr' form is only defined for the disassembler; for codegen826/// it is equivalent to the T2I_bin_irs counterpart.827multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> {828 // shifted imm829 def ri : T2sTwoRegImm<830 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,831 opc, ".w\t$Rd, $Rn, $imm",832 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,833 Sched<[WriteALU, ReadALU]> {834 let Inst{31-27} = 0b11110;835 let Inst{25} = 0;836 let Inst{24-21} = opcod;837 let Inst{15} = 0;838 }839 // register840 def rr : T2sThreeReg<841 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,842 opc, "\t$Rd, $Rn, $Rm",843 [/* For disassembly only; pattern left blank */]>,844 Sched<[WriteALU, ReadALU, ReadALU]> {845 let Inst{31-27} = 0b11101;846 let Inst{26-25} = 0b01;847 let Inst{24-21} = opcod;848 let Inst{14-12} = 0b000; // imm3849 let Inst{7-6} = 0b00; // imm2850 let Inst{5-4} = 0b00; // type851 }852 // shifted register853 def rs : T2sTwoRegShiftedReg<854 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),855 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",856 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,857 Sched<[WriteALUsi, ReadALU]> {858 let Inst{31-27} = 0b11101;859 let Inst{26-25} = 0b01;860 let Inst{24-21} = opcod;861 }862}863 864/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the865/// instruction modifies the CPSR register.866///867/// These opcodes will be converted to the real non-S opcodes by868/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.869let hasPostISelHook = 1, Defs = [CPSR] in {870multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,871 InstrItinClass iis, SDNode opnode,872 bit Commutable = 0> {873 // shifted imm874 def ri : t2PseudoInst<(outs rGPR:$Rd),875 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),876 4, iii,877 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,878 t2_so_imm:$imm))]>,879 Sched<[WriteALU, ReadALU]>;880 // register881 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),882 4, iir,883 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,884 rGPR:$Rm))]>,885 Sched<[WriteALU, ReadALU, ReadALU]> {886 let isCommutable = Commutable;887 }888 // shifted register889 def rs : t2PseudoInst<(outs rGPR:$Rd),890 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),891 4, iis,892 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,893 t2_so_reg:$ShiftedRm))]>,894 Sched<[WriteALUsi, ReadALUsr]>;895}896}897 898/// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG899/// operands are reversed.900let hasPostISelHook = 1, Defs = [CPSR] in {901multiclass T2I_rbin_s_is<SDNode opnode> {902 // shifted imm903 def ri : t2PseudoInst<(outs rGPR:$Rd),904 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),905 4, IIC_iALUi,906 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,907 rGPR:$Rn))]>,908 Sched<[WriteALU, ReadALU]>;909 // shifted register910 def rs : t2PseudoInst<(outs rGPR:$Rd),911 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),912 4, IIC_iALUsi,913 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,914 rGPR:$Rn))]>,915 Sched<[WriteALUsi, ReadALU]>;916}917}918 919/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})920/// patterns for a binary operation that produces a value.921multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,922 bit Commutable = 0> {923 // shifted imm924 // The register-immediate version is re-materializable. This is useful925 // in particular for taking the address of a local.926 let isReMaterializable = 1 in {927 def spImm : T2sTwoRegImm<928 (outs GPRsp:$Rd), (ins GPRsp:$Rn, t2_so_imm:$imm), IIC_iALUi,929 opc, ".w\t$Rd, $Rn, $imm",930 []>,931 Sched<[WriteALU, ReadALU]> {932 let Rn = 13;933 let Rd = 13;934 935 let Inst{31-27} = 0b11110;936 let Inst{25-24} = 0b01;937 let Inst{23-21} = op23_21;938 let Inst{15} = 0;939 940 let DecoderMethod = "DecodeT2AddSubSPImm";941 }942 943 def ri : T2sTwoRegImm<944 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,945 opc, ".w\t$Rd, $Rn, $imm",946 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,947 Sched<[WriteALU, ReadALU]> {948 let Inst{31-27} = 0b11110;949 let Inst{25} = 0;950 let Inst{24} = 1;951 let Inst{23-21} = op23_21;952 let Inst{15} = 0;953 }954 }955 // 12-bit imm956 def ri12 : T2I<957 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,958 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",959 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,960 Sched<[WriteALU, ReadALU]> {961 bits<4> Rd;962 bits<4> Rn;963 bits<12> imm;964 let Inst{31-27} = 0b11110;965 let Inst{26} = imm{11};966 let Inst{25-24} = 0b10;967 let Inst{23-21} = op23_21;968 let Inst{20} = 0; // The S bit.969 let Inst{19-16} = Rn;970 let Inst{15} = 0;971 let Inst{14-12} = imm{10-8};972 let Inst{11-8} = Rd;973 let Inst{7-0} = imm{7-0};974 }975 def spImm12 : T2I<976 (outs GPRsp:$Rd), (ins GPRsp:$Rn, imm0_4095:$imm), IIC_iALUi,977 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",978 []>,979 Sched<[WriteALU, ReadALU]> {980 bits<4> Rd = 13;981 bits<4> Rn = 13;982 bits<12> imm;983 let Inst{31-27} = 0b11110;984 let Inst{26} = imm{11};985 let Inst{25-24} = 0b10;986 let Inst{23-21} = op23_21;987 let Inst{20} = 0; // The S bit.988 let Inst{19-16} = Rn;989 let Inst{15} = 0;990 let Inst{14-12} = imm{10-8};991 let Inst{11-8} = Rd;992 let Inst{7-0} = imm{7-0};993 let DecoderMethod = "DecodeT2AddSubSPImm";994 }995 // register996 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),997 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",998 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,999 Sched<[WriteALU, ReadALU, ReadALU]> {1000 let isCommutable = Commutable;1001 let Inst{31-27} = 0b11101;1002 let Inst{26-25} = 0b01;1003 let Inst{24} = 1;1004 let Inst{23-21} = op23_21;1005 let Inst{14-12} = 0b000; // imm31006 let Inst{7-6} = 0b00; // imm21007 let Inst{5-4} = 0b00; // type1008 }1009 // shifted register1010 def rs : T2sTwoRegShiftedReg<1011 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),1012 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",1013 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,1014 Sched<[WriteALUsi, ReadALU]> {1015 let Inst{31-27} = 0b11101;1016 let Inst{26-25} = 0b01;1017 let Inst{24} = 1;1018 let Inst{23-21} = op23_21;1019 }1020}1021 1022/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns1023/// for a binary operation that produces a value and use the carry1024/// bit. It's not predicable.1025multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,1026 bit Commutable = 0, bit PostISelHook = 0> {1027 let Defs = [CPSR], Uses = [CPSR], hasPostISelHook = PostISelHook in {1028 // shifted imm1029 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),1030 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",1031 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,1032 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {1033 let Inst{31-27} = 0b11110;1034 let Inst{25} = 0;1035 let Inst{24-21} = opcod;1036 let Inst{15} = 0;1037 }1038 // register1039 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,1040 opc, ".w\t$Rd, $Rn, $Rm",1041 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,1042 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {1043 let isCommutable = Commutable;1044 let Inst{31-27} = 0b11101;1045 let Inst{26-25} = 0b01;1046 let Inst{24-21} = opcod;1047 let Inst{14-12} = 0b000; // imm31048 let Inst{7-6} = 0b00; // imm21049 let Inst{5-4} = 0b00; // type1050 }1051 // shifted register1052 def rs : T2sTwoRegShiftedReg<1053 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),1054 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",1055 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,1056 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {1057 let Inst{31-27} = 0b11101;1058 let Inst{26-25} = 0b01;1059 let Inst{24-21} = opcod;1060 }1061 }1062 // Shortened forms1063 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),1064 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p,1065 cc_out:$s)>;1066 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),1067 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,1068 cc_out:$s)>;1069 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $ShiftedRm"),1070 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,1071 cc_out:$s)>;1072 def : t2InstAlias<!strconcat(opc, "${s}${p}", "$Rdn, $imm"),1073 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p,1074 cc_out:$s)>;1075 def : t2InstAlias<!strconcat(opc, "${s}${p}", "$Rdn, $Rm"),1076 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,1077 cc_out:$s)>;1078 def : t2InstAlias<!strconcat(opc, "${s}${p}", "$Rdn, $ShiftedRm"),1079 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,1080 cc_out:$s)>;1081}1082 1083/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /1084// rotate operation that produces a value.1085multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> {1086 // 5-bit imm1087 def ri : T2sTwoRegShiftImm<1088 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,1089 opc, ".w\t$Rd, $Rm, $imm",1090 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,1091 Sched<[WriteALU]> {1092 let Inst{31-27} = 0b11101;1093 let Inst{26-21} = 0b010010;1094 let Inst{19-16} = 0b1111; // Rn1095 let Inst{15} = 0b0;1096 let Inst{5-4} = opcod;1097 }1098 // register1099 def rr : T2sThreeReg<1100 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,1101 opc, ".w\t$Rd, $Rn, $Rm",1102 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,1103 Sched<[WriteALU]> {1104 let Inst{31-27} = 0b11111;1105 let Inst{26-23} = 0b0100;1106 let Inst{22-21} = opcod;1107 let Inst{15-12} = 0b1111;1108 let Inst{7-4} = 0b0000;1109 }1110 1111 // Optional destination register1112 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),1113 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,1114 cc_out:$s)>;1115 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),1116 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,1117 cc_out:$s)>;1118 1119 // Assembler aliases w/o the ".w" suffix.1120 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),1121 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,1122 cc_out:$s)>;1123 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),1124 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,1125 cc_out:$s)>;1126 1127 // and with the optional destination operand, too.1128 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),1129 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,1130 cc_out:$s)>;1131 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),1132 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,1133 cc_out:$s)>;1134}1135 1136/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test1137/// patterns. Similar to T2I_bin_irs except the instruction does not produce1138/// a explicit result, only implicitly set CPSR.1139multiclass T2I_cmp_irs<bits<4> opcod, string opc, RegisterClass LHSGPR,1140 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,1141 SDPatternOperator opnode> {1142let isCompare = 1, Defs = [CPSR] in {1143 // shifted imm1144 def ri : T2OneRegCmpImm<1145 (outs), (ins LHSGPR:$Rn, t2_so_imm:$imm), iii,1146 opc, ".w\t$Rn, $imm",1147 [(set CPSR, (opnode LHSGPR:$Rn, t2_so_imm:$imm))]>,1148 Sched<[WriteCMP]> {1149 let Inst{31-27} = 0b11110;1150 let Inst{25} = 0;1151 let Inst{24-21} = opcod;1152 let Inst{20} = 1; // The S bit.1153 let Inst{15} = 0;1154 let Inst{11-8} = 0b1111; // Rd1155 }1156 // register1157 def rr : T2TwoRegCmp<1158 (outs), (ins LHSGPR:$Rn, rGPR:$Rm), iir,1159 opc, ".w\t$Rn, $Rm",1160 [(set CPSR, (opnode LHSGPR:$Rn, rGPR:$Rm))]>,1161 Sched<[WriteCMP]> {1162 let Inst{31-27} = 0b11101;1163 let Inst{26-25} = 0b01;1164 let Inst{24-21} = opcod;1165 let Inst{20} = 1; // The S bit.1166 let Inst{14-12} = 0b000; // imm31167 let Inst{11-8} = 0b1111; // Rd1168 let Inst{7-6} = 0b00; // imm21169 let Inst{5-4} = 0b00; // type1170 }1171 // shifted register1172 def rs : T2OneRegCmpShiftedReg<1173 (outs), (ins LHSGPR:$Rn, t2_so_reg:$ShiftedRm), iis,1174 opc, ".w\t$Rn, $ShiftedRm",1175 [(set CPSR, (opnode LHSGPR:$Rn, t2_so_reg:$ShiftedRm))]>,1176 Sched<[WriteCMPsi]> {1177 let Inst{31-27} = 0b11101;1178 let Inst{26-25} = 0b01;1179 let Inst{24-21} = opcod;1180 let Inst{20} = 1; // The S bit.1181 let Inst{11-8} = 0b1111; // Rd1182 }1183}1184 1185 // Assembler aliases w/o the ".w" suffix.1186 // No alias here for 'rr' version as not all instantiations of this1187 // multiclass want one (CMP in particular, does not).1188 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),1189 (!cast<Instruction>(NAME#"ri") LHSGPR:$Rn, t2_so_imm:$imm, pred:$p)>;1190 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),1191 (!cast<Instruction>(NAME#"rs") LHSGPR:$Rn, t2_so_reg:$shift, pred:$p)>;1192}1193 1194/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.1195multiclass T2I_ld<bit signed, bits<2> opcod, string opc,1196 InstrItinClass iii, InstrItinClass iis, RegisterClass target,1197 PatFrag opnode> {1198 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,1199 opc, ".w\t$Rt, $addr",1200 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,1201 Sched<[WriteLd]> {1202 bits<4> Rt;1203 bits<17> addr;1204 let Inst{31-25} = 0b1111100;1205 let Inst{24} = signed;1206 let Inst{23} = 1;1207 let Inst{22-21} = opcod;1208 let Inst{20} = 1; // load1209 let Inst{19-16} = addr{16-13}; // Rn1210 let Inst{15-12} = Rt;1211 let Inst{11-0} = addr{11-0}; // imm1212 1213 let DecoderMethod = "DecodeT2LoadImm12";1214 }1215 def i8 : T2Ii8n <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,1216 opc, "\t$Rt, $addr",1217 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,1218 Sched<[WriteLd]> {1219 bits<4> Rt;1220 bits<13> addr;1221 let Inst{31-27} = 0b11111;1222 let Inst{26-25} = 0b00;1223 let Inst{24} = signed;1224 let Inst{23} = 0;1225 let Inst{22-21} = opcod;1226 let Inst{20} = 1; // load1227 let Inst{19-16} = addr{12-9}; // Rn1228 let Inst{15-12} = Rt;1229 let Inst{11} = 1;1230 // Offset: index==TRUE, wback==FALSE1231 let Inst{10} = 1; // The P bit.1232 let Inst{9} = addr{8}; // U1233 let Inst{8} = 0; // The W bit.1234 let Inst{7-0} = addr{7-0}; // imm1235 1236 let DecoderMethod = "DecodeT2LoadImm8";1237 }1238 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,1239 opc, ".w\t$Rt, $addr",1240 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]>,1241 Sched<[WriteLd]> {1242 let Inst{31-27} = 0b11111;1243 let Inst{26-25} = 0b00;1244 let Inst{24} = signed;1245 let Inst{23} = 0;1246 let Inst{22-21} = opcod;1247 let Inst{20} = 1; // load1248 let Inst{11-6} = 0b000000;1249 1250 bits<4> Rt;1251 let Inst{15-12} = Rt;1252 1253 bits<10> addr;1254 let Inst{19-16} = addr{9-6}; // Rn1255 let Inst{3-0} = addr{5-2}; // Rm1256 let Inst{5-4} = addr{1-0}; // imm1257 1258 let DecoderMethod = "DecodeT2LoadShift";1259 }1260 1261 // pci variant is very similar to i12, but supports negative offsets1262 // from the PC.1263 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,1264 opc, ".w\t$Rt, $addr",1265 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>,1266 Sched<[WriteLd]> {1267 let isReMaterializable = 1;1268 let Inst{31-27} = 0b11111;1269 let Inst{26-25} = 0b00;1270 let Inst{24} = signed;1271 let Inst{22-21} = opcod;1272 let Inst{20} = 1; // load1273 let Inst{19-16} = 0b1111; // Rn1274 1275 bits<4> Rt;1276 let Inst{15-12} = Rt{3-0};1277 1278 bits<13> addr;1279 let Inst{23} = addr{12}; // add = (U == '1')1280 let Inst{11-0} = addr{11-0};1281 1282 let DecoderMethod = "DecodeT2LoadLabel";1283 }1284}1285 1286/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.1287multiclass T2I_st<bits<2> opcod, string opc,1288 InstrItinClass iii, InstrItinClass iis, RegisterClass target,1289 PatFrag opnode> {1290 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,1291 opc, ".w\t$Rt, $addr",1292 [(opnode target:$Rt, t2addrmode_imm12:$addr)]>,1293 Sched<[WriteST]> {1294 let Inst{31-27} = 0b11111;1295 let Inst{26-23} = 0b0001;1296 let Inst{22-21} = opcod;1297 let Inst{20} = 0; // !load1298 1299 bits<4> Rt;1300 let Inst{15-12} = Rt;1301 1302 bits<17> addr;1303 let addr{12} = 1; // add = TRUE1304 let Inst{19-16} = addr{16-13}; // Rn1305 let Inst{23} = addr{12}; // U1306 let Inst{11-0} = addr{11-0}; // imm1307 }1308 def i8 : T2Ii8n <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,1309 opc, "\t$Rt, $addr",1310 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]>,1311 Sched<[WriteST]> {1312 let Inst{31-27} = 0b11111;1313 let Inst{26-23} = 0b0000;1314 let Inst{22-21} = opcod;1315 let Inst{20} = 0; // !load1316 let Inst{11} = 1;1317 // Offset: index==TRUE, wback==FALSE1318 let Inst{10} = 1; // The P bit.1319 let Inst{8} = 0; // The W bit.1320 1321 bits<4> Rt;1322 let Inst{15-12} = Rt;1323 1324 bits<13> addr;1325 let Inst{19-16} = addr{12-9}; // Rn1326 let Inst{9} = addr{8}; // U1327 let Inst{7-0} = addr{7-0}; // imm1328 }1329 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,1330 opc, ".w\t$Rt, $addr",1331 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]>,1332 Sched<[WriteST]> {1333 let Inst{31-27} = 0b11111;1334 let Inst{26-23} = 0b0000;1335 let Inst{22-21} = opcod;1336 let Inst{20} = 0; // !load1337 let Inst{11-6} = 0b000000;1338 1339 bits<4> Rt;1340 let Inst{15-12} = Rt;1341 1342 bits<10> addr;1343 let Inst{19-16} = addr{9-6}; // Rn1344 let Inst{3-0} = addr{5-2}; // Rm1345 let Inst{5-4} = addr{1-0}; // imm1346 }1347}1348 1349/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a1350/// register and one whose operand is a register rotated by 8/16/24.1351class T2I_ext_rrot_base<bits<3> opcod, dag iops, dag oops,1352 string opc, string oprs,1353 list<dag> pattern>1354 : T2TwoReg<iops, oops, IIC_iEXTr, opc, oprs, pattern> {1355 bits<2> rot;1356 let Inst{31-27} = 0b11111;1357 let Inst{26-23} = 0b0100;1358 let Inst{22-20} = opcod;1359 let Inst{19-16} = 0b1111; // Rn1360 let Inst{15-12} = 0b1111;1361 let Inst{7} = 1;1362 let Inst{5-4} = rot; // rotate1363}1364 1365class T2I_ext_rrot<bits<3> opcod, string opc>1366 : T2I_ext_rrot_base<opcod,1367 (outs rGPR:$Rd),1368 (ins rGPR:$Rm, rot_imm:$rot),1369 opc, ".w\t$Rd, $Rm$rot", []>,1370 Requires<[IsThumb2]>,1371 Sched<[WriteALU, ReadALU]>;1372 1373// UXTB16, SXTB16 - Requires HasDSP, does not need the .w qualifier.1374class T2I_ext_rrot_xtb16<bits<3> opcod, string opc>1375 : T2I_ext_rrot_base<opcod,1376 (outs rGPR:$Rd),1377 (ins rGPR:$Rm, rot_imm:$rot),1378 opc, "\t$Rd, $Rm$rot", []>,1379 Requires<[HasDSP, IsThumb2]>,1380 Sched<[WriteALU, ReadALU]>;1381 1382/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a1383/// register and one whose operand is a register rotated by 8/16/24.1384class T2I_exta_rrot<bits<3> opcod, string opc>1385 : T2ThreeReg<(outs rGPR:$Rd),1386 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),1387 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,1388 Requires<[HasDSP, IsThumb2]>,1389 Sched<[WriteALU, ReadALU]> {1390 bits<2> rot;1391 let Inst{31-27} = 0b11111;1392 let Inst{26-23} = 0b0100;1393 let Inst{22-20} = opcod;1394 let Inst{15-12} = 0b1111;1395 let Inst{7} = 1;1396 let Inst{5-4} = rot;1397}1398 1399//===----------------------------------------------------------------------===//1400// Instructions1401//===----------------------------------------------------------------------===//1402 1403//===----------------------------------------------------------------------===//1404// Miscellaneous Instructions.1405//1406 1407class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,1408 string asm, list<dag> pattern>1409 : T2XI<oops, iops, itin, asm, pattern> {1410 bits<4> Rd;1411 bits<12> label;1412 1413 let Inst{11-8} = Rd;1414 let Inst{26} = label{11};1415 let Inst{14-12} = label{10-8};1416 let Inst{7-0} = label{7-0};1417}1418 1419// LEApcrel - Load a pc-relative address into a register without offending the1420// assembler.1421def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),1422 (ins t2adrlabel:$addr, pred:$p),1423 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,1424 Sched<[WriteALU, ReadALU]> {1425 let Inst{31-27} = 0b11110;1426 let Inst{25-24} = 0b10;1427 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)1428 let Inst{22} = 0;1429 let Inst{20} = 0;1430 let Inst{19-16} = 0b1111; // Rn1431 let Inst{15} = 0;1432 1433 bits<4> Rd;1434 bits<13> addr;1435 let Inst{11-8} = Rd;1436 let Inst{23} = addr{12};1437 let Inst{21} = addr{12};1438 let Inst{26} = addr{11};1439 let Inst{14-12} = addr{10-8};1440 let Inst{7-0} = addr{7-0};1441 1442 let DecoderMethod = "DecodeT2Adr";1443}1444 1445let hasSideEffects = 0, isReMaterializable = 1 in1446def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),1447 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;1448let hasSideEffects = 1 in1449def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),1450 (ins i32imm:$label, pred:$p),1451 4, IIC_iALUi,1452 []>, Sched<[WriteALU, ReadALU]>;1453 1454 1455//===----------------------------------------------------------------------===//1456// Load / store Instructions.1457//1458 1459// Load1460let canFoldAsLoad = 1, isReMaterializable = 1 in1461defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;1462 1463// Loads with zero extension1464defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,1465 GPRnopc, zextloadi16>;1466defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,1467 GPRnopc, zextloadi8>;1468 1469// Loads with sign extension1470defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,1471 GPRnopc, sextloadi16>;1472defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,1473 GPRnopc, sextloadi8>;1474 1475let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {1476// Load doubleword1477def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),1478 (ins t2addrmode_imm8s4:$addr),1479 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "",1480 [(set rGPR:$Rt, rGPR:$Rt2, (ARMldrd t2addrmode_imm8s4:$addr))]>,1481 Sched<[WriteLd]>;1482} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 11483 1484// zextload i1 -> zextload i81485def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),1486 (t2LDRBi12 t2addrmode_imm12:$addr)>;1487def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),1488 (t2LDRBi8 t2addrmode_negimm8:$addr)>;1489def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),1490 (t2LDRBs t2addrmode_so_reg:$addr)>;1491def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),1492 (t2LDRBpci tconstpool:$addr)>;1493 1494// extload -> zextload1495// FIXME: Reduce the number of patterns by legalizing extload to zextload1496// earlier?1497def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),1498 (t2LDRBi12 t2addrmode_imm12:$addr)>;1499def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),1500 (t2LDRBi8 t2addrmode_negimm8:$addr)>;1501def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),1502 (t2LDRBs t2addrmode_so_reg:$addr)>;1503def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),1504 (t2LDRBpci tconstpool:$addr)>;1505 1506def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),1507 (t2LDRBi12 t2addrmode_imm12:$addr)>;1508def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),1509 (t2LDRBi8 t2addrmode_negimm8:$addr)>;1510def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),1511 (t2LDRBs t2addrmode_so_reg:$addr)>;1512def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),1513 (t2LDRBpci tconstpool:$addr)>;1514 1515def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),1516 (t2LDRHi12 t2addrmode_imm12:$addr)>;1517def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),1518 (t2LDRHi8 t2addrmode_negimm8:$addr)>;1519def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),1520 (t2LDRHs t2addrmode_so_reg:$addr)>;1521def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),1522 (t2LDRHpci tconstpool:$addr)>;1523 1524// FIXME: The destination register of the loads and stores can't be PC, but1525// can be SP. We need another regclass (similar to rGPR) to represent1526// that. Not a pressing issue since these are selected manually,1527// not via pattern.1528 1529// Indexed loads1530 1531let mayLoad = 1, hasSideEffects = 0 in {1532def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),1533 (ins t2addrmode_imm8_pre:$addr),1534 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,1535 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,1536 Sched<[WriteLd]>;1537 1538def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),1539 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),1540 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,1541 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,1542 Sched<[WriteLd]>;1543 1544def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),1545 (ins t2addrmode_imm8_pre:$addr),1546 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,1547 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,1548 Sched<[WriteLd]>;1549 1550def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),1551 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),1552 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,1553 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,1554 Sched<[WriteLd]>;1555 1556def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),1557 (ins t2addrmode_imm8_pre:$addr),1558 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,1559 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,1560 Sched<[WriteLd]>;1561 1562def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),1563 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),1564 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,1565 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,1566 Sched<[WriteLd]>;1567 1568def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),1569 (ins t2addrmode_imm8_pre:$addr),1570 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,1571 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",1572 []>, Sched<[WriteLd]>;1573 1574def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),1575 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),1576 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,1577 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,1578 Sched<[WriteLd]>;1579 1580def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),1581 (ins t2addrmode_imm8_pre:$addr),1582 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,1583 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",1584 []>, Sched<[WriteLd]>;1585 1586def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),1587 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),1588 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,1589 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,1590 Sched<[WriteLd]>;1591} // mayLoad = 1, hasSideEffects = 01592 1593// F5.1.72 LDR (immediate) T41594// .w suffixes; Constraints can't be used on t2InstAlias to describe1595// "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.1596def t2LDR_PRE_imm : t2AsmPseudo<"ldr${p}.w $Rt, $addr!",1597 (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;1598def t2LDR_POST_imm : t2AsmPseudo<"ldr${p}.w $Rt, $Rn, $imm",1599 (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;1600 1601// A7.7.46 LDRB (immediate) T31602// .w suffixes; Constraints can't be used on t2InstAlias to describe1603// "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.1604def t2LDRB_OFFSET_imm : t2AsmPseudo<"ldrb${p}.w $Rt, $addr",1605 (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;1606def t2LDRB_PRE_imm : t2AsmPseudo<"ldrb${p}.w $Rt, $addr!",1607 (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;1608def t2LDRB_POST_imm : t2AsmPseudo<"ldrb${p}.w $Rt, $Rn, $imm",1609 (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;1610 1611// A7.7.55 LDRH (immediate) T31612// .w suffixes; Constraints can't be used on t2InstAlias to describe1613// "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.1614def t2LDRH_OFFSET_imm : t2AsmPseudo<"ldrh${p}.w $Rt, $addr",1615 (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;1616def t2LDRH_PRE_imm : t2AsmPseudo<"ldrh${p}.w $Rt, $addr!",1617 (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;1618def t2LDRH_POST_imm : t2AsmPseudo<"ldrh${p}.w $Rt, $Rn, $imm",1619 (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;1620 1621// A7.7.59 LDRSB (immediate) T21622// .w suffixes; Constraints can't be used on t2InstAlias to describe1623// "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.1624def t2LDRSB_OFFSET_imm : t2AsmPseudo<"ldrsb${p}.w $Rt, $addr",1625 (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;1626def t2LDRSB_PRE_imm : t2AsmPseudo<"ldrsb${p}.w $Rt, $addr!",1627 (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;1628def t2LDRSB_POST_imm : t2AsmPseudo<"ldrsb${p}.w $Rt, $Rn, $imm",1629 (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;1630 1631// A7.7.63 LDRSH (immediate) T21632// .w suffixes; Constraints can't be used on t2InstAlias to describe1633// "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.1634def t2LDRSH_OFFSET_imm : t2AsmPseudo<"ldrsh${p}.w $Rt, $addr",1635 (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;1636def t2LDRSH_PRE_imm : t2AsmPseudo<"ldrsh${p}.w $Rt, $addr!",1637 (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;1638def t2LDRSH_POST_imm : t2AsmPseudo<"ldrsh${p}.w $Rt, $Rn, $imm",1639 (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;1640 1641// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).1642// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T41643class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>1644 : T2Ii8p<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,1645 "\t$Rt, $addr", []>, Sched<[WriteLd]> {1646 bits<4> Rt;1647 bits<13> addr;1648 let Inst{31-27} = 0b11111;1649 let Inst{26-25} = 0b00;1650 let Inst{24} = signed;1651 let Inst{23} = 0;1652 let Inst{22-21} = type;1653 let Inst{20} = 1; // load1654 let Inst{19-16} = addr{12-9};1655 let Inst{15-12} = Rt;1656 let Inst{11} = 1;1657 let Inst{10-8} = 0b110; // PUW.1658 let Inst{7-0} = addr{7-0};1659 1660 let DecoderMethod = "DecodeT2LoadT";1661}1662 1663def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;1664def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;1665def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;1666def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;1667def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;1668 1669class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,1670 string opc, string asm, list<dag> pattern>1671 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,1672 opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {1673 bits<4> Rt;1674 bits<4> addr;1675 1676 let Inst{31-27} = 0b11101;1677 let Inst{26-24} = 0b000;1678 let Inst{23-20} = bits23_20;1679 let Inst{11-6} = 0b111110;1680 let Inst{5-4} = bit54;1681 let Inst{3-0} = 0b1111;1682 1683 // Encode instruction operands1684 let Inst{19-16} = addr;1685 let Inst{15-12} = Rt;1686}1687 1688def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),1689 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>,1690 Sched<[WriteLd]>;1691def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),1692 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>,1693 Sched<[WriteLd]>;1694def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),1695 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>,1696 Sched<[WriteLd]>;1697 1698// Store1699defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>;1700defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,1701 rGPR, truncstorei8>;1702defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,1703 rGPR, truncstorei16>;1704 1705// Store doubleword1706let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in1707def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),1708 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),1709 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "",1710 [(ARMstrd rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr)]>,1711 Sched<[WriteST]>;1712 1713// Indexed stores1714 1715let mayStore = 1, hasSideEffects = 0 in {1716def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),1717 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),1718 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,1719 "str", "\t$Rt, $addr!",1720 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,1721 Sched<[WriteST]>;1722 1723def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),1724 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),1725 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,1726 "strh", "\t$Rt, $addr!",1727 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,1728 Sched<[WriteST]>;1729 1730def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),1731 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),1732 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,1733 "strb", "\t$Rt, $addr!",1734 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,1735 Sched<[WriteST]>;1736} // mayStore = 1, hasSideEffects = 01737 1738def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),1739 (ins GPRnopc:$Rt, addr_offset_none:$Rn,1740 t2am_imm8_offset:$offset),1741 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,1742 "str", "\t$Rt, $Rn$offset",1743 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",1744 [(set GPRnopc:$Rn_wb,1745 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,1746 t2am_imm8_offset:$offset))]>,1747 Sched<[WriteST]>;1748 1749def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),1750 (ins rGPR:$Rt, addr_offset_none:$Rn,1751 t2am_imm8_offset:$offset),1752 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,1753 "strh", "\t$Rt, $Rn$offset",1754 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",1755 [(set GPRnopc:$Rn_wb,1756 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,1757 t2am_imm8_offset:$offset))]>,1758 Sched<[WriteST]>;1759 1760def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),1761 (ins rGPR:$Rt, addr_offset_none:$Rn,1762 t2am_imm8_offset:$offset),1763 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,1764 "strb", "\t$Rt, $Rn$offset",1765 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",1766 [(set GPRnopc:$Rn_wb,1767 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,1768 t2am_imm8_offset:$offset))]>,1769 Sched<[WriteST]>;1770 1771// Pseudo-instructions for pattern matching the pre-indexed stores. We can't1772// put the patterns on the instruction definitions directly as ISel wants1773// the address base and offset to be separate operands, not a single1774// complex operand like we represent the instructions themselves. The1775// pseudos map between the two.1776let usesCustomInserter = 1,1777 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {1778def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),1779 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),1780 4, IIC_iStore_ru,1781 [(set GPRnopc:$Rn_wb,1782 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,1783 Sched<[WriteST]>;1784def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),1785 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),1786 4, IIC_iStore_ru,1787 [(set GPRnopc:$Rn_wb,1788 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,1789 Sched<[WriteST]>;1790def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),1791 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),1792 4, IIC_iStore_ru,1793 [(set GPRnopc:$Rn_wb,1794 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,1795 Sched<[WriteST]>;1796}1797 1798let mayStore = 1, hasSideEffects = 0 in {1799 1800// F5.1.229 STR (immediate) T41801// .w suffixes; Constraints can't be used on t2InstAlias to describe1802// "$Rn = $Rn_wb,@earlyclobber $Rn_wb" on POST or1803// "$addr.base = $Rn_wb,@earlyclobber $Rn_wb" on PRE.1804def t2STR_PRE_imm : t2AsmPseudo<"str${p}.w $Rt, $addr!",1805 (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;1806def t2STR_POST_imm : t2AsmPseudo<"str${p}.w $Rt, $Rn, $imm",1807 (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;1808 1809// A7.7.163 STRB (immediate) T31810// .w suffixes; Constraints can't be used on t2InstAlias to describe1811// "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.1812def t2STRB_OFFSET_imm : t2AsmPseudo<"strb${p}.w $Rt, $addr",1813 (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;1814def t2STRB_PRE_imm : t2AsmPseudo<"strb${p}.w $Rt, $addr!",1815 (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;1816def t2STRB_POST_imm : t2AsmPseudo<"strb${p}.w $Rt, $Rn, $imm",1817 (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;1818 1819// A7.7.170 STRH (immediate) T31820// .w suffixes; Constraints can't be used on t2InstAlias to describe1821// "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.1822def t2STRH_OFFSET_imm : t2AsmPseudo<"strh${p}.w $Rt, $addr",1823 (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;1824def t2STRH_PRE_imm : t2AsmPseudo<"strh${p}.w $Rt, $addr!",1825 (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;1826def t2STRH_POST_imm : t2AsmPseudo<"strh${p}.w $Rt, $Rn, $imm",1827 (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;1828 1829// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly1830// only.1831// Ref: A8.6.193 STR (immediate, Thumb) Encoding T41832class T2IstT<bits<2> type, string opc, InstrItinClass ii>1833 : T2Ii8p<(outs), (ins rGPR:$Rt, t2addrmode_posimm8:$addr), ii, opc,1834 "\t$Rt, $addr", []>, Sched<[WriteST]> {1835 let Inst{31-27} = 0b11111;1836 let Inst{26-25} = 0b00;1837 let Inst{24} = 0; // not signed1838 let Inst{23} = 0;1839 let Inst{22-21} = type;1840 let Inst{20} = 0; // store1841 let Inst{11} = 1;1842 let Inst{10-8} = 0b110; // PUW1843 1844 bits<4> Rt;1845 bits<13> addr;1846 let Inst{15-12} = Rt;1847 let Inst{19-16} = addr{12-9};1848 let Inst{7-0} = addr{7-0};1849}1850 1851def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;1852def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;1853def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;1854 1855} // mayStore = 1, hasSideEffects = 01856 1857// ldrd / strd pre / post variants1858 1859let mayLoad = 1, hasSideEffects = 0 in1860def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),1861 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,1862 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,1863 Sched<[WriteLd]> {1864 let DecoderMethod = "DecodeT2LDRDPreInstruction";1865}1866 1867let mayLoad = 1, hasSideEffects = 0 in1868def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),1869 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),1870 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",1871 "$addr.base = $wb", []>, Sched<[WriteLd]>;1872 1873let mayStore = 1, hasSideEffects = 0 in1874def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),1875 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),1876 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",1877 "$addr.base = $wb", []>, Sched<[WriteST]> {1878 let DecoderMethod = "DecodeT2STRDPreInstruction";1879}1880 1881let mayStore = 1, hasSideEffects = 0 in1882def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),1883 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,1884 t2am_imm8s4_offset:$imm),1885 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",1886 "$addr.base = $wb", []>, Sched<[WriteST]>;1887 1888class T2Istrrel<bits<2> bit54, dag oops, dag iops,1889 string opc, string asm, list<dag> pattern>1890 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,1891 asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]>,1892 Sched<[WriteST]> {1893 bits<4> Rt;1894 bits<4> addr;1895 1896 let Inst{31-27} = 0b11101;1897 let Inst{26-20} = 0b0001100;1898 let Inst{11-6} = 0b111110;1899 let Inst{5-4} = bit54;1900 let Inst{3-0} = 0b1111;1901 1902 // Encode instruction operands1903 let Inst{19-16} = addr;1904 let Inst{15-12} = Rt;1905}1906 1907def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),1908 "stl", "\t$Rt, $addr", []>;1909def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),1910 "stlb", "\t$Rt, $addr", []>;1911def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),1912 "stlh", "\t$Rt, $addr", []>;1913 1914// T2Ipl (Preload Data/Instruction) signals the memory system of possible future1915// data/instruction access.1916// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),1917// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).1918multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {1919 1920 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,1921 "\t$addr",1922 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,1923 Sched<[WritePreLd]> {1924 let Inst{31-25} = 0b1111100;1925 let Inst{24} = instr;1926 let Inst{23} = 1;1927 let Inst{22} = 0;1928 let Inst{21} = write;1929 let Inst{20} = 1;1930 let Inst{15-12} = 0b1111;1931 1932 bits<17> addr;1933 let Inst{19-16} = addr{16-13}; // Rn1934 let Inst{11-0} = addr{11-0}; // imm121935 1936 let DecoderMethod = "DecodeT2LoadImm12";1937 }1938 1939 def i8 : T2Ii8n<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,1940 "\t$addr",1941 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,1942 Sched<[WritePreLd]> {1943 let Inst{31-25} = 0b1111100;1944 let Inst{24} = instr;1945 let Inst{23} = 0; // U = 01946 let Inst{22} = 0;1947 let Inst{21} = write;1948 let Inst{20} = 1;1949 let Inst{15-12} = 0b1111;1950 let Inst{11-8} = 0b1100;1951 1952 bits<13> addr;1953 let Inst{19-16} = addr{12-9}; // Rn1954 let Inst{7-0} = addr{7-0}; // imm81955 1956 let DecoderMethod = "DecodeT2LoadImm8";1957 }1958 1959 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,1960 "\t$addr",1961 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,1962 Sched<[WritePreLd]> {1963 let Inst{31-25} = 0b1111100;1964 let Inst{24} = instr;1965 let Inst{23} = 0; // add = TRUE for T11966 let Inst{22} = 0;1967 let Inst{21} = write;1968 let Inst{20} = 1;1969 let Inst{15-12} = 0b1111;1970 let Inst{11-6} = 0b000000;1971 1972 bits<10> addr;1973 let Inst{19-16} = addr{9-6}; // Rn1974 let Inst{3-0} = addr{5-2}; // Rm1975 let Inst{5-4} = addr{1-0}; // imm21976 1977 let DecoderMethod = "DecodeT2LoadShift";1978 }1979}1980 1981defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;1982defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;1983defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;1984 1985// PLD/PLDW/PLI aliases w/ the optional .w suffix1986def : t2InstAlias<"pld${p}.w\t$addr",1987 (t2PLDi12 t2addrmode_imm12:$addr, pred:$p)>;1988def : t2InstAlias<"pld${p}.w\t$addr",1989 (t2PLDi8 t2addrmode_negimm8:$addr, pred:$p)>;1990def : t2InstAlias<"pld${p}.w\t$addr",1991 (t2PLDs t2addrmode_so_reg:$addr, pred:$p)>;1992 1993def : InstAlias<"pldw${p}.w\t$addr",1994 (t2PLDWi12 t2addrmode_imm12:$addr, pred:$p), 0>,1995 Requires<[IsThumb2,HasV7,HasMP]>;1996def : InstAlias<"pldw${p}.w\t$addr",1997 (t2PLDWi8 t2addrmode_negimm8:$addr, pred:$p), 0>,1998 Requires<[IsThumb2,HasV7,HasMP]>;1999def : InstAlias<"pldw${p}.w\t$addr",2000 (t2PLDWs t2addrmode_so_reg:$addr, pred:$p), 0>,2001 Requires<[IsThumb2,HasV7,HasMP]>;2002 2003def : InstAlias<"pli${p}.w\t$addr",2004 (t2PLIi12 t2addrmode_imm12:$addr, pred:$p), 0>,2005 Requires<[IsThumb2,HasV7]>;2006def : InstAlias<"pli${p}.w\t$addr",2007 (t2PLIi8 t2addrmode_negimm8:$addr, pred:$p), 0>,2008 Requires<[IsThumb2,HasV7]>;2009def : InstAlias<"pli${p}.w\t$addr",2010 (t2PLIs t2addrmode_so_reg:$addr, pred:$p), 0>,2011 Requires<[IsThumb2,HasV7]>;2012 2013// pci variant is very similar to i12, but supports negative offsets2014// from the PC. Only PLD and PLI have pci variants (not PLDW)2015class T2Iplpci<bits<1> inst, string opc> : T2Ipc<(outs), (ins t2ldrlabel:$addr),2016 IIC_Preload, opc, "\t$addr",2017 [(ARMPreload (ARMWrapper tconstpool:$addr),2018 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {2019 let Inst{31-25} = 0b1111100;2020 let Inst{24} = inst;2021 let Inst{22-20} = 0b001;2022 let Inst{19-16} = 0b1111;2023 let Inst{15-12} = 0b1111;2024 2025 bits<13> addr;2026 let Inst{23} = addr{12}; // add = (U == '1')2027 let Inst{11-0} = addr{11-0}; // imm122028 2029 let DecoderMethod = "DecodeT2LoadLabel";2030}2031 2032def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;2033def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;2034 2035def : t2InstAlias<"pld${p}.w $addr",2036 (t2PLDpci t2ldrlabel:$addr, pred:$p)>;2037def : InstAlias<"pli${p}.w $addr",2038 (t2PLIpci t2ldrlabel:$addr, pred:$p), 0>,2039 Requires<[IsThumb2,HasV7]>;2040 2041// PLD/PLI with alternate literal form.2042def : t2InstAlias<"pld${p} $addr",2043 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;2044def : InstAlias<"pli${p} $addr",2045 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,2046 Requires<[IsThumb2,HasV7]>;2047def : t2InstAlias<"pld${p}.w $addr",2048 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;2049def : InstAlias<"pli${p}.w $addr",2050 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,2051 Requires<[IsThumb2,HasV7]>;2052 2053//===----------------------------------------------------------------------===//2054// Load / store multiple Instructions.2055//2056 2057multiclass thumb2_ld_mult<string asm, InstrItinClass itin,2058 InstrItinClass itin_upd, bit L_bit> {2059 def IA :2060 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),2061 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {2062 bits<0> p;2063 bits<4> Rn;2064 bits<16> regs;2065 2066 let Inst{31-27} = 0b11101;2067 let Inst{26-25} = 0b00;2068 let Inst{24-23} = 0b01; // Increment After2069 let Inst{22} = 0;2070 let Inst{21} = 0; // No writeback2071 let Inst{20} = L_bit;2072 let Inst{19-16} = Rn;2073 let Inst{15-0} = regs;2074 }2075 def IA_UPD :2076 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),2077 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {2078 bits<0> p;2079 bits<4> Rn;2080 bits<16> regs;2081 2082 let Inst{31-27} = 0b11101;2083 let Inst{26-25} = 0b00;2084 let Inst{24-23} = 0b01; // Increment After2085 let Inst{22} = 0;2086 let Inst{21} = 1; // Writeback2087 let Inst{20} = L_bit;2088 let Inst{19-16} = Rn;2089 let Inst{15-0} = regs;2090 }2091 def DB :2092 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),2093 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {2094 bits<0> p;2095 bits<4> Rn;2096 bits<16> regs;2097 2098 let Inst{31-27} = 0b11101;2099 let Inst{26-25} = 0b00;2100 let Inst{24-23} = 0b10; // Decrement Before2101 let Inst{22} = 0;2102 let Inst{21} = 0; // No writeback2103 let Inst{20} = L_bit;2104 let Inst{19-16} = Rn;2105 let Inst{15-0} = regs;2106 }2107 def DB_UPD :2108 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),2109 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {2110 bits<0> p;2111 bits<4> Rn;2112 bits<16> regs;2113 2114 let Inst{31-27} = 0b11101;2115 let Inst{26-25} = 0b00;2116 let Inst{24-23} = 0b10; // Decrement Before2117 let Inst{22} = 0;2118 let Inst{21} = 1; // Writeback2119 let Inst{20} = L_bit;2120 let Inst{19-16} = Rn;2121 let Inst{15-0} = regs;2122 }2123}2124 2125let hasSideEffects = 0 in {2126 2127let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in2128defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;2129 2130multiclass thumb2_st_mult<string asm, InstrItinClass itin,2131 InstrItinClass itin_upd, bit L_bit> {2132 def IA :2133 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),2134 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {2135 bits<0> p;2136 bits<4> Rn;2137 bits<16> regs;2138 2139 let Inst{31-27} = 0b11101;2140 let Inst{26-25} = 0b00;2141 let Inst{24-23} = 0b01; // Increment After2142 let Inst{22} = 0;2143 let Inst{21} = 0; // No writeback2144 let Inst{20} = L_bit;2145 let Inst{19-16} = Rn;2146 let Inst{15} = 0;2147 let Inst{14} = regs{14};2148 let Inst{13} = 0;2149 let Inst{12-0} = regs{12-0};2150 }2151 def IA_UPD :2152 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),2153 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {2154 bits<0> p;2155 bits<4> Rn;2156 bits<16> regs;2157 2158 let Inst{31-27} = 0b11101;2159 let Inst{26-25} = 0b00;2160 let Inst{24-23} = 0b01; // Increment After2161 let Inst{22} = 0;2162 let Inst{21} = 1; // Writeback2163 let Inst{20} = L_bit;2164 let Inst{19-16} = Rn;2165 let Inst{15} = 0;2166 let Inst{14} = regs{14};2167 let Inst{13} = 0;2168 let Inst{12-0} = regs{12-0};2169 }2170 def DB :2171 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),2172 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {2173 bits<0> p;2174 bits<4> Rn;2175 bits<16> regs;2176 2177 let Inst{31-27} = 0b11101;2178 let Inst{26-25} = 0b00;2179 let Inst{24-23} = 0b10; // Decrement Before2180 let Inst{22} = 0;2181 let Inst{21} = 0; // No writeback2182 let Inst{20} = L_bit;2183 let Inst{19-16} = Rn;2184 let Inst{15} = 0;2185 let Inst{14} = regs{14};2186 let Inst{13} = 0;2187 let Inst{12-0} = regs{12-0};2188 }2189 def DB_UPD :2190 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),2191 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {2192 bits<0> p;2193 bits<4> Rn;2194 bits<16> regs;2195 2196 let Inst{31-27} = 0b11101;2197 let Inst{26-25} = 0b00;2198 let Inst{24-23} = 0b10; // Decrement Before2199 let Inst{22} = 0;2200 let Inst{21} = 1; // Writeback2201 let Inst{20} = L_bit;2202 let Inst{19-16} = Rn;2203 let Inst{15} = 0;2204 let Inst{14} = regs{14};2205 let Inst{13} = 0;2206 let Inst{12-0} = regs{12-0};2207 }2208}2209 2210 2211let mayStore = 1, hasExtraSrcRegAllocReq = 1 in2212defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;2213 2214} // hasSideEffects2215 2216 2217//===----------------------------------------------------------------------===//2218// Move Instructions.2219//2220 2221let hasSideEffects = 0 in2222def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr,2223 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {2224 let Inst{31-27} = 0b11101;2225 let Inst{26-25} = 0b01;2226 let Inst{24-21} = 0b0010;2227 let Inst{19-16} = 0b1111; // Rn2228 let Inst{15} = 0b0;2229 let Inst{14-12} = 0b000;2230 let Inst{7-4} = 0b0000;2231}2232def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,2233 pred:$p, (cc_out zero_reg))>;2234def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,2235 pred:$p, (cc_out CPSR))>;2236def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,2237 pred:$p, (cc_out CPSR))>;2238 2239// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.2240let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,2241 AddedComplexity = 1 in2242def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,2243 "mov", ".w\t$Rd, $imm",2244 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {2245 let Inst{31-27} = 0b11110;2246 let Inst{25} = 0;2247 let Inst{24-21} = 0b0010;2248 let Inst{19-16} = 0b1111; // Rn2249 let Inst{15} = 0;2250}2251 2252// cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.2253// Use aliases to get that to play nice here.2254def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,2255 pred:$p, (cc_out CPSR))>;2256def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,2257 pred:$p, (cc_out CPSR))>;2258 2259def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,2260 pred:$p, (cc_out zero_reg))>;2261def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,2262 pred:$p, (cc_out zero_reg))>;2263 2264let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in2265def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,2266 "movw", "\t$Rd, $imm",2267 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,2268 Requires<[IsThumb, HasV8MBaseline]> {2269 let Inst{31-27} = 0b11110;2270 let Inst{25} = 1;2271 let Inst{24-21} = 0b0010;2272 let Inst{20} = 0; // The S bit.2273 let Inst{15} = 0;2274 2275 bits<4> Rd;2276 bits<16> imm;2277 2278 let Inst{11-8} = Rd;2279 let Inst{19-16} = imm{15-12};2280 let Inst{26} = imm{11};2281 let Inst{14-12} = imm{10-8};2282 let Inst{7-0} = imm{7-0};2283 let DecoderMethod = "DecodeT2MOVTWInstruction";2284}2285 2286def : InstAlias<"mov${p} $Rd, $imm",2287 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,2288 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>;2289 2290// This gets lowered to a single 4-byte instructions2291let Size = 4 in2292def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),2293 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,2294 Sched<[WriteALU]>;2295 2296let Constraints = "$src = $Rd" in {2297def t2MOVTi16 : T2I<(outs rGPR:$Rd),2298 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,2299 "movt", "\t$Rd, $imm",2300 [(set rGPR:$Rd,2301 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,2302 Sched<[WriteALU]>,2303 Requires<[IsThumb, HasV8MBaseline]> {2304 let Inst{31-27} = 0b11110;2305 let Inst{25} = 1;2306 let Inst{24-21} = 0b0110;2307 let Inst{20} = 0; // The S bit.2308 let Inst{15} = 0;2309 2310 bits<4> Rd;2311 bits<16> imm;2312 2313 let Inst{11-8} = Rd;2314 let Inst{19-16} = imm{15-12};2315 let Inst{26} = imm{11};2316 let Inst{14-12} = imm{10-8};2317 let Inst{7-0} = imm{7-0};2318 let DecoderMethod = "DecodeT2MOVTWInstruction";2319}2320 2321// This gets lowered to a single 4-byte instructions2322let Size = 4 in2323def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),2324 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,2325 Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;2326} // Constraints2327 2328def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;2329 2330//===----------------------------------------------------------------------===//2331// Extend Instructions.2332//2333 2334// Sign extenders2335 2336def t2SXTB : T2I_ext_rrot<0b100, "sxtb">;2337def t2SXTH : T2I_ext_rrot<0b000, "sxth">;2338def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">;2339 2340def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">;2341def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">;2342def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">;2343 2344def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8),2345 (t2SXTB rGPR:$Rn, rot_imm:$rot)>;2346def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16),2347 (t2SXTH rGPR:$Rn, rot_imm:$rot)>;2348def : Thumb2DSPPat<(add rGPR:$Rn,2349 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8)),2350 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2351def : Thumb2DSPPat<(add rGPR:$Rn,2352 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16)),2353 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2354def : Thumb2DSPPat<(int_arm_sxtb16 rGPR:$Rn),2355 (t2SXTB16 rGPR:$Rn, 0)>;2356def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, rGPR:$Rm),2357 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;2358def : Thumb2DSPPat<(int_arm_sxtb16 (rotr rGPR:$Rn, rot_imm:$rot)),2359 (t2SXTB16 rGPR:$Rn, rot_imm:$rot)>;2360def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)),2361 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2362 2363 2364// A simple right-shift can also be used in most cases (the exception is the2365// SXTH operations with a rotate of 24: there the non-contiguous bits are2366// relevant).2367def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg2368 (srl rGPR:$Rm, rot_imm:$rot), i8)),2369 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2370def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg2371 (srl rGPR:$Rm, imm8_or_16:$rot), i16)),2372 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2373def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg2374 (rotr rGPR:$Rm, (i32 24)), i16)),2375 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;2376def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg2377 (or (srl rGPR:$Rm, (i32 24)),2378 (shl rGPR:$Rm, (i32 8))), i16)),2379 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;2380 2381// Zero extenders2382 2383let AddedComplexity = 16 in {2384def t2UXTB : T2I_ext_rrot<0b101, "uxtb">;2385def t2UXTH : T2I_ext_rrot<0b001, "uxth">;2386def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">;2387 2388def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF),2389 (t2UXTB rGPR:$Rm, rot_imm:$rot)>;2390def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF),2391 (t2UXTH rGPR:$Rm, rot_imm:$rot)>;2392def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF),2393 (t2UXTB16 rGPR:$Rm, rot_imm:$rot)>;2394 2395def : Thumb2DSPPat<(int_arm_uxtb16 rGPR:$Rm),2396 (t2UXTB16 rGPR:$Rm, 0)>;2397def : Thumb2DSPPat<(int_arm_uxtb16 (rotr rGPR:$Rn, rot_imm:$rot)),2398 (t2UXTB16 rGPR:$Rn, rot_imm:$rot)>;2399 2400// FIXME: This pattern incorrectly assumes the shl operator is a rotate.2401// The transformation should probably be done as a combiner action2402// instead so we can include a check for masking back in the upper2403// eight bits of the source into the lower eight bits of the result.2404//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),2405// (t2UXTB16 rGPR:$Src, 3)>,2406// Requires<[HasDSP, IsThumb2]>;2407def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),2408 (t2UXTB16 rGPR:$Src, 1)>,2409 Requires<[HasDSP, IsThumb2]>;2410 2411def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">;2412def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">;2413def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">;2414 2415def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),2416 0x00FF)),2417 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2418def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),2419 0xFFFF)),2420 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2421def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot),2422 0xFF)),2423 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2424def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot),2425 0xFFFF)),2426 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2427def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, rGPR:$Rm),2428 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;2429def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)),2430 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;2431}2432 2433 2434//===----------------------------------------------------------------------===//2435// Arithmetic Instructions.2436//2437 2438let isAdd = 1 in2439defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;2440defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;2441 2442// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.2443//2444// Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the2445// selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by2446// AdjustInstrPostInstrSelection where we determine whether or not to2447// set the "s" bit based on CPSR liveness.2448//2449// FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen2450// support for an optional CPSR definition that corresponds to the DAG2451// node's second value. We can then eliminate the implicit def of CPSR.2452defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>;2453defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>;2454 2455defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1, 1>;2456defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube, 0, 1>;2457 2458def : t2InstSubst<"adc${s}${p} $rd, $rn, $imm",2459 (t2SBCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;2460def : t2InstSubst<"adc${s}${p} $rdn, $imm",2461 (t2SBCri rGPR:$rdn, rGPR:$rdn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;2462def : t2InstSubst<"sbc${s}${p} $rd, $rn, $imm",2463 (t2ADCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;2464def : t2InstSubst<"sbc${s}${p} $rdn, $imm",2465 (t2ADCri rGPR:$rdn, rGPR:$rdn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;2466 2467def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",2468 (t2SUBri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;2469def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",2470 (t2ADDri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;2471def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",2472 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;2473def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm",2474 (t2ADDri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;2475def : t2InstSubst<"sub${p} $rd, $rn, $imm",2476 (t2ADDri12 rGPR:$rd, GPR:$rn, imm0_4095_neg:$imm, pred:$p)>;2477 2478// SP to SP alike2479def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",2480 (t2SUBspImm GPRsp:$rd, GPRsp:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;2481def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",2482 (t2ADDspImm GPRsp:$rd, GPRsp:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;2483def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",2484 (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;2485def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm",2486 (t2ADDspImm GPRsp:$rd, GPRsp:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;2487def : t2InstSubst<"sub${p} $rd, $rn, $imm",2488 (t2ADDspImm12 GPRsp:$rd, GPRsp:$rn, imm0_4095_neg:$imm, pred:$p)>;2489 2490 2491// RSB2492defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>;2493 2494// FIXME: Eliminate them if we can write def : Pat patterns which defines2495// CPSR and the implicit def of CPSR is not needed.2496defm t2RSBS : T2I_rbin_s_is <ARMsubc>;2497 2498// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.2499// The assume-no-carry-in form uses the negation of the input since add/sub2500// assume opposite meanings of the carry flag (i.e., carry == !borrow).2501// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory2502// details.2503// The AddedComplexity preferences the first variant over the others since2504// it can be shrunk to a 16-bit wide encoding, while the others cannot.2505let AddedComplexity = 1 in2506def : T2Pat<(add rGPR:$src, imm1_255_neg:$imm),2507 (t2SUBri rGPR:$src, imm1_255_neg:$imm)>;2508def : T2Pat<(add rGPR:$src, t2_so_imm_neg:$imm),2509 (t2SUBri rGPR:$src, t2_so_imm_neg:$imm)>;2510def : T2Pat<(add rGPR:$src, imm0_4095_neg:$imm),2511 (t2SUBri12 rGPR:$src, imm0_4095_neg:$imm)>;2512def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),2513 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;2514 2515// Do the same for v8m targets since they support movw with a 16-bit value.2516def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm),2517 (tSUBrr tGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>,2518 Requires<[HasV8MBaseline]>;2519 2520let AddedComplexity = 1 in2521def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),2522 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;2523def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),2524 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;2525def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),2526 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;2527// The with-carry-in form matches bitwise not instead of the negation.2528// Effectively, the inverse interpretation of the carry flag already accounts2529// for part of the negation.2530let AddedComplexity = 1 in2531def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),2532 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;2533def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),2534 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;2535def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),2536 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;2537 2538def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),2539 NoItinerary, "sel", "\t$Rd, $Rn, $Rm",2540 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,2541 Requires<[IsThumb2, HasDSP]> {2542 let Inst{31-27} = 0b11111;2543 let Inst{26-24} = 0b010;2544 let Inst{23} = 0b1;2545 let Inst{22-20} = 0b010;2546 let Inst{15-12} = 0b1111;2547 let Inst{7} = 0b1;2548 let Inst{6-4} = 0b000;2549}2550 2551// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)2552// And Miscellaneous operations -- for disassembly only2553class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,2554 list<dag> pat, dag iops, string asm>2555 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,2556 Requires<[IsThumb2, HasDSP]> {2557 let Inst{31-27} = 0b11111;2558 let Inst{26-23} = 0b0101;2559 let Inst{22-20} = op22_20;2560 let Inst{15-12} = 0b1111;2561 let Inst{7-4} = op7_4;2562 2563 bits<4> Rd;2564 bits<4> Rn;2565 bits<4> Rm;2566 2567 let Inst{11-8} = Rd;2568 let Inst{19-16} = Rn;2569 let Inst{3-0} = Rm;2570}2571 2572class T2I_pam_intrinsics<bits<3> op22_20, bits<4> op7_4, string opc,2573 Intrinsic intrinsic>2574 : T2I_pam<op22_20, op7_4, opc,2575 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))],2576 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">;2577 2578class T2I_pam_intrinsics_rev<bits<3> op22_20, bits<4> op7_4, string opc>2579 : T2I_pam<op22_20, op7_4, opc, [],2580 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;2581 2582// Saturating add/subtract2583def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>;2584def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>;2585def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>;2586def t2UQSUB8 : T2I_pam_intrinsics<0b100, 0b0101, "uqsub8", int_arm_uqsub8>;2587def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>;2588def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>;2589def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;2590def t2UQADD16 : T2I_pam_intrinsics<0b001, 0b0101, "uqadd16", int_arm_uqadd16>;2591def t2UQADD8 : T2I_pam_intrinsics<0b000, 0b0101, "uqadd8", int_arm_uqadd8>;2592def t2UQASX : T2I_pam_intrinsics<0b010, 0b0101, "uqasx", int_arm_uqasx>;2593def t2UQSAX : T2I_pam_intrinsics<0b110, 0b0101, "uqsax", int_arm_uqsax>;2594def t2UQSUB16 : T2I_pam_intrinsics<0b101, 0b0101, "uqsub16", int_arm_uqsub16>;2595def t2QADD : T2I_pam_intrinsics_rev<0b000, 0b1000, "qadd">;2596def t2QSUB : T2I_pam_intrinsics_rev<0b000, 0b1010, "qsub">;2597def t2QDADD : T2I_pam_intrinsics_rev<0b000, 0b1001, "qdadd">;2598def t2QDSUB : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">;2599 2600def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, rGPR:$Rn),2601 (t2QADD rGPR:$Rm, rGPR:$Rn)>;2602def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, rGPR:$Rn),2603 (t2QSUB rGPR:$Rm, rGPR:$Rn)>;2604def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)),2605 (t2QDADD rGPR:$Rm, rGPR:$Rn)>;2606def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)),2607 (t2QDSUB rGPR:$Rm, rGPR:$Rn)>;2608 2609def : Thumb2DSPPat<(saddsat rGPR:$Rm, rGPR:$Rn),2610 (t2QADD rGPR:$Rm, rGPR:$Rn)>;2611def : Thumb2DSPPat<(ssubsat rGPR:$Rm, rGPR:$Rn),2612 (t2QSUB rGPR:$Rm, rGPR:$Rn)>;2613def : Thumb2DSPPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),2614 (t2QDADD rGPR:$Rm, rGPR:$Rn)>;2615def : Thumb2DSPPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),2616 (t2QDSUB rGPR:$Rm, rGPR:$Rn)>;2617 2618def : Thumb2DSPPat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),2619 (t2QADD8 rGPR:$Rm, rGPR:$Rn)>;2620def : Thumb2DSPPat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),2621 (t2QSUB8 rGPR:$Rm, rGPR:$Rn)>;2622def : Thumb2DSPPat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn),2623 (t2QADD16 rGPR:$Rm, rGPR:$Rn)>;2624def : Thumb2DSPPat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn),2625 (t2QSUB16 rGPR:$Rm, rGPR:$Rn)>;2626 2627def : Thumb2DSPPat<(ARMuqadd8b rGPR:$Rm, rGPR:$Rn),2628 (t2UQADD8 rGPR:$Rm, rGPR:$Rn)>;2629def : Thumb2DSPPat<(ARMuqsub8b rGPR:$Rm, rGPR:$Rn),2630 (t2UQSUB8 rGPR:$Rm, rGPR:$Rn)>;2631def : Thumb2DSPPat<(ARMuqadd16b rGPR:$Rm, rGPR:$Rn),2632 (t2UQADD16 rGPR:$Rm, rGPR:$Rn)>;2633def : Thumb2DSPPat<(ARMuqsub16b rGPR:$Rm, rGPR:$Rn),2634 (t2UQSUB16 rGPR:$Rm, rGPR:$Rn)>;2635 2636// Signed/Unsigned add/subtract2637 2638def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>;2639def t2SADD16 : T2I_pam_intrinsics<0b001, 0b0000, "sadd16", int_arm_sadd16>;2640def t2SADD8 : T2I_pam_intrinsics<0b000, 0b0000, "sadd8", int_arm_sadd8>;2641def t2SSAX : T2I_pam_intrinsics<0b110, 0b0000, "ssax", int_arm_ssax>;2642def t2SSUB16 : T2I_pam_intrinsics<0b101, 0b0000, "ssub16", int_arm_ssub16>;2643def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>;2644def t2UASX : T2I_pam_intrinsics<0b010, 0b0100, "uasx", int_arm_uasx>;2645def t2UADD16 : T2I_pam_intrinsics<0b001, 0b0100, "uadd16", int_arm_uadd16>;2646def t2UADD8 : T2I_pam_intrinsics<0b000, 0b0100, "uadd8", int_arm_uadd8>;2647def t2USAX : T2I_pam_intrinsics<0b110, 0b0100, "usax", int_arm_usax>;2648def t2USUB16 : T2I_pam_intrinsics<0b101, 0b0100, "usub16", int_arm_usub16>;2649def t2USUB8 : T2I_pam_intrinsics<0b100, 0b0100, "usub8", int_arm_usub8>;2650 2651// Signed/Unsigned halving add/subtract2652 2653def t2SHASX : T2I_pam_intrinsics<0b010, 0b0010, "shasx", int_arm_shasx>;2654def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>;2655def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>;2656def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>;2657def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>;2658def t2SHSUB8 : T2I_pam_intrinsics<0b100, 0b0010, "shsub8", int_arm_shsub8>;2659def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>;2660def t2UHADD16 : T2I_pam_intrinsics<0b001, 0b0110, "uhadd16", int_arm_uhadd16>;2661def t2UHADD8 : T2I_pam_intrinsics<0b000, 0b0110, "uhadd8", int_arm_uhadd8>;2662def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>;2663def t2UHSUB16 : T2I_pam_intrinsics<0b101, 0b0110, "uhsub16", int_arm_uhsub16>;2664def t2UHSUB8 : T2I_pam_intrinsics<0b100, 0b0110, "uhsub8", int_arm_uhsub8>;2665 2666// Helper class for disassembly only2667// A6.3.16 & A6.3.172668// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.2669class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,2670 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>2671 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {2672 let Inst{31-27} = 0b11111;2673 let Inst{26-24} = 0b011;2674 let Inst{23} = long;2675 let Inst{22-20} = op22_20;2676 let Inst{7-4} = op7_4;2677}2678 2679class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,2680 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>2681 : T2FourReg<oops, iops, itin, opc, asm, pattern> {2682 let Inst{31-27} = 0b11111;2683 let Inst{26-24} = 0b011;2684 let Inst{23} = long;2685 let Inst{22-20} = op22_20;2686 let Inst{7-4} = op7_4;2687}2688 2689// Unsigned Sum of Absolute Differences [and Accumulate].2690def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),2691 (ins rGPR:$Rn, rGPR:$Rm),2692 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm",2693 [(set rGPR:$Rd, (int_arm_usad8 rGPR:$Rn, rGPR:$Rm))]>,2694 Requires<[IsThumb2, HasDSP]> {2695 let Inst{15-12} = 0b1111;2696}2697def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),2698 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,2699 "usada8", "\t$Rd, $Rn, $Rm, $Ra",2700 [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,2701 Requires<[IsThumb2, HasDSP]>;2702 2703// Signed/Unsigned saturate.2704class T2SatI<dag iops, string opc, string asm>2705 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> {2706 bits<4> Rd;2707 bits<4> Rn;2708 bits<5> sat_imm;2709 bits<6> sh;2710 2711 let Inst{31-24} = 0b11110011;2712 let Inst{21} = sh{5};2713 let Inst{20} = 0;2714 let Inst{19-16} = Rn;2715 let Inst{15} = 0;2716 let Inst{14-12} = sh{4-2};2717 let Inst{11-8} = Rd;2718 let Inst{7-6} = sh{1-0};2719 let Inst{5} = 0;2720 let Inst{4-0} = sat_imm;2721}2722 2723def t2SSAT: T2SatI<(ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),2724 "ssat", "\t$Rd, $sat_imm, $Rn$sh">,2725 Requires<[IsThumb2]>, Sched<[WriteALU]> {2726 let Inst{23-22} = 0b00;2727 let Inst{5} = 0;2728}2729 2730def t2SSAT16: T2SatI<(ins imm1_16:$sat_imm, rGPR:$Rn),2731 "ssat16", "\t$Rd, $sat_imm, $Rn">,2732 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {2733 let Inst{23-22} = 0b00;2734 let sh = 0b100000;2735 let Inst{4} = 0;2736}2737 2738def t2USAT: T2SatI<(ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),2739 "usat", "\t$Rd, $sat_imm, $Rn$sh">,2740 Requires<[IsThumb2]>, Sched<[WriteALU]> {2741 let Inst{23-22} = 0b10;2742}2743 2744def t2USAT16: T2SatI<(ins imm0_15:$sat_imm, rGPR:$Rn),2745 "usat16", "\t$Rd, $sat_imm, $Rn">,2746 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {2747 let Inst{23-22} = 0b10;2748 let sh = 0b100000;2749 let Inst{4} = 0;2750}2751 2752def : T2Pat<(ARMssat GPRnopc:$Rn, imm0_31:$imm),2753 (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;2754def : T2Pat<(ARMusat GPRnopc:$Rn, imm0_31:$imm),2755 (t2USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;2756def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos),2757 (t2SSAT imm1_32:$pos, GPR:$a, 0)>;2758def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos),2759 (t2USAT imm0_31:$pos, GPR:$a, 0)>;2760def : T2Pat<(int_arm_ssat16 GPR:$a, imm1_16:$pos),2761 (t2SSAT16 imm1_16:$pos, GPR:$a)>;2762def : T2Pat<(int_arm_usat16 GPR:$a, imm0_15:$pos),2763 (t2USAT16 imm0_15:$pos, GPR:$a)>;2764def : T2Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos),2765 (t2SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>;2766def : T2Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos),2767 (t2SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>;2768def : T2Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),2769 (t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;2770def : T2Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),2771 (t2USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>;2772def : T2Pat<(ARMssat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),2773 (t2SSAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;2774def : T2Pat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),2775 (t2SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;2776def : T2Pat<(ARMusat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),2777 (t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;2778def : T2Pat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),2779 (t2USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;2780 2781 2782//===----------------------------------------------------------------------===//2783// Shift and rotate Instructions.2784//2785 2786defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;2787defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;2788defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>;2789defm t2ROR : T2I_sh_ir<0b11, "ror", imm1_31, rotr>;2790 2791// LSL #0 is actually MOV, and has slightly different permitted registers to2792// LSL with non-zero shift2793def : t2InstAlias<"lsl${s}${p} $Rd, $Rm, #0",2794 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;2795def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0",2796 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;2797 2798// (rotr x, (and y, 0x...1f)) ==> (ROR x, y)2799def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),2800 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;2801 2802let Uses = [CPSR] in {2803def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,2804 "rrx", "\t$Rd, $Rm",2805 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm, CPSR))]>,2806 Sched<[WriteALU]> {2807 let Inst{31-27} = 0b11101;2808 let Inst{26-25} = 0b01;2809 let Inst{24-21} = 0b0010;2810 let Inst{19-16} = 0b1111; // Rn2811 let Inst{15} = 0b0;2812 let Unpredictable{15} = 0b1;2813 let Inst{14-12} = 0b000;2814 let Inst{7-4} = 0b0011;2815}2816}2817 2818// These differ from t2LSRri / t2ASRri in that they are flag-setting2819// and have a hardcoded shift amount = 1.2820let isCodeGenOnly = 1, Defs = [CPSR] in {2821def t2LSRs1 : T2TwoRegShiftImm<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,2822 "lsrs", ".w\t$Rd, $Rm, #1",2823 [(set rGPR:$Rd, CPSR, (ARMlsrs1 rGPR:$Rm))]>,2824 Sched<[WriteALU]> {2825 let Inst{31-27} = 0b11101;2826 let Inst{26-25} = 0b01;2827 let Inst{24-21} = 0b0010;2828 let Inst{20} = 1; // The S bit.2829 let Inst{19-16} = 0b1111; // Rn2830 let Inst{5-4} = 0b01; // Shift type.2831 // Shift amount = Inst{14-12:7-6} = 1.2832 let Inst{14-12} = 0b000;2833 let Inst{7-6} = 0b01;2834}2835def t2ASRs1 : T2TwoRegShiftImm<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,2836 "asrs", ".w\t$Rd, $Rm, #1",2837 [(set rGPR:$Rd, CPSR, (ARMasrs1 rGPR:$Rm))]>,2838 Sched<[WriteALU]> {2839 let Inst{31-27} = 0b11101;2840 let Inst{26-25} = 0b01;2841 let Inst{24-21} = 0b0010;2842 let Inst{20} = 1; // The S bit.2843 let Inst{19-16} = 0b1111; // Rn2844 let Inst{5-4} = 0b10; // Shift type.2845 // Shift amount = Inst{14-12:7-6} = 1.2846 let Inst{14-12} = 0b000;2847 let Inst{7-6} = 0b01;2848}2849}2850 2851//===----------------------------------------------------------------------===//2852// Bitwise Instructions.2853//2854 2855defm t2AND : T2I_bin_w_irs<0b0000, "and",2856 IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, 1>;2857defm t2ORR : T2I_bin_w_irs<0b0010, "orr",2858 IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 1>;2859defm t2EOR : T2I_bin_w_irs<0b0100, "eor",2860 IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, 1>;2861 2862defm t2BIC : T2I_bin_w_irs<0b0001, "bic",2863 IIC_iBITi, IIC_iBITr, IIC_iBITsi,2864 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;2865 2866class T2BitFI<dag oops, dag iops, InstrItinClass itin,2867 string opc, string asm, list<dag> pattern>2868 : T2I<oops, iops, itin, opc, asm, pattern> {2869 bits<4> Rd;2870 bits<5> msb;2871 bits<5> lsb;2872 2873 let Inst{11-8} = Rd;2874 let Inst{4-0} = msb{4-0};2875 let Inst{14-12} = lsb{4-2};2876 let Inst{7-6} = lsb{1-0};2877}2878 2879class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,2880 string opc, string asm, list<dag> pattern>2881 : T2BitFI<oops, iops, itin, opc, asm, pattern> {2882 bits<4> Rn;2883 2884 let Inst{19-16} = Rn;2885}2886 2887let Constraints = "$src = $Rd" in2888def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),2889 IIC_iUNAsi, "bfc", "\t$Rd, $imm",2890 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {2891 let Inst{31-27} = 0b11110;2892 let Inst{26} = 0; // should be 0.2893 let Inst{25} = 1;2894 let Inst{24-20} = 0b10110;2895 let Inst{19-16} = 0b1111; // Rn2896 let Inst{15} = 0;2897 let Inst{5} = 0; // should be 0.2898 2899 bits<10> imm;2900 let msb{4-0} = imm{9-5};2901 let lsb{4-0} = imm{4-0};2902}2903 2904def t2SBFX: T2TwoRegBitFI<2905 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),2906 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {2907 let Inst{31-27} = 0b11110;2908 let Inst{25} = 1;2909 let Inst{24-20} = 0b10100;2910 let Inst{15} = 0;2911 2912 let hasSideEffects = 0;2913}2914 2915def t2UBFX: T2TwoRegBitFI<2916 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),2917 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {2918 let Inst{31-27} = 0b11110;2919 let Inst{25} = 1;2920 let Inst{24-20} = 0b11100;2921 let Inst{15} = 0;2922 2923 let hasSideEffects = 0;2924}2925 2926// A8.8.247 UDF - Undefined (Encoding T2)2927def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",2928 [(int_arm_undefined imm0_65535:$imm16)]> {2929 bits<16> imm16;2930 let Inst{31-29} = 0b111;2931 let Inst{28-27} = 0b10;2932 let Inst{26-20} = 0b1111111;2933 let Inst{19-16} = imm16{15-12};2934 let Inst{15} = 0b1;2935 let Inst{14-12} = 0b010;2936 let Inst{11-0} = imm16{11-0};2937}2938 2939// A8.6.18 BFI - Bitfield insert (Encoding T1)2940let Constraints = "$src = $Rd" in {2941 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),2942 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),2943 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",2944 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,2945 bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {2946 let Inst{31-27} = 0b11110;2947 let Inst{26} = 0; // should be 0.2948 let Inst{25} = 1;2949 let Inst{24-20} = 0b10110;2950 let Inst{15} = 0;2951 let Inst{5} = 0; // should be 0.2952 2953 bits<10> imm;2954 let msb{4-0} = imm{9-5};2955 let lsb{4-0} = imm{4-0};2956 }2957}2958 2959defm t2ORN : T2I_bin_irs<0b0011, "orn",2960 IIC_iBITi, IIC_iBITr, IIC_iBITsi,2961 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;2962def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $imm",2963 (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;2964def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $Rm",2965 (t2ORNrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;2966def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $ShiftedRm",2967 (t2ORNrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;2968 2969/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a2970/// unary operation that produces a value. These are predicable and can be2971/// changed to modify CPSR.2972multiclass T2I_un_irs<bits<4> opcod, string opc,2973 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,2974 PatFrag opnode,2975 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {2976 // shifted imm2977 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,2978 opc, "\t$Rd, $imm",2979 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {2980 let isAsCheapAsAMove = Cheap;2981 let isReMaterializable = ReMat;2982 let isMoveImm = MoveImm;2983 let Inst{31-27} = 0b11110;2984 let Inst{25} = 0;2985 let Inst{24-21} = opcod;2986 let Inst{19-16} = 0b1111; // Rn2987 let Inst{15} = 0;2988 }2989 // register2990 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,2991 opc, ".w\t$Rd, $Rm",2992 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {2993 let Inst{31-27} = 0b11101;2994 let Inst{26-25} = 0b01;2995 let Inst{24-21} = opcod;2996 let Inst{19-16} = 0b1111; // Rn2997 let Inst{14-12} = 0b000; // imm32998 let Inst{7-6} = 0b00; // imm22999 let Inst{5-4} = 0b00; // type3000 }3001 // shifted register3002 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,3003 opc, ".w\t$Rd, $ShiftedRm",3004 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,3005 Sched<[WriteALU]> {3006 let Inst{31-27} = 0b11101;3007 let Inst{26-25} = 0b01;3008 let Inst{24-21} = opcod;3009 let Inst{19-16} = 0b1111; // Rn3010 }3011}3012 3013// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version3014let AddedComplexity = 1 in3015defm t2MVN : T2I_un_irs <0b0011, "mvn",3016 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,3017 not, 1, 1, 1>;3018 3019let AddedComplexity = 1 in3020def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),3021 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;3022 3023// so_imm_notSext is needed instead of so_imm_not, as the value of imm3024// will match the extended, not the original bitWidth for $src.3025def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),3026 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;3027 3028// FIXME: Disable this pattern on Darwin to workaround an assembler bug.3029def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),3030 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,3031 Requires<[IsThumb2]>;3032 3033def : T2Pat<(t2_so_imm_not:$src),3034 (t2MVNi t2_so_imm_not:$src)>;3035 3036// There are shorter Thumb encodings for ADD than ORR, so to increase3037// Thumb2SizeReduction's chances later on we select a t2ADD for an or where3038// possible.3039def : T2Pat<(or AddLikeOrOp:$Rn, t2_so_imm:$imm),3040 (t2ADDri rGPR:$Rn, t2_so_imm:$imm)>;3041 3042def : T2Pat<(or AddLikeOrOp:$Rn, imm0_4095:$Rm),3043 (t2ADDri12 rGPR:$Rn, imm0_4095:$Rm)>;3044 3045def : T2Pat<(or AddLikeOrOp:$Rn, non_imm32:$Rm),3046 (t2ADDrr $Rn, $Rm)>;3047 3048//===----------------------------------------------------------------------===//3049// Multiply Instructions.3050//3051let isCommutable = 1 in3052def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,3053 "mul", "\t$Rd, $Rn, $Rm",3054 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]>,3055 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {3056 let Inst{31-27} = 0b11111;3057 let Inst{26-23} = 0b0110;3058 let Inst{22-20} = 0b000;3059 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)3060 let Inst{7-4} = 0b0000; // Multiply3061}3062 3063class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern>3064 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,3065 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,3066 Requires<[IsThumb2, UseMulOps]>,3067 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {3068 let Inst{31-27} = 0b11111;3069 let Inst{26-23} = 0b0110;3070 let Inst{22-20} = 0b000;3071 let Inst{7-4} = op7_4;3072}3073 3074def t2MLA : T2FourRegMLA<0b0000, "mla",3075 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),3076 rGPR:$Ra))]>;3077def t2MLS: T2FourRegMLA<0b0001, "mls",3078 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,3079 rGPR:$Rm)))]>;3080 3081// Extra precision multiplies with low / high results3082let hasSideEffects = 0 in {3083let isCommutable = 1 in {3084def t2SMULL : T2MulLong<0b000, 0b0000, "smull",3085 [(set rGPR:$RdLo, rGPR:$RdHi,3086 (smullohi rGPR:$Rn, rGPR:$Rm))]>;3087def t2UMULL : T2MulLong<0b010, 0b0000, "umull",3088 [(set rGPR:$RdLo, rGPR:$RdHi,3089 (umullohi rGPR:$Rn, rGPR:$Rm))]>;3090} // isCommutable3091 3092// Multiply + accumulate3093def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;3094def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;3095def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;3096} // hasSideEffects3097 3098// Rounding variants of the below included for disassembly only3099 3100// Most significant word multiply3101class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern>3102 : T2ThreeReg<(outs rGPR:$Rd),3103 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,3104 opc, "\t$Rd, $Rn, $Rm", pattern>,3105 Requires<[IsThumb2, HasDSP]>,3106 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {3107 let Inst{31-27} = 0b11111;3108 let Inst{26-23} = 0b0110;3109 let Inst{22-20} = 0b101;3110 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)3111 let Inst{7-4} = op7_4;3112}3113def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,3114 rGPR:$Rm))]>;3115def t2SMMULR :3116 T2SMMUL<0b0001, "smmulr",3117 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, (i32 0)))]>;3118 3119class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,3120 list<dag> pattern>3121 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,3122 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,3123 Requires<[IsThumb2, HasDSP, UseMulOps]>,3124 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {3125 let Inst{31-27} = 0b11111;3126 let Inst{26-23} = 0b0110;3127 let Inst{22-20} = op22_20;3128 let Inst{7-4} = op7_4;3129}3130 3131def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",3132 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;3133def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar",3134 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;3135def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;3136def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr",3137 [(set rGPR:$Rd, (ARMsmmlsr rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;3138 3139class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,3140 list<dag> pattern>3141 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,3142 "\t$Rd, $Rn, $Rm", pattern>,3143 Requires<[IsThumb2, HasDSP]>,3144 Sched<[WriteMUL16, ReadMUL, ReadMUL]> {3145 let Inst{31-27} = 0b11111;3146 let Inst{26-23} = 0b0110;3147 let Inst{22-20} = op22_20;3148 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)3149 let Inst{7-6} = 0b00;3150 let Inst{5-4} = op5_4;3151}3152 3153def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",3154 [(set rGPR:$Rd, (bb_mul rGPR:$Rn, rGPR:$Rm))]>;3155def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",3156 [(set rGPR:$Rd, (bt_mul rGPR:$Rn, rGPR:$Rm))]>;3157def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",3158 [(set rGPR:$Rd, (tb_mul rGPR:$Rn, rGPR:$Rm))]>;3159def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",3160 [(set rGPR:$Rd, (tt_mul rGPR:$Rn, rGPR:$Rm))]>;3161def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb",3162 [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>;3163def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt",3164 [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>;3165 3166def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_bottom_16 rGPR:$Rm)),3167 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>;3168def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_top_16 rGPR:$Rm)),3169 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;3170def : Thumb2DSPPat<(mul (sext_top_16 rGPR:$Rn), sext_16_node:$Rm),3171 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>;3172 3173def : Thumb2DSPPat<(int_arm_smulbb rGPR:$Rn, rGPR:$Rm),3174 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>;3175def : Thumb2DSPPat<(int_arm_smulbt rGPR:$Rn, rGPR:$Rm),3176 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;3177def : Thumb2DSPPat<(int_arm_smultb rGPR:$Rn, rGPR:$Rm),3178 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>;3179def : Thumb2DSPPat<(int_arm_smultt rGPR:$Rn, rGPR:$Rm),3180 (t2SMULTT rGPR:$Rn, rGPR:$Rm)>;3181def : Thumb2DSPPat<(int_arm_smulwb rGPR:$Rn, rGPR:$Rm),3182 (t2SMULWB rGPR:$Rn, rGPR:$Rm)>;3183def : Thumb2DSPPat<(int_arm_smulwt rGPR:$Rn, rGPR:$Rm),3184 (t2SMULWT rGPR:$Rn, rGPR:$Rm)>;3185 3186class T2FourRegSMLA<bits<3> op22_20, bits<2> op5_4, string opc,3187 list<dag> pattern>3188 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,3189 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,3190 Requires<[IsThumb2, HasDSP, UseMulOps]>,3191 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]> {3192 let Inst{31-27} = 0b11111;3193 let Inst{26-23} = 0b0110;3194 let Inst{22-20} = op22_20;3195 let Inst{7-6} = 0b00;3196 let Inst{5-4} = op5_4;3197}3198 3199def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb",3200 [(set rGPR:$Rd, (add rGPR:$Ra, (bb_mul rGPR:$Rn, rGPR:$Rm)))]>;3201def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt",3202 [(set rGPR:$Rd, (add rGPR:$Ra, (bt_mul rGPR:$Rn, rGPR:$Rm)))]>;3203def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb",3204 [(set rGPR:$Rd, (add rGPR:$Ra, (tb_mul rGPR:$Rn, rGPR:$Rm)))]>;3205def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt",3206 [(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>;3207def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",3208 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>;3209def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",3210 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>;3211 3212def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)),3213 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;3214def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, 3215 (sext_bottom_16 rGPR:$Rm))),3216 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;3217def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn,3218 (sext_top_16 rGPR:$Rm))),3219 (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;3220def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul (sext_top_16 rGPR:$Rn),3221 sext_16_node:$Rm)),3222 (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;3223 3224def : Thumb2DSPPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc),3225 (t2SMLABB GPR:$a, GPR:$b, GPR:$acc)>;3226def : Thumb2DSPPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc),3227 (t2SMLABT GPR:$a, GPR:$b, GPR:$acc)>;3228def : Thumb2DSPPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc),3229 (t2SMLATB GPR:$a, GPR:$b, GPR:$acc)>;3230def : Thumb2DSPPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc),3231 (t2SMLATT GPR:$a, GPR:$b, GPR:$acc)>;3232def : Thumb2DSPPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc),3233 (t2SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;3234def : Thumb2DSPPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc),3235 (t2SMLAWT GPR:$a, GPR:$b, GPR:$acc)>;3236 3237// Halfword multiple accumulate long: SMLAL<x><y>3238def t2SMLALBB : T2MlaLong<0b100, 0b1000, "smlalbb">,3239 Requires<[IsThumb2, HasDSP]>;3240def t2SMLALBT : T2MlaLong<0b100, 0b1001, "smlalbt">,3241 Requires<[IsThumb2, HasDSP]>;3242def t2SMLALTB : T2MlaLong<0b100, 0b1010, "smlaltb">,3243 Requires<[IsThumb2, HasDSP]>;3244def t2SMLALTT : T2MlaLong<0b100, 0b1011, "smlaltt">,3245 Requires<[IsThumb2, HasDSP]>;3246 3247def : Thumb2DSPPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),3248 (t2SMLALBB $Rn, $Rm, $RLo, $RHi)>;3249def : Thumb2DSPPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),3250 (t2SMLALBT $Rn, $Rm, $RLo, $RHi)>;3251def : Thumb2DSPPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),3252 (t2SMLALTB $Rn, $Rm, $RLo, $RHi)>;3253def : Thumb2DSPPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),3254 (t2SMLALTT $Rn, $Rm, $RLo, $RHi)>;3255 3256class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc,3257 Intrinsic intrinsic>3258 : T2ThreeReg_mac<0, op22_20, op7_4,3259 (outs rGPR:$Rd),3260 (ins rGPR:$Rn, rGPR:$Rm),3261 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm",3262 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))]>,3263 Requires<[IsThumb2, HasDSP]>,3264 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {3265 let Inst{15-12} = 0b1111;3266}3267 3268// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD3269def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad", int_arm_smuad>;3270def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx", int_arm_smuadx>;3271def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd", int_arm_smusd>;3272def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx", int_arm_smusdx>;3273 3274class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc,3275 Intrinsic intrinsic>3276 : T2FourReg_mac<0, op22_20, op7_4,3277 (outs rGPR:$Rd),3278 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),3279 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra",3280 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,3281 Requires<[IsThumb2, HasDSP]>;3282 3283def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad", int_arm_smlad>;3284def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx", int_arm_smladx>;3285def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd", int_arm_smlsd>;3286def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx", int_arm_smlsdx>;3287 3288class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc>3289 : T2FourReg_mac<1, op22_20, op7_4,3290 (outs rGPR:$Ra, rGPR:$Rd),3291 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),3292 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,3293 RegConstraint<"$Ra = $RLo, $Rd = $RHi">,3294 Requires<[IsThumb2, HasDSP]>,3295 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;3296 3297def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;3298def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;3299def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;3300def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;3301 3302def : Thumb2DSPPat<(ARMSmlald rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),3303 (t2SMLALD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;3304def : Thumb2DSPPat<(ARMSmlaldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),3305 (t2SMLALDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;3306def : Thumb2DSPPat<(ARMSmlsld rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),3307 (t2SMLSLD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;3308def : Thumb2DSPPat<(ARMSmlsldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),3309 (t2SMLSLDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;3310 3311//===----------------------------------------------------------------------===//3312// Division Instructions.3313// Signed and unsigned division on v7-M3314//3315let TwoOperandAliasConstraint = "$Rn = $Rd" in {3316def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,3317 "sdiv", "\t$Rd, $Rn, $Rm",3318 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,3319 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,3320 Sched<[WriteDIV]> {3321 let Inst{31-27} = 0b11111;3322 let Inst{26-21} = 0b011100;3323 let Inst{20} = 0b1;3324 let Inst{15-12} = 0b1111;3325 let Inst{7-4} = 0b1111;3326}3327 3328def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,3329 "udiv", "\t$Rd, $Rn, $Rm",3330 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,3331 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,3332 Sched<[WriteDIV]> {3333 let Inst{31-27} = 0b11111;3334 let Inst{26-21} = 0b011101;3335 let Inst{20} = 0b1;3336 let Inst{15-12} = 0b1111;3337 let Inst{7-4} = 0b1111;3338}3339}3340 3341//===----------------------------------------------------------------------===//3342// Misc. Arithmetic Instructions.3343//3344 3345class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,3346 InstrItinClass itin, string opc, string asm, list<dag> pattern>3347 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {3348 let Inst{31-27} = 0b11111;3349 let Inst{26-22} = 0b01010;3350 let Inst{21-20} = op1;3351 let Inst{15-12} = 0b1111;3352 let Inst{7-6} = 0b10;3353 let Inst{5-4} = op2;3354 let Rn{3-0} = Rm;3355}3356 3357def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,3358 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,3359 Sched<[WriteALU]>;3360 3361def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,3362 "rbit", "\t$Rd, $Rm",3363 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>,3364 Sched<[WriteALU]>;3365 3366def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,3367 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,3368 Sched<[WriteALU]>;3369 3370def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,3371 "rev16", ".w\t$Rd, $Rm",3372 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,3373 Sched<[WriteALU]>;3374 3375def : T2Pat<(srl (bswap top16Zero:$Rn), (i32 16)),3376 (t2REV16 rGPR:$Rn)>;3377 3378def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,3379 "revsh", ".w\t$Rd, $Rm",3380 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,3381 Sched<[WriteALU]>;3382 3383def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),3384 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),3385 (t2REVSH rGPR:$Rm)>;3386 3387def t2PKHBT : T2ThreeReg<3388 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),3389 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",3390 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),3391 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),3392 0xFFFF0000)))]>,3393 Requires<[HasDSP, IsThumb2]>,3394 Sched<[WriteALUsi, ReadALU]> {3395 let Inst{31-27} = 0b11101;3396 let Inst{26-25} = 0b01;3397 let Inst{24-20} = 0b01100;3398 let Inst{5} = 0; // BT form3399 let Inst{4} = 0;3400 3401 bits<5> sh;3402 let Inst{14-12} = sh{4-2};3403 let Inst{7-6} = sh{1-0};3404}3405 3406// Alternate cases for PKHBT where identities eliminate some nodes.3407def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),3408 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,3409 Requires<[HasDSP, IsThumb2]>;3410def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),3411 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,3412 Requires<[HasDSP, IsThumb2]>;3413 3414// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and3415// will match the pattern below.3416def t2PKHTB : T2ThreeReg<3417 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),3418 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",3419 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),3420 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),3421 0xFFFF)))]>,3422 Requires<[HasDSP, IsThumb2]>,3423 Sched<[WriteALUsi, ReadALU]> {3424 let Inst{31-27} = 0b11101;3425 let Inst{26-25} = 0b01;3426 let Inst{24-20} = 0b01100;3427 let Inst{5} = 1; // TB form3428 let Inst{4} = 0;3429 3430 bits<5> sh;3431 let Inst{14-12} = sh{4-2};3432 let Inst{7-6} = sh{1-0};3433}3434 3435// Alternate cases for PKHTB where identities eliminate some nodes. Note that3436// a shift amount of 0 is *not legal* here, it is PKHBT instead.3437// We also can not replace a srl (17..31) by an arithmetic shift we would use in3438// pkhtb src1, src2, asr (17..31).3439def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),3440 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,3441 Requires<[HasDSP, IsThumb2]>;3442def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),3443 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,3444 Requires<[HasDSP, IsThumb2]>;3445def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),3446 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),3447 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,3448 Requires<[HasDSP, IsThumb2]>;3449 3450//===----------------------------------------------------------------------===//3451// CRC32 Instructions3452//3453// Polynomials:3454// + CRC32{B,H,W} 0x04C11DB73455// + CRC32C{B,H,W} 0x1EDC6F413456//3457 3458class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>3459 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,3460 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),3461 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,3462 Requires<[IsThumb2, HasCRC]> {3463 let Inst{31-27} = 0b11111;3464 let Inst{26-21} = 0b010110;3465 let Inst{20} = C;3466 let Inst{15-12} = 0b1111;3467 let Inst{7-6} = 0b10;3468 let Inst{5-4} = sz;3469}3470 3471def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;3472def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;3473def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;3474def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;3475def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;3476def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;3477 3478//===----------------------------------------------------------------------===//3479// Comparison Instructions...3480//3481defm t2CMP : T2I_cmp_irs<0b1101, "cmp", GPRnopc,3482 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, ARMcmp>;3483 3484def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),3485 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;3486def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),3487 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;3488def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg_oneuse:$rhs),3489 (t2CMPrs GPRnopc:$lhs, t2_so_reg_oneuse:$rhs)>;3490 3491let isCompare = 1, Defs = [CPSR] in {3492 // shifted imm3493 def t2CMNri : T2OneRegCmpImm<3494 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,3495 "cmn", ".w\t$Rn, $imm",3496 [(set CPSR, (ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm)))]>,3497 Sched<[WriteCMP, ReadALU]> {3498 let Inst{31-27} = 0b11110;3499 let Inst{25} = 0;3500 let Inst{24-21} = 0b1000;3501 let Inst{20} = 1; // The S bit.3502 let Inst{15} = 0;3503 let Inst{11-8} = 0b1111; // Rd3504 }3505 // register3506 def t2CMNzrr : T2TwoRegCmp<3507 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,3508 "cmn", ".w\t$Rn, $Rm",3509 [(set CPSR, (BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>3510 GPRnopc:$Rn, rGPR:$Rm))]>,3511 Sched<[WriteCMP, ReadALU, ReadALU]> {3512 let Inst{31-27} = 0b11101;3513 let Inst{26-25} = 0b01;3514 let Inst{24-21} = 0b1000;3515 let Inst{20} = 1; // The S bit.3516 let Inst{14-12} = 0b000; // imm33517 let Inst{11-8} = 0b1111; // Rd3518 let Inst{7-6} = 0b00; // imm23519 let Inst{5-4} = 0b00; // type3520 }3521 // shifted register3522 def t2CMNzrs : T2OneRegCmpShiftedReg<3523 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,3524 "cmn", ".w\t$Rn, $ShiftedRm",3525 [(set CPSR, (BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>3526 GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,3527 Sched<[WriteCMPsi, ReadALU, ReadALU]> {3528 let Inst{31-27} = 0b11101;3529 let Inst{26-25} = 0b01;3530 let Inst{24-21} = 0b1000;3531 let Inst{20} = 1; // The S bit.3532 let Inst{11-8} = 0b1111; // Rd3533 }3534}3535 3536// Assembler aliases w/o the ".w" suffix.3537// No alias here for 'rr' version as not all instantiations of this multiclass3538// want one (CMP in particular, does not).3539def : t2InstAlias<"cmn${p} $Rn, $imm",3540 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;3541def : t2InstAlias<"cmn${p} $Rn, $shift",3542 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;3543 3544def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),3545 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;3546 3547def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),3548 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;3549 3550defm t2TST : T2I_cmp_irs<0b0000, "tst", rGPR,3551 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,3552 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;3553defm t2TEQ : T2I_cmp_irs<0b0100, "teq", rGPR,3554 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,3555 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;3556 3557// Conditional moves3558let hasSideEffects = 0 in {3559 3560let isCommutable = 1, isSelect = 1 in3561def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),3562 (ins rGPR:$false, rGPR:$Rm, pred:$p),3563 4, IIC_iCMOVr, []>,3564 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;3565 3566let isMoveImm = 1 in3567def t2MOVCCi3568 : t2PseudoInst<(outs rGPR:$Rd),3569 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),3570 4, IIC_iCMOVi, []>,3571 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;3572 3573let isCodeGenOnly = 1 in {3574let isMoveImm = 1 in3575def t2MOVCCi163576 : t2PseudoInst<(outs rGPR:$Rd),3577 (ins rGPR:$false, imm0_65535_expr:$imm, pred:$p),3578 4, IIC_iCMOVi, []>,3579 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;3580 3581let isMoveImm = 1 in3582def t2MVNCCi3583 : t2PseudoInst<(outs rGPR:$Rd),3584 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),3585 4, IIC_iCMOVi, []>,3586 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;3587 3588class MOVCCShPseudo3589 : t2PseudoInst<(outs rGPR:$Rd),3590 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, pred:$p),3591 4, IIC_iCMOVsi, []>,3592 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;3593 3594def t2MOVCClsl : MOVCCShPseudo;3595def t2MOVCClsr : MOVCCShPseudo;3596def t2MOVCCasr : MOVCCShPseudo;3597def t2MOVCCror : MOVCCShPseudo;3598 3599let isMoveImm = 1 in3600def t2MOVCCi32imm3601 : t2PseudoInst<(outs rGPR:$dst),3602 (ins rGPR:$false, i32imm:$src, pred:$p),3603 8, IIC_iCMOVix2, []>,3604 RegConstraint<"$false = $dst">;3605} // isCodeGenOnly = 13606 3607} // hasSideEffects3608 3609// The following patterns have to be defined out-of-line because the number3610// of instruction operands does not match the number of SDNode operands3611// (`pred` counts as one operand).3612 3613def : T2Pat<(ARMcmov i32:$false, i32:$Rm, imm:$cc, CPSR),3614 (t2MOVCCr $false, $Rm, imm:$cc, CPSR)>;3615 3616def : T2Pat<(ARMcmov i32:$false, t2_so_imm:$imm, imm:$cc, CPSR),3617 (t2MOVCCi $false, t2_so_imm:$imm, imm:$cc, CPSR)>;3618 3619def : T2Pat<(ARMcmov i32:$false, imm0_65535:$imm, imm:$cc, CPSR),3620 (t2MOVCCi16 $false, imm0_65535:$imm, imm:$cc, CPSR)>;3621 3622def : T2Pat<(ARMcmov i32:$false, t2_so_imm_not:$imm, imm:$cc, CPSR),3623 (t2MVNCCi $false, t2_so_imm_not:$imm, imm:$cc, CPSR)>;3624 3625def : T2Pat<(ARMcmov i32:$false, (shl i32:$Rm, imm0_31:$imm), imm:$cc, CPSR),3626 (t2MOVCClsl $false, $Rm, imm0_31:$imm, imm:$cc, CPSR)>;3627 3628def : T2Pat<(ARMcmov i32:$false, (srl i32:$Rm, imm_sr:$imm), imm:$cc, CPSR),3629 (t2MOVCClsr $false, $Rm, imm_sr:$imm, imm:$cc, CPSR)>;3630 3631def : T2Pat<(ARMcmov i32:$false, (sra i32:$Rm, imm_sr:$imm), imm:$cc, CPSR),3632 (t2MOVCCasr $false, $Rm, imm_sr:$imm, imm:$cc, CPSR)>;3633 3634def : T2Pat<(ARMcmov i32:$false, (rotr i32:$Rm, imm0_31:$imm), imm:$cc, CPSR),3635 (t2MOVCCror $false, $Rm, imm0_31:$imm, imm:$cc, CPSR)>;3636 3637def : T2Pat<(ARMcmov i32:$false, imm:$src, imm:$cc, CPSR),3638 (t2MOVCCi32imm $false, imm:$src, imm:$cc, CPSR)>;3639 3640//===----------------------------------------------------------------------===//3641// Atomic operations intrinsics3642//3643 3644// memory barriers protect the atomic sequences3645let hasSideEffects = 1 in {3646def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,3647 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,3648 Requires<[IsThumb, HasDB]> {3649 bits<4> opt;3650 let Inst{31-4} = 0xf3bf8f5;3651 let Inst{3-0} = opt;3652}3653 3654def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,3655 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,3656 Requires<[IsThumb, HasDB]> {3657 bits<4> opt;3658 let Inst{31-4} = 0xf3bf8f4;3659 let Inst{3-0} = opt;3660}3661 3662def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,3663 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,3664 Requires<[IsThumb, HasDB]> {3665 bits<4> opt;3666 let Inst{31-4} = 0xf3bf8f6;3667 let Inst{3-0} = opt;3668}3669 3670let hasNoSchedulingInfo = 1 in3671def t2TSB : T2I<(outs), (ins tsb_opt:$opt), NoItinerary,3672 "tsb", "\t$opt", []>, Requires<[IsThumb, HasV8_4a]> {3673 let Inst{31-0} = 0xf3af8012;3674 let DecoderMethod = "DecodeTSBInstruction";3675}3676}3677 3678// Armv8.5-A speculation barrier3679def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>,3680 Requires<[IsThumb2, HasSB]>, Sched<[]> {3681 let Inst{31-0} = 0xf3bf8f70;3682 let Unpredictable = 0x000f2f0f;3683 let hasSideEffects = 1;3684}3685 3686class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,3687 InstrItinClass itin, string opc, string asm, string cstr,3688 list<dag> pattern, bits<4> rt2 = 0b1111>3689 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {3690 let Inst{31-27} = 0b11101;3691 let Inst{26-20} = 0b0001101;3692 let Inst{11-8} = rt2;3693 let Inst{7-4} = opcod;3694 let Inst{3-0} = 0b1111;3695 3696 bits<4> addr;3697 bits<4> Rt;3698 let Inst{19-16} = addr;3699 let Inst{15-12} = Rt;3700}3701class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,3702 InstrItinClass itin, string opc, string asm, string cstr,3703 list<dag> pattern, bits<4> rt2 = 0b1111>3704 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {3705 let Inst{31-27} = 0b11101;3706 let Inst{26-20} = 0b0001100;3707 let Inst{11-8} = rt2;3708 let Inst{7-4} = opcod;3709 3710 bits<4> Rd;3711 bits<4> addr;3712 bits<4> Rt;3713 let Inst{3-0} = Rd;3714 let Inst{19-16} = addr;3715 let Inst{15-12} = Rt;3716}3717 3718let mayLoad = 1 in {3719def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),3720 AddrModeNone, 4, NoItinerary,3721 "ldrexb", "\t$Rt, $addr", "",3722 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>,3723 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>;3724def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),3725 AddrModeNone, 4, NoItinerary,3726 "ldrexh", "\t$Rt, $addr", "",3727 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>,3728 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>;3729def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),3730 AddrModeT2_ldrex, 4, NoItinerary,3731 "ldrex", "\t$Rt, $addr", "",3732 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>,3733 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]> {3734 bits<4> Rt;3735 bits<12> addr;3736 let Inst{31-27} = 0b11101;3737 let Inst{26-20} = 0b0000101;3738 let Inst{19-16} = addr{11-8};3739 let Inst{15-12} = Rt;3740 let Inst{11-8} = 0b1111;3741 let Inst{7-0} = addr{7-0};3742}3743let hasExtraDefRegAllocReq = 1 in3744def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),3745 (ins addr_offset_none:$addr),3746 AddrModeNone, 4, NoItinerary,3747 "ldrexd", "\t$Rt, $Rt2, $addr", "",3748 [], {?, ?, ?, ?}>,3749 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteLd]> {3750 bits<4> Rt2;3751 let Inst{11-8} = Rt2;3752}3753def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),3754 AddrModeNone, 4, NoItinerary,3755 "ldaexb", "\t$Rt, $addr", "",3756 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,3757 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>;3758def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),3759 AddrModeNone, 4, NoItinerary,3760 "ldaexh", "\t$Rt, $addr", "",3761 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,3762 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>;3763def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),3764 AddrModeNone, 4, NoItinerary,3765 "ldaex", "\t$Rt, $addr", "",3766 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,3767 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]> {3768 bits<4> Rt;3769 bits<4> addr;3770 let Inst{31-27} = 0b11101;3771 let Inst{26-20} = 0b0001101;3772 let Inst{19-16} = addr;3773 let Inst{15-12} = Rt;3774 let Inst{11-8} = 0b1111;3775 let Inst{7-0} = 0b11101111;3776}3777let hasExtraDefRegAllocReq = 1 in3778def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),3779 (ins addr_offset_none:$addr),3780 AddrModeNone, 4, NoItinerary,3781 "ldaexd", "\t$Rt, $Rt2, $addr", "",3782 [], {?, ?, ?, ?}>, Requires<[IsThumb,3783 HasAcquireRelease, HasV7Clrex, IsNotMClass]>, Sched<[WriteLd]> {3784 bits<4> Rt2;3785 let Inst{11-8} = Rt2;3786 3787 let Inst{7} = 1;3788}3789}3790 3791let mayStore = 1, Constraints = "@earlyclobber $Rd" in {3792def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),3793 (ins rGPR:$Rt, addr_offset_none:$addr),3794 AddrModeNone, 4, NoItinerary,3795 "strexb", "\t$Rd, $Rt, $addr", "",3796 [(set rGPR:$Rd,3797 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>,3798 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>;3799def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),3800 (ins rGPR:$Rt, addr_offset_none:$addr),3801 AddrModeNone, 4, NoItinerary,3802 "strexh", "\t$Rd, $Rt, $addr", "",3803 [(set rGPR:$Rd,3804 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>,3805 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>;3806 3807def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,3808 t2addrmode_imm0_1020s4:$addr),3809 AddrModeT2_ldrex, 4, NoItinerary,3810 "strex", "\t$Rd, $Rt, $addr", "",3811 [(set rGPR:$Rd,3812 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>,3813 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]> {3814 bits<4> Rd;3815 bits<4> Rt;3816 bits<12> addr;3817 let Inst{31-27} = 0b11101;3818 let Inst{26-20} = 0b0000100;3819 let Inst{19-16} = addr{11-8};3820 let Inst{15-12} = Rt;3821 let Inst{11-8} = Rd;3822 let Inst{7-0} = addr{7-0};3823}3824let hasExtraSrcRegAllocReq = 1 in3825def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),3826 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),3827 AddrModeNone, 4, NoItinerary,3828 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],3829 {?, ?, ?, ?}>,3830 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteST]> {3831 bits<4> Rt2;3832 let Inst{11-8} = Rt2;3833}3834def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),3835 (ins rGPR:$Rt, addr_offset_none:$addr),3836 AddrModeNone, 4, NoItinerary,3837 "stlexb", "\t$Rd, $Rt, $addr", "",3838 [(set rGPR:$Rd,3839 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,3840 Requires<[IsThumb, HasAcquireRelease,3841 HasV7Clrex]>, Sched<[WriteST]>;3842 3843def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),3844 (ins rGPR:$Rt, addr_offset_none:$addr),3845 AddrModeNone, 4, NoItinerary,3846 "stlexh", "\t$Rd, $Rt, $addr", "",3847 [(set rGPR:$Rd,3848 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,3849 Requires<[IsThumb, HasAcquireRelease,3850 HasV7Clrex]>, Sched<[WriteST]>;3851 3852def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,3853 addr_offset_none:$addr),3854 AddrModeNone, 4, NoItinerary,3855 "stlex", "\t$Rd, $Rt, $addr", "",3856 [(set rGPR:$Rd,3857 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,3858 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>,3859 Sched<[WriteST]> {3860 bits<4> Rd;3861 bits<4> Rt;3862 bits<4> addr;3863 let Inst{31-27} = 0b11101;3864 let Inst{26-20} = 0b0001100;3865 let Inst{19-16} = addr;3866 let Inst{15-12} = Rt;3867 let Inst{11-4} = 0b11111110;3868 let Inst{3-0} = Rd;3869}3870let hasExtraSrcRegAllocReq = 1 in3871def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),3872 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),3873 AddrModeNone, 4, NoItinerary,3874 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],3875 {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease,3876 HasV7Clrex, IsNotMClass]>, Sched<[WriteST]> {3877 bits<4> Rt2;3878 let Inst{11-8} = Rt2;3879}3880}3881 3882def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,3883 Requires<[IsThumb, HasV7Clrex]> {3884 let Inst{31-16} = 0xf3bf;3885 let Inst{15-14} = 0b10;3886 let Inst{13} = 0;3887 let Inst{12} = 0;3888 let Inst{11-8} = 0b1111;3889 let Inst{7-4} = 0b0010;3890 let Inst{3-0} = 0b1111;3891}3892 3893def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),3894 (t2LDREXB addr_offset_none:$addr)>,3895 Requires<[IsThumb, HasV8MBaseline]>;3896def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),3897 (t2LDREXH addr_offset_none:$addr)>,3898 Requires<[IsThumb, HasV8MBaseline]>;3899def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),3900 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>,3901 Requires<[IsThumb, HasV8MBaseline]>;3902def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),3903 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>,3904 Requires<[IsThumb, HasV8MBaseline]>;3905 3906def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),3907 (t2LDAEXB addr_offset_none:$addr)>,3908 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;3909def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),3910 (t2LDAEXH addr_offset_none:$addr)>,3911 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;3912def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),3913 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>,3914 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;3915def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),3916 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>,3917 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;3918 3919//===----------------------------------------------------------------------===//3920// SJLJ Exception handling intrinsics3921// eh_sjlj_setjmp() is an instruction sequence to store the return3922// address and save #0 in R0 for the non-longjmp case.3923// Since by its nature we may be coming from some other function to get3924// here, and we're using the stack frame for the containing function to3925// save/restore registers, we can't keep anything live in regs across3926// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon3927// when we get here from a longjmp(). We force everything out of registers3928// except for our own input by listing the relevant registers in Defs. By3929// doing so, we also cause the prologue/epilogue code to actively preserve3930// all of the callee-saved registers, which is exactly what we want.3931// $val is a scratch register for our use.3932// This gets lowered to an instruction sequence of 12 bytes3933let Defs =3934 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,3935 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],3936 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, Size = 12,3937 usesCustomInserter = 1 in {3938 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),3939 AddrModeNone, 0, NoItinerary, "", "",3940 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,3941 Requires<[IsThumb2, HasVFP2]>;3942}3943 3944// This gets lowered to an instruction sequence of 12 bytes3945let Defs =3946 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],3947 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, Size = 12,3948 usesCustomInserter = 1 in {3949 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),3950 AddrModeNone, 0, NoItinerary, "", "",3951 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,3952 Requires<[IsThumb2, NoVFP]>;3953}3954 3955 3956//===----------------------------------------------------------------------===//3957// Control-Flow Instructions3958//3959 3960// FIXME: remove when we have a way to marking a MI with these properties.3961// FIXME: Should pc be an implicit operand like PICADD, etc?3962let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,3963 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in3964def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,3965 reglist:$regs, variable_ops),3966 4, IIC_iLoad_mBr, [],3967 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,3968 RegConstraint<"$Rn = $wb">;3969 3970let isBranch = 1, isTerminator = 1, isBarrier = 1 in {3971let isPredicable = 1 in3972def t2B : T2I<(outs), (ins thumb_br_target:$target), IIC_Br,3973 "b", ".w\t$target",3974 [(br bb:$target)]>, Sched<[WriteBr]>,3975 Requires<[IsThumb, HasV8MBaseline]> {3976 let Inst{31-27} = 0b11110;3977 let Inst{15-14} = 0b10;3978 let Inst{12} = 1;3979 3980 bits<24> target;3981 let Inst{26} = target{23};3982 let Inst{13} = target{22};3983 let Inst{11} = target{21};3984 let Inst{25-16} = target{20-11};3985 let Inst{10-0} = target{10-0};3986 let DecoderMethod = "DecodeT2BInstruction";3987 let AsmMatchConverter = "cvtThumbBranches";3988}3989 3990let Size = 4, isNotDuplicable = 1, isBranch = 1, isTerminator = 1,3991 isBarrier = 1, isIndirectBranch = 1 in {3992 3993// available in both v8-M.Baseline and Thumb2 targets3994def t2BR_JT : t2basePseudoInst<(outs),3995 (ins GPR:$target, GPR:$index, i32imm:$jt),3996 0, IIC_Br,3997 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>,3998 Sched<[WriteBr]>;3999 4000// FIXME: Add a case that can be predicated.4001def t2TBB_JT : t2PseudoInst<(outs),4002 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,4003 Sched<[WriteBr]>;4004 4005def t2TBH_JT : t2PseudoInst<(outs),4006 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,4007 Sched<[WriteBr]>;4008 4009def t2TBB : T2I<(outs), (ins (addrmode_tbb $Rn, $Rm):$addr), IIC_Br,4010 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {4011 bits<4> Rn;4012 bits<4> Rm;4013 let Inst{31-20} = 0b111010001101;4014 let Inst{19-16} = Rn;4015 let Inst{15-5} = 0b11110000000;4016 let Inst{4} = 0; // B form4017 let Inst{3-0} = Rm;4018 4019 let DecoderMethod = "DecodeThumbTableBranch";4020}4021 4022def t2TBH : T2I<(outs), (ins (addrmode_tbh $Rn, $Rm):$addr), IIC_Br,4023 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {4024 bits<4> Rn;4025 bits<4> Rm;4026 let Inst{31-20} = 0b111010001101;4027 let Inst{19-16} = Rn;4028 let Inst{15-5} = 0b11110000000;4029 let Inst{4} = 1; // H form4030 let Inst{3-0} = Rm;4031 4032 let DecoderMethod = "DecodeThumbTableBranch";4033}4034} // isNotDuplicable, isIndirectBranch4035 4036} // isBranch, isTerminator, isBarrier4037 4038// FIXME: should be able to write a pattern for ARMBrcond, but can't use4039// a two-value operand where a dag node expects ", "two operands. :(4040let isBranch = 1, isTerminator = 1 in4041def t2Bcc : Thumb2XI<(outs), (ins brtarget:$target, pred:$p),4042 AddrModeNone, 4, IIC_Br,4043 "b${p}.w\t$target", "",4044 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,4045 Sched<[WriteBr]> {4046 let Inst{31-27} = 0b11110;4047 let Inst{15-14} = 0b10;4048 let Inst{12} = 0;4049 4050 bits<4> p;4051 let Inst{25-22} = p;4052 4053 bits<21> target;4054 let Inst{26} = target{20};4055 let Inst{11} = target{19};4056 let Inst{13} = target{18};4057 let Inst{21-16} = target{17-12};4058 let Inst{10-0} = target{11-1};4059 4060 let DecoderMethod = "DecodeThumb2BCCInstruction";4061 let AsmMatchConverter = "cvtThumbBranches";4062}4063 4064// Tail calls. The MachO version of thumb tail calls uses a t2 branch, so4065// it goes here.4066// Windows SEH unwinding also needs a strict t2 branch for tail calls.4067let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {4068 // IOS version.4069 let Uses = [SP] in4070 def tTAILJMPd: tPseudoExpand<(outs),4071 (ins thumb_br_target:$dst, pred:$p),4072 4, IIC_Br, [],4073 (t2B thumb_br_target:$dst, pred:$p)>,4074 Requires<[IsThumb2]>, Sched<[WriteBr]>;4075}4076 4077// IT block4078let Defs = [ITSTATE] in4079def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),4080 AddrModeNone, 2, IIC_iALUx,4081 "it$mask\t$cc", "", []> {4082 // 16-bit instruction.4083 let Inst{31-16} = 0x0000;4084 let Inst{15-8} = 0b10111111;4085 4086 bits<4> cc;4087 bits<4> mask;4088 let Inst{7-4} = cc;4089 let Inst{3-0} = mask;4090 4091 let DecoderMethod = "DecodeIT";4092}4093 4094// Branch and Exchange Jazelle -- for disassembly only4095// Rm = Inst{19-16}4096let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in4097def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,4098 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {4099 bits<4> func;4100 let Inst{31-27} = 0b11110;4101 let Inst{26} = 0;4102 let Inst{25-20} = 0b111100;4103 let Inst{19-16} = func;4104 let Inst{15-0} = 0b1000111100000000;4105}4106 4107def : t2InstAlias<"bl${p}.w $func", (tBL pred:$p, thumb_bl_target:$func), 0>;4108 4109// Compare and branch on zero / non-zero4110let isBranch = 1, isTerminator = 1 in {4111 def tCBZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,4112 "cbz\t$Rn, $target", []>,4113 T1Misc<{0,0,?,1,?,?,?}>,4114 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {4115 // A8.6.274116 bits<6> target;4117 bits<3> Rn;4118 let Inst{9} = target{5};4119 let Inst{7-3} = target{4-0};4120 let Inst{2-0} = Rn;4121 }4122 4123 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,4124 "cbnz\t$Rn, $target", []>,4125 T1Misc<{1,0,?,1,?,?,?}>,4126 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {4127 // A8.6.274128 bits<6> target;4129 bits<3> Rn;4130 let Inst{9} = target{5};4131 let Inst{7-3} = target{4-0};4132 let Inst{2-0} = Rn;4133 }4134}4135 4136 4137// Change Processor State is a system instruction.4138// FIXME: Since the asm parser has currently no clean way to handle optional4139// operands, create 3 versions of the same instruction. Once there's a clean4140// framework to represent optional operands, change this behavior.4141class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,4142 !strconcat("cps", asm_op), []>,4143 Requires<[IsThumb2, IsNotMClass]> {4144 bits<2> imod;4145 bits<3> iflags;4146 bits<5> mode;4147 bit M;4148 4149 let Inst{31-11} = 0b111100111010111110000;4150 let Inst{10-9} = imod;4151 let Inst{8} = M;4152 let Inst{7-5} = iflags;4153 let Inst{4-0} = mode;4154 let DecoderMethod = "DecodeT2CPSInstruction";4155}4156 4157let M = 1 in4158 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),4159 "$imod\t$iflags, $mode">;4160let mode = 0, M = 0 in4161 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),4162 "$imod.w\t$iflags">;4163let imod = 0, iflags = 0, M = 1 in4164 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;4165 4166def : t2InstAlias<"cps$imod.w $iflags, $mode",4167 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;4168def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;4169 4170// A6.3.4 Branches and miscellaneous control4171// Table A6-14 Change Processor State, and hint instructions4172def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",4173 [(int_arm_hint imm0_239:$imm)]> {4174 bits<8> imm;4175 let Inst{31-3} = 0b11110011101011111000000000000;4176 let Inst{7-0} = imm;4177 4178 let DecoderMethod = "DecodeT2HintSpaceInstruction";4179}4180 4181def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;4182def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;4183def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;4184def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;4185def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;4186def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;4187def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {4188 let Predicates = [IsThumb2, HasV8];4189}4190def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {4191 let Predicates = [IsThumb2, HasRAS];4192}4193def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {4194 let Predicates = [IsThumb2, HasRAS];4195}4196def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;4197def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>;4198 4199def : t2InstAlias<"pacbti$p r12,lr,sp", (t2HINT 13, pred:$p), 1>;4200def : t2InstAlias<"bti$p", (t2HINT 15, pred:$p), 1>;4201def : t2InstAlias<"pac$p r12,lr,sp", (t2HINT 29, pred:$p), 1>;4202def : t2InstAlias<"aut$p r12,lr,sp", (t2HINT 45, pred:$p), 1>;4203 4204// Clear BHB instruction4205def : InstAlias<"clrbhb$p", (t2HINT 22, pred:$p), 0>, Requires<[IsThumb2, HasV8]>;4206def : InstAlias<"clrbhb$p", (t2HINT 22, pred:$p), 1>, Requires<[IsThumb2, HasV8, HasCLRBHB]>;4207 4208def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",4209 [(int_arm_dbg imm0_15:$opt)]> {4210 bits<4> opt;4211 let Inst{31-20} = 0b111100111010;4212 let Inst{19-16} = 0b1111;4213 let Inst{15-8} = 0b10000000;4214 let Inst{7-4} = 0b1111;4215 let Inst{3-0} = opt;4216}4217def : t2InstAlias<"dbg${p}.w $opt", (t2DBG imm0_15:$opt, pred:$p), 0>;4218 4219// Secure Monitor Call is a system instruction.4220// Option = Inst{19-16}4221let isCall = 1, Uses = [SP] in4222def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",4223 []>, Requires<[IsThumb2, HasTrustZone]> {4224 let Inst{31-27} = 0b11110;4225 let Inst{26-20} = 0b1111111;4226 let Inst{15-12} = 0b1000;4227 4228 bits<4> opt;4229 let Inst{19-16} = opt;4230}4231 4232class T2DCPS<bits<2> opt, string opc>4233 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {4234 let Inst{31-27} = 0b11110;4235 let Inst{26-20} = 0b1111000;4236 let Inst{19-16} = 0b1111;4237 let Inst{15-12} = 0b1000;4238 let Inst{11-2} = 0b0000000000;4239 let Inst{1-0} = opt;4240}4241 4242def t2DCPS1 : T2DCPS<0b01, "dcps1">;4243def t2DCPS2 : T2DCPS<0b10, "dcps2">;4244def t2DCPS3 : T2DCPS<0b11, "dcps3">;4245 4246class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,4247 string opc, string asm, list<dag> pattern>4248 : T2I<oops, iops, itin, opc, asm, pattern>,4249 Requires<[IsThumb2,IsNotMClass]> {4250 bits<5> mode;4251 let Inst{31-25} = 0b1110100;4252 let Inst{24-23} = Op;4253 let Inst{22} = 0;4254 let Inst{21} = W;4255 let Inst{20-16} = 0b01101;4256 let Inst{15-5} = 0b11000000000;4257 let Inst{4-0} = mode{4-0};4258}4259 4260// Store Return State is a system instruction.4261def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,4262 "srsdb", "\tsp!, $mode", []>;4263def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,4264 "srsdb","\tsp, $mode", []>;4265def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,4266 "srsia","\tsp!, $mode", []>;4267def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,4268 "srsia","\tsp, $mode", []>;4269 4270 4271def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;4272def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;4273 4274def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;4275def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;4276 4277// Return From Exception is a system instruction.4278let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in4279class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,4280 string opc, string asm, list<dag> pattern>4281 : T2I<oops, iops, itin, opc, asm, pattern>,4282 Requires<[IsThumb2,IsNotMClass]> {4283 let Inst{31-20} = op31_20{11-0};4284 4285 bits<4> Rn;4286 let Inst{19-16} = Rn;4287 let Inst{15-0} = 0xc000;4288}4289 4290def t2RFEDBW : T2RFE<0b111010000011,4291 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",4292 [/* For disassembly only; pattern left blank */]>;4293def t2RFEDB : T2RFE<0b111010000001,4294 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",4295 [/* For disassembly only; pattern left blank */]>;4296def t2RFEIAW : T2RFE<0b111010011011,4297 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",4298 [/* For disassembly only; pattern left blank */]>;4299def t2RFEIA : T2RFE<0b111010011001,4300 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",4301 [/* For disassembly only; pattern left blank */]>;4302 4303// B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.4304// Exception return instruction is "subs pc, lr, #imm".4305let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in4306def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,4307 "subs", "\tpc, lr, $imm",4308 [(ARMintretglue imm0_255:$imm)]>,4309 Requires<[IsThumb2,IsNotMClass]> {4310 let Inst{31-8} = 0b111100111101111010001111;4311 4312 bits<8> imm;4313 let Inst{7-0} = imm;4314}4315 4316// B9.3.19 SUBS PC, LR (Thumb)4317// In the Thumb instruction set, MOVS{<c>}{<q>} PC, LR is a pseudo-instruction4318// for SUBS{<c>}{<q>} PC, LR, #0.4319def : t2InstAlias<"movs${p}\tpc, lr", (t2SUBS_PC_LR 0, pred:$p)>;4320def : t2InstAlias<"movs${p}.w\tpc, lr", (t2SUBS_PC_LR 0, pred:$p)>;4321 4322// ERET - Return from exception in Hypervisor mode.4323// B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that4324// includes virtualization extensions.4325def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,4326 Requires<[IsThumb2, HasVirtualization]>;4327 4328// Hypervisor Call is a system instruction.4329let isCall = 1 in {4330def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>,4331 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {4332 bits<16> imm16;4333 let Inst{31-20} = 0b111101111110;4334 let Inst{19-16} = imm16{15-12};4335 let Inst{15-12} = 0b1000;4336 let Inst{11-0} = imm16{11-0};4337}4338}4339 4340// Alias for HVC without the ".w" optional width specifier4341def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;4342 4343//===----------------------------------------------------------------------===//4344// Non-Instruction Patterns4345//4346 4347// 32-bit immediate using movw + movt.4348// This is a single pseudo instruction to make it re-materializable.4349// FIXME: Remove this when we can do generalized remat.4350let isReMaterializable = 1, isMoveImm = 1, Size = 8 in4351def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,4352 [(set rGPR:$dst, (i32 imm:$src))]>,4353 Requires<[IsThumb, UseMovt]>;4354 4355// Pseudo instruction that combines movw + movt + add pc (if pic).4356// It also makes it possible to rematerialize the instructions.4357// FIXME: Remove this when we can do generalized remat and when machine licm4358// can properly the instructions.4359let isReMaterializable = 1 in {4360def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),4361 IIC_iMOVix2addpc,4362 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,4363 Requires<[IsThumb, HasV8MBaseline, UseMovtInPic]>;4364 4365}4366 4367def : T2Pat<(ARMWrapperPIC tglobaltlsaddr :$dst),4368 (t2MOV_ga_pcrel tglobaltlsaddr:$dst)>,4369 Requires<[IsThumb2, UseMovtInPic]>;4370def : T2Pat<(ARMWrapper tglobaltlsaddr:$dst),4371 (t2MOVi32imm tglobaltlsaddr:$dst)>,4372 Requires<[IsThumb2, UseMovt]>;4373 4374// ConstantPool, GlobalAddress, and JumpTable4375def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;4376def : T2Pat<(ARMWrapper texternalsym :$dst), (t2MOVi32imm texternalsym :$dst)>,4377 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;4378def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,4379 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;4380 4381def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>;4382 4383let hasNoSchedulingInfo = 1 in {4384def t2LDRLIT_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),4385 IIC_iLoadiALU,4386 [(set rGPR:$dst,4387 (ARMWrapperPIC tglobaladdr:$addr))]>,4388 Requires<[IsThumb, HasV8MBaseline, DontUseMovtInPic]>;4389}4390 4391// TLS globals4392def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),4393 (t2LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,4394 Requires<[IsThumb, HasV8MBaseline, DontUseMovtInPic]>;4395 4396// Pseudo instruction that combines ldr from constpool and add pc. This should4397// be expanded into two instructions late to allow if-conversion and4398// scheduling.4399let canFoldAsLoad = 1, isReMaterializable = 1 in4400def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),4401 IIC_iLoadiALU,4402 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),4403 imm:$cp))]>,4404 Requires<[IsThumb2]>;4405 4406//===----------------------------------------------------------------------===//4407// Coprocessor load/store -- for disassembly only4408//4409class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm,4410 list<dag> pattern, AddrMode am = AddrModeNone>4411 : T2I<oops, iops, NoItinerary, opc, asm, pattern, am> {4412 let Inst{31-28} = op31_28;4413 let Inst{27-25} = 0b110;4414}4415 4416multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag> pattern> {4417 def _OFFSET : T2CI<op31_28,4418 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),4419 asm, "\t$cop, $CRd, $addr", pattern, AddrMode5> {4420 bits<13> addr;4421 bits<4> cop;4422 bits<4> CRd;4423 let Inst{24} = 1; // P = 14424 let Inst{23} = addr{8};4425 let Inst{22} = Dbit;4426 let Inst{21} = 0; // W = 04427 let Inst{20} = load;4428 let Inst{19-16} = addr{12-9};4429 let Inst{15-12} = CRd;4430 let Inst{11-8} = cop;4431 let Inst{7-0} = addr{7-0};4432 let DecoderMethod = "DecodeCopMemInstruction";4433 }4434 def _PRE : T2CI<op31_28,4435 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),4436 asm, "\t$cop, $CRd, $addr!", []> {4437 bits<13> addr;4438 bits<4> cop;4439 bits<4> CRd;4440 let Inst{24} = 1; // P = 14441 let Inst{23} = addr{8};4442 let Inst{22} = Dbit;4443 let Inst{21} = 1; // W = 14444 let Inst{20} = load;4445 let Inst{19-16} = addr{12-9};4446 let Inst{15-12} = CRd;4447 let Inst{11-8} = cop;4448 let Inst{7-0} = addr{7-0};4449 let DecoderMethod = "DecodeCopMemInstruction";4450 }4451 def _POST: T2CI<op31_28,4452 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,4453 postidx_imm8s4:$offset),4454 asm, "\t$cop, $CRd, $addr, $offset", []> {4455 bits<9> offset;4456 bits<4> addr;4457 bits<4> cop;4458 bits<4> CRd;4459 let Inst{24} = 0; // P = 04460 let Inst{23} = offset{8};4461 let Inst{22} = Dbit;4462 let Inst{21} = 1; // W = 14463 let Inst{20} = load;4464 let Inst{19-16} = addr;4465 let Inst{15-12} = CRd;4466 let Inst{11-8} = cop;4467 let Inst{7-0} = offset{7-0};4468 let DecoderMethod = "DecodeCopMemInstruction";4469 }4470 def _OPTION : T2CI<op31_28, (outs),4471 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,4472 coproc_option_imm:$option),4473 asm, "\t$cop, $CRd, $addr, $option", []> {4474 bits<8> option;4475 bits<4> addr;4476 bits<4> cop;4477 bits<4> CRd;4478 let Inst{24} = 0; // P = 04479 let Inst{23} = 1; // U = 14480 let Inst{22} = Dbit;4481 let Inst{21} = 0; // W = 04482 let Inst{20} = load;4483 let Inst{19-16} = addr;4484 let Inst{15-12} = CRd;4485 let Inst{11-8} = cop;4486 let Inst{7-0} = option;4487 let DecoderMethod = "DecodeCopMemInstruction";4488 }4489}4490 4491let DecoderNamespace = "Thumb2CoProc" in {4492let mayLoad = 1 in {4493defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]>;4494defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;4495defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;4496defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;4497}4498let mayStore = 1 in {4499defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]>;4500defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>;4501defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;4502defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;4503}4504}4505 4506 4507//===----------------------------------------------------------------------===//4508// Move between special register and ARM core register -- for disassembly only4509//4510// Move to ARM core register from Special Register4511 4512// A/R class MRS.4513//4514// A/R class can only move from CPSR or SPSR.4515def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",4516 []>, Requires<[IsThumb2,IsNotMClass]> {4517 bits<4> Rd;4518 let Inst{31-12} = 0b11110011111011111000;4519 let Inst{11-8} = Rd;4520 let Inst{7-0} = 0b00000000;4521}4522 4523def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;4524 4525def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",4526 []>, Requires<[IsThumb2,IsNotMClass]> {4527 bits<4> Rd;4528 let Inst{31-12} = 0b11110011111111111000;4529 let Inst{11-8} = Rd;4530 let Inst{7-0} = 0b00000000;4531}4532 4533def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),4534 NoItinerary, "mrs", "\t$Rd, $banked", []>,4535 Requires<[IsThumb, HasVirtualization]> {4536 bits<6> banked;4537 bits<4> Rd;4538 4539 let Inst{31-21} = 0b11110011111;4540 let Inst{20} = banked{5}; // R bit4541 let Inst{19-16} = banked{3-0};4542 let Inst{15-12} = 0b1000;4543 let Inst{11-8} = Rd;4544 let Inst{7-5} = 0b001;4545 let Inst{4} = banked{4};4546 let Inst{3-0} = 0b0000;4547}4548 4549 4550// M class MRS.4551//4552// This MRS has a mask field in bits 7-0 and can take more values than4553// the A/R class (a full msr_mask).4554def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,4555 "mrs", "\t$Rd, $SYSm", []>,4556 Requires<[IsThumb,IsMClass]> {4557 bits<4> Rd;4558 bits<8> SYSm;4559 let Inst{31-12} = 0b11110011111011111000;4560 let Inst{11-8} = Rd;4561 let Inst{7-0} = SYSm;4562 4563 let Unpredictable{20-16} = 0b11111;4564 let Unpredictable{13} = 0b1;4565}4566 4567 4568// Move from ARM core register to Special Register4569//4570// A/R class MSR.4571//4572// No need to have both system and application versions, the encodings are the4573// same and the assembly parser has no way to distinguish between them. The mask4574// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains4575// the mask with the fields to be accessed in the special register.4576let Defs = [CPSR] in4577def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),4578 NoItinerary, "msr", "\t$mask, $Rn", []>,4579 Requires<[IsThumb2,IsNotMClass]> {4580 bits<5> mask;4581 bits<4> Rn;4582 let Inst{31-21} = 0b11110011100;4583 let Inst{20} = mask{4}; // R Bit4584 let Inst{19-16} = Rn;4585 let Inst{15-12} = 0b1000;4586 let Inst{11-8} = mask{3-0};4587 let Inst{7-0} = 0;4588}4589 4590// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a4591// separate encoding (distinguished by bit 5.4592def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn),4593 NoItinerary, "msr", "\t$banked, $Rn", []>,4594 Requires<[IsThumb, HasVirtualization]> {4595 bits<6> banked;4596 bits<4> Rn;4597 4598 let Inst{31-21} = 0b11110011100;4599 let Inst{20} = banked{5}; // R bit4600 let Inst{19-16} = Rn;4601 let Inst{15-12} = 0b1000;4602 let Inst{11-8} = banked{3-0};4603 let Inst{7-5} = 0b001;4604 let Inst{4} = banked{4};4605 let Inst{3-0} = 0b0000;4606}4607 4608 4609// M class MSR.4610//4611// Move from ARM core register to Special Register4612let Defs = [CPSR] in4613def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),4614 NoItinerary, "msr", "\t$SYSm, $Rn", []>,4615 Requires<[IsThumb,IsMClass]> {4616 bits<12> SYSm;4617 bits<4> Rn;4618 let Inst{31-21} = 0b11110011100;4619 let Inst{20} = 0b0;4620 let Inst{19-16} = Rn;4621 let Inst{15-12} = 0b1000;4622 let Inst{11-10} = SYSm{11-10};4623 let Inst{9-8} = 0b00;4624 let Inst{7-0} = SYSm{7-0};4625 4626 let Unpredictable{20} = 0b1;4627 let Unpredictable{13} = 0b1;4628 let Unpredictable{9-8} = 0b11;4629}4630 4631 4632//===----------------------------------------------------------------------===//4633// Move between coprocessor and ARM core register4634//4635 4636class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,4637 list<dag> pattern>4638 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",4639 pattern> {4640 let Inst{27-24} = 0b1110;4641 let Inst{20} = direction;4642 let Inst{4} = 1;4643 4644 bits<4> Rt;4645 bits<4> cop;4646 bits<3> opc1;4647 bits<3> opc2;4648 bits<4> CRm;4649 bits<4> CRn;4650 4651 let Inst{15-12} = Rt;4652 let Inst{11-8} = cop;4653 let Inst{23-21} = opc1;4654 let Inst{7-5} = opc2;4655 let Inst{3-0} = CRm;4656 let Inst{19-16} = CRn;4657 4658 let DecoderNamespace = "Thumb2CoProc";4659}4660 4661class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,4662 list<dag> pattern = []>4663 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {4664 let Inst{27-24} = 0b1100;4665 let Inst{23-21} = 0b010;4666 let Inst{20} = direction;4667 4668 bits<4> Rt;4669 bits<4> Rt2;4670 bits<4> cop;4671 bits<4> opc1;4672 bits<4> CRm;4673 4674 let Inst{15-12} = Rt;4675 let Inst{19-16} = Rt2;4676 let Inst{11-8} = cop;4677 let Inst{7-4} = opc1;4678 let Inst{3-0} = CRm;4679 4680 let DecoderNamespace = "Thumb2CoProc";4681}4682 4683/* from ARM core register to coprocessor */4684def t2MCR : t2MovRCopro<0b1110, "mcr", 0,4685 (outs),4686 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,4687 c_imm:$CRm, imm0_7:$opc2),4688 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,4689 timm:$CRm, timm:$opc2)]>,4690 ComplexDeprecationPredicate<"MCR">;4691def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",4692 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,4693 c_imm:$CRm, 0, pred:$p)>;4694def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,4695 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,4696 c_imm:$CRm, imm0_7:$opc2),4697 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,4698 timm:$CRm, timm:$opc2)]> {4699 let Predicates = [IsThumb2, PreV8];4700}4701def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",4702 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,4703 c_imm:$CRm, 0, pred:$p)>;4704 4705/* from coprocessor to ARM core register */4706def t2MRC : t2MovRCopro<0b1110, "mrc", 1,4707 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,4708 c_imm:$CRm, imm0_7:$opc2), []>;4709def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",4710 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,4711 c_imm:$CRm, 0, pred:$p)>;4712 4713def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,4714 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,4715 c_imm:$CRm, imm0_7:$opc2), []> {4716 let Predicates = [IsThumb2, PreV8];4717}4718def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",4719 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,4720 c_imm:$CRm, 0, pred:$p)>;4721 4722def : T2v6Pat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2),4723 (t2MRC p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>;4724 4725def : T2v6Pat<(int_arm_mrc2 timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2),4726 (t2MRC2 p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>;4727 4728 4729/* from ARM core register to coprocessor */4730def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs),4731 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,4732 c_imm:$CRm),4733 [(int_arm_mcrr timm:$cop, timm:$opc1, GPR:$Rt, GPR:$Rt2,4734 timm:$CRm)]>;4735def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs),4736 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,4737 c_imm:$CRm),4738 [(int_arm_mcrr2 timm:$cop, timm:$opc1, GPR:$Rt,4739 GPR:$Rt2, timm:$CRm)]> {4740 let Predicates = [IsThumb2, PreV8];4741}4742 4743/* from coprocessor to ARM core register */4744def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),4745 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)>;4746 4747def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),4748 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)> {4749 let Predicates = [IsThumb2, PreV8];4750}4751 4752//===----------------------------------------------------------------------===//4753// Other Coprocessor Instructions.4754//4755 4756def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,4757 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),4758 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",4759 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn,4760 timm:$CRm, timm:$opc2)]> {4761 let Inst{27-24} = 0b1110;4762 4763 bits<4> opc1;4764 bits<4> CRn;4765 bits<4> CRd;4766 bits<4> cop;4767 bits<3> opc2;4768 bits<4> CRm;4769 4770 let Inst{3-0} = CRm;4771 let Inst{4} = 0;4772 let Inst{7-5} = opc2;4773 let Inst{11-8} = cop;4774 let Inst{15-12} = CRd;4775 let Inst{19-16} = CRn;4776 let Inst{23-20} = opc1;4777 4778 let Predicates = [IsThumb2, PreV8];4779 let DecoderNamespace = "Thumb2CoProc";4780}4781 4782def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,4783 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),4784 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",4785 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn,4786 timm:$CRm, timm:$opc2)]> {4787 let Inst{27-24} = 0b1110;4788 4789 bits<4> opc1;4790 bits<4> CRn;4791 bits<4> CRd;4792 bits<4> cop;4793 bits<3> opc2;4794 bits<4> CRm;4795 4796 let Inst{3-0} = CRm;4797 let Inst{4} = 0;4798 let Inst{7-5} = opc2;4799 let Inst{11-8} = cop;4800 let Inst{15-12} = CRd;4801 let Inst{19-16} = CRn;4802 let Inst{23-20} = opc1;4803 4804 let Predicates = [IsThumb2, PreV8];4805 let DecoderNamespace = "Thumb2CoProc";4806}4807 4808 4809// Reading thread pointer from coprocessor register4810def : T2Pat<(ARMthread_pointer), (t2MRC 15, 0, 13, 0, 2)>,4811 Requires<[IsThumb2, IsReadTPTPIDRURW]>;4812def : T2Pat<(ARMthread_pointer), (t2MRC 15, 0, 13, 0, 3)>,4813 Requires<[IsThumb2, IsReadTPTPIDRURO]>;4814def : T2Pat<(ARMthread_pointer), (t2MRC 15, 0, 13, 0, 4)>,4815 Requires<[IsThumb2, IsReadTPTPIDRPRW]>;4816 4817//===----------------------------------------------------------------------===//4818// ARMv8.1 Privilege Access Never extension4819//4820// SETPAN #imm14821 4822def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,4823 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {4824 bits<1> imm;4825 4826 let Inst{4} = 0b1;4827 let Inst{3} = imm;4828 let Inst{2-0} = 0b000;4829 4830 let Unpredictable{4} = 0b1;4831 let Unpredictable{2-0} = 0b111;4832}4833 4834//===----------------------------------------------------------------------===//4835// ARMv8-M Security Extensions instructions4836//4837 4838let hasSideEffects = 1 in4839def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>,4840 Requires<[Has8MSecExt]> {4841 let Inst = 0xe97fe97f;4842}4843 4844class T2TT<bits<2> at, string asm, list<dag> pattern>4845 : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn",4846 pattern> {4847 bits<4> Rn;4848 bits<4> Rt;4849 4850 let Inst{31-20} = 0b111010000100;4851 let Inst{19-16} = Rn;4852 let Inst{15-12} = 0b1111;4853 let Inst{11-8} = Rt;4854 let Inst{7-6} = at;4855 let Inst{5-0} = 0b000000;4856 4857 let Unpredictable{5-0} = 0b111111;4858}4859 4860def t2TT : T2TT<0b00, "tt",4861 [(set rGPR:$Rt, (int_arm_cmse_tt GPRnopc:$Rn))]>,4862 Requires<[IsThumb, Has8MSecExt]>;4863def t2TTT : T2TT<0b01, "ttt",4864 [(set rGPR:$Rt, (int_arm_cmse_ttt GPRnopc:$Rn))]>,4865 Requires<[IsThumb, Has8MSecExt]>;4866def t2TTA : T2TT<0b10, "tta",4867 [(set rGPR:$Rt, (int_arm_cmse_tta GPRnopc:$Rn))]>,4868 Requires<[IsThumb, Has8MSecExt]>;4869def t2TTAT : T2TT<0b11, "ttat",4870 [(set rGPR:$Rt, (int_arm_cmse_ttat GPRnopc:$Rn))]>,4871 Requires<[IsThumb, Has8MSecExt]>;4872 4873//===----------------------------------------------------------------------===//4874// Non-Instruction Patterns4875//4876 4877// SXT/UXT with no rotate4878let AddedComplexity = 16 in {4879def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,4880 Requires<[IsThumb2]>;4881def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,4882 Requires<[IsThumb2]>;4883def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,4884 Requires<[HasDSP, IsThumb2]>;4885def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),4886 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,4887 Requires<[HasDSP, IsThumb2]>;4888def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),4889 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,4890 Requires<[HasDSP, IsThumb2]>;4891}4892 4893def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,4894 Requires<[IsThumb2]>;4895def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,4896 Requires<[IsThumb2]>;4897def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),4898 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,4899 Requires<[HasDSP, IsThumb2]>;4900def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),4901 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,4902 Requires<[HasDSP, IsThumb2]>;4903 4904// Atomic load/store patterns4905def : T2Pat<(atomic_load_azext_8 t2addrmode_imm12:$addr),4906 (t2LDRBi12 t2addrmode_imm12:$addr)>;4907def : T2Pat<(atomic_load_azext_8 t2addrmode_negimm8:$addr),4908 (t2LDRBi8 t2addrmode_negimm8:$addr)>;4909def : T2Pat<(atomic_load_azext_8 t2addrmode_so_reg:$addr),4910 (t2LDRBs t2addrmode_so_reg:$addr)>;4911def : T2Pat<(atomic_load_azext_16 t2addrmode_imm12:$addr),4912 (t2LDRHi12 t2addrmode_imm12:$addr)>;4913def : T2Pat<(atomic_load_azext_16 t2addrmode_negimm8:$addr),4914 (t2LDRHi8 t2addrmode_negimm8:$addr)>;4915def : T2Pat<(atomic_load_azext_16 t2addrmode_so_reg:$addr),4916 (t2LDRHs t2addrmode_so_reg:$addr)>;4917def : T2Pat<(atomic_load_nonext_32 t2addrmode_imm12:$addr),4918 (t2LDRi12 t2addrmode_imm12:$addr)>;4919def : T2Pat<(atomic_load_nonext_32 t2addrmode_negimm8:$addr),4920 (t2LDRi8 t2addrmode_negimm8:$addr)>;4921def : T2Pat<(atomic_load_nonext_32 t2addrmode_so_reg:$addr),4922 (t2LDRs t2addrmode_so_reg:$addr)>;4923def : T2Pat<(atomic_store_8 GPR:$val, t2addrmode_imm12:$addr),4924 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;4925def : T2Pat<(atomic_store_8 GPR:$val, t2addrmode_negimm8:$addr),4926 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;4927def : T2Pat<(atomic_store_8 GPR:$val, t2addrmode_so_reg:$addr),4928 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;4929def : T2Pat<(atomic_store_16 GPR:$val, t2addrmode_imm12:$addr),4930 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;4931def : T2Pat<(atomic_store_16 GPR:$val, t2addrmode_negimm8:$addr),4932 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;4933def : T2Pat<(atomic_store_16 GPR:$val, t2addrmode_so_reg:$addr),4934 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;4935def : T2Pat<(atomic_store_32 GPR:$val,t2addrmode_imm12:$addr),4936 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;4937def : T2Pat<(atomic_store_32 GPR:$val, t2addrmode_negimm8:$addr),4938 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;4939def : T2Pat<(atomic_store_32 GPR:$val, t2addrmode_so_reg:$addr),4940 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;4941 4942let AddedComplexity = 8, Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex] in {4943 def : Pat<(atomic_load_azext_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;4944 def : Pat<(atomic_load_azext_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;4945 def : Pat<(atomic_load_nonext_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;4946 def : Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;4947 def : Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;4948 def : Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>;4949}4950 4951 4952//===----------------------------------------------------------------------===//4953// Assembler aliases4954//4955 4956// Aliases for ADC without the ".w" optional width specifier.4957def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",4958 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;4959def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",4960 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,4961 pred:$p, cc_out:$s)>;4962def : t2InstAlias<"adc${s}${p} $Rdn, $Rm",4963 (t2ADCrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;4964def : t2InstAlias<"adc${s}${p} $Rdn, $ShiftedRm",4965 (t2ADCrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm,4966 pred:$p, cc_out:$s)>;4967 4968// Aliases for SBC without the ".w" optional width specifier.4969def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",4970 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;4971def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",4972 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,4973 pred:$p, cc_out:$s)>;4974 4975// Aliases for ADD without the ".w" optional width specifier.4976def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",4977 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,4978 cc_out:$s)>;4979def : t2InstAlias<"add${p} $Rd, $Rn, $imm",4980 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;4981def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",4982 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;4983def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",4984 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,4985 pred:$p, cc_out:$s)>;4986// ... and with the destination and source register combined.4987def : t2InstAlias<"add${s}${p} $Rdn, $imm",4988 (t2ADDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;4989def : t2InstAlias<"add${p} $Rdn, $imm",4990 (t2ADDri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>;4991def : t2InstAlias<"addw${p} $Rdn, $imm",4992 (t2ADDri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>;4993def : t2InstAlias<"add${s}${p} $Rdn, $Rm",4994 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;4995def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",4996 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,4997 pred:$p, cc_out:$s)>;4998 4999// add w/ negative immediates is just a sub.5000def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",5001 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,5002 cc_out:$s)>;5003def : t2InstSubst<"add${p} $Rd, $Rn, $imm",5004 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;5005def : t2InstSubst<"add${s}${p} $Rdn, $imm",5006 (t2SUBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_neg:$imm, pred:$p,5007 cc_out:$s)>;5008def : t2InstSubst<"add${p} $Rdn, $imm",5009 (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095_neg:$imm, pred:$p)>;5010 5011def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",5012 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,5013 cc_out:$s)>;5014def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",5015 (t2SUBri12 rGPR:$Rd, rGPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;5016def : t2InstSubst<"add${s}${p}.w $Rdn, $imm",5017 (t2SUBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_neg:$imm, pred:$p,5018 cc_out:$s)>;5019def : t2InstSubst<"addw${p} $Rdn, $imm",5020 (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095_neg:$imm, pred:$p)>;5021 5022 5023// Aliases for SUB without the ".w" optional width specifier.5024def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",5025 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5026def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",5027 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;5028def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",5029 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;5030def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",5031 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,5032 pred:$p, cc_out:$s)>;5033// ... and with the destination and source register combined.5034def : t2InstAlias<"sub${s}${p} $Rdn, $imm",5035 (t2SUBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5036def : t2InstAlias<"sub${p} $Rdn, $imm",5037 (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>;5038def : t2InstAlias<"subw${p} $Rdn, $imm",5039 (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>;5040def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",5041 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;5042def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",5043 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;5044def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",5045 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,5046 pred:$p, cc_out:$s)>;5047 5048// SP to SP alike aliases5049// Aliases for ADD without the ".w" optional width specifier.5050def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",5051 (t2ADDspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p,5052 cc_out:$s)>;5053def : t2InstAlias<"add${p} $Rd, $Rn, $imm",5054 (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>;5055// ... and with the destination and source register combined.5056def : t2InstAlias<"add${s}${p} $Rdn, $imm",5057 (t2ADDspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5058 5059def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",5060 (t2ADDspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5061 5062def : t2InstAlias<"add${p} $Rdn, $imm",5063 (t2ADDspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>;5064 5065def : t2InstAlias<"addw${p} $Rdn, $imm",5066 (t2ADDspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>;5067 5068// add w/ negative immediates is just a sub.5069def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",5070 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p,5071 cc_out:$s)>;5072def : t2InstSubst<"add${p} $Rd, $Rn, $imm",5073 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;5074def : t2InstSubst<"add${s}${p} $Rdn, $imm",5075 (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm_neg:$imm, pred:$p,5076 cc_out:$s)>;5077def : t2InstSubst<"add${p} $Rdn, $imm",5078 (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095_neg:$imm, pred:$p)>;5079 5080def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",5081 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p,5082 cc_out:$s)>;5083def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",5084 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;5085def : t2InstSubst<"add${s}${p}.w $Rdn, $imm",5086 (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm_neg:$imm, pred:$p,5087 cc_out:$s)>;5088def : t2InstSubst<"addw${p} $Rdn, $imm",5089 (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095_neg:$imm, pred:$p)>;5090 5091 5092// Aliases for SUB without the ".w" optional width specifier.5093def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",5094 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5095def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",5096 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>;5097// ... and with the destination and source register combined.5098def : t2InstAlias<"sub${s}${p} $Rdn, $imm",5099 (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5100def : t2InstAlias<"sub${s}${p}.w $Rdn, $imm",5101 (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5102def : t2InstAlias<"sub${p} $Rdn, $imm",5103 (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>;5104def : t2InstAlias<"subw${p} $Rdn, $imm",5105 (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>;5106 5107// Alias for compares without the ".w" optional width specifier.5108def : t2InstAlias<"cmn${p} $Rn, $Rm",5109 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;5110def : t2InstAlias<"teq${p} $Rn, $Rm",5111 (t2TEQrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;5112def : t2InstAlias<"tst${p} $Rn, $Rm",5113 (t2TSTrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;5114 5115// Memory barriers5116def : InstAlias<"dmb${p}.w\t$opt", (t2DMB memb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>;5117def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;5118def : InstAlias<"dmb${p}.w", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;5119def : InstAlias<"dsb${p}.w\t$opt", (t2DSB memb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>;5120def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;5121def : InstAlias<"dsb${p}.w", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;5122def : InstAlias<"isb${p}.w\t$opt", (t2ISB instsyncb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>;5123def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;5124def : InstAlias<"isb${p}.w", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;5125 5126// Non-predicable aliases of a predicable DSB: the predicate is (14, zero_reg) where5127// 14 = AL (always execute) and zero_reg = "instruction doesn't read the CPSR".5128def : InstAlias<"ssbb", (t2DSB 0x0, (pred 14, zero_reg)), 1>,5129 Requires<[HasDB, IsThumb2]>;5130def : InstAlias<"pssbb", (t2DSB 0x4, (pred 14, zero_reg)), 1>,5131 Requires<[HasDB, IsThumb2]>;5132 5133// Armv8-R 'Data Full Barrier'5134def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>;5135 5136// SpeculationBarrierEndBB must only be used after an unconditional control5137// flow, i.e. after a terminator for which isBarrier is True.5138let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in {5139 // This gets lowered to a pair of 4-byte instructions5140 let Size = 8 in5141 def t2SpeculationBarrierISBDSBEndBB5142 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;5143 // This gets lowered to a single 4-byte instructions5144 let Size = 4 in5145 def t2SpeculationBarrierSBEndBB5146 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;5147}5148 5149// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional5150// width specifier.5151def : t2InstAlias<"ldr${p} $Rt, $addr",5152 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;5153def : t2InstAlias<"ldrb${p} $Rt, $addr",5154 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;5155def : t2InstAlias<"ldrh${p} $Rt, $addr",5156 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;5157def : t2InstAlias<"ldrsb${p} $Rt, $addr",5158 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;5159def : t2InstAlias<"ldrsh${p} $Rt, $addr",5160 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;5161 5162def : t2InstAlias<"ldr${p} $Rt, $addr",5163 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;5164def : t2InstAlias<"ldrb${p} $Rt, $addr",5165 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;5166def : t2InstAlias<"ldrh${p} $Rt, $addr",5167 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;5168def : t2InstAlias<"ldrsb${p} $Rt, $addr",5169 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;5170def : t2InstAlias<"ldrsh${p} $Rt, $addr",5171 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;5172 5173def : t2InstAlias<"ldr${p} $Rt, $addr",5174 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;5175def : t2InstAlias<"ldrb${p} $Rt, $addr",5176 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;5177def : t2InstAlias<"ldrh${p} $Rt, $addr",5178 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;5179def : t2InstAlias<"ldrsb${p} $Rt, $addr",5180 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;5181def : t2InstAlias<"ldrsh${p} $Rt, $addr",5182 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;5183 5184// Alias for MVN with(out) the ".w" optional width specifier.5185def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",5186 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5187def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",5188 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;5189def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",5190 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;5191 5192// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the5193// input operands swapped when the shift amount is zero (i.e., unspecified).5194def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",5195 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,5196 Requires<[HasDSP, IsThumb2]>;5197def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",5198 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,5199 Requires<[HasDSP, IsThumb2]>;5200 5201// PUSH/POP aliases for STM/LDM5202def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;5203def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;5204def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;5205def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;5206 5207// STMIA/STMIA_UPD aliases w/o the optional .w suffix5208def : t2InstAlias<"stm${p} $Rn, $regs",5209 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;5210def : t2InstAlias<"stm${p} $Rn!, $regs",5211 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;5212 5213// LDMIA/LDMIA_UPD aliases w/o the optional .w suffix5214def : t2InstAlias<"ldm${p} $Rn, $regs",5215 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;5216def : t2InstAlias<"ldm${p} $Rn!, $regs",5217 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;5218 5219// STMDB/STMDB_UPD aliases w/ the optional .w suffix5220def : t2InstAlias<"stmdb${p}.w $Rn, $regs",5221 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;5222def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",5223 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;5224 5225// LDMDB/LDMDB_UPD aliases w/ the optional .w suffix5226def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",5227 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;5228def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",5229 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;5230 5231// Alias for REV/REV16/REVSH without the ".w" optional width specifier.5232def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;5233def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;5234def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;5235 5236 5237// Alias for RSB with and without the ".w" optional width specifier, with and5238// without explicit destination register.5239def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",5240 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5241def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",5242 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;5243def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",5244 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;5245def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",5246 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,5247 cc_out:$s)>;5248def : t2InstAlias<"rsb${s}${p}.w $Rdn, $Rm",5249 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;5250def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $Rm",5251 (t2RSBrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;5252def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $ShiftedRm",5253 (t2RSBrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p,5254 cc_out:$s)>;5255 5256// SSAT/USAT optional shift operand.5257def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",5258 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;5259def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",5260 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;5261 5262// STM w/o the .w suffix.5263def : t2InstAlias<"stm${p} $Rn, $regs",5264 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;5265 5266// Alias for STR, STRB, and STRH without the ".w" optional5267// width specifier.5268def : t2InstAlias<"str${p} $Rt, $addr",5269 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;5270def : t2InstAlias<"strb${p} $Rt, $addr",5271 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;5272def : t2InstAlias<"strh${p} $Rt, $addr",5273 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;5274 5275def : t2InstAlias<"str${p} $Rt, $addr",5276 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;5277def : t2InstAlias<"strb${p} $Rt, $addr",5278 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;5279def : t2InstAlias<"strh${p} $Rt, $addr",5280 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;5281 5282// Extend instruction optional rotate operand.5283def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",5284 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,5285 Requires<[HasDSP, IsThumb2]>;5286def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",5287 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,5288 Requires<[HasDSP, IsThumb2]>;5289def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",5290 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,5291 Requires<[HasDSP, IsThumb2]>;5292def : InstAlias<"sxtb16${p} $Rd, $Rm",5293 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,5294 Requires<[HasDSP, IsThumb2]>;5295 5296def : t2InstAlias<"sxtb${p} $Rd, $Rm",5297 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;5298def : t2InstAlias<"sxth${p} $Rd, $Rm",5299 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;5300def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",5301 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;5302def : t2InstAlias<"sxth${p}.w $Rd, $Rm",5303 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;5304 5305def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",5306 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,5307 Requires<[HasDSP, IsThumb2]>;5308def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",5309 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,5310 Requires<[HasDSP, IsThumb2]>;5311def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",5312 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,5313 Requires<[HasDSP, IsThumb2]>;5314def : InstAlias<"uxtb16${p} $Rd, $Rm",5315 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,5316 Requires<[HasDSP, IsThumb2]>;5317 5318def : t2InstAlias<"uxtb${p} $Rd, $Rm",5319 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;5320def : t2InstAlias<"uxth${p} $Rd, $Rm",5321 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;5322def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",5323 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;5324def : t2InstAlias<"uxth${p}.w $Rd, $Rm",5325 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;5326 5327// Extend instruction w/o the ".w" optional width specifier.5328def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",5329 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;5330def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",5331 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,5332 Requires<[HasDSP, IsThumb2]>;5333def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",5334 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;5335 5336def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",5337 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;5338def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",5339 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,5340 Requires<[HasDSP, IsThumb2]>;5341def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",5342 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;5343 5344 5345// "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like5346// for isel.5347def : t2InstSubst<"mov${p} $Rd, $imm",5348 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p,5349 (cc_out zero_reg))>;5350def : t2InstSubst<"mvn${s}${p} $Rd, $imm",5351 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;5352// Same for AND <--> BIC5353def : t2InstSubst<"bic${s}${p} $Rd, $Rn, $imm",5354 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,5355 pred:$p, cc_out:$s)>;5356def : t2InstSubst<"bic${s}${p} $Rdn, $imm",5357 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,5358 pred:$p, cc_out:$s)>;5359def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm",5360 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,5361 pred:$p, cc_out:$s)>;5362def : t2InstSubst<"bic${s}${p}.w $Rdn, $imm",5363 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,5364 pred:$p, cc_out:$s)>;5365def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm",5366 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,5367 pred:$p, cc_out:$s)>;5368def : t2InstSubst<"and${s}${p} $Rdn, $imm",5369 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,5370 pred:$p, cc_out:$s)>;5371def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm",5372 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,5373 pred:$p, cc_out:$s)>;5374def : t2InstSubst<"and${s}${p}.w $Rdn, $imm",5375 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,5376 pred:$p, cc_out:$s)>;5377// And ORR <--> ORN5378def : t2InstSubst<"orn${s}${p} $Rd, $Rn, $imm",5379 (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,5380 pred:$p, cc_out:$s)>;5381def : t2InstSubst<"orn${s}${p} $Rdn, $imm",5382 (t2ORRri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,5383 pred:$p, cc_out:$s)>;5384def : t2InstSubst<"orr${s}${p} $Rd, $Rn, $imm",5385 (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,5386 pred:$p, cc_out:$s)>;5387def : t2InstSubst<"orr${s}${p} $Rdn, $imm",5388 (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,5389 pred:$p, cc_out:$s)>;5390// Likewise, "add Rd, t2_so_imm_neg" -> sub5391def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",5392 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,5393 pred:$p, cc_out:$s)>;5394def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",5395 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm,5396 pred:$p, cc_out:$s)>;5397def : t2InstSubst<"add${s}${p} $Rd, $imm",5398 (t2SUBri rGPR:$Rd, rGPR:$Rd, t2_so_imm_neg:$imm,5399 pred:$p, cc_out:$s)>;5400def : t2InstSubst<"add${s}${p} $Rd, $imm",5401 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rd, t2_so_imm_neg:$imm,5402 pred:$p, cc_out:$s)>;5403// Same for CMP <--> CMN via t2_so_imm_neg5404def : t2InstSubst<"cmp${p} $Rd, $imm",5405 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;5406def : t2InstSubst<"cmn${p} $Rd, $imm",5407 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;5408 5409 5410// Wide 'mul' encoding can be specified with only two operands.5411def : t2InstAlias<"mul${p} $Rn, $Rm",5412 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;5413 5414// "neg" is and alias for "rsb rd, rn, #0"5415def : t2InstAlias<"neg${s}${p} $Rd, $Rm",5416 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;5417 5418// MOV so_reg assembler pseudos. InstAlias isn't expressive enough for5419// these, unfortunately.5420// FIXME: LSL #0 in the shift should allow SP to be used as either the5421// source or destination (but not both).5422def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",5423 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;5424def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",5425 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;5426 5427def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",5428 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;5429def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",5430 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;5431 5432// Aliases for the above with the .w qualifier5433def : t2InstAlias<"mov${p}.w $Rd, $shift",5434 (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;5435def : t2InstAlias<"movs${p}.w $Rd, $shift",5436 (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;5437def : t2InstAlias<"mov${p}.w $Rd, $shift",5438 (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;5439def : t2InstAlias<"movs${p}.w $Rd, $shift",5440 (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;5441 5442// ADR w/o the .w suffix5443def : t2InstAlias<"adr${p} $Rd, $addr",5444 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;5445 5446// LDR(literal) w/ alternate [pc, #imm] syntax.5447def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",5448 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;5449def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",5450 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;5451def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",5452 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;5453def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",5454 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;5455def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",5456 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;5457 // Version w/ the .w suffix.5458def : t2InstAlias<"ldr${p}.w $Rt, $addr",5459 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;5460def : t2InstAlias<"ldrb${p}.w $Rt, $addr",5461 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;5462def : t2InstAlias<"ldrh${p}.w $Rt, $addr",5463 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;5464def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",5465 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;5466def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",5467 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;5468 5469def : t2InstAlias<"add${p} $Rd, pc, $imm",5470 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;5471 5472// Pseudo instruction ldr Rt, =immediate5473def t2LDRConstPool5474 : t2AsmPseudo<"ldr${p} $Rt, $immediate",5475 (ins GPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;5476// Version w/ the .w suffix.5477def : t2InstAlias<"ldr${p}.w $Rt, $immediate",5478 (t2LDRConstPool GPRnopc:$Rt,5479 const_pool_asm_imm:$immediate, pred:$p)>;5480 5481//===----------------------------------------------------------------------===//5482// ARMv8.1m instructions5483//5484 5485class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm,5486 string ops, string cstr, list<dag> pattern>5487 : Thumb2XI<oops, iops, am, 4, itin, !strconcat(asm, "\t", ops), cstr,5488 pattern>,5489 Requires<[HasV8_1MMainline]>;5490 5491def t2CLRM : V8_1MI<(outs),5492 (ins pred:$p, reglist_with_apsr:$regs, variable_ops),5493 AddrModeNone, NoItinerary, "clrm${p}", "$regs", "", []> {5494 bits<0> p;5495 bits<16> regs;5496 5497 let Inst{31-16} = 0b1110100010011111;5498 let Inst{15-14} = regs{15-14};5499 let Inst{13} = 0b0;5500 let Inst{12-0} = regs{12-0};5501}5502 5503class t2BF<dag iops, string asm, string ops>5504 : V8_1MI<(outs ), iops, AddrModeNone, NoItinerary, asm, ops, "", []> {5505 5506 let Inst{31-27} = 0b11110;5507 let Inst{15-14} = 0b11;5508 let Inst{12} = 0b0;5509 let Inst{0} = 0b1;5510 5511 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];5512}5513 5514def t2BF_LabelPseudo5515 : t2PseudoInst<(outs ), (ins pclabel:$cp), 0, NoItinerary, []> {5516 let isTerminator = 1;5517 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];5518 let hasNoSchedulingInfo = 1;5519}5520 5521def t2BFi : t2BF<(ins bflabel_u4:$b_label, bflabel_s16:$label, pred:$p),5522 !strconcat("bf", "${p}"), "$b_label, $label"> {5523 bits<0> p;5524 bits<4> b_label;5525 bits<16> label;5526 5527 let Inst{26-23} = b_label{3-0};5528 let Inst{22-21} = 0b10;5529 let Inst{20-16} = label{15-11};5530 let Inst{13} = 0b1;5531 let Inst{11} = label{0};5532 let Inst{10-1} = label{10-1};5533}5534 5535def t2BFic : t2BF<(ins bflabel_u4:$b_label, bflabel_s12:$label,5536 bfafter_target:$ba_label, pred_noal:$bcond), "bfcsel",5537 "$b_label, $label, $ba_label, $bcond"> {5538 bits<4> bcond;5539 bits<12> label;5540 bits<1> ba_label;5541 bits<4> b_label;5542 5543 let Inst{26-23} = b_label{3-0};5544 let Inst{22} = 0b0;5545 let Inst{21-18} = bcond{3-0};5546 let Inst{17} = ba_label{0};5547 let Inst{16} = label{11};5548 let Inst{13} = 0b1;5549 let Inst{11} = label{0};5550 let Inst{10-1} = label{10-1};5551}5552 5553def t2BFr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),5554 !strconcat("bfx", "${p}"), "$b_label, $Rn"> {5555 bits<0> p;5556 bits<4> b_label;5557 bits<4> Rn;5558 5559 let Inst{26-23} = b_label{3-0};5560 let Inst{22-20} = 0b110;5561 let Inst{19-16} = Rn{3-0};5562 let Inst{13-1} = 0b1000000000000;5563}5564 5565def t2BFLi : t2BF<(ins bflabel_u4:$b_label, bflabel_s18:$label, pred:$p),5566 !strconcat("bfl", "${p}"), "$b_label, $label"> {5567 bits<0> p;5568 bits<4> b_label;5569 bits<18> label;5570 5571 let Inst{26-23} = b_label{3-0};5572 let Inst{22-16} = label{17-11};5573 let Inst{13} = 0b0;5574 let Inst{11} = label{0};5575 let Inst{10-1} = label{10-1};5576}5577 5578def t2BFLr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p),5579 !strconcat("bflx", "${p}"), "$b_label, $Rn"> {5580 bits<0> p;5581 bits<4> b_label;5582 bits<4> Rn;5583 5584 let Inst{26-23} = b_label{3-0};5585 let Inst{22-20} = 0b111;5586 let Inst{19-16} = Rn{3-0};5587 let Inst{13-1} = 0b1000000000000;5588}5589 5590class t2LOL<dag oops, dag iops, string asm, string ops>5591 : V8_1MI<oops, iops, AddrModeNone, NoItinerary, asm, ops, "", [] > {5592 let Inst{31-23} = 0b111100000;5593 let Inst{15-14} = 0b11;5594 let Inst{0} = 0b1;5595 let DecoderMethod = "DecodeLOLoop";5596 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];5597}5598 5599// Setup for the iteration count of a WLS. See t2WhileLoopSetup.5600def arm_wlssetup5601 : SDNode<"ARMISD::WLSSETUP",5602 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisSameAs<1, 0>]>,5603 [SDNPSideEffect]>;5604 5605// Low-overhead loops, While Loop Start branch. See t2WhileLoopStart5606def arm_wls : SDNode<"ARMISD::WLS",5607 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>,5608 [SDNPHasChain]>;5609 5610// Really a part of LE, performs the sub5611def arm_loop_dec : SDNode<"ARMISD::LOOP_DEC", SDTIntBinOp, [SDNPHasChain]>;5612 5613// Low-overhead loops, Loop End5614def arm_le : SDNode<"ARMISD::LE",5615 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>,5616 [SDNPHasChain]>;5617 5618let isNotDuplicable = 1 in {5619def t2WLS : t2LOL<(outs GPRlr:$LR),5620 (ins rGPR:$Rn, wlslabel_u11:$label),5621 "wls", "$LR, $Rn, $label"> {5622 bits<4> Rn;5623 bits<11> label;5624 let Inst{22-20} = 0b100;5625 let Inst{19-16} = Rn{3-0};5626 let Inst{13-12} = 0b00;5627 let Inst{11} = label{0};5628 let Inst{10-1} = label{10-1};5629 let usesCustomInserter = 1;5630 let isBranch = 1;5631 let isTerminator = 1;5632}5633 5634def t2DLS : t2LOL<(outs GPRlr:$LR), (ins rGPR:$Rn),5635 "dls", "$LR, $Rn"> {5636 bits<4> Rn;5637 let Inst{22-20} = 0b100;5638 let Inst{19-16} = Rn{3-0};5639 let Inst{13-1} = 0b1000000000000;5640 let usesCustomInserter = 1;5641}5642 5643def t2LEUpdate : t2LOL<(outs GPRlr:$LRout),5644 (ins GPRlr:$LRin, lelabel_u11:$label),5645 "le", "$LRin, $label"> {5646 bits<11> label;5647 let Inst{22-16} = 0b0001111;5648 let Inst{13-12} = 0b00;5649 let Inst{11} = label{0};5650 let Inst{10-1} = label{10-1};5651 let usesCustomInserter = 1;5652 let isBranch = 1;5653 let isTerminator = 1;5654}5655 5656def t2LE : t2LOL<(outs ), (ins lelabel_u11:$label), "le", "$label"> {5657 bits<11> label;5658 let Inst{22-16} = 0b0101111;5659 let Inst{13-12} = 0b00;5660 let Inst{11} = label{0};5661 let Inst{10-1} = label{10-1};5662 let isBranch = 1;5663 let isTerminator = 1;5664}5665 5666let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB] in {5667 5668// t2DoLoopStart a pseudo for DLS hardware loops. Lowered into a DLS in5669// ARMLowOverheadLoops if possible, or reverted to a Mov if not.5670def t2DoLoopStart :5671 t2PseudoInst<(outs GPRlr:$X), (ins rGPR:$tc), 4, IIC_Br,5672 [(set GPRlr:$X, (int_start_loop_iterations rGPR:$tc))]>;5673 5674// A pseudo for a DLSTP, created in the MVETPAndVPTOptimizationPass from a5675// t2DoLoopStart if the loops is tail predicated. Holds both the element5676// count and trip count of the loop, picking the correct one during5677// ARMLowOverheadLoops when it is converted to a DLSTP or DLS as required.5678let isTerminator = 1, hasSideEffects = 1 in5679def t2DoLoopStartTP :5680 t2PseudoInst<(outs GPRlr:$X), (ins rGPR:$tc, rGPR:$elts), 4, IIC_Br, []>;5681 5682// Setup for a t2WhileLoopStart. A pair of t2WhileLoopSetup and t2WhileLoopStart5683// will be created post-ISel from a llvm.test.start.loop.iterations. This5684// t2WhileLoopSetup to setup LR and t2WhileLoopStart to perform the branch. Not5685// valid after reg alloc, as it should be lowered during MVETPAndVPTOptimisations5686// into a t2WhileLoopStartLR (or expanded).5687let hasSideEffects = 1 in5688def t2WhileLoopSetup :5689 t2PseudoInst<(outs GPRlr:$lr), (ins rGPR:$tc), 4, IIC_Br,5690 [(set i32:$lr, (arm_wlssetup i32:$tc))]>;5691 5692// A pseudo to represent the decrement in a low overhead loop. A t2LoopDec and5693// t2LoopEnd together represent a LE instruction. Ideally these are converted5694// to a t2LoopEndDec which is lowered as a single instruction.5695let hasSideEffects = 0 in5696def t2LoopDec :5697 t2PseudoInst<(outs GPRlr:$Rm), (ins GPRlr:$Rn, imm0_7:$size), 4, IIC_Br,5698 [(set i32:$Rm, (arm_loop_dec i32:$Rn, timm:$size))]>,5699 Sched<[WriteBr]>;5700 5701let isBranch = 1, isTerminator = 1, hasSideEffects = 1, Defs = [CPSR] in {5702// The branch in a t2WhileLoopSetup/t2WhileLoopStart pair, eventually turned5703// into a t2WhileLoopStartLR that does both the LR setup and branch.5704def t2WhileLoopStart :5705 t2PseudoInst<(outs),5706 (ins GPRlr:$tc, brtarget:$target),5707 4, IIC_Br, [(arm_wls i32:$tc, bb:$target)]>,5708 Sched<[WriteBr]>;5709 5710// WhileLoopStartLR that sets up LR and branches on zero, equivalent to WLS. It5711// is lowered in the ARMLowOverheadLoops pass providing the branches are within5712// range. WhileLoopStartLR and LoopEnd to occupy 8 bytes because they may get5713// converted into t2CMP and t2Bcc.5714def t2WhileLoopStartLR :5715 t2PseudoInst<(outs GPRlr:$lr),5716 (ins rGPR:$tc, brtarget:$target),5717 8, IIC_Br, []>,5718 Sched<[WriteBr]>;5719 5720// Similar to a t2DoLoopStartTP, a t2WhileLoopStartTP is a pseudo for a WLSTP5721// holding both the element count and the tripcount of the loop.5722def t2WhileLoopStartTP :5723 t2PseudoInst<(outs GPRlr:$lr),5724 (ins rGPR:$tc, rGPR:$elts, brtarget:$target),5725 8, IIC_Br, []>,5726 Sched<[WriteBr]>;5727 5728// t2LoopEnd - the branch half of a t2LoopDec/t2LoopEnd pair.5729def t2LoopEnd :5730 t2PseudoInst<(outs), (ins GPRlr:$tc, brtarget:$target),5731 8, IIC_Br, [(arm_le i32:$tc, bb:$target)]>,5732 Sched<[WriteBr]>;5733 5734// The combination of a t2LoopDec and t2LoopEnd, performing both the LR5735// decrement and branch as a single instruction. Is lowered to a LE or5736// LETP in ARMLowOverheadLoops as appropriate, or converted to t2CMP/t2Bcc5737// if the branches are out of range.5738def t2LoopEndDec :5739 t2PseudoInst<(outs GPRlr:$Rm), (ins GPRlr:$tc, brtarget:$target),5740 8, IIC_Br, []>, Sched<[WriteBr]>;5741 5742} // end isBranch, isTerminator, hasSideEffects5743 5744}5745 5746} // end isNotDuplicable5747 5748class CS<string iname, bits<4> opcode, list<dag> pattern=[]>5749 : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond),5750 AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> {5751 bits<4> Rd;5752 bits<4> Rm;5753 bits<4> Rn;5754 bits<4> fcond;5755 5756 let Inst{31-20} = 0b111010100101;5757 let Inst{19-16} = Rn{3-0};5758 let Inst{15-12} = opcode;5759 let Inst{11-8} = Rd{3-0};5760 let Inst{7-4} = fcond{3-0};5761 let Inst{3-0} = Rm{3-0};5762 5763 let Uses = [CPSR];5764 let hasSideEffects = 0;5765}5766 5767def t2CSEL : CS<"csel", 0b1000>;5768def t2CSINC : CS<"csinc", 0b1001>;5769def t2CSINV : CS<"csinv", 0b1010>;5770def t2CSNEG : CS<"csneg", 0b1011>;5771 5772let HasOneUse = 1 in5773def ARMcsinc_su5774 : PatFrag<(ops node:$lhs, node:$rhs, node:$cc, node:$flags),5775 (ARMcsinc node:$lhs, node:$rhs, node:$cc, node:$flags)>;5776 5777let Predicates = [HasV8_1MMainline] in {5778 multiclass CSPats<SDNode Node, Instruction Insn> {5779 def : T2Pat<(Node GPRwithZR:$tval, GPRwithZR:$fval, imm:$cc, CPSR),5780 (Insn GPRwithZR:$tval, GPRwithZR:$fval, imm:$cc)>;5781 def : T2Pat<(Node (i32 0), GPRwithZR:$fval, imm:$cc, CPSR),5782 (Insn ZR, GPRwithZR:$fval, imm:$cc)>;5783 def : T2Pat<(Node GPRwithZR:$tval, (i32 0), imm:$cc, CPSR),5784 (Insn GPRwithZR:$tval, ZR, imm:$cc)>;5785 def : T2Pat<(Node (i32 0), (i32 0), imm:$cc, CPSR),5786 (Insn ZR, ZR, imm:$cc)>;5787 }5788 5789 defm : CSPats<ARMcsinc, t2CSINC>;5790 defm : CSPats<ARMcsinv, t2CSINV>;5791 defm : CSPats<ARMcsneg, t2CSNEG>;5792 5793 def : T2Pat<(ARMcmov (i32 1), (i32 0), imm:$cc, CPSR),5794 (t2CSINC ZR, ZR, imm:$cc)>;5795 def : T2Pat<(ARMcmov (i32 -1), (i32 0), imm:$cc, CPSR),5796 (t2CSINV ZR, ZR, imm:$cc)>;5797 def : T2Pat<(ARMcmov (i32 0), (i32 1), imm:$cc, CPSR),5798 (t2CSINC ZR, ZR, (inv_cond_XFORM imm:$cc))>;5799 def : T2Pat<(ARMcmov (i32 0), (i32 -1), imm:$cc, CPSR),5800 (t2CSINV ZR, ZR, (inv_cond_XFORM imm:$cc))>;5801 5802 multiclass ModifiedV8_1CSEL<Instruction Insn, dag modvalue> {5803 def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, imm:$cc, CPSR),5804 (Insn GPRwithZR:$tval, GPRwithZR:$fval, imm:$cc)>;5805 def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, imm:$cc, CPSR),5806 (Insn GPRwithZR:$tval, GPRwithZR:$fval,5807 (i32 (inv_cond_XFORM imm:$cc)))>;5808 }5809 defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>;5810 defm : ModifiedV8_1CSEL<t2CSINV, (xor rGPR:$fval, -1)>;5811 defm : ModifiedV8_1CSEL<t2CSNEG, (sub 0, rGPR:$fval)>;5812 5813 def : T2Pat<(ARMcmov (topbitsallzero32:$Rn), (i32 1), imm:$cc, CPSR),5814 (t2CSINC $Rn, ZR, (inv_cond_XFORM imm:$cc))>;5815 def : T2Pat<(and (topbitsallzero32:$Rn),5816 (ARMcsinc_su (i32 0), (i32 0), imm:$cc, CPSR)),5817 (t2CSEL ZR, $Rn, imm:$cc)>;5818}5819 5820// CS aliases.5821let Predicates = [HasV8_1MMainline] in {5822 def : InstAlias<"csetm\t$Rd, $fcond",5823 (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;5824 5825 def : InstAlias<"cset\t$Rd, $fcond",5826 (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;5827 5828 def : InstAlias<"cinc\t$Rd, $Rn, $fcond",5829 (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;5830 5831 def : InstAlias<"cinv\t$Rd, $Rn, $fcond",5832 (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;5833 5834 def : InstAlias<"cneg\t$Rd, $Rn, $fcond",5835 (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;5836}5837 5838 5839// PACBTI5840let Predicates = [IsThumb2, HasV8_1MMainline, HasPACBTI] in {5841def t2PACG : V8_1MI<(outs rGPR:$Rd),5842 (ins pred:$p, GPRnopc:$Rn, GPRnopc:$Rm),5843 AddrModeNone, NoItinerary, "pacg${p}", "$Rd, $Rn, $Rm", "", []> {5844 bits<0> p;5845 bits<4> Rd;5846 bits<4> Rn;5847 bits<4> Rm;5848 let Inst{31-20} = 0b111110110110;5849 let Inst{19-16} = Rn;5850 let Inst{15-12} = 0b1111;5851 let Inst{11-8} = Rd;5852 let Inst{7-4} = 0b0000;5853 let Inst{3-0} = Rm;5854}5855 5856let hasSideEffects = 1 in {5857class PACBTIAut<dag iops, string asm, bit b>5858 : V8_1MI<(outs), iops,5859 AddrModeNone, NoItinerary, asm, "$Ra, $Rn, $Rm", "", []> {5860 bits<0> p;5861 bits<4> Ra;5862 bits<4> Rn;5863 bits<4> Rm;5864 let Inst{31-20} = 0b111110110101;5865 let Inst{19-16} = Rn;5866 let Inst{15-12} = Ra;5867 let Inst{11-5} = 0b1111000;5868 let Inst{4} = b;5869 let Inst{3-0} = Rm;5870}5871}5872 5873def t2AUTG : PACBTIAut<(ins pred:$p, GPRnosp:$Ra, GPRnopc:$Rn, GPRnopc:$Rm),5874 "autg${p}", 0>;5875 5876let isBranch = 1, isTerminator = 1, isIndirectBranch = 1 in {5877 def t2BXAUT : PACBTIAut<(ins pred:$p, GPRnosp:$Ra, rGPR:$Rn, GPRnopc:$Rm),5878 "bxaut${p}", 1>;5879}5880}5881 5882 5883class PACBTIHintSpaceInst<string asm, string ops, bits<8> imm>5884 : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, !strconcat(asm, "\t", ops), "", []>,5885 Requires<[HasV7, IsMClass]> {5886 let Inst{31-8} = 0b111100111010111110000000;5887 let Inst{7-0} = imm;5888 5889 let Unpredictable{19-16} = 0b1111;5890 let Unpredictable{13-11} = 0b101;5891 5892 let DecoderMethod = "DecodeT2HintSpaceInstruction";5893}5894 5895class PACBTIHintSpaceNoOpsInst<string asm, bits<8> imm>5896 : PACBTIHintSpaceInst<asm, "", imm>;5897 5898class PACBTIHintSpaceDefInst<string asm, bits<8> imm>5899 : PACBTIHintSpaceInst<asm, "r12, lr, sp", imm> {5900 let Defs = [R12];5901 let Uses = [LR, SP];5902}5903 5904class PACBTIHintSpaceUseInst<string asm, bits<8> imm>5905 : PACBTIHintSpaceInst<asm, "r12, lr, sp", imm> {5906 let Uses = [R12, LR, SP];5907}5908 5909def t2PAC : PACBTIHintSpaceDefInst<"pac", 0b00011101>;5910def t2PACBTI : PACBTIHintSpaceDefInst<"pacbti", 0b00001101>;5911def t2BTI : PACBTIHintSpaceNoOpsInst<"bti", 0b00001111>;5912def t2AUT : PACBTIHintSpaceUseInst<"aut", 0b00101101> {5913 let hasSideEffects = 1;5914}5915 5916// Thumb function call followed by BTI instruction.5917def ARMt2CallBTI : SDNode<"ARMISD::t2CALL_BTI", SDT_ARMcall,5918 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;5919 5920let Defs = [LR], Uses = [SP] in5921def t2CALL_BTI : PseudoInst<(outs), (ins pred:$p, thumb_bl_target:$func),5922 IIC_Br, [(ARMt2CallBTI tglobaladdr:$func)]>,5923 Requires<[IsThumb2]>, Sched<[WriteBrL]>;5924