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1//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the ARM VFP instruction set.10//11//===----------------------------------------------------------------------===//12 13def SDT_CMPFP : SDTypeProfile<1, 2, [14 SDTCisVT<0, FlagsVT>, // out flags15 SDTCisFP<1>, // lhs16 SDTCisSameAs<2, 1> // rhs17]>;18 19def SDT_CMPFP0 : SDTypeProfile<1, 1, [20 SDTCisVT<0, FlagsVT>, // out flags21 SDTCisFP<1> // operand22]>;23 24def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,25 SDTCisSameAs<1, 2>]>;26def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,27 SDTCisVT<2, f64>]>;28 29def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>;30 31// ARM VFP compare instruction, sets FPSCR.32def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_CMPFP>;33 34// ARM VFP compare against zero instruction, sets FPSCR.35def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0>;36 37// ARM VFP signalling compare instruction, sets FPSCR.38def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_CMPFP>;39 40// ARM VFP signalling compare against zero instruction, sets41// FPSCR.42def arm_cmpfpe0 : SDNode<"ARMISD::CMPFPEw0", SDT_CMPFP0>;43 44// ARM fmstat instruction.45def arm_fmstat : SDNode<"ARMISD::FMSTAT",46 SDTypeProfile<1, 1, [47 SDTCisVT<0, FlagsVT>, // out flags48 SDTCisVT<1, FlagsVT> // in flags49 ]>50>;51 52// Two gprs to double.53def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;54 55// double to two gprs.56def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>;57 58// move gpr to single, used for f32 literal constructed in a gpr59def arm_vmovsr : SDNode<"ARMISD::VMOVSR", SDT_VMOVSR>;60 61def SDT_VMOVhr : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, i32>] >;62def SDT_VMOVrh : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisFP<1>] >;63 64// Move H <-> R, clearing top 16 bits65def arm_vmovhr : SDNode<"ARMISD::VMOVhr", SDT_VMOVhr>;66def arm_vmovrh : SDNode<"ARMISD::VMOVrh", SDT_VMOVrh>;67 68//===----------------------------------------------------------------------===//69// Operand Definitions.70//71 72// 8-bit floating-point immediate encodings.73def FPImmOperand : AsmOperandClass {74 let Name = "FPImm";75 let ParserMethod = "parseFPImm";76}77 78def vfp_f16imm : Operand<f16>,79 PatLeaf<(f16 fpimm), [{80 return ARM_AM::getFP16Imm(N->getValueAPF()) != -1;81 }], SDNodeXForm<fpimm, [{82 uint32_t Enc = ARM_AM::getFP16Imm(N->getValueAPF());83 return CurDAG->getTargetConstant(Enc, SDLoc(N), MVT::i32);84 }]>> {85 let PrintMethod = "printFPImmOperand";86 let ParserMatchClass = FPImmOperand;87}88 89def vfp_f32f16imm_xform : SDNodeXForm<fpimm, [{90 uint32_t Enc = ARM_AM::getFP32FP16Imm(N->getValueAPF());91 return CurDAG->getTargetConstant(Enc, SDLoc(N), MVT::i32);92 }]>;93 94def vfp_f32f16imm : PatLeaf<(f32 fpimm), [{95 return ARM_AM::getFP32FP16Imm(N->getValueAPF()) != -1;96 }], vfp_f32f16imm_xform>;97 98def vfp_f32imm_xform : SDNodeXForm<fpimm, [{99 uint32_t Enc = ARM_AM::getFP32Imm(N->getValueAPF());100 return CurDAG->getTargetConstant(Enc, SDLoc(N), MVT::i32);101 }]>;102 103def gi_vfp_f32imm : GICustomOperandRenderer<"renderVFPF32Imm">,104 GISDNodeXFormEquiv<vfp_f32imm_xform>;105 106def vfp_f32imm : Operand<f32>,107 PatLeaf<(f32 fpimm), [{108 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;109 }], vfp_f32imm_xform> {110 let PrintMethod = "printFPImmOperand";111 let ParserMatchClass = FPImmOperand;112 let GISelPredicateCode = [{113 const auto &MO = MI.getOperand(1);114 if (!MO.isFPImm())115 return false;116 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;117 }];118}119 120def vfp_f64imm_xform : SDNodeXForm<fpimm, [{121 uint32_t Enc = ARM_AM::getFP64Imm(N->getValueAPF());122 return CurDAG->getTargetConstant(Enc, SDLoc(N), MVT::i32);123 }]>;124 125def gi_vfp_f64imm : GICustomOperandRenderer<"renderVFPF64Imm">,126 GISDNodeXFormEquiv<vfp_f64imm_xform>;127 128def vfp_f64imm : Operand<f64>,129 PatLeaf<(f64 fpimm), [{130 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;131 }], vfp_f64imm_xform> {132 let PrintMethod = "printFPImmOperand";133 let ParserMatchClass = FPImmOperand;134 let GISelPredicateCode = [{135 const auto &MO = MI.getOperand(1);136 if (!MO.isFPImm())137 return false;138 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;139 }];140}141 142def alignedload16 : PatFrag<(ops node:$ptr), (load node:$ptr), [{143 return cast<LoadSDNode>(N)->getAlign() >= 2;144}]>;145 146def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{147 return cast<LoadSDNode>(N)->getAlign() >= 4;148}]>;149 150def alignedstore16 : PatFrag<(ops node:$val, node:$ptr),151 (store node:$val, node:$ptr), [{152 return cast<StoreSDNode>(N)->getAlign() >= 2;153}]>;154 155def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),156 (store node:$val, node:$ptr), [{157 return cast<StoreSDNode>(N)->getAlign() >= 4;158}]>;159 160// The VCVT to/from fixed-point instructions encode the 'fbits' operand161// (the number of fixed bits) differently than it appears in the assembly162// source. It's encoded as "Size - fbits" where Size is the size of the163// fixed-point representation (32 or 16) and fbits is the value appearing164// in the assembly source, an integer in [0,16] or (0,32], depending on size.165def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }166def fbits32 : Operand<i32> {167 let PrintMethod = "printFBits32";168 let ParserMatchClass = fbits32_asm_operand;169}170 171def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }172def fbits16 : Operand<i32> {173 let PrintMethod = "printFBits16";174 let ParserMatchClass = fbits16_asm_operand;175}176 177//===----------------------------------------------------------------------===//178// Load / store Instructions.179//180 181let canFoldAsLoad = 1, isReMaterializable = 1 in {182 183def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),184 IIC_fpLoad64, "vldr", "\t$Dd, $addr",185 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>,186 Requires<[HasFPRegs]>;187 188def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),189 IIC_fpLoad32, "vldr", "\t$Sd, $addr",190 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>,191 Requires<[HasFPRegs]> {192 // Some single precision VFP instructions may be executed on both NEON and VFP193 // pipelines.194 let D = VFPNeonDomain;195}196 197let isUnpredicable = 1 in198def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),199 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",200 [(set HPR:$Sd, (f16 (alignedload16 addrmode5fp16:$addr)))]>,201 Requires<[HasFPRegs16]>;202 203} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'204 205def : Pat<(bf16 (alignedload16 addrmode5fp16:$addr)),206 (VLDRH addrmode5fp16:$addr)> {207 let Predicates = [HasFPRegs16];208}209def : Pat<(bf16 (alignedload16 addrmode3:$addr)),210 (COPY_TO_REGCLASS (LDRH addrmode3:$addr), HPR)> {211 let Predicates = [HasNoFPRegs16, IsARM];212}213def : Pat<(bf16 (alignedload16 t2addrmode_imm12:$addr)),214 (COPY_TO_REGCLASS (t2LDRHi12 t2addrmode_imm12:$addr), HPR)> {215 let Predicates = [HasNoFPRegs16, IsThumb];216}217 218def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),219 IIC_fpStore64, "vstr", "\t$Dd, $addr",220 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>,221 Requires<[HasFPRegs]>;222 223def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),224 IIC_fpStore32, "vstr", "\t$Sd, $addr",225 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>,226 Requires<[HasFPRegs]> {227 // Some single precision VFP instructions may be executed on both NEON and VFP228 // pipelines.229 let D = VFPNeonDomain;230}231 232let isUnpredicable = 1 in233def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr),234 IIC_fpStore16, "vstr", ".16\t$Sd, $addr",235 [(alignedstore16 (f16 HPR:$Sd), addrmode5fp16:$addr)]>,236 Requires<[HasFPRegs16]>;237 238def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode5fp16:$addr),239 (VSTRH (bf16 HPR:$Sd), addrmode5fp16:$addr)> {240 let Predicates = [HasFPRegs16];241}242def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode3:$addr),243 (STRH (COPY_TO_REGCLASS $Sd, GPR), addrmode3:$addr)> {244 let Predicates = [HasNoFPRegs16, IsARM];245}246def : Pat<(alignedstore16 (bf16 HPR:$Sd), t2addrmode_imm12:$addr),247 (t2STRHi12 (COPY_TO_REGCLASS $Sd, GPR), t2addrmode_imm12:$addr)> {248 let Predicates = [HasNoFPRegs16, IsThumb];249}250 251//===----------------------------------------------------------------------===//252// Load / store multiple Instructions.253//254 255multiclass vfp_ldst_mult<string asm, bit L_bit,256 InstrItinClass itin, InstrItinClass itin_upd> {257 let Predicates = [HasFPRegs] in {258 // Double Precision259 def DIA :260 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),261 IndexModeNone, itin,262 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {263 let Inst{24-23} = 0b01; // Increment After264 let Inst{21} = 0; // No writeback265 let Inst{20} = L_bit;266 }267 def DIA_UPD :268 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,269 variable_ops),270 IndexModeUpd, itin_upd,271 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {272 let Inst{24-23} = 0b01; // Increment After273 let Inst{21} = 1; // Writeback274 let Inst{20} = L_bit;275 }276 def DDB_UPD :277 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,278 variable_ops),279 IndexModeUpd, itin_upd,280 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {281 let Inst{24-23} = 0b10; // Decrement Before282 let Inst{21} = 1; // Writeback283 let Inst{20} = L_bit;284 }285 286 // Single Precision287 def SIA :288 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),289 IndexModeNone, itin,290 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {291 let Inst{24-23} = 0b01; // Increment After292 let Inst{21} = 0; // No writeback293 let Inst{20} = L_bit;294 295 // Some single precision VFP instructions may be executed on both NEON and296 // VFP pipelines.297 let D = VFPNeonDomain;298 }299 def SIA_UPD :300 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,301 variable_ops),302 IndexModeUpd, itin_upd,303 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {304 let Inst{24-23} = 0b01; // Increment After305 let Inst{21} = 1; // Writeback306 let Inst{20} = L_bit;307 308 // Some single precision VFP instructions may be executed on both NEON and309 // VFP pipelines.310 let D = VFPNeonDomain;311 }312 def SDB_UPD :313 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,314 variable_ops),315 IndexModeUpd, itin_upd,316 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {317 let Inst{24-23} = 0b10; // Decrement Before318 let Inst{21} = 1; // Writeback319 let Inst{20} = L_bit;320 321 // Some single precision VFP instructions may be executed on both NEON and322 // VFP pipelines.323 let D = VFPNeonDomain;324 }325 }326}327 328let hasSideEffects = 0 in {329 330let mayLoad = 1, hasExtraDefRegAllocReq = 1 in331defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;332 333let mayStore = 1, hasExtraSrcRegAllocReq = 1 in334defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;335 336} // hasSideEffects337 338def : MnemonicAlias<"vldm", "vldmia">;339def : MnemonicAlias<"vstm", "vstmia">;340 341 342//===----------------------------------------------------------------------===//343// Lazy load / store multiple Instructions344//345// VLLDM and VLSTM:346// 2 encoding options:347// T1 (bit 7 is 0):348// T1 takes an optional dpr_reglist, must be '{d0-d15}' (exactly)349// T1 require v8-M.Main, secure state, target with 16 D registers (or with no D registers - NOP)350// T2 (bit 7 is 1):351// T2 takes a mandatory dpr_reglist, must be '{d0-d31}' (exactly)352// T2 require v8.1-M.Main, secure state, target with 16/32 D registers (or with no D registers - NOP)353// (source: Arm v8-M ARM, DDI0553B.v ID16122022)354 355def VLLDM : AXSI4FR<"vlldm${p}\t$Rn, $regs", 0, 1>,356 Requires<[HasV8MMainline, Has8MSecExt]> {357 let Defs = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15];358 let DecoderMethod = "DecodeLazyLoadStoreMul";359}360// T1: assembly does not contains the register list.361def : InstAlias<"vlldm${p}\t$Rn", (VLLDM GPRnopc:$Rn, pred:$p, 0)>,362 Requires<[HasV8MMainline, Has8MSecExt]>;363// T2: assembly must contains the register list.364// The register list has no effect on the encoding, it is for assembly/disassembly purposes only.365def VLLDM_T2 : AXSI4FR<"vlldm${p}\t$Rn, $regs", 1, 1>,366 Requires<[HasV8_1MMainline, Has8MSecExt]> {367 let Defs = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,368 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31];369 let DecoderMethod = "DecodeLazyLoadStoreMul";370}371// T1: assembly contains the register list.372// The register list has no effect on the encoding, it is for assembly/disassembly purposes only.373def VLSTM : AXSI4FR<"vlstm${p}\t$Rn, $regs", 0, 0>,374 Requires<[HasV8MMainline, Has8MSecExt]> {375 let Defs = [VPR, FPSCR, FPSCR_NZCV];376 let Uses = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15];377 let DecoderMethod = "DecodeLazyLoadStoreMul";378}379// T1: assembly does not contain the register list.380def : InstAlias<"vlstm${p}\t$Rn", (VLSTM GPRnopc:$Rn, pred:$p, 0)>,381 Requires<[HasV8MMainline, Has8MSecExt]>;382// T2: assembly must contain the register list.383// The register list has no effect on the encoding, it is for assembly/disassembly purposes only.384def VLSTM_T2 : AXSI4FR<"vlstm${p}\t$Rn, $regs", 1, 0>,385 Requires<[HasV8_1MMainline, Has8MSecExt]> {386 let Defs = [VPR, FPSCR, FPSCR_NZCV];387 let Uses = [VPR, FPSCR, FPSCR_NZCV, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,388 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31];389 let DecoderMethod = "DecodeLazyLoadStoreMul";390}391 392def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>,393 Requires<[HasFPRegs]>;394def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>,395 Requires<[HasFPRegs]>;396def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>,397 Requires<[HasFPRegs]>;398def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>,399 Requires<[HasFPRegs]>;400defm : VFPDTAnyInstAlias<"vpush${p}", "$r",401 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;402defm : VFPDTAnyInstAlias<"vpush${p}", "$r",403 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;404defm : VFPDTAnyInstAlias<"vpop${p}", "$r",405 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;406defm : VFPDTAnyInstAlias<"vpop${p}", "$r",407 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;408 409// FLDMX, FSTMX - Load and store multiple unknown precision registers for410// pre-armv6 cores.411// These instruction are deprecated so we don't want them to get selected.412// However, there is no UAL syntax for them, so we keep them around for413// (dis)assembly only.414multiclass vfp_ldstx_mult<string asm, bit L_bit> {415 let Predicates = [HasFPRegs], hasNoSchedulingInfo = 1 in {416 // Unknown precision417 def XIA :418 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),419 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {420 let Inst{24-23} = 0b01; // Increment After421 let Inst{21} = 0; // No writeback422 let Inst{20} = L_bit;423 }424 def XIA_UPD :425 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),426 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {427 let Inst{24-23} = 0b01; // Increment After428 let Inst{21} = 1; // Writeback429 let Inst{20} = L_bit;430 }431 def XDB_UPD :432 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),433 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {434 let Inst{24-23} = 0b10; // Decrement Before435 let Inst{21} = 1; // Writeback436 let Inst{20} = L_bit;437 }438 }439}440 441defm FLDM : vfp_ldstx_mult<"fldm", 1>;442defm FSTM : vfp_ldstx_mult<"fstm", 0>;443 444def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;445def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;446 447def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;448def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;449 450//===----------------------------------------------------------------------===//451// FP Binary Operations.452//453 454let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in455def VADDD : ADbI<0b11100, 0b11, 0, 0,456 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),457 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",458 [(set DPR:$Dd, (any_fadd DPR:$Dn, (f64 DPR:$Dm)))]>,459 Sched<[WriteFPALU64]>;460 461let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in462def VADDS : ASbIn<0b11100, 0b11, 0, 0,463 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),464 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",465 [(set SPR:$Sd, (any_fadd SPR:$Sn, SPR:$Sm))]>,466 Sched<[WriteFPALU32]> {467 // Some single precision VFP instructions may be executed on both NEON and468 // VFP pipelines on A8.469 let D = VFPNeonA8Domain;470}471 472let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in473def VADDH : AHbI<0b11100, 0b11, 0, 0,474 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),475 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",476 [(set (f16 HPR:$Sd), (any_fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,477 Sched<[WriteFPALU32]>;478 479let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in480def VSUBD : ADbI<0b11100, 0b11, 1, 0,481 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),482 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",483 [(set DPR:$Dd, (any_fsub DPR:$Dn, (f64 DPR:$Dm)))]>,484 Sched<[WriteFPALU64]>;485 486let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in487def VSUBS : ASbIn<0b11100, 0b11, 1, 0,488 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),489 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",490 [(set SPR:$Sd, (any_fsub SPR:$Sn, SPR:$Sm))]>,491 Sched<[WriteFPALU32]>{492 // Some single precision VFP instructions may be executed on both NEON and493 // VFP pipelines on A8.494 let D = VFPNeonA8Domain;495}496 497let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in498def VSUBH : AHbI<0b11100, 0b11, 1, 0,499 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),500 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",501 [(set (f16 HPR:$Sd), (any_fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,502 Sched<[WriteFPALU32]>;503 504let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in505def VDIVD : ADbI<0b11101, 0b00, 0, 0,506 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),507 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",508 [(set DPR:$Dd, (any_fdiv DPR:$Dn, (f64 DPR:$Dm)))]>,509 Sched<[WriteFPDIV64]>;510 511let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in512def VDIVS : ASbI<0b11101, 0b00, 0, 0,513 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),514 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",515 [(set SPR:$Sd, (any_fdiv SPR:$Sn, SPR:$Sm))]>,516 Sched<[WriteFPDIV32]>;517 518let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in519def VDIVH : AHbI<0b11101, 0b00, 0, 0,520 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),521 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",522 [(set (f16 HPR:$Sd), (any_fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,523 Sched<[WriteFPDIV32]>;524 525let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in526def VMULD : ADbI<0b11100, 0b10, 0, 0,527 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),528 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",529 [(set DPR:$Dd, (any_fmul DPR:$Dn, (f64 DPR:$Dm)))]>,530 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>;531 532let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in533def VMULS : ASbIn<0b11100, 0b10, 0, 0,534 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),535 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",536 [(set SPR:$Sd, (any_fmul SPR:$Sn, SPR:$Sm))]>,537 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> {538 // Some single precision VFP instructions may be executed on both NEON and539 // VFP pipelines on A8.540 let D = VFPNeonA8Domain;541}542 543let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in544def VMULH : AHbI<0b11100, 0b10, 0, 0,545 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),546 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",547 [(set (f16 HPR:$Sd), (any_fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,548 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>;549 550let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in551def VNMULD : ADbI<0b11100, 0b10, 1, 0,552 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),553 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",554 [(set DPR:$Dd, (fneg (any_fmul DPR:$Dn, (f64 DPR:$Dm))))]>,555 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>;556 557let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in558def VNMULS : ASbI<0b11100, 0b10, 1, 0,559 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),560 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",561 [(set SPR:$Sd, (fneg (any_fmul SPR:$Sn, SPR:$Sm)))]>,562 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> {563 // Some single precision VFP instructions may be executed on both NEON and564 // VFP pipelines on A8.565 let D = VFPNeonA8Domain;566}567 568let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in569def VNMULH : AHbI<0b11100, 0b10, 1, 0,570 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),571 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",572 [(set (f16 HPR:$Sd), (fneg (any_fmul (f16 HPR:$Sn), (f16 HPR:$Sm))))]>,573 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>;574 575multiclass vsel_inst<string op, bits<2> opc, int CC> {576 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",577 Uses = [CPSR], AddedComplexity = 4, isUnpredicable = 1 in {578 def H : AHbInp<0b11100, opc, 0,579 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),580 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),581 [(set (f16 HPR:$Sd),582 (ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC, CPSR))]>,583 Requires<[HasFullFP16]>;584 585 def S : ASbInp<0b11100, opc, 0,586 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),587 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),588 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC, CPSR))]>,589 Requires<[HasFPARMv8]>;590 591 def D : ADbInp<0b11100, opc, 0,592 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),593 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),594 [(set DPR:$Dd,595 (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC, CPSR))]>,596 Requires<[HasFPARMv8, HasDPVFP]>;597 }598}599 600// The CC constants here match ARMCC::CondCodes.601defm VSELGT : vsel_inst<"gt", 0b11, 12>;602defm VSELGE : vsel_inst<"ge", 0b10, 10>;603defm VSELEQ : vsel_inst<"eq", 0b00, 0>;604defm VSELVS : vsel_inst<"vs", 0b01, 6>;605 606multiclass vmaxmin_inst<string op, bit opc, PatFrags SD> {607 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",608 isUnpredicable = 1, mayRaiseFPException = 1 in {609 def H : AHbInp<0b11101, 0b00, opc,610 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),611 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),612 [(set (f16 HPR:$Sd), (SD (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,613 Requires<[HasFullFP16]>;614 615 def S : ASbInp<0b11101, 0b00, opc,616 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),617 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),618 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,619 Requires<[HasFPARMv8]>;620 621 def D : ADbInp<0b11101, 0b00, opc,622 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),623 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),624 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,625 Requires<[HasFPARMv8, HasDPVFP]>;626 }627}628 629defm VFP_VMAXNM : vmaxmin_inst<"vmaxnm", 0, any_fmaxnum>;630defm VFP_VMINNM : vmaxmin_inst<"vminnm", 1, any_fminnum>;631 632// Match reassociated forms only if not sign dependent rounding.633def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),634 (VNMULD DPR:$a, DPR:$b)>,635 Requires<[NoHonorSignDependentRounding,HasDPVFP]>;636def : Pat<(fmul (fneg SPR:$a), SPR:$b),637 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;638 639// These are encoded as unary instructions.640let Defs = [FPSCR_NZCV], mayRaiseFPException = 1, Uses = [FPSCR_RM] in {641def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,642 (outs), (ins DPR:$Dd, DPR:$Dm),643 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", "",644 [(set FPSCR_NZCV, (arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm)))]>;645 646def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,647 (outs), (ins SPR:$Sd, SPR:$Sm),648 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", "",649 [(set FPSCR_NZCV, (arm_cmpfpe SPR:$Sd, SPR:$Sm))]> {650 // Some single precision VFP instructions may be executed on both NEON and651 // VFP pipelines on A8.652 let D = VFPNeonA8Domain;653}654 655def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,656 (outs), (ins HPR:$Sd, HPR:$Sm),657 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",658 [(set FPSCR_NZCV, (arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm)))]>;659 660def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,661 (outs), (ins DPR:$Dd, DPR:$Dm),662 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", "",663 [(set FPSCR_NZCV, (arm_cmpfp DPR:$Dd, (f64 DPR:$Dm)))]>;664 665def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,666 (outs), (ins SPR:$Sd, SPR:$Sm),667 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", "",668 [(set FPSCR_NZCV, (arm_cmpfp SPR:$Sd, SPR:$Sm))]> {669 // Some single precision VFP instructions may be executed on both NEON and670 // VFP pipelines on A8.671 let D = VFPNeonA8Domain;672}673 674def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0,675 (outs), (ins HPR:$Sd, HPR:$Sm),676 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",677 [(set FPSCR_NZCV, (arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm)))]>;678} // Defs = [FPSCR_NZCV]679 680//===----------------------------------------------------------------------===//681// FP Unary Operations.682//683 684def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,685 (outs DPR:$Dd), (ins DPR:$Dm),686 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", "",687 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;688 689def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,690 (outs SPR:$Sd), (ins SPR:$Sm),691 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",692 [(set SPR:$Sd, (fabs SPR:$Sm))]> {693 // Some single precision VFP instructions may be executed on both NEON and694 // VFP pipelines on A8.695 let D = VFPNeonA8Domain;696}697 698def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0,699 (outs HPR:$Sd), (ins HPR:$Sm),700 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm",701 [(set (f16 HPR:$Sd), (fabs (f16 HPR:$Sm)))]>;702 703let Defs = [FPSCR_NZCV], mayRaiseFPException = 1, Uses = [FPSCR_RM] in {704def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,705 (outs), (ins DPR:$Dd),706 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", "",707 [(set FPSCR_NZCV, (arm_cmpfpe0 (f64 DPR:$Dd)))]> {708 let Inst{3-0} = 0b0000;709 let Inst{5} = 0;710}711 712def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,713 (outs), (ins SPR:$Sd),714 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", "",715 [(set FPSCR_NZCV, (arm_cmpfpe0 SPR:$Sd))]> {716 let Inst{3-0} = 0b0000;717 let Inst{5} = 0;718 719 // Some single precision VFP instructions may be executed on both NEON and720 // VFP pipelines on A8.721 let D = VFPNeonA8Domain;722}723 724def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,725 (outs), (ins HPR:$Sd),726 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",727 [(set FPSCR_NZCV, (arm_cmpfpe0 (f16 HPR:$Sd)))]> {728 let Inst{3-0} = 0b0000;729 let Inst{5} = 0;730}731 732def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,733 (outs), (ins DPR:$Dd),734 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", "",735 [(set FPSCR_NZCV, (arm_cmpfp0 (f64 DPR:$Dd)))]> {736 let Inst{3-0} = 0b0000;737 let Inst{5} = 0;738}739 740def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,741 (outs), (ins SPR:$Sd),742 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", "",743 [(set FPSCR_NZCV, (arm_cmpfp0 SPR:$Sd))]> {744 let Inst{3-0} = 0b0000;745 let Inst{5} = 0;746 747 // Some single precision VFP instructions may be executed on both NEON and748 // VFP pipelines on A8.749 let D = VFPNeonA8Domain;750}751 752def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,753 (outs), (ins HPR:$Sd),754 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",755 [(set FPSCR_NZCV, (arm_cmpfp0 (f16 HPR:$Sd)))]> {756 let Inst{3-0} = 0b0000;757 let Inst{5} = 0;758}759} // Defs = [FPSCR_NZCV]760 761let mayRaiseFPException = 1, Uses = [FPSCR_RM] in762def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,763 (outs DPR:$Dd), (ins SPR:$Sm),764 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", "",765 [(set DPR:$Dd, (any_fpextend SPR:$Sm))]>,766 Sched<[WriteFPCVT]> {767 // Instruction operands.768 bits<5> Dd;769 bits<5> Sm;770 771 // Encode instruction operands.772 let Inst{3-0} = Sm{4-1};773 let Inst{5} = Sm{0};774 let Inst{15-12} = Dd{3-0};775 let Inst{22} = Dd{4};776 777 let Predicates = [HasVFP2, HasDPVFP];778 let hasSideEffects = 0;779}780 781// Special case encoding: bits 11-8 is 0b1011.782let mayRaiseFPException = 1, Uses = [FPSCR_RM] in783def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,784 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", "",785 [(set SPR:$Sd, (any_fpround DPR:$Dm))]>,786 Sched<[WriteFPCVT]> {787 // Instruction operands.788 bits<5> Sd;789 bits<5> Dm;790 791 // Encode instruction operands.792 let Inst{3-0} = Dm{3-0};793 let Inst{5} = Dm{4};794 let Inst{15-12} = Sd{4-1};795 let Inst{22} = Sd{0};796 797 let Inst{27-23} = 0b11101;798 let Inst{21-16} = 0b110111;799 let Inst{11-8} = 0b1011;800 let Inst{7-6} = 0b11;801 let Inst{4} = 0;802 803 let Predicates = [HasVFP2, HasDPVFP];804 let hasSideEffects = 0;805}806 807// Between half, single and double-precision.808let hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPSCR_RM] in809def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),810 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", "",811 [/* Intentionally left blank, see patterns below */]>,812 Requires<[HasFP16]>,813 Sched<[WriteFPCVT]>;814 815def : FP16Pat<(f32 (any_fpextend (f16 HPR:$Sm))),816 (VCVTBHS (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>;817def : FP16Pat<(any_f16_to_fp GPR:$a),818 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;819 820let hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPSCR_RM] in821def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),822 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda",823 [/* Intentionally left blank, see patterns below */]>,824 Requires<[HasFP16]>,825 Sched<[WriteFPCVT]>;826 827def : FP16Pat<(f16 (any_fpround SPR:$Sm)),828 (COPY_TO_REGCLASS (VCVTBSH (IMPLICIT_DEF), SPR:$Sm), HPR)>;829def : FP16Pat<(any_fp_to_f16 SPR:$a),830 (i32 (COPY_TO_REGCLASS (VCVTBSH (IMPLICIT_DEF), SPR:$a), GPR))>;831def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (any_fpround (f32 SPR:$src2))), imm_even:$lane),832 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1),833 (VCVTBSH (EXTRACT_SUBREG (v8f16 MQPR:$src1), (SSubReg_f16_reg imm:$lane)),834 SPR:$src2),835 (SSubReg_f16_reg imm:$lane)))>;836def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (any_fpround (f32 SPR:$src2))), imm_even:$lane),837 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1),838 (VCVTBSH (EXTRACT_SUBREG (v4f16 DPR:$src1), (SSubReg_f16_reg imm:$lane)),839 SPR:$src2),840 (SSubReg_f16_reg imm:$lane)))>;841 842let hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPSCR_RM] in843def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),844 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", "",845 [/* Intentionally left blank, see patterns below */]>,846 Requires<[HasFP16]>,847 Sched<[WriteFPCVT]>;848 849def : FP16Pat<(f32 (any_fpextend (extractelt (v8f16 MQPR:$src), imm_odd:$lane))),850 (VCVTTHS (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane)))>;851def : FP16Pat<(f32 (any_fpextend (extractelt (v4f16 DPR:$src), imm_odd:$lane))),852 (VCVTTHS (EXTRACT_SUBREG853 (v2f32 (COPY_TO_REGCLASS (v4f16 DPR:$src), DPR_VFP2)),854 (SSubReg_f16_reg imm_odd:$lane)))>;855 856let hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPSCR_RM] in857def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),858 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda",859 [/* Intentionally left blank, see patterns below */]>,860 Requires<[HasFP16]>,861 Sched<[WriteFPCVT]>;862 863def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (any_fpround (f32 SPR:$src2))), imm_odd:$lane),864 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1),865 (VCVTTSH (EXTRACT_SUBREG (v8f16 MQPR:$src1), (SSubReg_f16_reg imm:$lane)),866 SPR:$src2),867 (SSubReg_f16_reg imm:$lane)))>;868def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (any_fpround (f32 SPR:$src2))), imm_odd:$lane),869 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1),870 (VCVTTSH (EXTRACT_SUBREG (v4f16 DPR:$src1), (SSubReg_f16_reg imm:$lane)),871 SPR:$src2),872 (SSubReg_f16_reg imm:$lane)))>;873 874let mayRaiseFPException = 1, Uses = [FPSCR_RM] in 875def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,876 (outs DPR:$Dd), (ins SPR:$Sm),877 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", "",878 [/* Intentionally left blank, see patterns below */]>,879 Requires<[HasFPARMv8, HasDPVFP]>,880 Sched<[WriteFPCVT]> {881 // Instruction operands.882 bits<5> Sm;883 884 // Encode instruction operands.885 let Inst{3-0} = Sm{4-1};886 let Inst{5} = Sm{0};887 888 let hasSideEffects = 0;889}890 891def : FullFP16Pat<(f64 (any_fpextend (f16 HPR:$Sm))),892 (VCVTBHD (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>,893 Requires<[HasFPARMv8, HasDPVFP]>;894def : FP16Pat<(f64 (any_f16_to_fp GPR:$a)),895 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,896 Requires<[HasFPARMv8, HasDPVFP]>;897 898let mayRaiseFPException = 1, Uses = [FPSCR_RM] in899def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,900 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),901 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",902 [/* Intentionally left blank, see patterns below */]>,903 Requires<[HasFPARMv8, HasDPVFP]> {904 // Instruction operands.905 bits<5> Sd;906 bits<5> Dm;907 908 // Encode instruction operands.909 let Inst{3-0} = Dm{3-0};910 let Inst{5} = Dm{4};911 let Inst{15-12} = Sd{4-1};912 let Inst{22} = Sd{0};913 914 let hasSideEffects = 0;915}916 917def : FullFP16Pat<(f16 (any_fpround DPR:$Dm)),918 (COPY_TO_REGCLASS (VCVTBDH (IMPLICIT_DEF), DPR:$Dm), HPR)>,919 Requires<[HasFPARMv8, HasDPVFP]>;920def : FP16Pat<(any_fp_to_f16 (f64 DPR:$a)),921 (i32 (COPY_TO_REGCLASS (VCVTBDH (IMPLICIT_DEF), DPR:$a), GPR))>,922 Requires<[HasFPARMv8, HasDPVFP]>;923 924let mayRaiseFPException = 1, Uses = [FPSCR_RM] in925def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,926 (outs DPR:$Dd), (ins SPR:$Sm),927 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", "",928 []>, Requires<[HasFPARMv8, HasDPVFP]> {929 // Instruction operands.930 bits<5> Sm;931 932 // Encode instruction operands.933 let Inst{3-0} = Sm{4-1};934 let Inst{5} = Sm{0};935 936 let hasSideEffects = 0;937}938 939let mayRaiseFPException = 1, Uses = [FPSCR_RM] in940def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,941 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),942 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",943 []>, Requires<[HasFPARMv8, HasDPVFP]> {944 // Instruction operands.945 bits<5> Sd;946 bits<5> Dm;947 948 // Encode instruction operands.949 let Inst{15-12} = Sd{4-1};950 let Inst{22} = Sd{0};951 let Inst{3-0} = Dm{3-0};952 let Inst{5} = Dm{4};953 954 let hasSideEffects = 0;955}956 957multiclass vcvt_inst<string opc, bits<2> rm,958 SDPatternOperator node = null_frag> {959 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", hasSideEffects = 0, 960 mayRaiseFPException = 1 in {961 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,962 (outs SPR:$Sd), (ins HPR:$Sm),963 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),964 []>,965 Requires<[HasFullFP16]> {966 let Inst{17-16} = rm;967 }968 969 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,970 (outs SPR:$Sd), (ins HPR:$Sm),971 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),972 []>,973 Requires<[HasFullFP16]> {974 let Inst{17-16} = rm;975 }976 977 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,978 (outs SPR:$Sd), (ins SPR:$Sm),979 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),980 []>,981 Requires<[HasFPARMv8]> {982 let Inst{17-16} = rm;983 }984 985 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,986 (outs SPR:$Sd), (ins SPR:$Sm),987 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),988 []>,989 Requires<[HasFPARMv8]> {990 let Inst{17-16} = rm;991 }992 993 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,994 (outs SPR:$Sd), (ins DPR:$Dm),995 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),996 []>,997 Requires<[HasFPARMv8, HasDPVFP]> {998 bits<5> Dm;999 1000 let Inst{17-16} = rm;1001 1002 // Encode instruction operands.1003 let Inst{3-0} = Dm{3-0};1004 let Inst{5} = Dm{4};1005 let Inst{8} = 1;1006 }1007 1008 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,1009 (outs SPR:$Sd), (ins DPR:$Dm),1010 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),1011 []>,1012 Requires<[HasFPARMv8, HasDPVFP]> {1013 bits<5> Dm;1014 1015 let Inst{17-16} = rm;1016 1017 // Encode instruction operands1018 let Inst{3-0} = Dm{3-0};1019 let Inst{5} = Dm{4};1020 let Inst{8} = 1;1021 }1022 }1023 1024 let Predicates = [HasFPARMv8] in {1025 let Predicates = [HasFullFP16] in {1026 def : Pat<(i32 (any_fp_to_sint (node (f16 HPR:$a)))),1027 (COPY_TO_REGCLASS1028 (!cast<Instruction>(NAME#"SH") (f16 HPR:$a)),1029 GPR)>;1030 1031 def : Pat<(i32 (any_fp_to_uint (node (f16 HPR:$a)))),1032 (COPY_TO_REGCLASS1033 (!cast<Instruction>(NAME#"UH") (f16 HPR:$a)),1034 GPR)>;1035 }1036 def : Pat<(i32 (any_fp_to_sint (node SPR:$a))),1037 (COPY_TO_REGCLASS1038 (!cast<Instruction>(NAME#"SS") SPR:$a),1039 GPR)>;1040 def : Pat<(i32 (any_fp_to_uint (node SPR:$a))),1041 (COPY_TO_REGCLASS1042 (!cast<Instruction>(NAME#"US") SPR:$a),1043 GPR)>;1044 }1045 let Predicates = [HasFPARMv8, HasDPVFP] in {1046 def : Pat<(i32 (any_fp_to_sint (node (f64 DPR:$a)))),1047 (COPY_TO_REGCLASS1048 (!cast<Instruction>(NAME#"SD") DPR:$a),1049 GPR)>;1050 def : Pat<(i32 (any_fp_to_uint (node (f64 DPR:$a)))),1051 (COPY_TO_REGCLASS1052 (!cast<Instruction>(NAME#"UD") DPR:$a),1053 GPR)>;1054 }1055}1056 1057defm VCVTA : vcvt_inst<"a", 0b00, any_fround>;1058defm VCVTN : vcvt_inst<"n", 0b01>;1059defm VCVTP : vcvt_inst<"p", 0b10, any_fceil>;1060defm VCVTM : vcvt_inst<"m", 0b11, any_ffloor>;1061 1062def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,1063 (outs DPR:$Dd), (ins DPR:$Dm),1064 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", "",1065 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;1066 1067def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,1068 (outs SPR:$Sd), (ins SPR:$Sm),1069 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",1070 [(set SPR:$Sd, (fneg SPR:$Sm))]> {1071 // Some single precision VFP instructions may be executed on both NEON and1072 // VFP pipelines on A8.1073 let D = VFPNeonA8Domain;1074}1075 1076def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,1077 (outs HPR:$Sd), (ins HPR:$Sm),1078 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",1079 [(set (f16 HPR:$Sd), (fneg (f16 HPR:$Sm)))]>;1080 1081multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node,1082 list<Register> uses = [], bit fpexc = 0> {1083 let Uses = uses, mayRaiseFPException = fpexc in {1084 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,1085 (outs HPR:$Sd), (ins HPR:$Sm),1086 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",1087 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,1088 Requires<[HasFullFP16]> {1089 let Inst{7} = op2;1090 let Inst{16} = op;1091 }1092 1093 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,1094 (outs SPR:$Sd), (ins SPR:$Sm),1095 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", "",1096 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,1097 Requires<[HasFPARMv8]> {1098 let Inst{7} = op2;1099 let Inst{16} = op;1100 }1101 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,1102 (outs DPR:$Dd), (ins DPR:$Dm),1103 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", "",1104 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,1105 Requires<[HasFPARMv8, HasDPVFP]> {1106 let Inst{7} = op2;1107 let Inst{16} = op;1108 }1109 }1110 1111 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"),1112 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,1113 Requires<[HasFullFP16]>;1114 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),1115 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,1116 Requires<[HasFPARMv8]>;1117 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),1118 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>,1119 Requires<[HasFPARMv8,HasDPVFP]>;1120}1121 1122defm VRINTZ : vrint_inst_zrx<"z", 0, 1, any_ftrunc, [], 0>;1123defm VRINTR : vrint_inst_zrx<"r", 0, 0, any_fnearbyint, [FPSCR_RM], 0>;1124defm VRINTX : vrint_inst_zrx<"x", 1, 0, any_frint, [FPSCR_RM], 1>;1125 1126multiclass vrint_inst_anpm<string opc, bits<2> rm,1127 SDPatternOperator node = null_frag> {1128 let PostEncoderMethod = "", DecoderNamespace = "VFPV8",1129 isUnpredicable = 1 in {1130 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,1131 (outs HPR:$Sd), (ins HPR:$Sm),1132 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),1133 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,1134 Requires<[HasFullFP16]> {1135 let Inst{17-16} = rm;1136 }1137 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,1138 (outs SPR:$Sd), (ins SPR:$Sm),1139 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),1140 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,1141 Requires<[HasFPARMv8]> {1142 let Inst{17-16} = rm;1143 }1144 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,1145 (outs DPR:$Dd), (ins DPR:$Dm),1146 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),1147 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,1148 Requires<[HasFPARMv8, HasDPVFP]> {1149 let Inst{17-16} = rm;1150 }1151 }1152 1153 def : InstAlias<!strconcat("vrint", opc, ".f16.f16\t$Sd, $Sm"),1154 (!cast<Instruction>(NAME#"H") HPR:$Sd, HPR:$Sm), 0>,1155 Requires<[HasFullFP16]>;1156 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),1157 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,1158 Requires<[HasFPARMv8]>;1159 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),1160 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>,1161 Requires<[HasFPARMv8,HasDPVFP]>;1162}1163 1164defm VRINTA : vrint_inst_anpm<"a", 0b00, any_fround>;1165defm VRINTN : vrint_inst_anpm<"n", 0b01, any_froundeven>;1166defm VRINTP : vrint_inst_anpm<"p", 0b10, any_fceil>;1167defm VRINTM : vrint_inst_anpm<"m", 0b11, any_ffloor>;1168 1169 1170let mayRaiseFPException = 1, Uses = [FPSCR_RM] in1171def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,1172 (outs DPR:$Dd), (ins DPR:$Dm),1173 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", "",1174 [(set DPR:$Dd, (any_fsqrt (f64 DPR:$Dm)))]>,1175 Sched<[WriteFPSQRT64]>;1176 1177let mayRaiseFPException = 1, Uses = [FPSCR_RM] in1178def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,1179 (outs SPR:$Sd), (ins SPR:$Sm),1180 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", "",1181 [(set SPR:$Sd, (any_fsqrt SPR:$Sm))]>,1182 Sched<[WriteFPSQRT32]>;1183 1184let mayRaiseFPException = 1, Uses = [FPSCR_RM] in1185def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,1186 (outs HPR:$Sd), (ins HPR:$Sm),1187 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",1188 [(set (f16 HPR:$Sd), (any_fsqrt (f16 HPR:$Sm)))]>;1189 1190let hasSideEffects = 0 in {1191let isMoveReg = 1 in {1192def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,1193 (outs DPR:$Dd), (ins DPR:$Dm),1194 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", "", []>,1195 Requires<[HasFPRegs64]>;1196 1197def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,1198 (outs SPR:$Sd), (ins SPR:$Sm),1199 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", "", []>,1200 Requires<[HasFPRegs]>;1201} // isMoveReg1202 1203let PostEncoderMethod = "", DecoderNamespace = "VFPV8", isUnpredicable = 1 in {1204def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0,1205 (outs SPR:$Sd), (ins SPR:$Sm),1206 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,1207 Requires<[HasFullFP16]>;1208 1209def VINSH : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0,1210 (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),1211 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,1212 Requires<[HasFullFP16]> {1213 let Constraints = "$Sd = $Sda";1214}1215 1216} // PostEncoderMethod1217} // hasSideEffects1218 1219//===----------------------------------------------------------------------===//1220// FP <-> GPR Copies. Int <-> FP Conversions.1221//1222 1223let isMoveReg = 1 in {1224def VMOVRS : AVConv2I<0b11100001, 0b1010,1225 (outs GPR:$Rt), (ins SPR:$Sn),1226 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",1227 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>,1228 Requires<[HasFPRegs]>,1229 Sched<[WriteFPMOV]> {1230 // Instruction operands.1231 bits<4> Rt;1232 bits<5> Sn;1233 1234 // Encode instruction operands.1235 let Inst{19-16} = Sn{4-1};1236 let Inst{7} = Sn{0};1237 let Inst{15-12} = Rt;1238 1239 let Inst{6-5} = 0b00;1240 let Inst{3-0} = 0b0000;1241 1242 // Some single precision VFP instructions may be executed on both NEON and VFP1243 // pipelines.1244 let D = VFPNeonDomain;1245}1246 1247// Bitcast i32 -> f32. NEON prefers to use VMOVDRR.1248def VMOVSR : AVConv4I<0b11100000, 0b1010,1249 (outs SPR:$Sn), (ins GPR:$Rt),1250 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",1251 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,1252 Requires<[HasFPRegs, UseVMOVSR]>,1253 Sched<[WriteFPMOV]> {1254 // Instruction operands.1255 bits<5> Sn;1256 bits<4> Rt;1257 1258 // Encode instruction operands.1259 let Inst{19-16} = Sn{4-1};1260 let Inst{7} = Sn{0};1261 let Inst{15-12} = Rt;1262 1263 let Inst{6-5} = 0b00;1264 let Inst{3-0} = 0b0000;1265 1266 // Some single precision VFP instructions may be executed on both NEON and VFP1267 // pipelines.1268 let D = VFPNeonDomain;1269}1270} // isMoveReg1271def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasFPRegs, UseVMOVSR]>;1272 1273let hasSideEffects = 0 in {1274def VMOVRRD : AVConv3I<0b11000101, 0b1011,1275 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),1276 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",1277 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,1278 Requires<[HasFPRegs]>,1279 Sched<[WriteFPMOV]> {1280 // Instruction operands.1281 bits<5> Dm;1282 bits<4> Rt;1283 bits<4> Rt2;1284 1285 // Encode instruction operands.1286 let Inst{3-0} = Dm{3-0};1287 let Inst{5} = Dm{4};1288 let Inst{15-12} = Rt;1289 let Inst{19-16} = Rt2;1290 1291 let Inst{7-6} = 0b00;1292 1293 // Some single precision VFP instructions may be executed on both NEON and VFP1294 // pipelines.1295 let D = VFPNeonDomain;1296 1297 // This instruction is equivalent to1298 // $Rt = EXTRACT_SUBREG $Dm, ssub_01299 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_11300 let isExtractSubreg = 1;1301}1302 1303def VMOVRRS : AVConv3I<0b11000101, 0b1010,1304 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),1305 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",1306 [/* For disassembly only; pattern left blank */]>,1307 Requires<[HasFPRegs]>,1308 Sched<[WriteFPMOV]> {1309 bits<5> src1;1310 bits<4> Rt;1311 bits<4> Rt2;1312 1313 // Encode instruction operands.1314 let Inst{3-0} = src1{4-1};1315 let Inst{5} = src1{0};1316 let Inst{15-12} = Rt;1317 let Inst{19-16} = Rt2;1318 1319 let Inst{7-6} = 0b00;1320 1321 // Some single precision VFP instructions may be executed on both NEON and VFP1322 // pipelines.1323 let D = VFPNeonDomain;1324 let DecoderMethod = "DecodeVMOVRRS";1325}1326} // hasSideEffects1327 1328// FMDHR: GPR -> SPR1329// FMDLR: GPR -> SPR1330 1331def VMOVDRR : AVConv5I<0b11000100, 0b1011,1332 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),1333 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",1334 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]>,1335 Requires<[HasFPRegs]>,1336 Sched<[WriteFPMOV]> {1337 // Instruction operands.1338 bits<5> Dm;1339 bits<4> Rt;1340 bits<4> Rt2;1341 1342 // Encode instruction operands.1343 let Inst{3-0} = Dm{3-0};1344 let Inst{5} = Dm{4};1345 let Inst{15-12} = Rt;1346 let Inst{19-16} = Rt2;1347 1348 let Inst{7-6} = 0b00;1349 1350 // Some single precision VFP instructions may be executed on both NEON and VFP1351 // pipelines.1352 let D = VFPNeonDomain;1353 1354 // This instruction is equivalent to1355 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_11356 let isRegSequence = 1;1357}1358 1359// Hoist an fabs or a fneg of a value coming from integer registers1360// and do the fabs/fneg on the integer value. This is never a lose1361// and could enable the conversion to float to be removed completely.1362def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),1363 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,1364 Requires<[IsARM, HasV6T2]>;1365def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),1366 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,1367 Requires<[IsThumb2, HasV6T2]>;1368def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),1369 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,1370 Requires<[IsARM]>;1371def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),1372 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,1373 Requires<[IsThumb2]>;1374 1375let hasSideEffects = 0 in1376def VMOVSRR : AVConv5I<0b11000100, 0b1010,1377 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),1378 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",1379 [/* For disassembly only; pattern left blank */]>,1380 Requires<[HasFPRegs]>,1381 Sched<[WriteFPMOV]> {1382 // Instruction operands.1383 bits<5> dst1;1384 bits<4> src1;1385 bits<4> src2;1386 1387 // Encode instruction operands.1388 let Inst{3-0} = dst1{4-1};1389 let Inst{5} = dst1{0};1390 let Inst{15-12} = src1;1391 let Inst{19-16} = src2;1392 1393 let Inst{7-6} = 0b00;1394 1395 // Some single precision VFP instructions may be executed on both NEON and VFP1396 // pipelines.1397 let D = VFPNeonDomain;1398 1399 let DecoderMethod = "DecodeVMOVSRR";1400}1401 1402// Move H->R, clearing top 16 bits1403def VMOVRH : AVConv2I<0b11100001, 0b1001,1404 (outs rGPR:$Rt), (ins HPR:$Sn),1405 IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn",1406 []>,1407 Requires<[HasFPRegs16]>,1408 Sched<[WriteFPMOV]> {1409 // Instruction operands.1410 bits<4> Rt;1411 bits<5> Sn;1412 1413 // Encode instruction operands.1414 let Inst{19-16} = Sn{4-1};1415 let Inst{7} = Sn{0};1416 let Inst{15-12} = Rt;1417 1418 let Inst{6-5} = 0b00;1419 let Inst{3-0} = 0b0000;1420 1421 let isUnpredicable = 1;1422}1423 1424// Move R->H, clearing top 16 bits1425def VMOVHR : AVConv4I<0b11100000, 0b1001,1426 (outs HPR:$Sn), (ins rGPR:$Rt),1427 IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt",1428 []>,1429 Requires<[HasFPRegs16]>,1430 Sched<[WriteFPMOV]> {1431 // Instruction operands.1432 bits<5> Sn;1433 bits<4> Rt;1434 1435 // Encode instruction operands.1436 let Inst{19-16} = Sn{4-1};1437 let Inst{7} = Sn{0};1438 let Inst{15-12} = Rt;1439 1440 let Inst{6-5} = 0b00;1441 let Inst{3-0} = 0b0000;1442 1443 let isUnpredicable = 1;1444}1445 1446def : FPRegs16Pat<(arm_vmovrh (f16 HPR:$Sn)), (VMOVRH (f16 HPR:$Sn))>;1447def : FPRegs16Pat<(arm_vmovrh (bf16 HPR:$Sn)), (VMOVRH (bf16 HPR:$Sn))>;1448def : FPRegs16Pat<(f16 (arm_vmovhr rGPR:$Rt)), (VMOVHR rGPR:$Rt)>;1449def : FPRegs16Pat<(bf16 (arm_vmovhr rGPR:$Rt)), (VMOVHR rGPR:$Rt)>;1450 1451// FMRDH: SPR -> GPR1452// FMRDL: SPR -> GPR1453// FMRRS: SPR -> GPR1454// FMRX: SPR system reg -> GPR1455// FMSRR: GPR -> SPR1456// FMXR: GPR -> VFP system reg1457 1458 1459// Int -> FP:1460 1461class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,1462 bits<4> opcod4, dag oops, dag iops,1463 InstrItinClass itin, string opc, string asm,1464 list<dag> pattern>1465 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,1466 pattern> {1467 // Instruction operands.1468 bits<5> Dd;1469 bits<5> Sm;1470 1471 // Encode instruction operands.1472 let Inst{3-0} = Sm{4-1};1473 let Inst{5} = Sm{0};1474 let Inst{15-12} = Dd{3-0};1475 let Inst{22} = Dd{4};1476 1477 let Predicates = [HasVFP2, HasDPVFP];1478 let hasSideEffects = 0;1479}1480 1481class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,1482 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,1483 string opc, string asm, list<dag> pattern>1484 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,1485 pattern> {1486 // Instruction operands.1487 bits<5> Sd;1488 bits<5> Sm;1489 1490 // Encode instruction operands.1491 let Inst{3-0} = Sm{4-1};1492 let Inst{5} = Sm{0};1493 let Inst{15-12} = Sd{4-1};1494 let Inst{22} = Sd{0};1495 1496 let hasSideEffects = 0;1497}1498 1499class AVConv1IHs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,1500 bits<4> opcod4, dag oops, dag iops,1501 InstrItinClass itin, string opc, string asm,1502 list<dag> pattern>1503 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,1504 pattern> {1505 // Instruction operands.1506 bits<5> Sd;1507 bits<5> Sm;1508 1509 // Encode instruction operands.1510 let Inst{3-0} = Sm{4-1};1511 let Inst{5} = Sm{0};1512 let Inst{15-12} = Sd{4-1};1513 let Inst{22} = Sd{0};1514 1515 let Predicates = [HasFullFP16];1516 let hasSideEffects = 0;1517}1518 1519let mayRaiseFPException = 1 in 1520def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,1521 (outs DPR:$Dd), (ins SPR:$Sm),1522 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",1523 []>,1524 Sched<[WriteFPCVT]> {1525 let Inst{7} = 1; // s321526}1527 1528let Predicates=[HasVFP2, HasDPVFP] in {1529 def : VFPPat<(f64 (any_sint_to_fp GPR:$a)),1530 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;1531 1532 def : VFPPat<(f64 (any_sint_to_fp (i32 (alignedload32 addrmode5:$a)))),1533 (VSITOD (VLDRS addrmode5:$a))>;1534}1535 1536let mayRaiseFPException = 1 in 1537def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,1538 (outs SPR:$Sd),(ins SPR:$Sm),1539 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",1540 []>,1541 Sched<[WriteFPCVT]> {1542 let Inst{7} = 1; // s321543 1544 // Some single precision VFP instructions may be executed on both NEON and1545 // VFP pipelines on A8.1546 let D = VFPNeonA8Domain;1547}1548 1549def : VFPNoNEONPat<(f32 (any_sint_to_fp GPR:$a)),1550 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;1551 1552def : VFPNoNEONPat<(f32 (any_sint_to_fp (i32 (alignedload32 addrmode5:$a)))),1553 (VSITOS (VLDRS addrmode5:$a))>;1554 1555let mayRaiseFPException = 1 in 1556def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,1557 (outs HPR:$Sd), (ins SPR:$Sm),1558 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",1559 []>,1560 Sched<[WriteFPCVT]> {1561 let Inst{7} = 1; // s321562 let isUnpredicable = 1;1563}1564 1565def : VFPNoNEONPat<(f16 (any_sint_to_fp GPR:$a)),1566 (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;1567 1568let mayRaiseFPException = 1 in 1569def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,1570 (outs DPR:$Dd), (ins SPR:$Sm),1571 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",1572 []>,1573 Sched<[WriteFPCVT]> {1574 let Inst{7} = 0; // u321575}1576 1577let Predicates=[HasVFP2, HasDPVFP] in {1578 def : VFPPat<(f64 (any_uint_to_fp GPR:$a)),1579 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;1580 1581 def : VFPPat<(f64 (any_uint_to_fp (i32 (alignedload32 addrmode5:$a)))),1582 (VUITOD (VLDRS addrmode5:$a))>;1583}1584 1585let mayRaiseFPException = 1 in 1586def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,1587 (outs SPR:$Sd), (ins SPR:$Sm),1588 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",1589 []>,1590 Sched<[WriteFPCVT]> {1591 let Inst{7} = 0; // u321592 1593 // Some single precision VFP instructions may be executed on both NEON and1594 // VFP pipelines on A8.1595 let D = VFPNeonA8Domain;1596}1597 1598def : VFPNoNEONPat<(f32 (any_uint_to_fp GPR:$a)),1599 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;1600 1601def : VFPNoNEONPat<(f32 (any_uint_to_fp (i32 (alignedload32 addrmode5:$a)))),1602 (VUITOS (VLDRS addrmode5:$a))>;1603 1604let mayRaiseFPException = 1 in 1605def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,1606 (outs HPR:$Sd), (ins SPR:$Sm),1607 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",1608 []>,1609 Sched<[WriteFPCVT]> {1610 let Inst{7} = 0; // u321611 let isUnpredicable = 1;1612}1613 1614def : VFPNoNEONPat<(f16 (any_uint_to_fp GPR:$a)),1615 (VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;1616 1617// FP -> Int:1618 1619class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,1620 bits<4> opcod4, dag oops, dag iops,1621 InstrItinClass itin, string opc, string asm,1622 list<dag> pattern>1623 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,1624 pattern> {1625 // Instruction operands.1626 bits<5> Sd;1627 bits<5> Dm;1628 1629 // Encode instruction operands.1630 let Inst{3-0} = Dm{3-0};1631 let Inst{5} = Dm{4};1632 let Inst{15-12} = Sd{4-1};1633 let Inst{22} = Sd{0};1634 1635 let Predicates = [HasVFP2, HasDPVFP];1636 let hasSideEffects = 0;1637}1638 1639class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,1640 bits<4> opcod4, dag oops, dag iops,1641 InstrItinClass itin, string opc, string asm,1642 list<dag> pattern>1643 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,1644 pattern> {1645 // Instruction operands.1646 bits<5> Sd;1647 bits<5> Sm;1648 1649 // Encode instruction operands.1650 let Inst{3-0} = Sm{4-1};1651 let Inst{5} = Sm{0};1652 let Inst{15-12} = Sd{4-1};1653 let Inst{22} = Sd{0};1654 1655 let hasSideEffects = 0;1656}1657 1658class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,1659 bits<4> opcod4, dag oops, dag iops,1660 InstrItinClass itin, string opc, string asm,1661 list<dag> pattern>1662 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,1663 pattern> {1664 // Instruction operands.1665 bits<5> Sd;1666 bits<5> Sm;1667 1668 // Encode instruction operands.1669 let Inst{3-0} = Sm{4-1};1670 let Inst{5} = Sm{0};1671 let Inst{15-12} = Sd{4-1};1672 let Inst{22} = Sd{0};1673 1674 let Predicates = [HasFullFP16];1675 let hasSideEffects = 0;1676}1677 1678// Always set Z bit in the instruction, i.e. "round towards zero" variants.1679let mayRaiseFPException = 1 in1680def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,1681 (outs SPR:$Sd), (ins DPR:$Dm),1682 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",1683 []>,1684 Sched<[WriteFPCVT]> {1685 let Inst{7} = 1; // Z bit1686}1687 1688let Predicates=[HasVFP2, HasDPVFP] in {1689 def : VFPPat<(i32 (any_fp_to_sint (f64 DPR:$a))),1690 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;1691 def : VFPPat<(i32 (fp_to_sint_sat (f64 DPR:$a), i32)),1692 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;1693 1694 def : VFPPat<(alignedstore32 (i32 (any_fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),1695 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;1696 def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f64 DPR:$a), i32)), addrmode5:$ptr),1697 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;1698}1699 1700let mayRaiseFPException = 1 in1701def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1702 (outs SPR:$Sd), (ins SPR:$Sm),1703 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",1704 []>,1705 Sched<[WriteFPCVT]> {1706 let Inst{7} = 1; // Z bit1707 1708 // Some single precision VFP instructions may be executed on both NEON and1709 // VFP pipelines on A8.1710 let D = VFPNeonA8Domain;1711}1712 1713def : VFPNoNEONPat<(i32 (any_fp_to_sint SPR:$a)),1714 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;1715def : VFPPat<(i32 (fp_to_sint_sat SPR:$a, i32)),1716 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;1717 1718def : VFPNoNEONPat<(alignedstore32 (i32 (any_fp_to_sint (f32 SPR:$a))),1719 addrmode5:$ptr),1720 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;1721def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f32 SPR:$a), i32)),1722 addrmode5:$ptr),1723 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;1724 1725let mayRaiseFPException = 1 in1726def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,1727 (outs SPR:$Sd), (ins HPR:$Sm),1728 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",1729 []>,1730 Sched<[WriteFPCVT]> {1731 let Inst{7} = 1; // Z bit1732 let isUnpredicable = 1;1733}1734 1735def : VFPNoNEONPat<(i32 (any_fp_to_sint (f16 HPR:$a))),1736 (COPY_TO_REGCLASS (VTOSIZH (f16 HPR:$a)), GPR)>;1737def : VFPPat<(i32 (fp_to_sint_sat (f16 HPR:$a), i32)),1738 (COPY_TO_REGCLASS (VTOSIZH (f16 HPR:$a)), GPR)>;1739 1740let mayRaiseFPException = 1 in1741def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,1742 (outs SPR:$Sd), (ins DPR:$Dm),1743 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",1744 []>,1745 Sched<[WriteFPCVT]> {1746 let Inst{7} = 1; // Z bit1747}1748 1749let Predicates=[HasVFP2, HasDPVFP] in {1750 def : VFPPat<(i32 (any_fp_to_uint (f64 DPR:$a))),1751 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;1752 def : VFPPat<(i32 (fp_to_uint_sat (f64 DPR:$a), i32)),1753 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;1754 1755 def : VFPPat<(alignedstore32 (i32 (any_fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),1756 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;1757 def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f64 DPR:$a), i32)), addrmode5:$ptr),1758 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;1759}1760 1761let mayRaiseFPException = 1 in1762def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,1763 (outs SPR:$Sd), (ins SPR:$Sm),1764 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",1765 []>,1766 Sched<[WriteFPCVT]> {1767 let Inst{7} = 1; // Z bit1768 1769 // Some single precision VFP instructions may be executed on both NEON and1770 // VFP pipelines on A8.1771 let D = VFPNeonA8Domain;1772}1773 1774def : VFPNoNEONPat<(i32 (any_fp_to_uint SPR:$a)),1775 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;1776def : VFPPat<(i32 (fp_to_uint_sat SPR:$a, i32)),1777 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;1778 1779def : VFPNoNEONPat<(alignedstore32 (i32 (any_fp_to_uint (f32 SPR:$a))),1780 addrmode5:$ptr),1781 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;1782def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f32 SPR:$a), i32)),1783 addrmode5:$ptr),1784 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;1785 1786let mayRaiseFPException = 1 in1787def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,1788 (outs SPR:$Sd), (ins HPR:$Sm),1789 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",1790 []>,1791 Sched<[WriteFPCVT]> {1792 let Inst{7} = 1; // Z bit1793 let isUnpredicable = 1;1794}1795 1796def : VFPNoNEONPat<(i32 (any_fp_to_uint (f16 HPR:$a))),1797 (COPY_TO_REGCLASS (VTOUIZH (f16 HPR:$a)), GPR)>;1798def : VFPPat<(i32 (fp_to_uint_sat (f16 HPR:$a), i32)),1799 (COPY_TO_REGCLASS (VTOUIZH (f16 HPR:$a)), GPR)>;1800 1801// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.1802let mayRaiseFPException = 1, Uses = [FPSCR_RM] in {1803def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,1804 (outs SPR:$Sd), (ins DPR:$Dm),1805 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",1806 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,1807 Sched<[WriteFPCVT]> {1808 let Inst{7} = 0; // Z bit1809}1810 1811def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,1812 (outs SPR:$Sd), (ins SPR:$Sm),1813 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",1814 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>,1815 Sched<[WriteFPCVT]> {1816 let Inst{7} = 0; // Z bit1817}1818 1819def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,1820 (outs SPR:$Sd), (ins SPR:$Sm),1821 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",1822 []>,1823 Sched<[WriteFPCVT]> {1824 let Inst{7} = 0; // Z bit1825 let isUnpredicable = 1;1826}1827 1828def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,1829 (outs SPR:$Sd), (ins DPR:$Dm),1830 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",1831 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>,1832 Sched<[WriteFPCVT]> {1833 let Inst{7} = 0; // Z bit1834}1835 1836def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,1837 (outs SPR:$Sd), (ins SPR:$Sm),1838 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",1839 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>,1840 Sched<[WriteFPCVT]> {1841 let Inst{7} = 0; // Z bit1842}1843 1844def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,1845 (outs SPR:$Sd), (ins SPR:$Sm),1846 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",1847 []>,1848 Sched<[WriteFPCVT]> {1849 let Inst{7} = 0; // Z bit1850 let isUnpredicable = 1;1851}1852} // mayRaiseFPException = 1, Uses = [FPSCR_RM]1853 1854// v8.3-a Javascript Convert to Signed fixed-point1855def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011,1856 (outs SPR:$Sd), (ins DPR:$Dm),1857 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm",1858 []>,1859 Requires<[HasFPARMv8, HasV8_3a]> {1860 let Inst{7} = 1; // Z bit1861}1862 1863// Convert between floating-point and fixed-point1864// Data type for fixed-point naming convention:1865// S16 (U=0, sx=0) -> SH1866// U16 (U=1, sx=0) -> UH1867// S32 (U=0, sx=1) -> SL1868// U32 (U=1, sx=1) -> UL1869 1870let Constraints = "$a = $dst", mayRaiseFPException = 1 in {1871 1872// FP to Fixed-Point:1873 1874// Single Precision register1875class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,1876 bit op5, dag oops, dag iops, InstrItinClass itin,1877 string opc, string asm, list<dag> pattern>1878 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {1879 bits<5> dst;1880 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);1881 let Inst{22} = dst{0};1882 let Inst{15-12} = dst{4-1};1883 1884 let hasSideEffects = 0;1885}1886 1887// Double Precision register1888class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,1889 bit op5, dag oops, dag iops, InstrItinClass itin,1890 string opc, string asm, list<dag> pattern>1891 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {1892 bits<5> dst;1893 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);1894 let Inst{22} = dst{4};1895 let Inst{15-12} = dst{3-0};1896 1897 let hasSideEffects = 0;1898 let Predicates = [HasVFP2, HasDPVFP];1899}1900 1901let isUnpredicable = 1 in {1902 1903def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,1904 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),1905 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,1906 Requires<[HasFullFP16]>,1907 Sched<[WriteFPCVT]>;1908 1909def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0,1910 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),1911 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>,1912 Requires<[HasFullFP16]>,1913 Sched<[WriteFPCVT]>;1914 1915def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1,1916 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),1917 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>,1918 Requires<[HasFullFP16]>,1919 Sched<[WriteFPCVT]>;1920 1921def VTOULH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 1,1922 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),1923 IIC_fpCVTHI, "vcvt", ".u32.f16\t$dst, $a, $fbits", []>,1924 Requires<[HasFullFP16]>,1925 Sched<[WriteFPCVT]>;1926 1927} // End of 'let isUnpredicable = 1 in'1928 1929def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,1930 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),1931 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []>,1932 Sched<[WriteFPCVT]> {1933 // Some single precision VFP instructions may be executed on both NEON and1934 // VFP pipelines on A8.1935 let D = VFPNeonA8Domain;1936}1937 1938def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,1939 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),1940 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []>,1941 Sched<[WriteFPCVT]> {1942 // Some single precision VFP instructions may be executed on both NEON and1943 // VFP pipelines on A8.1944 let D = VFPNeonA8Domain;1945}1946 1947def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,1948 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),1949 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []>,1950 Sched<[WriteFPCVT]> {1951 // Some single precision VFP instructions may be executed on both NEON and1952 // VFP pipelines on A8.1953 let D = VFPNeonA8Domain;1954}1955 1956def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,1957 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),1958 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []>,1959 Sched<[WriteFPCVT]> {1960 // Some single precision VFP instructions may be executed on both NEON and1961 // VFP pipelines on A8.1962 let D = VFPNeonA8Domain;1963}1964 1965def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,1966 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),1967 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>,1968 Sched<[WriteFPCVT]>;1969 1970def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,1971 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),1972 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>,1973 Sched<[WriteFPCVT]>;1974 1975def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,1976 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),1977 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>,1978 Sched<[WriteFPCVT]>;1979 1980def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,1981 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),1982 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>,1983 Sched<[WriteFPCVT]>;1984 1985// Fixed-Point to FP:1986 1987let isUnpredicable = 1 in {1988 1989def VSHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 0,1990 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),1991 IIC_fpCVTIH, "vcvt", ".f16.s16\t$dst, $a, $fbits", []>,1992 Requires<[HasFullFP16]>,1993 Sched<[WriteFPCVT]>;1994 1995def VUHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 0,1996 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),1997 IIC_fpCVTIH, "vcvt", ".f16.u16\t$dst, $a, $fbits", []>,1998 Requires<[HasFullFP16]>,1999 Sched<[WriteFPCVT]>;2000 2001def VSLTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 1,2002 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),2003 IIC_fpCVTIH, "vcvt", ".f16.s32\t$dst, $a, $fbits", []>,2004 Requires<[HasFullFP16]>,2005 Sched<[WriteFPCVT]>;2006 2007def VULTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 1,2008 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),2009 IIC_fpCVTIH, "vcvt", ".f16.u32\t$dst, $a, $fbits", []>,2010 Requires<[HasFullFP16]>,2011 Sched<[WriteFPCVT]>;2012 2013} // End of 'let isUnpredicable = 1 in'2014 2015def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,2016 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),2017 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []>,2018 Sched<[WriteFPCVT]> {2019 // Some single precision VFP instructions may be executed on both NEON and2020 // VFP pipelines on A8.2021 let D = VFPNeonA8Domain;2022}2023 2024def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,2025 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),2026 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []>,2027 Sched<[WriteFPCVT]> {2028 // Some single precision VFP instructions may be executed on both NEON and2029 // VFP pipelines on A8.2030 let D = VFPNeonA8Domain;2031}2032 2033def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,2034 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),2035 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []>,2036 Sched<[WriteFPCVT]> {2037 // Some single precision VFP instructions may be executed on both NEON and2038 // VFP pipelines on A8.2039 let D = VFPNeonA8Domain;2040}2041 2042def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,2043 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),2044 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []>,2045 Sched<[WriteFPCVT]> {2046 // Some single precision VFP instructions may be executed on both NEON and2047 // VFP pipelines on A8.2048 let D = VFPNeonA8Domain;2049}2050 2051def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,2052 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),2053 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>,2054 Sched<[WriteFPCVT]>;2055 2056def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,2057 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),2058 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>,2059 Sched<[WriteFPCVT]>;2060 2061def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,2062 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),2063 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>,2064 Sched<[WriteFPCVT]>;2065 2066def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,2067 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),2068 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>,2069 Sched<[WriteFPCVT]>;2070 2071} // End of 'let Constraints = "$a = $dst", mayRaiseFPException = 1 in'2072 2073// BFloat16 - Single precision, unary, predicated2074let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2075class BF16_VCVT<string opc, bits<2> op7_6>2076 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm),2077 VFPUnaryFrm, NoItinerary,2078 opc, ".bf16.f32\t$Sd, $Sm", "", []>,2079 RegConstraint<"$dst = $Sd">,2080 Requires<[HasBF16]>,2081 Sched<[]> {2082 bits<5> Sd;2083 bits<5> Sm;2084 2085 // Encode instruction operands.2086 let Inst{3-0} = Sm{4-1};2087 let Inst{5} = Sm{0};2088 let Inst{15-12} = Sd{4-1};2089 let Inst{22} = Sd{0};2090 2091 let Inst{27-23} = 0b11101; // opcode12092 let Inst{21-20} = 0b11; // opcode22093 let Inst{19-16} = 0b0011; // opcode32094 let Inst{11-8} = 0b1001;2095 let Inst{7-6} = op7_6;2096 let Inst{4} = 0;2097 2098 let DecoderNamespace = "VFPV8";2099 let hasSideEffects = 0;2100}2101 2102def BF16_VCVTB : BF16_VCVT<"vcvtb", 0b01>;2103def BF16_VCVTT : BF16_VCVT<"vcvtt", 0b11>;2104 2105//===----------------------------------------------------------------------===//2106// FP Multiply-Accumulate Operations.2107//2108 2109let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2110def VMLAD : ADbI<0b11100, 0b00, 0, 0,2111 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),2112 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",2113 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),2114 (f64 DPR:$Ddin)))]>,2115 RegConstraint<"$Ddin = $Dd">,2116 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>,2117 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2118 2119let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2120def VMLAS : ASbIn<0b11100, 0b00, 0, 0,2121 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),2122 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",2123 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),2124 SPR:$Sdin))]>,2125 RegConstraint<"$Sdin = $Sd">,2126 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>,2127 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {2128 // Some single precision VFP instructions may be executed on both NEON and2129 // VFP pipelines on A8.2130 let D = VFPNeonA8Domain;2131}2132 2133let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2134def VMLAH : AHbI<0b11100, 0b00, 0, 0,2135 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),2136 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",2137 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)),2138 (f16 HPR:$Sdin)))]>,2139 RegConstraint<"$Sdin = $Sd">,2140 Requires<[HasFullFP16,UseFPVMLx]>;2141 2142def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),2143 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,2144 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>;2145def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),2146 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,2147 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>;2148def : Pat<(fadd_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)),2149 (VMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>,2150 Requires<[HasFullFP16,DontUseNEONForFP, UseFPVMLx]>;2151 2152 2153let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2154def VMLSD : ADbI<0b11100, 0b00, 1, 0,2155 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),2156 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",2157 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),2158 (f64 DPR:$Ddin)))]>,2159 RegConstraint<"$Ddin = $Dd">,2160 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>,2161 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2162 2163let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2164def VMLSS : ASbIn<0b11100, 0b00, 1, 0,2165 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),2166 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",2167 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),2168 SPR:$Sdin))]>,2169 RegConstraint<"$Sdin = $Sd">,2170 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>,2171 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {2172 // Some single precision VFP instructions may be executed on both NEON and2173 // VFP pipelines on A8.2174 let D = VFPNeonA8Domain;2175}2176 2177let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2178def VMLSH : AHbI<0b11100, 0b00, 1, 0,2179 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),2180 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",2181 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),2182 (f16 HPR:$Sdin)))]>,2183 RegConstraint<"$Sdin = $Sd">,2184 Requires<[HasFullFP16,UseFPVMLx]>;2185 2186def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),2187 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,2188 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>;2189def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),2190 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,2191 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;2192def : Pat<(fsub_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)),2193 (VMLSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>,2194 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>;2195 2196let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2197def VNMLAD : ADbI<0b11100, 0b01, 1, 0,2198 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),2199 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",2200 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),2201 (f64 DPR:$Ddin)))]>,2202 RegConstraint<"$Ddin = $Dd">,2203 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>,2204 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2205 2206let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2207def VNMLAS : ASbI<0b11100, 0b01, 1, 0,2208 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),2209 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",2210 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),2211 SPR:$Sdin))]>,2212 RegConstraint<"$Sdin = $Sd">,2213 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>,2214 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {2215 // Some single precision VFP instructions may be executed on both NEON and2216 // VFP pipelines on A8.2217 let D = VFPNeonA8Domain;2218}2219 2220let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2221def VNMLAH : AHbI<0b11100, 0b01, 1, 0,2222 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),2223 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",2224 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),2225 (f16 HPR:$Sdin)))]>,2226 RegConstraint<"$Sdin = $Sd">,2227 Requires<[HasFullFP16,UseFPVMLx]>;2228 2229// (-(a * b) - dst) -> -(dst + (a * b))2230def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),2231 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,2232 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>;2233def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),2234 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,2235 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;2236def : Pat<(fsub_mlx (fneg (fmul_su (f16 HPR:$a), HPR:$b)), HPR:$dstin),2237 (VNMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>,2238 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>;2239 2240// (-dst - (a * b)) -> -(dst + (a * b))2241def : Pat<(fsub_mlx (fneg DPR:$dstin), (fmul_su DPR:$a, (f64 DPR:$b))),2242 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,2243 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>;2244def : Pat<(fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b)),2245 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,2246 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;2247def : Pat<(fsub_mlx (fneg HPR:$dstin), (fmul_su (f16 HPR:$a), HPR:$b)),2248 (VNMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>,2249 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>;2250 2251let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2252def VNMLSD : ADbI<0b11100, 0b01, 0, 0,2253 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),2254 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",2255 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),2256 (f64 DPR:$Ddin)))]>,2257 RegConstraint<"$Ddin = $Dd">,2258 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>,2259 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2260 2261let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2262def VNMLSS : ASbI<0b11100, 0b01, 0, 0,2263 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),2264 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",2265 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,2266 RegConstraint<"$Sdin = $Sd">,2267 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>,2268 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {2269 // Some single precision VFP instructions may be executed on both NEON and2270 // VFP pipelines on A8.2271 let D = VFPNeonA8Domain;2272}2273 2274let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2275def VNMLSH : AHbI<0b11100, 0b01, 0, 0,2276 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),2277 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",2278 [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>,2279 RegConstraint<"$Sdin = $Sd">,2280 Requires<[HasFullFP16,UseFPVMLx]>;2281 2282def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),2283 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,2284 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>;2285def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),2286 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,2287 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;2288def : Pat<(fsub_mlx (fmul_su (f16 HPR:$a), HPR:$b), HPR:$dstin),2289 (VNMLSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>,2290 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>;2291 2292//===----------------------------------------------------------------------===//2293// Fused FP Multiply-Accumulate Operations.2294//2295let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2296def VFMAD : ADbI<0b11101, 0b10, 0, 0,2297 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),2298 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",2299 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),2300 (f64 DPR:$Ddin)))]>,2301 RegConstraint<"$Ddin = $Dd">,2302 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>,2303 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2304 2305let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2306def VFMAS : ASbIn<0b11101, 0b10, 0, 0,2307 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),2308 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",2309 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),2310 SPR:$Sdin))]>,2311 RegConstraint<"$Sdin = $Sd">,2312 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>,2313 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {2314 // Some single precision VFP instructions may be executed on both NEON and2315 // VFP pipelines.2316}2317 2318let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2319def VFMAH : AHbI<0b11101, 0b10, 0, 0,2320 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),2321 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",2322 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)),2323 (f16 HPR:$Sdin)))]>,2324 RegConstraint<"$Sdin = $Sd">,2325 Requires<[HasFullFP16,UseFusedMAC]>,2326 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2327 2328def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),2329 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,2330 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;2331def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),2332 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,2333 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;2334def : Pat<(fadd_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)),2335 (VFMAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>,2336 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>;2337 2338// Match @llvm.fma.* intrinsics2339// (fma x, y, z) -> (vfms z, x, y)2340def : Pat<(f64 (any_fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),2341 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,2342 Requires<[HasVFP4,HasDPVFP]>;2343def : Pat<(f32 (any_fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),2344 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,2345 Requires<[HasVFP4]>;2346def : Pat<(f16 (any_fma HPR:$Sn, HPR:$Sm, (f16 HPR:$Sdin))),2347 (VFMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,2348 Requires<[HasFullFP16]>;2349 2350let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2351def VFMSD : ADbI<0b11101, 0b10, 1, 0,2352 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),2353 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",2354 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),2355 (f64 DPR:$Ddin)))]>,2356 RegConstraint<"$Ddin = $Dd">,2357 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>,2358 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2359 2360let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2361def VFMSS : ASbIn<0b11101, 0b10, 1, 0,2362 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),2363 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",2364 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),2365 SPR:$Sdin))]>,2366 RegConstraint<"$Sdin = $Sd">,2367 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>,2368 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {2369 // Some single precision VFP instructions may be executed on both NEON and2370 // VFP pipelines.2371}2372 2373let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2374def VFMSH : AHbI<0b11101, 0b10, 1, 0,2375 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),2376 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",2377 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),2378 (f16 HPR:$Sdin)))]>,2379 RegConstraint<"$Sdin = $Sd">,2380 Requires<[HasFullFP16,UseFusedMAC]>,2381 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2382 2383def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),2384 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,2385 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;2386def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),2387 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,2388 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;2389def : Pat<(fsub_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)),2390 (VFMSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>,2391 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>;2392 2393// Match @llvm.fma.* intrinsics2394// (fma (fneg x), y, z) -> (vfms z, x, y)2395def : Pat<(f64 (any_fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),2396 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,2397 Requires<[HasVFP4,HasDPVFP]>;2398def : Pat<(f32 (any_fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),2399 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,2400 Requires<[HasVFP4]>;2401def : Pat<(f16 (any_fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin))),2402 (VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,2403 Requires<[HasFullFP16]>;2404 2405let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2406def VFNMAD : ADbI<0b11101, 0b01, 1, 0,2407 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),2408 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",2409 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),2410 (f64 DPR:$Ddin)))]>,2411 RegConstraint<"$Ddin = $Dd">,2412 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>,2413 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2414 2415let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2416def VFNMAS : ASbI<0b11101, 0b01, 1, 0,2417 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),2418 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",2419 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),2420 SPR:$Sdin))]>,2421 RegConstraint<"$Sdin = $Sd">,2422 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>,2423 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {2424 // Some single precision VFP instructions may be executed on both NEON and2425 // VFP pipelines.2426}2427 2428let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2429def VFNMAH : AHbI<0b11101, 0b01, 1, 0,2430 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),2431 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",2432 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),2433 (f16 HPR:$Sdin)))]>,2434 RegConstraint<"$Sdin = $Sd">,2435 Requires<[HasFullFP16,UseFusedMAC]>,2436 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2437 2438def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),2439 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,2440 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;2441def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),2442 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,2443 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;2444 2445// Match @llvm.fma.* intrinsics2446// (fneg (fma x, y, z)) -> (vfnma z, x, y)2447def : Pat<(fneg (any_fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),2448 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,2449 Requires<[HasVFP4,HasDPVFP]>;2450def : Pat<(fneg (any_fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),2451 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,2452 Requires<[HasVFP4]>;2453def : Pat<(fneg (any_fma (f16 HPR:$Sn), (f16 HPR:$Sm), (f16 (f16 HPR:$Sdin)))),2454 (VFNMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,2455 Requires<[HasFullFP16]>;2456// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)2457def : Pat<(f64 (any_fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),2458 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,2459 Requires<[HasVFP4,HasDPVFP]>;2460def : Pat<(f32 (any_fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),2461 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,2462 Requires<[HasVFP4]>;2463def : Pat<(f16 (any_fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (fneg (f16 HPR:$Sdin)))),2464 (VFNMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,2465 Requires<[HasFullFP16]>;2466 2467let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2468def VFNMSD : ADbI<0b11101, 0b01, 0, 0,2469 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),2470 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",2471 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),2472 (f64 DPR:$Ddin)))]>,2473 RegConstraint<"$Ddin = $Dd">,2474 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>,2475 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2476 2477let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2478def VFNMSS : ASbI<0b11101, 0b01, 0, 0,2479 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),2480 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",2481 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,2482 RegConstraint<"$Sdin = $Sd">,2483 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>,2484 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {2485 // Some single precision VFP instructions may be executed on both NEON and2486 // VFP pipelines.2487}2488 2489let mayRaiseFPException = 1, Uses = [FPSCR_RM] in2490def VFNMSH : AHbI<0b11101, 0b01, 0, 0,2491 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),2492 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",2493 [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>,2494 RegConstraint<"$Sdin = $Sd">,2495 Requires<[HasFullFP16,UseFusedMAC]>,2496 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;2497 2498def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),2499 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,2500 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;2501def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),2502 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,2503 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;2504 2505// Match @llvm.fma.* intrinsics2506 2507// (fma x, y, (fneg z)) -> (vfnms z, x, y))2508def : Pat<(f64 (any_fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),2509 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,2510 Requires<[HasVFP4,HasDPVFP]>;2511def : Pat<(f32 (any_fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),2512 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,2513 Requires<[HasVFP4]>;2514def : Pat<(f16 (any_fma (f16 HPR:$Sn), (f16 HPR:$Sm), (fneg (f16 HPR:$Sdin)))),2515 (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,2516 Requires<[HasFullFP16]>;2517// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)2518def : Pat<(fneg (f64 (any_fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),2519 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,2520 Requires<[HasVFP4,HasDPVFP]>;2521def : Pat<(fneg (f32 (any_fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),2522 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,2523 Requires<[HasVFP4]>;2524def : Pat<(fneg (f16 (any_fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin)))),2525 (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,2526 Requires<[HasFullFP16]>;2527 2528//===----------------------------------------------------------------------===//2529// FP Conditional moves.2530//2531 2532let hasSideEffects = 0 in {2533def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),2534 IIC_fpUNA64, []>,2535 RegConstraint<"$Dn = $Dd">, Requires<[HasFPRegs64]>;2536 2537def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),2538 IIC_fpUNA32, []>,2539 RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>;2540 2541def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, pred:$p),2542 IIC_fpUNA16, []>,2543 RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>;2544} // hasSideEffects2545 2546// The following patterns have to be defined out-of-line because the number2547// of instruction operands does not match the number of SDNode operands2548// (`pred` counts as one operand).2549 2550def : Pat<(ARMcmov f64:$Dn, f64:$Dm, imm:$cc, CPSR),2551 (VMOVDcc $Dn, $Dm, imm:$cc, CPSR)>,2552 Requires<[HasFPRegs64]>;2553 2554def : Pat<(ARMcmov f32:$Sn, f32:$Sm, imm:$cc, CPSR),2555 (VMOVScc $Sn, $Sm, imm:$cc, CPSR)>,2556 Requires<[HasFPRegs]>;2557 2558def : Pat<(ARMcmov f16:$Sn, f16:$Sm, imm:$cc, CPSR),2559 (VMOVHcc $Sn, $Sm, imm:$cc, CPSR)>,2560 Requires<[HasFPRegs]>; // FIXME: Shouldn't this be HasFPRegs16?2561 2562//===----------------------------------------------------------------------===//2563// Move from VFP System Register to ARM core register.2564//2565 2566class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,2567 list<dag> pattern>:2568 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, "", pattern> {2569 2570 // Instruction operand.2571 bits<4> Rt;2572 2573 let Inst{27-20} = 0b11101111;2574 let Inst{19-16} = opc19_16;2575 let Inst{15-12} = Rt;2576 let Inst{11-8} = 0b1010;2577 let Inst{7} = 0;2578 let Inst{6-5} = 0b00;2579 let Inst{4} = 1;2580 let Inst{3-0} = 0b0000;2581 let Unpredictable{7-5} = 0b111;2582 let Unpredictable{3-0} = 0b1111;2583 2584 // Needed to avoid errors when a MachineInstrt::FrameSetup flag is set.2585 let mayStore = 0;2586}2587 2588let DecoderMethod = "DecodeForVMRSandVMSR" in {2589 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags2590 // to APSR.2591 let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs],2592 Rt = 0b1111 /* apsr_nzcv */ in2593 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),2594 "vmrs", "\tAPSR_nzcv, fpscr",2595 [(set CPSR, (arm_fmstat FPSCR_NZCV))]>;2596 2597 // Application level FPSCR -> GPR2598 let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in2599 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),2600 "vmrs", "\t$Rt, fpscr",2601 [(set GPRnopc:$Rt, (int_arm_get_fpscr))]>;2602 2603 // System level FPEXC, FPSID -> GPR2604 let Uses = [FPSCR] in {2605 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPRnopc:$Rt), (ins),2606 "vmrs", "\t$Rt, fpexc", []>;2607 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPRnopc:$Rt), (ins),2608 "vmrs", "\t$Rt, fpsid", []>;2609 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPRnopc:$Rt), (ins),2610 "vmrs", "\t$Rt, mvfr0", []>;2611 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPRnopc:$Rt), (ins),2612 "vmrs", "\t$Rt, mvfr1", []>;2613 let Predicates = [HasFPARMv8] in {2614 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins),2615 "vmrs", "\t$Rt, mvfr2", []>;2616 }2617 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPRnopc:$Rt), (ins),2618 "vmrs", "\t$Rt, fpinst", []>;2619 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt),2620 (ins), "vmrs", "\t$Rt, fpinst2", []>;2621 let Predicates = [HasV8_1MMainline, HasFPRegs] in {2622 // System level FPSCR_NZCVQC -> GPR2623 def VMRS_FPSCR_NZCVQC2624 : MovFromVFP<0b0010 /* fpscr_nzcvqc */,2625 (outs GPR:$Rt), (ins cl_FPSCR_NZCV:$fpscr_in),2626 "vmrs", "\t$Rt, fpscr_nzcvqc", []>;2627 }2628 }2629 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {2630 // System level FPSCR -> GPR, with context saving for security extensions2631 def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins),2632 "vmrs", "\t$Rt, fpcxtns", []>;2633 }2634 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {2635 // System level FPSCR -> GPR, with context saving for security extensions2636 def VMRS_FPCXTS : MovFromVFP<0b1111 /* fpcxts */, (outs GPR:$Rt), (ins),2637 "vmrs", "\t$Rt, fpcxts", []>;2638 }2639 2640 let Predicates = [HasV8_1MMainline, HasMVEInt] in {2641 // System level VPR/P0 -> GPR2642 let Uses = [VPR] in2643 def VMRS_VPR : MovFromVFP<0b1100 /* vpr */, (outs GPR:$Rt), (ins),2644 "vmrs", "\t$Rt, vpr", []>;2645 2646 def VMRS_P0 : MovFromVFP<0b1101 /* p0 */, (outs GPR:$Rt), (ins VCCR:$cond),2647 "vmrs", "\t$Rt, p0", []>;2648 }2649}2650 2651//===----------------------------------------------------------------------===//2652// Move from ARM core register to VFP System Register.2653//2654 2655class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,2656 list<dag> pattern>:2657 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, "", pattern> {2658 2659 // Instruction operand.2660 bits<4> Rt;2661 2662 let Inst{27-20} = 0b11101110;2663 let Inst{19-16} = opc19_16;2664 let Inst{15-12} = Rt;2665 let Inst{11-8} = 0b1010;2666 let Inst{7} = 0;2667 let Inst{6-5} = 0b00;2668 let Inst{4} = 1;2669 let Inst{3-0} = 0b0000;2670 let Predicates = [HasVFP2];2671 let Unpredictable{7-5} = 0b111;2672 let Unpredictable{3-0} = 0b1111;2673}2674 2675let DecoderMethod = "DecodeForVMRSandVMSR" in {2676 let Defs = [FPSCR] in {2677 let Predicates = [HasFPRegs] in2678 // Application level GPR -> FPSCR2679 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$Rt),2680 "vmsr", "\tfpscr, $Rt",2681 [(int_arm_set_fpscr GPRnopc:$Rt)]>;2682 // System level GPR -> FPEXC2683 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$Rt),2684 "vmsr", "\tfpexc, $Rt", []>;2685 // System level GPR -> FPSID2686 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$Rt),2687 "vmsr", "\tfpsid, $Rt", []>;2688 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$Rt),2689 "vmsr", "\tfpinst, $Rt", []>;2690 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$Rt),2691 "vmsr", "\tfpinst2, $Rt", []>;2692 }2693 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {2694 // System level GPR -> FPSCR with context saving for security extensions2695 def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$Rt),2696 "vmsr", "\tfpcxtns, $Rt", []>;2697 }2698 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {2699 // System level GPR -> FPSCR with context saving for security extensions2700 def VMSR_FPCXTS : MovToVFP<0b1111 /* fpcxts */, (outs), (ins GPR:$Rt),2701 "vmsr", "\tfpcxts, $Rt", []>;2702 }2703 let Predicates = [HasV8_1MMainline, HasFPRegs] in {2704 // System level GPR -> FPSCR_NZCVQC2705 def VMSR_FPSCR_NZCVQC2706 : MovToVFP<0b0010 /* fpscr_nzcvqc */,2707 (outs cl_FPSCR_NZCV:$fpscr_out), (ins GPR:$Rt),2708 "vmsr", "\tfpscr_nzcvqc, $Rt", []>;2709 }2710 2711 let Predicates = [HasV8_1MMainline, HasMVEInt] in {2712 // System level GPR -> VPR/P02713 let Defs = [VPR] in2714 def VMSR_VPR : MovToVFP<0b1100 /* vpr */, (outs), (ins GPR:$Rt),2715 "vmsr", "\tvpr, $Rt", []>;2716 2717 def VMSR_P0 : MovToVFP<0b1101 /* p0 */, (outs VCCR:$cond), (ins GPR:$Rt),2718 "vmsr", "\tp0, $Rt", []>;2719 }2720}2721 2722//===----------------------------------------------------------------------===//2723// Misc.2724//2725 2726// Materialize FP immediates. VFP3 only.2727let isReMaterializable = 1 in {2728def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),2729 VFPMiscFrm, IIC_fpUNA64,2730 "vmov", ".f64\t$Dd, $imm", "",2731 [(set DPR:$Dd, vfp_f64imm:$imm)]>,2732 Requires<[HasVFP3,HasDPVFP]> {2733 bits<5> Dd;2734 bits<8> imm;2735 2736 let Inst{27-23} = 0b11101;2737 let Inst{22} = Dd{4};2738 let Inst{21-20} = 0b11;2739 let Inst{19-16} = imm{7-4};2740 let Inst{15-12} = Dd{3-0};2741 let Inst{11-9} = 0b101;2742 let Inst{8} = 1; // Double precision.2743 let Inst{7-4} = 0b0000;2744 let Inst{3-0} = imm{3-0};2745}2746 2747def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),2748 VFPMiscFrm, IIC_fpUNA32,2749 "vmov", ".f32\t$Sd, $imm", "",2750 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {2751 bits<5> Sd;2752 bits<8> imm;2753 2754 let Inst{27-23} = 0b11101;2755 let Inst{22} = Sd{0};2756 let Inst{21-20} = 0b11;2757 let Inst{19-16} = imm{7-4};2758 let Inst{15-12} = Sd{4-1};2759 let Inst{11-9} = 0b101;2760 let Inst{8} = 0; // Single precision.2761 let Inst{7-4} = 0b0000;2762 let Inst{3-0} = imm{3-0};2763}2764 2765def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm),2766 VFPMiscFrm, IIC_fpUNA16,2767 "vmov", ".f16\t$Sd, $imm", "",2768 [(set (f16 HPR:$Sd), vfp_f16imm:$imm)]>,2769 Requires<[HasFullFP16]> {2770 bits<5> Sd;2771 bits<8> imm;2772 2773 let Inst{27-23} = 0b11101;2774 let Inst{22} = Sd{0};2775 let Inst{21-20} = 0b11;2776 let Inst{19-16} = imm{7-4};2777 let Inst{15-12} = Sd{4-1};2778 let Inst{11-8} = 0b1001; // Half precision2779 let Inst{7-4} = 0b0000;2780 let Inst{3-0} = imm{3-0};2781 2782 let isUnpredicable = 1;2783}2784}2785 2786def : Pat<(f32 (vfp_f32f16imm:$imm)),2787 (f32 (COPY_TO_REGCLASS (f16 (FCONSTH (vfp_f32f16imm_xform (f32 $imm)))), SPR))> {2788 let Predicates = [HasFullFP16];2789}2790 2791// Floating-point environment management.2792def : Pat<(get_fpenv), (VMRS)>;2793def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;2794def : Pat<(reset_fpenv), (VMSR (MOVi 0))>, Requires<[IsARM]>;2795def : Pat<(reset_fpenv), (VMSR (tMOVi8 0))>, Requires<[IsThumb]>;2796def : Pat<(get_fpmode), (VMRS)>;2797 2798//===----------------------------------------------------------------------===//2799// Assembler aliases.2800//2801// A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to2802// support them all, but supporting at least some of the basics is2803// good to be friendly.2804def : VFP2MnemonicAlias<"flds", "vldr">;2805def : VFP2MnemonicAlias<"fldd", "vldr">;2806def : VFP2MnemonicAlias<"fmrs", "vmov">;2807def : VFP2MnemonicAlias<"fmsr", "vmov">;2808def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;2809def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;2810def : VFP2MnemonicAlias<"fadds", "vadd.f32">;2811def : VFP2MnemonicAlias<"faddd", "vadd.f64">;2812def : VFP2MnemonicAlias<"fmrdd", "vmov">;2813def : VFP2MnemonicAlias<"fmrds", "vmov">;2814def : VFP2MnemonicAlias<"fmrrd", "vmov">;2815def : VFP2MnemonicAlias<"fmdrr", "vmov">;2816def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;2817def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;2818def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;2819def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;2820def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;2821def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;2822def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;2823def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;2824def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;2825def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;2826def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;2827def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;2828def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;2829def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;2830def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;2831def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;2832def : VFP2MnemonicAlias<"fsts", "vstr">;2833def : VFP2MnemonicAlias<"fstd", "vstr">;2834def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;2835def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;2836def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;2837def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;2838def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;2839def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;2840def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;2841def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;2842def : VFP2MnemonicAlias<"fmrx", "vmrs">;2843def : VFP2MnemonicAlias<"fmxr", "vmsr">;2844 2845// Be friendly and accept the old form of zero-compare2846def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;2847def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;2848 2849 2850def : InstAlias<"fmstat${p}", (FMSTAT pred:$p), 0>, Requires<[HasFPRegs]>;2851def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",2852 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;2853def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",2854 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;2855def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",2856 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;2857def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",2858 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;2859 2860// No need for the size suffix on VSQRT. It's implied by the register classes.2861def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;2862def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;2863 2864// VLDR/VSTR accept an optional type suffix.2865def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",2866 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;2867def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",2868 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;2869def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",2870 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;2871def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",2872 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;2873 2874// VMOV can accept optional 32-bit or less data type suffix suffix.2875def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",2876 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;2877def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",2878 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;2879def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",2880 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;2881def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",2882 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;2883def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",2884 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;2885def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",2886 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;2887 2888def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",2889 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;2890def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",2891 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;2892 2893// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way2894// VMOVD does.2895def : VFP2InstAlias<"vmov${p} $Sd, $Sm",2896 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;2897 2898// FCONSTD/FCONSTS alias for vmov.f64/vmov.f322899// These aliases provide added functionality over vmov.f instructions by2900// allowing users to write assembly containing encoded floating point constants2901// (e.g. #0x70 vs #1.0). Without these alises there is no way for the2902// assembler to accept encoded fp constants (but the equivalent fp-literal is2903// accepted directly by vmovf).2904def : VFP3InstAlias<"fconstd${p} $Dd, $val",2905 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;2906def : VFP3InstAlias<"fconsts${p} $Sd, $val",2907 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;2908 2909def VSCCLRMD : VFPXI<(outs), (ins pred:$p, fp_dreglist_with_vpr:$regs, variable_ops),2910 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary,2911 "vscclrm{$p}\t$regs", "", []>, Sched<[]> {2912 bits<13> regs;2913 let Inst{31-23} = 0b111011001;2914 let Inst{22} = regs{12};2915 let Inst{21-16} = 0b011111;2916 let Inst{15-12} = regs{11-8};2917 let Inst{11-8} = 0b1011;2918 let Inst{7-1} = regs{7-1};2919 let Inst{0} = 0;2920 2921 let DecoderMethod = "DecodeVSCCLRM";2922 2923 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt];2924}2925 2926def VSCCLRMS : VFPXI<(outs), (ins pred:$p, fp_sreglist_with_vpr:$regs, variable_ops),2927 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary,2928 "vscclrm{$p}\t$regs", "", []>, Sched<[]> {2929 bits<13> regs;2930 let Inst{31-23} = 0b111011001;2931 let Inst{22} = regs{8};2932 let Inst{21-16} = 0b011111;2933 let Inst{15-12} = regs{12-9};2934 let Inst{11-8} = 0b1010;2935 let Inst{7-0} = regs{7-0};2936 2937 let DecoderMethod = "DecodeVSCCLRM";2938 2939 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt];2940}2941 2942//===----------------------------------------------------------------------===//2943// Store VFP System Register to memory.2944//2945 2946class vfp_vstrldr<bit opc, bit P, bit W, bits<4> SysReg, string sysreg,2947 dag oops, dag iops, IndexMode im, string Dest, string cstr>2948 : VFPI<oops, iops, AddrModeT2_i7s4, 4, im, VFPLdStFrm, IIC_fpSTAT,2949 !if(opc,"vldr","vstr"), !strconcat("\t", sysreg, ", ", Dest), cstr, []>,2950 Sched<[]> {2951 bits<12> addr;2952 let Inst{27-25} = 0b110;2953 let Inst{24} = P;2954 let Inst{23} = addr{7};2955 let Inst{22} = SysReg{3};2956 let Inst{21} = W;2957 let Inst{20} = opc;2958 let Inst{19-16} = addr{11-8};2959 let Inst{15-13} = SysReg{2-0};2960 let Inst{12-7} = 0b011111;2961 let Inst{6-0} = addr{6-0};2962 list<Predicate> Predicates = [HasFPRegs, HasV8_1MMainline];2963 let mayLoad = opc;2964 let mayStore = !if(opc, 0b0, 0b1);2965 let hasSideEffects = 1;2966}2967 2968multiclass vfp_vstrldr_sysreg<bit opc, bits<4> SysReg, string sysreg,2969 dag oops=(outs), dag iops=(ins)> {2970 def _off :2971 vfp_vstrldr<opc, 1, 0, SysReg, sysreg,2972 oops, !con(iops, (ins t2addrmode_imm7s4:$addr)),2973 IndexModePost, "$addr", "" > {2974 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<false>";2975 }2976 2977 def _pre :2978 vfp_vstrldr<opc, 1, 1, SysReg, sysreg,2979 !con(oops, (outs GPRnopc:$wb)),2980 !con(iops, (ins t2addrmode_imm7s4_pre:$addr)),2981 IndexModePre, "$addr!", "$addr.base = $wb"> {2982 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>";2983 }2984 2985 def _post :2986 vfp_vstrldr<opc, 0, 1, SysReg, sysreg,2987 !con(oops, (outs GPRnopc:$wb)),2988 !con(iops, (ins t2_addr_offset_none:$Rn,2989 t2am_imm7s4_offset:$addr)),2990 IndexModePost, "$Rn$addr", "$Rn.base = $wb"> {2991 bits<4> Rn;2992 let Inst{19-16} = Rn{3-0};2993 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>";2994 }2995}2996 2997let Uses = [FPSCR] in {2998 defm VSTR_FPSCR : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">;2999 3000 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {3001 defm VSTR_FPCXTNS : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">;3002 defm VSTR_FPCXTS : vfp_vstrldr_sysreg<0b0,0b1111, "fpcxts">;3003 }3004}3005 3006let Predicates = [HasV8_1MMainline, HasMVEInt] in {3007 let Uses = [VPR] in {3008 defm VSTR_VPR : vfp_vstrldr_sysreg<0b0,0b1100, "vpr">;3009 }3010 defm VSTR_P0 : vfp_vstrldr_sysreg<0b0,0b1101, "p0",3011 (outs), (ins VCCR:$P0)>;3012 3013 let Defs = [VPR] in {3014 defm VLDR_VPR : vfp_vstrldr_sysreg<0b1,0b1100, "vpr">;3015 }3016 defm VLDR_P0 : vfp_vstrldr_sysreg<0b1,0b1101, "p0",3017 (outs VCCR:$P0), (ins)>;3018}3019 3020let Defs = [FPSCR] in {3021 defm VLDR_FPSCR : vfp_vstrldr_sysreg<0b1,0b0001, "fpscr">;3022 3023 let Predicates = [HasV8_1MMainline, Has8MSecExt] in {3024 defm VLDR_FPCXTNS : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">;3025 defm VLDR_FPCXTS : vfp_vstrldr_sysreg<0b1,0b1111, "fpcxts">;3026 }3027}3028 3029defm VSTR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b0,0b0010, "fpscr_nzcvqc",3030 (outs), (ins cl_FPSCR_NZCV:$fpscr)>;3031let canFoldAsLoad = 1, isReMaterializable = 1 in {3032defm VLDR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b1,0b0010, "fpscr_nzcvqc",3033 (outs cl_FPSCR_NZCV:$fpscr), (ins)>;3034}3035