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1//===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9include "ARMSystemRegister.td"10 11//===----------------------------------------------------------------------===//12// Declarations that describe the ARM register file13//===----------------------------------------------------------------------===//14 15// Registers are identified with 4-bit ID numbers.16class ARMReg<bits<16> Enc, string n, list<Register> subregs = [],17 list<string> altNames = []> : Register<n, altNames> {18 let HWEncoding = Enc;19 let Namespace = "ARM";20 let SubRegs = subregs;21 // All bits of ARM registers with sub-registers are covered by sub-registers.22 let CoveredBySubRegs = 1;23}24 25class ARMFReg<bits<16> Enc, string n> : Register<n> {26 let HWEncoding = Enc;27 let Namespace = "ARM";28}29 30let Namespace = "ARM",31 FallbackRegAltNameIndex = NoRegAltName in {32 def RegNamesRaw : RegAltNameIndex;33}34 35// Subregister indices.36let Namespace = "ARM" in {37def qqsub_0 : SubRegIndex<256>;38def qqsub_1 : SubRegIndex<256, 256>;39 40// Note: Code depends on these having consecutive numbers.41def qsub_0 : SubRegIndex<128>;42def qsub_1 : SubRegIndex<128, 128>;43def qsub_2 : ComposedSubRegIndex<qqsub_1, qsub_0>;44def qsub_3 : ComposedSubRegIndex<qqsub_1, qsub_1>;45 46def dsub_0 : SubRegIndex<64>;47def dsub_1 : SubRegIndex<64, 64>;48def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>;49def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>;50def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>;51def dsub_5 : ComposedSubRegIndex<qsub_2, dsub_1>;52def dsub_6 : ComposedSubRegIndex<qsub_3, dsub_0>;53def dsub_7 : ComposedSubRegIndex<qsub_3, dsub_1>;54 55def ssub_0 : SubRegIndex<32>;56def ssub_1 : SubRegIndex<32, 32>;57def ssub_2 : ComposedSubRegIndex<dsub_1, ssub_0>;58def ssub_3 : ComposedSubRegIndex<dsub_1, ssub_1>;59def ssub_4 : ComposedSubRegIndex<dsub_2, ssub_0>;60def ssub_5 : ComposedSubRegIndex<dsub_2, ssub_1>;61def ssub_6 : ComposedSubRegIndex<dsub_3, ssub_0>;62def ssub_7 : ComposedSubRegIndex<dsub_3, ssub_1>;63def ssub_8 : ComposedSubRegIndex<dsub_4, ssub_0>;64def ssub_9 : ComposedSubRegIndex<dsub_4, ssub_1>;65def ssub_10 : ComposedSubRegIndex<dsub_5, ssub_0>;66def ssub_11 : ComposedSubRegIndex<dsub_5, ssub_1>;67def ssub_12 : ComposedSubRegIndex<dsub_6, ssub_0>;68def ssub_13 : ComposedSubRegIndex<dsub_6, ssub_1>;69def ssub_14 : ComposedSubRegIndex<dsub_7, ssub_0>;70def ssub_15 : ComposedSubRegIndex<dsub_7, ssub_1>;71 72def gsub_0 : SubRegIndex<32>;73def gsub_1 : SubRegIndex<32, 32>;74// Let TableGen synthesize the remaining 12 ssub_* indices.75// We don't need to name them.76}77 78// Integer registers79def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;80def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;81def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;82def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;83def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;84def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;85def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;86def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;87// These require 32-bit instructions.88let CostPerUse = [1] in {89def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;90def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;91def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;92def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;93def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;94let RegAltNameIndices = [RegNamesRaw] in {95def SP : ARMReg<13, "sp", [], ["r13"]>, DwarfRegNum<[13]>;96def LR : ARMReg<14, "lr", [], ["r14"]>, DwarfRegNum<[14]>;97def PC : ARMReg<15, "pc", [], ["r15"]>, DwarfRegNum<[15]>;98}99}100 101// Float registers102def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;103def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;104def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;105def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;106def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;107def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;108def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;109def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;110def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;111def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;112def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;113def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;114def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;115def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;116def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;117def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;118 119// Aliases of the F* registers used to hold 64-bit fp values (doubles)120let SubRegIndices = [ssub_0, ssub_1] in {121def D0 : ARMReg< 0, "d0", [S0, S1]>, DwarfRegNum<[256]>;122def D1 : ARMReg< 1, "d1", [S2, S3]>, DwarfRegNum<[257]>;123def D2 : ARMReg< 2, "d2", [S4, S5]>, DwarfRegNum<[258]>;124def D3 : ARMReg< 3, "d3", [S6, S7]>, DwarfRegNum<[259]>;125def D4 : ARMReg< 4, "d4", [S8, S9]>, DwarfRegNum<[260]>;126def D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>;127def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;128def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>;129def D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>;130def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>;131def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;132def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>;133def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;134def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>;135def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>;136def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>;137}138 139// VFP3 defines 16 additional double registers140def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>;141def D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>;142def D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>;143def D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>;144def D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>;145def D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>;146def D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>;147def D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>;148def D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>;149def D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>;150def D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>;151def D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>;152def D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>;153def D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>;154def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>;155def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;156 157// Advanced SIMD (NEON) defines 16 quad-word aliases158let SubRegIndices = [dsub_0, dsub_1] in {159def Q0 : ARMReg< 0, "q0", [D0, D1]>;160def Q1 : ARMReg< 1, "q1", [D2, D3]>;161def Q2 : ARMReg< 2, "q2", [D4, D5]>;162def Q3 : ARMReg< 3, "q3", [D6, D7]>;163def Q4 : ARMReg< 4, "q4", [D8, D9]>;164def Q5 : ARMReg< 5, "q5", [D10, D11]>;165def Q6 : ARMReg< 6, "q6", [D12, D13]>;166def Q7 : ARMReg< 7, "q7", [D14, D15]>;167}168let SubRegIndices = [dsub_0, dsub_1] in {169def Q8 : ARMReg< 8, "q8", [D16, D17]>;170def Q9 : ARMReg< 9, "q9", [D18, D19]>;171def Q10 : ARMReg<10, "q10", [D20, D21]>;172def Q11 : ARMReg<11, "q11", [D22, D23]>;173def Q12 : ARMReg<12, "q12", [D24, D25]>;174def Q13 : ARMReg<13, "q13", [D26, D27]>;175def Q14 : ARMReg<14, "q14", [D28, D29]>;176def Q15 : ARMReg<15, "q15", [D30, D31]>;177}178 179// Current Program Status Register.180// We model fpscr with three registers. FPSCR models the control bits and will be181// reserved. FPSCR_RM models rounding mode control bits and will be reserved.182// FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV183// models the APSR when it's accessed by some special instructions. In such cases184// it has the same encoding as PC.185def CPSR : ARMReg<0, "cpsr">;186def APSR : ARMReg<15, "apsr">;187def APSR_NZCV : ARMReg<15, "apsr_nzcv">;188def SPSR : ARMReg<2, "spsr">;189def FPSCR : ARMReg<3, "fpscr">;190def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> {191 let Aliases = [FPSCR];192}193def FPSCR_RM : ARMReg<3, "fpscr_rm"> {194 let Aliases = [FPSCR];195}196def ITSTATE : ARMReg<4, "itstate">;197 198// Special Registers - only available in privileged mode.199def FPSID : ARMReg<0, "fpsid">;200def MVFR2 : ARMReg<5, "mvfr2">;201def MVFR1 : ARMReg<6, "mvfr1">;202def MVFR0 : ARMReg<7, "mvfr0">;203def FPEXC : ARMReg<8, "fpexc">;204def FPINST : ARMReg<9, "fpinst">;205def FPINST2 : ARMReg<10, "fpinst2">;206// These encodings aren't actual instruction encodings, their encoding depends207// on the instruction they are used in and for VPR 64 was chosen such that it208// always comes last in spr_reglist_with_vpr.209def VPR : ARMReg<64, "vpr">;210def FPSCR_NZCVQC211 : ARMReg<2, "fpscr_nzcvqc">;212def P0 : ARMReg<13, "p0">;213def FPCXTNS : ARMReg<14, "fpcxtns">;214def FPCXTS : ARMReg<15, "fpcxts">;215 216def ZR : ARMReg<15, "zr">, DwarfRegNum<[15]>;217 218def RA_AUTH_CODE : ARMReg<12, "ra_auth_code">, DwarfRegNum<[143]>;219 220// Register classes.221//222// pc == Program Counter223// lr == Link Register224// sp == Stack Pointer225// r12 == ip (scratch)226// r7 == Frame Pointer (thumb-style backtraces)227// r9 == May be reserved as Thread Register228// r11 == Frame Pointer (arm-style backtraces)229// r10 == Stack Limit230//231def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),232 SP, LR, PC)> {233 // Allocate LR as the first CSR since it is always saved anyway.234 // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't235 // know how to spill them. If we make our prologue/epilogue code smarter at236 // some point, we can go back to using the above allocation orders for the237 // Thumb1 instructions that know how to use hi regs.238 let AltOrders = [(add LR, GPR), (trunc GPR, 8),239 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))];240 let AltOrderSelect = [{241 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);242 }];243 let DiagnosticString = "operand must be a register in range [r0, r15]";244}245 246// Register set that excludes registers that are reserved for procedure calls.247// This is used for pseudo-instructions that are actually implemented using a248// procedure call.249def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> {250 // Allocate LR as the first CSR since it is always saved anyway.251 // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't252 // know how to spill them. If we make our prologue/epilogue code smarter at253 // some point, we can go back to using the above allocation orders for the254 // Thumb1 instructions that know how to use hi regs.255 let AltOrders = [(add GPRnoip, GPRnoip), (trunc GPRnoip, 8),256 (add (trunc GPRnoip, 8), (shl GPRnoip, 8))];257 let AltOrderSelect = [{258 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);259 }];260 let DiagnosticString = "operand must be a register in range [r0, r14]";261}262 263// GPRs without the PC. Some ARM instructions do not allow the PC in264// certain operand slots, particularly as the destination. Primarily265// useful for disassembly.266def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {267 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8),268 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))];269 let AltOrderSelect = [{270 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);271 }];272 let DiagnosticString = "operand must be a register in range [r0, r14]";273}274 275// GPRs without the PC but with APSR. Some instructions allow accessing the276// APSR, while actually encoding PC in the register field. This is useful277// for assembly and disassembly only.278def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {279 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];280 let AltOrderSelect = [{281 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();282 }];283 let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv";284}285 286// GPRs without the SP register. Used for BXAUT and AUTG287def GPRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, PC)> {288 let AltOrders = [(add LR, GPRnosp), (trunc GPRnosp, 8),289 (add (trunc GPRnosp, 8), R12, LR, (shl GPRnosp, 8))];290 let AltOrderSelect = [{291 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);292 }];293 let DiagnosticString = "operand must be a register in range [r0, r12] or LR or PC";294}295 296// GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.297def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {298 let isAllocatable = 0;299}300 301def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> {302 let AltOrders = [(add LR, GPRwithZR), (trunc GPRwithZR, 8)];303 let AltOrderSelect = [{304 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();305 }];306 let DiagnosticString = "operand must be a register in range [r0, r14] or zr";307}308 309def GPRwithZRnosp : RegisterClass<"ARM", [i32], 32, (sub GPRwithZR, SP)> {310 let AltOrders = [(add LR, GPRwithZRnosp), (trunc GPRwithZRnosp, 8)];311 let AltOrderSelect = [{312 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();313 }];314 let DiagnosticString = "operand must be a register in range [r0, r12] or r14 or zr";315}316 317// GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the318// implied SP argument list.319// FIXME: It would be better to not use this at all and refactor the320// instructions to not have SP an an explicit argument. That makes321// frame index resolution a bit trickier, though.322def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)> {323 let DiagnosticString = "operand must be a register sp";324}325 326// GPRlr - Only LR is legal. Used by ARMv8.1-M Low Overhead Loop instructions327// where LR is the only legal loop counter register.328def GPRlr : RegisterClass<"ARM", [i32], 32, (add LR)>;329 330// restricted GPR register class. Many Thumb2 instructions allow the full331// register range for operands, but have undefined behaviours when PC332// or SP (R13 or R15) are used. The ARM ISA refers to these operands333// via the BadReg() pseudo-code description.334def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {335 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8),336 (add (trunc rGPR, 8), R12, LR, (shl rGPR, 8))];337 let AltOrderSelect = [{338 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);339 }];340 let DiagnosticType = "rGPR";341}342 343// GPRs without the PC and SP but with APSR_NZCV.Some instructions allow344// accessing the APSR_NZCV, while actually encoding PC in the register field.345// This is useful for assembly and disassembly only.346// Currently used by the CDE extension.347def GPRwithAPSR_NZCVnosp348 : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR_NZCV)> {349 let isAllocatable = 0;350 let DiagnosticString =351 "operand must be a register in the range [r0, r12], r14 or apsr_nzcv";352}353 354// Thumb registers are R0-R7 normally. Some instructions can still use355// the general GPR register class above (MOV, e.g.)356def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {357 let DiagnosticString = "operand must be a register in range [r0, r7]";358}359 360// Thumb registers R0-R7 and the PC. Some instructions like TBB or THH allow361// the PC to be used as a destination operand as well.362def tGPRwithpc : RegisterClass<"ARM", [i32], 32, (add tGPR, PC)>;363 364// The high registers in thumb mode, R8-R15.365def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)> {366 let DiagnosticString = "operand must be a register in range [r8, r15]";367}368 369// For tail calls, we can't use callee-saved registers, as they are restored370// to the saved value before the tail call, which would clobber a call address.371// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of372// this class and the preceding one(!) This is what we want.373def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {374 let AltOrders = [(and tcGPR, tGPR)];375 let AltOrderSelect = [{376 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();377 }];378}379 380// Some pointer authentication instructions require the use of R12. When return381// address signing is enabled, authentication of the caller's return address382// must be performed before a tail call is made. Therefore, indirect tail call383// jump cannot be from R12.384// FIXME: All PACBTI instruction currently implemented in the compiler385// implicitly use R12. When instructions that allow PAC to be placed in a386// specific register are implemented the restriction needs to be updated to387// make sure that PACBTI signature and indirect tail call both use a different register.388def tcGPRnotr12 : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3)>;389 390def tGPROdd : RegisterClass<"ARM", [i32], 32, (add R1, R3, R5, R7, R9, R11)> {391 let AltOrders = [(and tGPROdd, tGPR)];392 let AltOrderSelect = [{393 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();394 }];395 let DiagnosticString =396 "operand must be an odd-numbered register in range [r1,r11]";397}398 399def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> {400 let AltOrders = [(and tGPREven, tGPR)];401 let AltOrderSelect = [{402 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();403 }];404 let DiagnosticString = "operand must be an even-numbered register";405}406 407// Condition code registers.408def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {409 let CopyCost = -1; // Don't allow copying of status registers.410 let isAllocatable = 0;411}412 413// MVE Condition code register.414def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> {415// let CopyCost = -1; // Don't allow copying of status registers.416}417 418// FPSCR, when the flags at the top of it are used as the input or419// output to an instruction such as MVE VADC.420def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)> {421 let CopyCost = -1;422}423 424// This RegisterClass is required to add FPSCR and FPEXC into a calling425// convention.426def FP_STATUS_REGS : RegisterClass<"ARM", [i32], 32, (add FPSCR, FPEXC)> {427 let CopyCost = -1; // Don't allow copying of status registers.428 let isAllocatable = 0;429}430 431// Scalar single precision floating point register class..432// FIXME: Allocation order changed to s0, s2, ... or s0, s4, ... as a quick hack433// to avoid partial-write dependencies on D or Q (depending on platform)434// registers (S registers are renamed as portions of D/Q registers).435def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {436 let AltOrders = [(add (decimate SPR, 2), SPR),437 (add (decimate SPR, 4),438 (decimate SPR, 2),439 (decimate (rotl SPR, 1), 4),440 (decimate (rotl SPR, 1), 2))];441 let AltOrderSelect = [{442 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs();443 }];444 let DiagnosticString = "operand must be a register in range [s0, s31]";445}446 447def HPR : RegisterClass<"ARM", [f16, bf16], 32, (sequence "S%u", 0, 31)> {448 let AltOrders = [(add (decimate HPR, 2), SPR),449 (add (decimate HPR, 4),450 (decimate HPR, 2),451 (decimate (rotl HPR, 1), 4),452 (decimate (rotl HPR, 1), 2))];453 let AltOrderSelect = [{454 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs();455 }];456 let DiagnosticString = "operand must be a register in range [s0, s31]";457}458 459// Subset of SPR which can be used as a source of NEON scalars for 16-bit460// operations461def SPR_8 : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 15)> {462 let DiagnosticString = "operand must be a register in range [s0, s15]";463}464 465// Scalar double precision floating point / generic 64-bit vector register466// class.467// ARM requires only word alignment for double. It's more performant if it468// is double-word alignment though.469def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,470 (sequence "D%u", 0, 31)> {471 // Allocate non-VFP2 registers D16-D31 first, and prefer even registers on472 // Darwin platforms.473 let AltOrders = [(rotl DPR, 16),474 (add (decimate (rotl DPR, 16), 2), (rotl DPR, 16))];475 let AltOrderSelect = [{476 return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs();477 }];478 let DiagnosticType = "DPR";479}480 481// Scalar single and double precision floating point and VPR register class,482// this is only used for parsing, don't use it anywhere else as the size and483// types don't match!484def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {485 let isAllocatable = 0;486}487 488// Subset of DPR that are accessible with VFP2 (and so that also have489// 32-bit SPR subregs).490def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,491 (trunc DPR, 16)> {492 let DiagnosticString = "operand must be a register in range [d0, d15]";493}494 495// Subset of DPR which can be used as a source of NEON scalars for 16-bit496// operations497def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,498 (trunc DPR, 8)> {499 let DiagnosticString = "operand must be a register in range [d0, d7]";500}501 502// Generic 128-bit vector register class.503def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16, v8bf16], 128,504 (sequence "Q%u", 0, 15)> {505 // Allocate non-VFP2 aliases Q8-Q15 first.506 let AltOrders = [(rotl QPR, 8), (trunc QPR, 8)];507 let AltOrderSelect = [{508 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();509 }];510 let DiagnosticString = "operand must be a register in range [q0, q15]";511}512 513// Subset of QPR that have 32-bit SPR subregs.514def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],515 128, (trunc QPR, 8)> {516 let DiagnosticString = "operand must be a register in range [q0, q7]";517}518 519// Subset of QPR that have DPR_8 and SPR_8 subregs.520def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],521 128, (trunc QPR, 4)> {522 let DiagnosticString = "operand must be a register in range [q0, q3]";523}524 525// MVE 128-bit vector register class. This class is only really needed for526// parsing assembly, since we still have to truncate the register set in the QPR527// class anyway.528def MQPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16],529 128, (trunc QPR, 8)>;530 531// Pseudo-registers representing odd-even pairs of D registers. The even-odd532// pairs are already represented by the Q registers.533// These are needed by NEON instructions requiring two consecutive D registers.534// There is no D31_D0 register as that is always an UNPREDICTABLE encoding.535def TuplesOE2D : RegisterTuples<[dsub_0, dsub_1],536 [(decimate (shl DPR, 1), 2),537 (decimate (shl DPR, 2), 2)]>;538 539// Register class representing a pair of consecutive D registers.540// Use the Q registers for the even-odd pairs.541def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],542 128, (interleave QPR, TuplesOE2D)> {543 // Allocate starting at non-VFP2 registers D16-D31 first.544 // Prefer even-odd pairs as they are easier to copy.545 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16)),546 (add (trunc QPR, 8), (trunc DPair, 16))];547 let AltOrderSelect = [{548 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();549 }];550}551 552// Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.553// These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.554def Tuples2Rnosp : RegisterTuples<[gsub_0, gsub_1],555 [(add R0, R2, R4, R6, R8, R10),556 (add R1, R3, R5, R7, R9, R11)]>;557 558def Tuples2Rsp : RegisterTuples<[gsub_0, gsub_1],559 [(add R12), (add SP)]>;560 561// Register class representing a pair of even-odd GPRs.562def GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp, Tuples2Rsp)> {563 let Size = 64; // 2 x 32 bits, we have no predefined type of that size.564}565 566// Register class representing a pair of even-odd GPRs, except (R12, SP).567def GPRPairnosp : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp)> {568 let Size = 64; // 2 x 32 bits, we have no predefined type of that size.569}570 571// Pseudo-registers representing 3 consecutive D registers.572def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2],573 [(shl DPR, 0),574 (shl DPR, 1),575 (shl DPR, 2)]>;576 577// 3 consecutive D registers.578def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> {579 let Size = 192; // 3 x 64 bits, we have no predefined type of that size.580}581 582// Pseudo 256-bit registers to represent pairs of Q registers. These should583// never be present in the emitted code.584// These are used for NEON load / store instructions, e.g., vld4, vst3.585def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;586 587// Pseudo 256-bit vector register class to model pairs of Q registers588// (4 consecutive D registers).589def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> {590 // Allocate non-VFP2 aliases first.591 let AltOrders = [(rotl QQPR, 8)];592 let AltOrderSelect = [{ return 1; }];593}594 595// Same as QQPR but for MVE, containing the 7 register pairs made up from Q0-Q7.596def MQQPR : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 7)>;597 598// Tuples of 4 D regs that isn't also a pair of Q regs.599def TuplesOE4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3],600 [(decimate (shl DPR, 1), 2),601 (decimate (shl DPR, 2), 2),602 (decimate (shl DPR, 3), 2),603 (decimate (shl DPR, 4), 2)]>;604 605// 4 consecutive D registers.606def DQuad : RegisterClass<"ARM", [v4i64], 256,607 (interleave Tuples2Q, TuplesOE4D)>;608 609// Pseudo 512-bit registers to represent four consecutive Q registers.610def Tuples2QQ : RegisterTuples<[qqsub_0, qqsub_1],611 [(shl QQPR, 0), (shl QQPR, 2)]>;612 613// Pseudo 512-bit vector register class to model 4 consecutive Q registers614// (8 consecutive D registers).615def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {616 // Allocate non-VFP2 aliases first.617 let AltOrders = [(rotl QQQQPR, 8)];618 let AltOrderSelect = [{ return 1; }];619}620 621// Same as QQPR but for MVE, containing the 5 register quads made up from Q0-Q7.622def MQQQQPR : RegisterClass<"ARM", [v8i64], 256, (trunc QQQQPR, 5)>;623 624 625// Pseudo-registers representing 2-spaced consecutive D registers.626def Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2],627 [(shl DPR, 0),628 (shl DPR, 2)]>;629 630// Spaced pairs of D registers.631def DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>;632 633def Tuples3DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4],634 [(shl DPR, 0),635 (shl DPR, 2),636 (shl DPR, 4)]>;637 638// Spaced triples of D registers.639def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> {640 let Size = 192; // 3 x 64 bits, we have no predefined type of that size.641}642 643def Tuples4DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4, dsub_6],644 [(shl DPR, 0),645 (shl DPR, 2),646 (shl DPR, 4),647 (shl DPR, 6)]>;648 649// Spaced quads of D registers.650def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>;651 652// FP context payload653def FPCXTRegs : RegisterClass<"ARM", [i32], 32, (add FPCXTNS)>;654