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1//=- ARMScheduleA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the machine model for ARM Cortex-A57 to support10// instruction scheduling and other instruction cost heuristics.11//12//===----------------------------------------------------------------------===//13 14//===----------------------------------------------------------------------===//15// *** Common description and scheduling model parameters taken from AArch64 ***16// The Cortex-A57 is a traditional superscalar microprocessor with a17// conservative 3-wide in-order stage for decode and dispatch. Combined with the18// much wider out-of-order issue stage, this produced a need to carefully19// schedule micro-ops so that all three decoded each cycle are successfully20// issued as the reservation station(s) simply don't stay occupied for long.21// Therefore, IssueWidth is set to the narrower of the two at three, while still22// modeling the machine as out-of-order.23 24def IsCPSRDefinedAndPredicated : CheckAll<[IsCPSRDefined, IsPredicated]>;25def IsCPSRDefinedAndPredicatedPred :26 MCSchedPredicate<IsCPSRDefinedAndPredicated>;27 28// Cortex A57 rev. r1p0 or later (false = r0px)29def IsR1P0AndLaterPred : MCSchedPredicate<FalsePred>;30 31def IsLdrAm3RegOffPred : MCSchedPredicate<CheckInvalidRegOperand<2>>;32def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckInvalidRegOperand<3>>;33def IsLdrAm3RegOffPredX3 : MCSchedPredicate<CheckInvalidRegOperand<4>>;34 35// If Addrmode3 contains "minus register"36class Am3NegativeRegOffset<int n> : MCSchedPredicate<CheckAll<[37 CheckValidRegOperand<n>,38 CheckAM3OpSub<!add(n, 1)>]>>;39 40def IsLdrAm3NegRegOffPred : Am3NegativeRegOffset<2>;41def IsLdrAm3NegRegOffPredX2 : Am3NegativeRegOffset<3>;42def IsLdrAm3NegRegOffPredX3 : Am3NegativeRegOffset<4>;43 44// Load, scaled register offset, not plus LSL245class ScaledRegNotPlusLsl2<int n> : CheckNot<46 CheckAny<[47 CheckAM2NoShift<n>,48 CheckAll<[49 CheckAM2OpAdd<n>,50 CheckAM2ShiftLSL<n>,51 CheckAM2Offset<n, 2>52 ]>53 ]>54 >;55 56def IsLdstsoScaledNotOptimalPredX0 : MCSchedPredicate<ScaledRegNotPlusLsl2<2>>;57def IsLdstsoScaledNotOptimalPred : MCSchedPredicate<ScaledRegNotPlusLsl2<3>>;58def IsLdstsoScaledNotOptimalPredX2 : MCSchedPredicate<ScaledRegNotPlusLsl2<4>>;59 60def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckAM2NoShift<4>>>;61 62def IsLdstsoMinusRegPredX0 : MCSchedPredicate<CheckAM2OpSub<2>>;63def IsLdstsoMinusRegPred : MCSchedPredicate<CheckAM2OpSub<3>>;64def IsLdstsoMinusRegPredX2 : MCSchedPredicate<CheckAM2OpSub<4>>;65 66class A57WriteLMOpsListType<list<SchedWriteRes> writes> {67 list <SchedWriteRes> Writes = writes;68 SchedMachineModel SchedModel = ?;69}70 71// *** Common description and scheduling model parameters taken from AArch64 ***72// (AArch64SchedA57.td)73def CortexA57Model : SchedMachineModel {74 let IssueWidth = 3; // 3-way decode and dispatch75 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer76 let LoadLatency = 4; // Optimistic load latency77 let MispredictPenalty = 16; // Fetch + Decode/Rename/Dispatch + Branch78 79 // Enable partial & runtime unrolling.80 let LoopMicroOpBufferSize = 16;81 let CompleteModel = 1;82 83 // FIXME: Remove when all errors have been fixed.84 let FullInstRWOverlapCheck = 0;85 86 let UnsupportedFeatures = [HasV8_1MMainline, HasMVEInt, HasMVEFloat, IsMClass,87 HasFPRegsV8_1M, HasFP16FML, HasMatMulInt8, HasBF16];88}89 90//===----------------------------------------------------------------------===//91// Define each kind of processor resource and number available on Cortex-A57.92// Cortex A-57 has 8 pipelines that each has its own 8-entry queue where93// micro-ops wait for their operands and then issue out-of-order.94 95def A57UnitB : ProcResource<1>; // Type B micro-ops96def A57UnitI : ProcResource<2>; // Type I micro-ops97def A57UnitM : ProcResource<1>; // Type M micro-ops98def A57UnitL : ProcResource<1>; // Type L micro-ops99def A57UnitS : ProcResource<1>; // Type S micro-ops100 101def A57UnitX : ProcResource<1>; // Type X micro-ops (F1)102def A57UnitW : ProcResource<1>; // Type W micro-ops (F0)103 104let SchedModel = CortexA57Model in {105 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops106}107 108let SchedModel = CortexA57Model in {109 110//===----------------------------------------------------------------------===//111// Define customized scheduler read/write types specific to the Cortex-A57.112 113include "ARMScheduleA57WriteRes.td"114 115// To have "CompleteModel = 1", support of pseudos and special instructions116def : InstRW<[WriteNoop], (instregex "(t)?BKPT$", "(t2)?CDP(2)?$",117 "(t2)?CLREX$", "CONSTPOOL_ENTRY$", "COPY_STRUCT_BYVAL_I32$",118 "(t2)?CPS[123]p$", "(t2)?DBG$", "(t2)?DMB$", "(t2)?DSB$", "ERET$",119 "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",120 "(t2)?RFE(DA|DB|IA|IB)", "(t)?SETEND", "(t2)?SETPAN", "(t2)?SMC", "SPACE",121 "(t2)?SRS(DA|DB|IA|IB)", "SWP(B)?", "t?TRAP", "(t2|t)?UDF$", "t2DCPS", "t2SG",122 "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "t__brkdiv0")>;123 124def : InstRW<[WriteNoop], (instregex "VMRS", "VMSR", "FMSTAT")>;125 126// Specific memory instrs127def : InstRW<[WriteNoop, WriteNoop], (instregex "(t2)?LDA", "(t2)?LDC", "(t2)?STC",128 "(t2)?STL", "(t2)?LDREX", "(t2)?STREX", "MEMCPY")>;129 130// coprocessor moves131def : InstRW<[WriteNoop, WriteNoop], (instregex132 "(t2)?MCR(2|R|R2)?$", "(t2)?MRC(2)?$",133 "(t2)?MRRC(2)?$", "(t2)?MRS(banked|sys|_AR|_M|sys_AR)?$",134 "(t2)?MSR(banked|i|_AR|_M)?$")>;135 136// Deprecated instructions137def : InstRW<[WriteNoop], (instregex "FLDM", "FSTM")>;138 139// Pseudos140def : InstRW<[WriteNoop], (instregex "(t)?ADJCALLSTACKDOWN$", "(t)?ADJCALLSTACKUP$",141 "(t2|t)?Int_eh_sjlj", "tLDRpci_pic", "(t2)?SUBS_PC_LR",142 "JUMPTABLE", "tInt_WIN_eh_sjlj_longjmp",143 "VLD(1|2)LN(d|q)(WB_fixed_|WB_register_)?Asm",144 "VLD(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm",145 "VST(1|2)LN(d|q)(WB_fixed_|WB_register_)?Asm",146 "VST(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm",147 "WIN__CHKSTK", "WIN__DBZCHK")>;148 149// Miscellaneous150// -----------------------------------------------------------------------------151 152def : InstRW<[A57Write_1cyc_1I], (instrs COPY)>;153 154// --- 3.2 Branch Instructions ---155// B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ156 157def : InstRW<[A57Write_1cyc_1B], (instregex "(t2|t)?B$", "t?BX", "(t2|t)?Bcc$",158 "t?TAILJMP(d|r)", "TCRETURN(d|r)i", "tBfar", "tCBN?Z")>;159def : InstRW<[A57Write_1cyc_1B_1I],160 (instregex "t?BL$", "BL_pred$", "t?BLXi", "t?TPsoft")>;161def : InstRW<[A57Write_2cyc_1B_1I], (instregex "BLX", "tBLX(NS)?r")>;162// Pseudos163def : InstRW<[A57Write_2cyc_1B_1I], (instregex "BCCi64", "BCCZi64")>;164def : InstRW<[A57Write_3cyc_1B_1I], (instregex "BR_JTadd", "t?BR_JTr",165 "t2BR_JT", "t2BXJ", "(t2)?TB(B|H)(_JT)?$", "tBRIND")>;166def : InstRW<[A57Write_6cyc_1B_1L], (instregex "BR_JTm")>;167 168// --- 3.3 Arithmetic and Logical Instructions ---169// ADD{S}, ADC{S}, ADR, AND{S}, BIC{S}, CMN, CMP, EOR{S}, ORN{S}, ORR{S},170// RSB{S}, RSC{S}, SUB{S}, SBC{S}, TEQ, TST171 172def : InstRW<[A57Write_1cyc_1I], (instregex "tADDframe")>;173 174// Check branch forms of ALU ops:175// check reg 0 for ARM_AM::PC176// if so adds 2 cyc to latency, 1 uop, 1 res cycle for A57UnitB177class A57BranchForm<SchedWriteRes non_br> :178 BranchWriteRes<2, 1, [A57UnitB], [1], non_br>;179 180// shift by register, conditional or unconditional181// TODO: according to the doc, conditional uses I0/I1, unconditional uses M182// Why more complex instruction uses more simple pipeline?183// May be an error in doc.184def A57WriteALUsr : SchedWriteVariant<[185 SchedVar<IsPredicatedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1I>>]>,186 SchedVar<NoSchedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>187]>;188def A57WriteALUSsr : SchedWriteVariant<[189 SchedVar<IsPredicatedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1I>>]>,190 SchedVar<NoSchedPred, [CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>]>191]>;192def A57ReadALUsr : SchedReadVariant<[193 SchedVar<IsPredicatedPred, [ReadDefault]>,194 SchedVar<NoSchedPred, [ReadDefault]>195]>;196def : SchedAlias<WriteALUsi, CheckBranchForm<0, A57BranchForm<A57Write_2cyc_1M>>>;197def : SchedAlias<WriteALUsr, A57WriteALUsr>;198def : SchedAlias<WriteALUSsr, A57WriteALUSsr>;199def : SchedAlias<ReadALUsr, A57ReadALUsr>;200 201def A57WriteCMPsr : SchedWriteVariant<[202 SchedVar<IsPredicatedPred, [A57Write_2cyc_1I]>,203 SchedVar<NoSchedPred, [A57Write_2cyc_1M]>204]>;205def : SchedAlias<WriteCMP, A57Write_1cyc_1I>;206def : SchedAlias<WriteCMPsi, A57Write_2cyc_1M>;207def : SchedAlias<WriteCMPsr, A57WriteCMPsr>;208 209// --- 3.4 Move and Shift Instructions ---210// Move, basic211// MOV{S}, MOVW, MVN{S}212def : InstRW<[A57Write_1cyc_1I], (instregex "MOV(r|i|i16|r_TC)",213 "(t2)?MVN(CC)?(r|i)", "BMOVPCB_CALL", "BMOVPCRX_CALL",214 "MOVCC(r|i|i16|i32imm)", "tMOV", "tMVN")>;215 216// Move, shift by immed, setflags/no setflags217// (ASR, LSL, LSR, ROR, RRX)=MOVsi, MVN218// setflags = isCPSRDefined219def A57WriteMOVsi : SchedWriteVariant<[220 SchedVar<IsCPSRDefinedPred, [A57Write_2cyc_1M]>,221 SchedVar<NoSchedPred, [A57Write_1cyc_1I]>222]>;223def : InstRW<[A57WriteMOVsi], (instregex "MOV(CC)?si", "MVNsi",224 "ASRi", "(t2|t)ASRri", "LSRi", "(t2|t)LSRri", "LSLi", "(t2|t)LSLri", "RORi",225 "(t2|t)RORri", "(t2)?RRX", "t2MOV", "tROR")>;226 227// shift by register, conditional or unconditional, setflags/no setflags228def A57WriteMOVsr : SchedWriteVariant<[229 SchedVar<IsCPSRDefinedAndPredicatedPred, [A57Write_2cyc_1I]>,230 SchedVar<IsCPSRDefinedPred, [A57Write_2cyc_1M]>,231 SchedVar<IsPredicatedPred, [A57Write_2cyc_1I]>,232 SchedVar<NoSchedPred, [A57Write_1cyc_1I]>233]>;234def : InstRW<[A57WriteMOVsr], (instregex "MOV(CC)?sr", "MVNsr", "t2MVNs",235 "ASRr", "(t2|t)ASRrr", "LSRr", "(t2|t)LSRrr", "LSLr", "(t2|t)?LSLrr", "RORr",236 "(t2|t)RORrr")>;237 238// Move, top239// MOVT - A57Write_2cyc_1M for r0px, A57Write_1cyc_1I for r1p0 and later240def A57WriteMOVT : SchedWriteVariant<[241 SchedVar<IsR1P0AndLaterPred, [A57Write_1cyc_1I]>,242 SchedVar<NoSchedPred, [A57Write_2cyc_1M]>243]>;244def : InstRW<[A57WriteMOVT], (instregex "MOVTi16")>;245 246def A57WriteI2pc :247 WriteSequence<[A57Write_1cyc_1I, A57Write_1cyc_1I, A57Write_1cyc_1I]>;248def A57WriteI2ld :249 WriteSequence<[A57Write_1cyc_1I, A57Write_1cyc_1I, A57Write_4cyc_1L]>;250def : InstRW< [A57WriteI2pc], (instregex "MOV_ga_pcrel")>;251def : InstRW< [A57WriteI2ld], (instregex "MOV_ga_pcrel_ldr")>;252 253// +2cyc for branch forms254def : InstRW<[A57Write_3cyc_1I], (instregex "MOVPC(LR|RX)")>;255 256// --- 3.5 Divide and Multiply Instructions ---257// Divide: SDIV, UDIV258// latency from documentration: 4 ‐ 20, maximum taken259def : SchedAlias<WriteDIV, A57Write_20cyc_1M>;260// Multiply: tMul not bound to common WriteRes types261def : InstRW<[A57Write_3cyc_1M], (instregex "tMUL")>;262def : SchedAlias<WriteMUL16, A57Write_3cyc_1M>;263def : SchedAlias<WriteMUL32, A57Write_3cyc_1M>;264def : ReadAdvance<ReadMUL, 0>;265 266// Multiply accumulate: MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB,267// SMLAWT, SMLAD{X}, SMLSD{X}, SMMLA{R}, SMMLS{R}268// Multiply-accumulate pipelines support late-forwarding of accumulate operands269// from similar μops, allowing a typical sequence of multiply-accumulate μops270// to issue one every 1 cycle (sched advance = 2).271def A57WriteMLA : SchedWriteRes<[A57UnitM]> { let Latency = 3; }272def A57WriteMLAL : SchedWriteVariant<[273 SchedVar<IsCPSRDefinedPred, [A57Write_5cyc_1I_1M]>,274 SchedVar<NoSchedPred, [A57Write_4cyc_1M]>275]>;276 277def A57ReadMLA : SchedReadAdvance<2, [A57WriteMLA, A57WriteMLAL]>;278 279def : InstRW<[A57WriteMLA],280 (instregex "t2SMLAD", "t2SMLADX", "t2SMLSD", "t2SMLSDX")>;281 282def : SchedAlias<WriteMAC16, A57WriteMLA>;283def : SchedAlias<WriteMAC32, A57WriteMLA>;284def : SchedAlias<ReadMAC, A57ReadMLA>;285 286def : SchedAlias<WriteMAC64Lo, A57WriteMLAL>;287def : SchedAlias<WriteMAC64Hi, A57WriteMLAL>;288 289// Multiply long: SMULL, UMULL290def : SchedAlias<WriteMUL64Lo, A57Write_4cyc_1M>;291def : SchedAlias<WriteMUL64Hi, A57Write_4cyc_1M>;292 293// --- 3.6 Saturating and Parallel Arithmetic Instructions ---294// Parallel arith295// SADD16, SADD8, SSUB16, SSUB8, UADD16, UADD8, USUB16, USUB8296// Conditional GE-setting instructions require three extra μops297// and two additional cycles to conditionally update the GE field.298def A57WriteParArith : SchedWriteVariant<[299 SchedVar<IsPredicatedPred, [A57Write_4cyc_1I_1M]>,300 SchedVar<NoSchedPred, [A57Write_2cyc_1I_1M]>301]>;302def : InstRW< [A57WriteParArith], (instregex303 "(t2)?SADD(16|8)", "(t2)?SSUB(16|8)",304 "(t2)?UADD(16|8)", "(t2)?USUB(16|8)")>;305 306// Parallel arith with exchange: SASX, SSAX, UASX, USAX307def A57WriteParArithExch : SchedWriteVariant<[308 SchedVar<IsPredicatedPred, [A57Write_5cyc_1I_1M]>,309 SchedVar<NoSchedPred, [A57Write_3cyc_1I_1M]>310]>;311def : InstRW<[A57WriteParArithExch],312 (instregex "(t2)?SASX", "(t2)?SSAX", "(t2)?UASX", "(t2)?USAX")>;313 314// Parallel halving arith315// SHADD16, SHADD8, SHSUB16, SHSUB8, UHADD16, UHADD8, UHSUB16, UHSUB8316def : InstRW<[A57Write_2cyc_1M], (instregex317 "(t2)?SHADD(16|8)", "(t2)?SHSUB(16|8)",318 "(t2)?UHADD(16|8)", "(t2)?UHSUB(16|8)")>;319 320// Parallel halving arith with exchange321// SHASX, SHSAX, UHASX, UHSAX322def : InstRW<[A57Write_3cyc_1I_1M], (instregex "(t2)?SHASX", "(t2)?SHSAX",323 "(t2)?UHASX", "(t2)?UHSAX")>;324 325// Parallel saturating arith326// QADD16, QADD8, QSUB16, QSUB8, UQADD16, UQADD8, UQSUB16, UQSUB8327def : InstRW<[A57Write_2cyc_1M], (instregex "QADD(16|8)", "QSUB(16|8)",328 "UQADD(16|8)", "UQSUB(16|8)", "t2(U?)QADD", "t2(U?)QSUB")>;329 330// Parallel saturating arith with exchange331// QASX, QSAX, UQASX, UQSAX332def : InstRW<[A57Write_3cyc_1I_1M], (instregex "(t2)?QASX", "(t2)?QSAX",333 "(t2)?UQASX", "(t2)?UQSAX")>;334 335// Saturate: SSAT, SSAT16, USAT, USAT16336def : InstRW<[A57Write_2cyc_1M],337 (instregex "(t2)?SSAT(16)?", "(t2)?USAT(16)?")>;338 339// Saturating arith: QADD, QSUB340def : InstRW<[A57Write_2cyc_1M], (instregex "QADD$", "QSUB$")>;341 342// Saturating doubling arith: QDADD, QDSUB343def : InstRW<[A57Write_3cyc_1I_1M], (instregex "(t2)?QDADD", "(t2)?QDSUB")>;344 345// --- 3.7 Miscellaneous Data-Processing Instructions ---346// Bit field extract: SBFX, UBFX347def : InstRW<[A57Write_1cyc_1I], (instregex "(t2)?SBFX", "(t2)?UBFX")>;348 349// Bit field insert/clear: BFI, BFC350def : InstRW<[A57Write_2cyc_1M], (instregex "(t2)?BFI", "(t2)?BFC")>;351 352// Select bytes, conditional/unconditional353def A57WriteSEL : SchedWriteVariant<[354 SchedVar<IsPredicatedPred, [A57Write_2cyc_1I]>,355 SchedVar<NoSchedPred, [A57Write_1cyc_1I]>356]>;357def : InstRW<[A57WriteSEL], (instregex "(t2)?SEL")>;358 359// Sign/zero extend, normal: SXTB, SXTH, UXTB, UXTH360def : InstRW<[A57Write_1cyc_1I],361 (instregex "(t2|t)?SXT(B|H)$", "(t2|t)?UXT(B|H)$")>;362 363// Sign/zero extend and add, normal: SXTAB, SXTAH, UXTAB, UXTAH364def : InstRW<[A57Write_2cyc_1M],365 (instregex "(t2)?SXTA(B|H)$", "(t2)?UXTA(B|H)$")>;366 367// Sign/zero extend and add, parallel: SXTAB16, UXTAB16368def : InstRW<[A57Write_4cyc_1M], (instregex "(t2)?SXTAB16", "(t2)?UXTAB16")>;369 370// Sum of absolute differences: USAD8, USADA8371def : InstRW<[A57Write_3cyc_1M], (instregex "(t2)?USAD8", "(t2)?USADA8")>;372 373// --- 3.8 Load Instructions ---374 375// Load, immed offset376// LDR and LDRB have LDRi12 and LDRBi12 forms for immediate377def : InstRW<[A57Write_4cyc_1L], (instregex "LDRi12", "LDRBi12",378 "LDRcp", "(t2|t)?LDRConstPool", "LDRLIT_ga_(pcrel|abs)",379 "PICLDR", "tLDR")>;380 381def : InstRW<[A57Write_4cyc_1L],382 (instregex "t2LDRS?(B|H)?(pcrel|T|i8|i12|pci|pci_pic|s)?$")>;383 384// For "Load, register offset, minus" we need +1cyc, +1I385def A57WriteLdrAm3 : SchedWriteVariant<[386 SchedVar<IsLdrAm3NegRegOffPred, [A57Write_5cyc_1I_1L]>,387 SchedVar<NoSchedPred, [A57Write_4cyc_1L]>388]>;389def : InstRW<[A57WriteLdrAm3], (instregex "LDR(H|SH|SB)$")>;390def A57WriteLdrAm3X2 : SchedWriteVariant<[391 SchedVar<IsLdrAm3NegRegOffPredX2, [A57Write_5cyc_1I_1L]>,392 SchedVar<NoSchedPred, [A57Write_4cyc_1L]>393]>;394def : InstRW<[A57WriteLdrAm3X2, A57WriteLdrAm3X2], (instregex "LDRD$")>;395def : InstRW<[A57Write_4cyc_1L, A57Write_4cyc_1L], (instregex "t2LDRDi8")>;396 397def A57WriteLdrAmLDSTSO : SchedWriteVariant<[398 SchedVar<IsLdstsoScaledNotOptimalPred, [A57Write_5cyc_1I_1L]>,399 SchedVar<IsLdstsoMinusRegPred, [A57Write_5cyc_1I_1L]>,400 SchedVar<NoSchedPred, [A57Write_4cyc_1L]>401]>;402def : InstRW<[A57WriteLdrAmLDSTSO], (instregex "LDRrs", "LDRBrs")>;403 404def A57WrBackOne : SchedWriteRes<[]> {405 let Latency = 1;406 let NumMicroOps = 0;407}408def A57WrBackTwo : SchedWriteRes<[]> {409 let Latency = 2;410 let NumMicroOps = 0;411}412def A57WrBackThree : SchedWriteRes<[]> {413 let Latency = 3;414 let NumMicroOps = 0;415}416 417// --- LDR pre-indexed ---418// Load, immed pre-indexed (4 cyc for load result, 1 cyc for Base update)419def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackOne], (instregex "LDR_PRE_IMM",420 "LDRB_PRE_IMM", "t2LDRB_PRE")>;421 422// Load, register pre-indexed (4 cyc for load result, 2 cyc for Base update)423// (5 cyc load result for not-lsl2 scaled)424def A57WriteLdrAmLDSTSOPre : SchedWriteVariant<[425 SchedVar<IsLdstsoScaledNotOptimalPredX2, [A57Write_5cyc_1I_1L]>,426 SchedVar<NoSchedPred, [A57Write_4cyc_1L_1I]>427]>;428def : InstRW<[A57WriteLdrAmLDSTSOPre, A57WrBackTwo],429 (instregex "LDR_PRE_REG", "LDRB_PRE_REG")>;430 431def A57WriteLdrAm3PreWrBack : SchedWriteVariant<[432 SchedVar<IsLdrAm3RegOffPredX2, [A57WrBackTwo]>,433 SchedVar<NoSchedPred, [A57WrBackOne]>434]>;435def : InstRW<[A57Write_4cyc_1L, A57WriteLdrAm3PreWrBack],436 (instregex "LDR(H|SH|SB)_PRE")>;437def : InstRW<[A57Write_4cyc_1L, A57WrBackOne],438 (instregex "t2LDR(H|SH|SB)?_PRE")>;439 440// LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm.441def A57WriteLdrDAm3Pre : SchedWriteVariant<[442 SchedVar<IsLdrAm3RegOffPredX3, [A57Write_5cyc_1I_1L]>,443 SchedVar<NoSchedPred, [A57Write_4cyc_1L_1I]>444]>;445def A57WriteLdrDAm3PreWrBack : SchedWriteVariant<[446 SchedVar<IsLdrAm3RegOffPredX3, [A57WrBackTwo]>,447 SchedVar<NoSchedPred, [A57WrBackOne]>448]>;449def : InstRW<[A57WriteLdrDAm3Pre, A57WriteLdrDAm3Pre, A57WriteLdrDAm3PreWrBack],450 (instregex "LDRD_PRE")>;451def : InstRW<[A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57WrBackOne],452 (instregex "t2LDRD_PRE")>;453 454// --- LDR post-indexed ---455def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackOne], (instregex "LDR(T?)_POST_IMM",456 "LDRB(T?)_POST_IMM", "LDR(SB|H|SH)Ti", "t2LDRB_POST")>;457 458def A57WriteLdrAm3PostWrBack : SchedWriteVariant<[459 SchedVar<IsLdrAm3RegOffPred, [A57WrBackTwo]>,460 SchedVar<NoSchedPred, [A57WrBackOne]>461]>;462def : InstRW<[A57Write_4cyc_1L_1I, A57WriteLdrAm3PostWrBack],463 (instregex "LDR(H|SH|SB)_POST")>;464def : InstRW<[A57Write_4cyc_1L, A57WrBackOne],465 (instregex "t2LDR(H|SH|SB)?_POST")>;466 467def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR_POST_REG",468 "LDRB_POST_REG", "LDR(B?)T_POST$")>;469 470def A57WriteLdrTRegPost : SchedWriteVariant<[471 SchedVar<IsLdstsoScaledPredX2, [A57Write_4cyc_1I_1L_1M]>,472 SchedVar<NoSchedPred, [A57Write_4cyc_1L_1I]>473]>;474def A57WriteLdrTRegPostWrBack : SchedWriteVariant<[475 SchedVar<IsLdstsoScaledPredX2, [A57WrBackThree]>,476 SchedVar<NoSchedPred, [A57WrBackTwo]>477]>;478// 4(3) "I0/I1,L,M" for scaled register, otherwise 4(2) "I0/I1,L"479def : InstRW<[A57WriteLdrTRegPost, A57WriteLdrTRegPostWrBack],480 (instregex "LDRT_POST_REG", "LDRBT_POST_REG")>;481 482def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR(SB|H|SH)Tr")>;483 484def A57WriteLdrAm3PostWrBackX3 : SchedWriteVariant<[485 SchedVar<IsLdrAm3RegOffPredX3, [A57WrBackTwo]>,486 SchedVar<NoSchedPred, [A57WrBackOne]>487]>;488// LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm.489def : InstRW<[A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I,490 A57WriteLdrAm3PostWrBackX3], (instregex "LDRD_POST")>;491def : InstRW<[A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I, A57WrBackOne],492 (instregex "t2LDRD_POST")>;493 494// --- Preload instructions ---495// Preload, immed offset496def : InstRW<[A57Write_4cyc_1L], (instregex "(t2)?PLDi12", "(t2)?PLDWi12",497 "t2PLDW?(i8|pci|s)", "(t2)?PLI")>;498 499// Preload, register offset,500// 5cyc "I0/I1,L" for minus reg or scaled not plus lsl2501// otherwise 4cyc "L"502def A57WritePLD : SchedWriteVariant<[503 SchedVar<IsLdstsoScaledNotOptimalPredX0, [A57Write_5cyc_1I_1L]>,504 SchedVar<IsLdstsoMinusRegPredX0, [A57Write_5cyc_1I_1L]>,505 SchedVar<NoSchedPred, [A57Write_4cyc_1L]>506]>;507def : InstRW<[A57WritePLD], (instregex "PLDrs", "PLDWrs")>;508 509// --- Load multiple instructions ---510foreach NumAddr = 1-8 in {511 def A57LMAddrPred#NumAddr : MCSchedPredicate<CheckAny<[512 CheckNumOperands<!add(!shl(NumAddr, 1), 2)>,513 CheckNumOperands<!add(!shl(NumAddr, 1), 3)>]>>;514 def A57LMAddrUpdPred#NumAddr : MCSchedPredicate<CheckAny<[515 CheckNumOperands<!add(!shl(NumAddr, 1), 3)>,516 CheckNumOperands<!add(!shl(NumAddr, 1), 4)>]>>;517}518 519def A57LDMOpsListNoregin : A57WriteLMOpsListType<520 [A57Write_3cyc_1L, A57Write_3cyc_1L,521 A57Write_4cyc_1L, A57Write_4cyc_1L,522 A57Write_5cyc_1L, A57Write_5cyc_1L,523 A57Write_6cyc_1L, A57Write_6cyc_1L,524 A57Write_7cyc_1L, A57Write_7cyc_1L,525 A57Write_8cyc_1L, A57Write_8cyc_1L,526 A57Write_9cyc_1L, A57Write_9cyc_1L,527 A57Write_10cyc_1L, A57Write_10cyc_1L]>;528def A57WriteLDMnoreginlist : SchedWriteVariant<[529 SchedVar<A57LMAddrPred1, A57LDMOpsListNoregin.Writes[0-1]>,530 SchedVar<A57LMAddrPred2, A57LDMOpsListNoregin.Writes[0-3]>,531 SchedVar<A57LMAddrPred3, A57LDMOpsListNoregin.Writes[0-5]>,532 SchedVar<A57LMAddrPred4, A57LDMOpsListNoregin.Writes[0-7]>,533 SchedVar<A57LMAddrPred5, A57LDMOpsListNoregin.Writes[0-9]>,534 SchedVar<A57LMAddrPred6, A57LDMOpsListNoregin.Writes[0-11]>,535 SchedVar<A57LMAddrPred7, A57LDMOpsListNoregin.Writes[0-13]>,536 SchedVar<A57LMAddrPred8, A57LDMOpsListNoregin.Writes[0-15]>,537 SchedVar<NoSchedPred, A57LDMOpsListNoregin.Writes[0-15]>538]> { let Variadic=1; }539 540def A57LDMOpsListRegin : A57WriteLMOpsListType<541 [A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I,542 A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I,543 A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I,544 A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I,545 A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I,546 A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I,547 A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I,548 A57Write_11cyc_1L_1I, A57Write_11cyc_1L_1I]>;549def A57WriteLDMreginlist : SchedWriteVariant<[550 SchedVar<A57LMAddrPred1, A57LDMOpsListRegin.Writes[0-1]>,551 SchedVar<A57LMAddrPred2, A57LDMOpsListRegin.Writes[0-3]>,552 SchedVar<A57LMAddrPred3, A57LDMOpsListRegin.Writes[0-5]>,553 SchedVar<A57LMAddrPred4, A57LDMOpsListRegin.Writes[0-7]>,554 SchedVar<A57LMAddrPred5, A57LDMOpsListRegin.Writes[0-9]>,555 SchedVar<A57LMAddrPred6, A57LDMOpsListRegin.Writes[0-11]>,556 SchedVar<A57LMAddrPred7, A57LDMOpsListRegin.Writes[0-13]>,557 SchedVar<A57LMAddrPred8, A57LDMOpsListRegin.Writes[0-15]>,558 SchedVar<NoSchedPred, A57LDMOpsListRegin.Writes[0-15]>559]> { let Variadic=1; }560 561def A57LDMOpsList_Upd : A57WriteLMOpsListType<562 [A57WrBackOne,563 A57Write_3cyc_1L_1I, A57Write_3cyc_1L_1I,564 A57Write_4cyc_1L_1I, A57Write_4cyc_1L_1I,565 A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I,566 A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I,567 A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I,568 A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I,569 A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I,570 A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I]>;571def A57WriteLDM_Upd : SchedWriteVariant<[572 SchedVar<A57LMAddrUpdPred1, A57LDMOpsList_Upd.Writes[0-2]>,573 SchedVar<A57LMAddrUpdPred2, A57LDMOpsList_Upd.Writes[0-4]>,574 SchedVar<A57LMAddrUpdPred3, A57LDMOpsList_Upd.Writes[0-6]>,575 SchedVar<A57LMAddrUpdPred4, A57LDMOpsList_Upd.Writes[0-8]>,576 SchedVar<A57LMAddrUpdPred5, A57LDMOpsList_Upd.Writes[0-10]>,577 SchedVar<A57LMAddrUpdPred6, A57LDMOpsList_Upd.Writes[0-12]>,578 SchedVar<A57LMAddrUpdPred7, A57LDMOpsList_Upd.Writes[0-14]>,579 SchedVar<A57LMAddrUpdPred8, A57LDMOpsList_Upd.Writes[0-16]>,580 SchedVar<NoSchedPred, A57LDMOpsList_Upd.Writes[0-16]>581]> { let Variadic=1; }582 583def A57WriteLDM : SchedWriteVariant<[584 SchedVar<IsLDMBaseRegInListPred, [A57WriteLDMreginlist]>,585 SchedVar<NoSchedPred, [A57WriteLDMnoreginlist]>586]> { let Variadic=1; }587 588def : InstRW<[A57WriteLDM], (instregex "(t|t2|sys)?LDM(IA|DA|DB|IB)$")>;589 590// TODO: no writeback latency defined in documentation (implemented as 1 cyc)591def : InstRW<[A57WriteLDM_Upd],592 (instregex "(t|t2|sys)?LDM(IA_UPD|DA_UPD|DB_UPD|IB_UPD|IA_RET)", "tPOP")>;593 594def : InstRW<[A57Write_5cyc_1L], (instregex "VLLDM")>;595 596// --- 3.9 Store Instructions ---597 598// Store, immed offset599def : InstRW<[A57Write_1cyc_1S], (instregex "STRi12", "STRBi12", "PICSTR",600 "t2STR(B?)(T|i12|i8|s)", "t2STRDi8", "t2STRH(i12|i8|s)", "tSTR")>;601 602// Store, register offset603// For minus or for not plus lsl2 scaled we need 3cyc "I0/I1, S",604// otherwise 1cyc S.605def A57WriteStrAmLDSTSO : SchedWriteVariant<[606 SchedVar<IsLdstsoScaledNotOptimalPred, [A57Write_3cyc_1I_1S]>,607 SchedVar<IsLdstsoMinusRegPred, [A57Write_3cyc_1I_1S]>,608 SchedVar<NoSchedPred, [A57Write_1cyc_1S]>609]>;610def : InstRW<[A57WriteStrAmLDSTSO], (instregex "STRrs", "STRBrs")>;611 612// STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg.613def A57WriteStrAm3 : SchedWriteVariant<[614 SchedVar<IsLdrAm3NegRegOffPred, [A57Write_3cyc_1I_1S]>,615 SchedVar<NoSchedPred, [A57Write_1cyc_1S]>616]>;617def : InstRW<[A57WriteStrAm3], (instregex "STRH$")>;618def A57WriteStrAm3X2 : SchedWriteVariant<[619 SchedVar<IsLdrAm3NegRegOffPredX2, [A57Write_3cyc_1I_1S]>,620 SchedVar<NoSchedPred, [A57Write_1cyc_1S]>621]>;622def : InstRW<[A57WriteStrAm3X2], (instregex "STRD$")>;623 624// Store, immed pre-indexed (1cyc "S, I0/I1", 1cyc writeback)625def : InstRW<[A57WrBackOne, A57Write_1cyc_1S_1I], (instregex "STR_PRE_IMM",626 "STRB_PRE_IMM", "STR(B)?(r|i)_preidx", "(t2)?STRH_(preidx|PRE)",627 "t2STR(B?)_(PRE|preidx)", "t2STRD_PRE")>;628 629// Store, register pre-indexed:630// 1(1) "S, I0/I1" for plus reg631// 3(2) "I0/I1, S" for minus reg632// 1(2) "S, M" for scaled plus lsl2633// 3(2) "I0/I1, S" for other scaled634def A57WriteStrAmLDSTSOPre : SchedWriteVariant<[635 SchedVar<IsLdstsoScaledNotOptimalPredX2, [A57Write_3cyc_1I_1S]>,636 SchedVar<IsLdstsoMinusRegPredX2, [A57Write_3cyc_1I_1S]>,637 SchedVar<IsLdstsoScaledPredX2, [A57Write_1cyc_1S_1M]>,638 SchedVar<NoSchedPred, [A57Write_1cyc_1S_1I]>639]>;640def A57WriteStrAmLDSTSOPreWrBack : SchedWriteVariant<[641 SchedVar<IsLdstsoScaledPredX2, [A57WrBackTwo]>,642 SchedVar<IsLdstsoMinusRegPredX2, [A57WrBackTwo]>,643 SchedVar<NoSchedPred, [A57WrBackOne]>644]>;645def : InstRW<[A57WriteStrAmLDSTSOPreWrBack, A57WriteStrAmLDSTSOPre],646 (instregex "STR_PRE_REG", "STRB_PRE_REG")>;647 648// pre-indexed STRH/STRD (STRH_PRE, STRD_PRE)649// 1(1) "S, I0/I1" for imm or reg plus650// 3(2) "I0/I1, S" for reg minus651def A57WriteStrAm3PreX2 : SchedWriteVariant<[652 SchedVar<IsLdrAm3NegRegOffPredX2, [A57Write_3cyc_1I_1S]>,653 SchedVar<NoSchedPred, [A57Write_1cyc_1S_1I]>654]>;655def A57WriteStrAm3PreWrBackX2 : SchedWriteVariant<[656 SchedVar<IsLdrAm3NegRegOffPredX2, [A57WrBackTwo]>,657 SchedVar<NoSchedPred, [A57WrBackOne]>658]>;659def : InstRW<[A57WriteStrAm3PreWrBackX2, A57WriteStrAm3PreX2],660 (instregex "STRH_PRE")>;661 662def A57WriteStrAm3PreX3 : SchedWriteVariant<[663 SchedVar<IsLdrAm3NegRegOffPredX3, [A57Write_3cyc_1I_1S]>,664 SchedVar<NoSchedPred, [A57Write_1cyc_1S_1I]>665]>;666def A57WriteStrAm3PreWrBackX3 : SchedWriteVariant<[667 SchedVar<IsLdrAm3NegRegOffPredX3, [A57WrBackTwo]>,668 SchedVar<NoSchedPred, [A57WrBackOne]>669]>;670def : InstRW<[A57WriteStrAm3PreWrBackX3, A57WriteStrAm3PreX3],671 (instregex "STRD_PRE")>;672 673def : InstRW<[A57WrBackOne, A57Write_1cyc_1S_1I], (instregex "STR(T?)_POST_IMM",674 "STRB(T?)_POST_IMM", "t2STR(B?)_POST")>;675 676// 1(2) "S, M" for STR/STRB register post-indexed (both scaled or not)677def : InstRW<[A57WrBackTwo, A57Write_1cyc_1S_1M], (instregex "STR(T?)_POST_REG",678 "STRB(T?)_POST_REG", "STR(B?)T_POST$")>;679 680// post-indexed STRH/STRD(STRH_POST, STRD_POST), STRHTi, STRHTr681// 1(1) "S, I0/I1" both for reg or imm682def : InstRW<[A57WrBackOne, A57Write_1cyc_1S_1I],683 (instregex "(t2)?STR(H|D)_POST", "STRHT(i|r)", "t2STRHT")>;684 685// --- Store multiple instructions ---686// TODO: no writeback latency defined in documentation687def A57WriteSTM : SchedWriteVariant<[688 SchedVar<A57LMAddrPred1, [A57Write_1cyc_1S]>,689 SchedVar<A57LMAddrPred2, [A57Write_2cyc_1S]>,690 SchedVar<A57LMAddrPred3, [A57Write_3cyc_1S]>,691 SchedVar<A57LMAddrPred4, [A57Write_4cyc_1S]>,692 SchedVar<A57LMAddrPred5, [A57Write_5cyc_1S]>,693 SchedVar<A57LMAddrPred6, [A57Write_6cyc_1S]>,694 SchedVar<A57LMAddrPred7, [A57Write_7cyc_1S]>,695 SchedVar<A57LMAddrPred8, [A57Write_8cyc_1S]>,696 SchedVar<NoSchedPred, [A57Write_2cyc_1S]>697]>;698def A57WriteSTM_Upd : SchedWriteVariant<[699 SchedVar<A57LMAddrPred1, [A57Write_1cyc_1S_1I]>,700 SchedVar<A57LMAddrPred2, [A57Write_2cyc_1S_1I]>,701 SchedVar<A57LMAddrPred3, [A57Write_3cyc_1S_1I]>,702 SchedVar<A57LMAddrPred4, [A57Write_4cyc_1S_1I]>,703 SchedVar<A57LMAddrPred5, [A57Write_5cyc_1S_1I]>,704 SchedVar<A57LMAddrPred6, [A57Write_6cyc_1S_1I]>,705 SchedVar<A57LMAddrPred7, [A57Write_7cyc_1S_1I]>,706 SchedVar<A57LMAddrPred8, [A57Write_8cyc_1S_1I]>,707 SchedVar<NoSchedPred, [A57Write_2cyc_1S_1I]>708]>;709 710def : InstRW<[A57WriteSTM], (instregex "(t2|sys|t)?STM(IA|DA|DB|IB)$")>;711def : InstRW<[A57WrBackOne, A57WriteSTM_Upd],712 (instregex "(t2|sys|t)?STM(IA_UPD|DA_UPD|DB_UPD|IB_UPD)", "tPUSH")>;713 714def : InstRW<[A57Write_5cyc_1S], (instregex "VLSTM")>;715 716// --- 3.10 FP Data Processing Instructions ---717def : SchedAlias<WriteFPALU32, A57Write_5cyc_1V>;718def : SchedAlias<WriteFPALU64, A57Write_5cyc_1V>;719 720def : InstRW<[A57Write_3cyc_1V], (instregex "VABS(S|D|H)")>;721 722// fp compare - 3cyc F1 for unconditional, 6cyc "F0/F1, F1" for conditional723def A57WriteVcmp : SchedWriteVariant<[724 SchedVar<IsPredicatedPred, [A57Write_6cyc_1V_1X]>,725 SchedVar<NoSchedPred, [A57Write_3cyc_1X]>726]>;727def : InstRW<[A57WriteVcmp],728 (instregex "VCMP(D|S|H|ZD|ZS|ZH)$", "VCMPE(D|S|H|ZD|ZS|ZH)")>;729 730// fp convert731def : InstRW<[A57Write_5cyc_1V], (instregex732 "VCVT(A|N|P|M)(SH|UH|SS|US|SD|UD)", "VCVT(BDH|THD|TDH)")>;733def : InstRW<[A57Write_5cyc_1V], (instregex "VTOSLS", "VTOUHS", "VTOULS")>;734def : SchedAlias<WriteFPCVT, A57Write_5cyc_1V>;735 736def : InstRW<[A57Write_5cyc_1V], (instregex "VJCVT")>;737 738// FP round to integral739def : InstRW<[A57Write_5cyc_1V], (instregex "VRINT(A|N|P|M|Z|R|X)(H|S|D)$")>;740 741// FP divide, FP square root742def : SchedAlias<WriteFPDIV32, A57Write_17cyc_1W>;743def : SchedAlias<WriteFPDIV64, A57Write_32cyc_1W>;744def : SchedAlias<WriteFPSQRT32, A57Write_17cyc_1W>;745def : SchedAlias<WriteFPSQRT64, A57Write_32cyc_1W>;746 747def : InstRW<[A57Write_17cyc_1W], (instregex "VSQRTH")>;748 749// FP max/min750def : InstRW<[A57Write_5cyc_1V], (instregex "VMAX", "VMIN")>;751 752// FP multiply-accumulate pipelines support late forwarding of the result753// from FP multiply μops to the accumulate operands of an754// FP multiply-accumulate μop. The latter can potentially be issued 1 cycle755// after the FP multiply μop has been issued756// FP multiply, FZ757def A57WriteVMUL : SchedWriteRes<[A57UnitV]> { let Latency = 5; }758 759def : SchedAlias<WriteFPMUL32, A57WriteVMUL>;760def : SchedAlias<WriteFPMUL64, A57WriteVMUL>;761def : ReadAdvance<ReadFPMUL, 0>;762 763// FP multiply accumulate, FZ: 9cyc "F0/F1" or 4 cyc for sequenced accumulate764// VFMA, VFMS, VFNMA, VFNMS, VMLA, VMLS, VNMLA, VNMLS765def A57WriteVFMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; }766 767// VFMA takes 9 cyc for common case and 4 cyc for VFMA->VFMA chain (5 read adv.)768// VMUL takes 5 cyc for common case and 1 cyc for VMUL->VFMA chain (4 read adv.)769// Currently, there is no way to define different read advances for VFMA operand770// from VFMA or from VMUL, so there will be 5 read advance.771// Zero latency (instead of one) for VMUL->VFMA shouldn't break something.772// The same situation with ASIMD VMUL/VFMA instructions773// def A57ReadVFMA : SchedRead;774// def : ReadAdvance<A57ReadVFMA, 5, [A57WriteVFMA]>;775// def : ReadAdvance<A57ReadVFMA, 4, [A57WriteVMUL]>;776def A57ReadVFMA5 : SchedReadAdvance<5, [A57WriteVFMA, A57WriteVMUL]>;777 778def : SchedAlias<WriteFPMAC32, A57WriteVFMA>;779def : SchedAlias<WriteFPMAC64, A57WriteVFMA>;780def : SchedAlias<ReadFPMAC, A57ReadVFMA5>;781 782// VMLAH/VMLSH are not binded to scheduling classes by default, so here custom:783def : InstRW<[A57WriteVFMA, A57ReadVFMA5, ReadFPMUL, ReadFPMUL],784 (instregex "VMLAH", "VMLSH", "VNMLAH", "VNMLSH")>;785 786def : InstRW<[A57WriteVMUL],787 (instregex "VUDOTD", "VSDOTD", "VUDOTQ", "VSDOTQ")>;788 789def : InstRW<[A57Write_3cyc_1V], (instregex "VNEG")>;790def : InstRW<[A57Write_3cyc_1V], (instregex "VSEL")>;791 792// --- 3.11 FP Miscellaneous Instructions ---793// VMOV: 3cyc "F0/F1" for imm/reg794def : InstRW<[A57Write_3cyc_1V], (instregex "FCONST(D|S|H)")>;795def : InstRW<[A57Write_3cyc_1V], (instregex "VMOV(D|S|H)(cc)?$")>;796 797def : InstRW<[A57Write_3cyc_1V], (instregex "VINSH")>;798 799// 5cyc L for FP transfer, vfp to core reg,800// 5cyc L for FP transfer, core reg to vfp801def : SchedAlias<WriteFPMOV, A57Write_5cyc_1L>;802// VMOVRRS/VMOVRRD in common code declared with one WriteFPMOV (instead of 2).803def : InstRW<[A57Write_5cyc_1L, A57Write_5cyc_1L], (instregex "VMOV(RRS|RRD)")>;804 805// 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg806def : InstRW<[A57Write_8cyc_1L_1I], (instregex "VMOVDRR")>;807 808// --- 3.12 FP Load Instructions ---809def : InstRW<[A57Write_5cyc_1L], (instregex "VLDR(D|S|H)")>;810 811def : InstRW<[A57Write_5cyc_1L], (instregex "VLDMQIA$")>;812 813// FP load multiple (VLDM)814 815def A57VLDMOpsListUncond : A57WriteLMOpsListType<816 [A57Write_5cyc_1L, A57Write_5cyc_1L,817 A57Write_6cyc_1L, A57Write_6cyc_1L,818 A57Write_7cyc_1L, A57Write_7cyc_1L,819 A57Write_8cyc_1L, A57Write_8cyc_1L,820 A57Write_9cyc_1L, A57Write_9cyc_1L,821 A57Write_10cyc_1L, A57Write_10cyc_1L,822 A57Write_11cyc_1L, A57Write_11cyc_1L,823 A57Write_12cyc_1L, A57Write_12cyc_1L]>;824def A57WriteVLDMuncond : SchedWriteVariant<[825 SchedVar<A57LMAddrPred1, A57VLDMOpsListUncond.Writes[0-1]>,826 SchedVar<A57LMAddrPred2, A57VLDMOpsListUncond.Writes[0-3]>,827 SchedVar<A57LMAddrPred3, A57VLDMOpsListUncond.Writes[0-5]>,828 SchedVar<A57LMAddrPred4, A57VLDMOpsListUncond.Writes[0-7]>,829 SchedVar<A57LMAddrPred5, A57VLDMOpsListUncond.Writes[0-9]>,830 SchedVar<A57LMAddrPred6, A57VLDMOpsListUncond.Writes[0-11]>,831 SchedVar<A57LMAddrPred7, A57VLDMOpsListUncond.Writes[0-13]>,832 SchedVar<NoSchedPred, A57VLDMOpsListUncond.Writes[0-15]>833]> { let Variadic=1; }834 835def A57VLDMOpsListCond : A57WriteLMOpsListType<836 [A57Write_5cyc_1L, A57Write_6cyc_1L,837 A57Write_7cyc_1L, A57Write_8cyc_1L,838 A57Write_9cyc_1L, A57Write_10cyc_1L,839 A57Write_11cyc_1L, A57Write_12cyc_1L,840 A57Write_13cyc_1L, A57Write_14cyc_1L,841 A57Write_15cyc_1L, A57Write_16cyc_1L,842 A57Write_17cyc_1L, A57Write_18cyc_1L,843 A57Write_19cyc_1L, A57Write_20cyc_1L]>;844def A57WriteVLDMcond : SchedWriteVariant<[845 SchedVar<A57LMAddrPred1, A57VLDMOpsListCond.Writes[0-1]>,846 SchedVar<A57LMAddrPred2, A57VLDMOpsListCond.Writes[0-3]>,847 SchedVar<A57LMAddrPred3, A57VLDMOpsListCond.Writes[0-5]>,848 SchedVar<A57LMAddrPred4, A57VLDMOpsListCond.Writes[0-7]>,849 SchedVar<A57LMAddrPred5, A57VLDMOpsListCond.Writes[0-9]>,850 SchedVar<A57LMAddrPred6, A57VLDMOpsListCond.Writes[0-11]>,851 SchedVar<A57LMAddrPred7, A57VLDMOpsListCond.Writes[0-13]>,852 SchedVar<NoSchedPred, A57VLDMOpsListCond.Writes[0-15]>853]> { let Variadic=1; }854 855def A57WriteVLDM : SchedWriteVariant<[856 SchedVar<IsPredicatedPred, [A57WriteVLDMcond]>,857 SchedVar<NoSchedPred, [A57WriteVLDMuncond]>858]> { let Variadic=1; }859 860def : InstRW<[A57WriteVLDM], (instregex "VLDM(DIA|SIA)$")>;861 862def A57VLDMOpsListUncond_Upd : A57WriteLMOpsListType<863 [A57Write_5cyc_1L_1I, A57Write_5cyc_1L_1I,864 A57Write_6cyc_1L_1I, A57Write_6cyc_1L_1I,865 A57Write_7cyc_1L_1I, A57Write_7cyc_1L_1I,866 A57Write_8cyc_1L_1I, A57Write_8cyc_1L_1I,867 A57Write_9cyc_1L_1I, A57Write_9cyc_1L_1I,868 A57Write_10cyc_1L_1I, A57Write_10cyc_1L_1I,869 A57Write_11cyc_1L_1I, A57Write_11cyc_1L_1I,870 A57Write_12cyc_1L_1I, A57Write_12cyc_1L_1I]>;871def A57WriteVLDMuncond_UPD : SchedWriteVariant<[872 SchedVar<A57LMAddrPred1, A57VLDMOpsListUncond_Upd.Writes[0-1]>,873 SchedVar<A57LMAddrPred2, A57VLDMOpsListUncond_Upd.Writes[0-3]>,874 SchedVar<A57LMAddrPred3, A57VLDMOpsListUncond_Upd.Writes[0-5]>,875 SchedVar<A57LMAddrPred4, A57VLDMOpsListUncond_Upd.Writes[0-7]>,876 SchedVar<A57LMAddrPred5, A57VLDMOpsListUncond_Upd.Writes[0-9]>,877 SchedVar<A57LMAddrPred6, A57VLDMOpsListUncond_Upd.Writes[0-11]>,878 SchedVar<A57LMAddrPred7, A57VLDMOpsListUncond_Upd.Writes[0-13]>,879 SchedVar<NoSchedPred, A57VLDMOpsListUncond_Upd.Writes[0-15]>880]> { let Variadic=1; }881 882def A57VLDMOpsListCond_Upd : A57WriteLMOpsListType<883 [A57Write_5cyc_1L_1I, A57Write_6cyc_1L_1I,884 A57Write_7cyc_1L_1I, A57Write_8cyc_1L_1I,885 A57Write_9cyc_1L_1I, A57Write_10cyc_1L_1I,886 A57Write_11cyc_1L_1I, A57Write_12cyc_1L_1I,887 A57Write_13cyc_1L_1I, A57Write_14cyc_1L_1I,888 A57Write_15cyc_1L_1I, A57Write_16cyc_1L_1I,889 A57Write_17cyc_1L_1I, A57Write_18cyc_1L_1I,890 A57Write_19cyc_1L_1I, A57Write_20cyc_1L_1I]>;891def A57WriteVLDMcond_UPD : SchedWriteVariant<[892 SchedVar<A57LMAddrPred1, A57VLDMOpsListCond_Upd.Writes[0-1]>,893 SchedVar<A57LMAddrPred2, A57VLDMOpsListCond_Upd.Writes[0-3]>,894 SchedVar<A57LMAddrPred3, A57VLDMOpsListCond_Upd.Writes[0-5]>,895 SchedVar<A57LMAddrPred4, A57VLDMOpsListCond_Upd.Writes[0-7]>,896 SchedVar<A57LMAddrPred5, A57VLDMOpsListCond_Upd.Writes[0-9]>,897 SchedVar<A57LMAddrPred6, A57VLDMOpsListCond_Upd.Writes[0-11]>,898 SchedVar<A57LMAddrPred7, A57VLDMOpsListCond_Upd.Writes[0-13]>,899 SchedVar<NoSchedPred, A57VLDMOpsListCond_Upd.Writes[0-15]>900]> { let Variadic=1; }901 902def A57WriteVLDM_UPD : SchedWriteVariant<[903 SchedVar<IsPredicatedPred, [A57WriteVLDMcond_UPD]>,904 SchedVar<NoSchedPred, [A57WriteVLDMuncond_UPD]>905]> { let Variadic=1; }906 907def : InstRW<[A57WrBackOne, A57WriteVLDM_UPD],908 (instregex "VLDM(DIA_UPD|DDB_UPD|SIA_UPD|SDB_UPD)")>;909 910// --- 3.13 FP Store Instructions ---911def : InstRW<[A57Write_1cyc_1S], (instregex "VSTR(D|S|H)")>;912 913def : InstRW<[A57Write_2cyc_1S], (instregex "VSTMQIA$")>;914 915def A57WriteVSTMs : SchedWriteVariant<[916 SchedVar<A57LMAddrPred1, [A57Write_1cyc_1S]>,917 SchedVar<A57LMAddrPred2, [A57Write_2cyc_1S]>,918 SchedVar<A57LMAddrPred3, [A57Write_3cyc_1S]>,919 SchedVar<A57LMAddrPred4, [A57Write_4cyc_1S]>,920 SchedVar<A57LMAddrPred5, [A57Write_5cyc_1S]>,921 SchedVar<A57LMAddrPred6, [A57Write_6cyc_1S]>,922 SchedVar<A57LMAddrPred7, [A57Write_7cyc_1S]>,923 SchedVar<A57LMAddrPred8, [A57Write_8cyc_1S]>,924 SchedVar<NoSchedPred, [A57Write_2cyc_1S]>925]>;926def A57WriteVSTMd : SchedWriteVariant<[927 SchedVar<A57LMAddrPred1, [A57Write_2cyc_1S]>,928 SchedVar<A57LMAddrPred2, [A57Write_4cyc_1S]>,929 SchedVar<A57LMAddrPred3, [A57Write_6cyc_1S]>,930 SchedVar<A57LMAddrPred4, [A57Write_8cyc_1S]>,931 SchedVar<A57LMAddrPred5, [A57Write_10cyc_1S]>,932 SchedVar<A57LMAddrPred6, [A57Write_12cyc_1S]>,933 SchedVar<A57LMAddrPred7, [A57Write_14cyc_1S]>,934 SchedVar<A57LMAddrPred8, [A57Write_16cyc_1S]>,935 SchedVar<NoSchedPred, [A57Write_4cyc_1S]>936]>;937def A57WriteVSTMs_Upd : SchedWriteVariant<[938 SchedVar<A57LMAddrPred1, [A57Write_1cyc_1S_1I]>,939 SchedVar<A57LMAddrPred2, [A57Write_2cyc_1S_1I]>,940 SchedVar<A57LMAddrPred3, [A57Write_3cyc_1S_1I]>,941 SchedVar<A57LMAddrPred4, [A57Write_4cyc_1S_1I]>,942 SchedVar<A57LMAddrPred5, [A57Write_5cyc_1S_1I]>,943 SchedVar<A57LMAddrPred6, [A57Write_6cyc_1S_1I]>,944 SchedVar<A57LMAddrPred7, [A57Write_7cyc_1S_1I]>,945 SchedVar<A57LMAddrPred8, [A57Write_8cyc_1S_1I]>,946 SchedVar<NoSchedPred, [A57Write_2cyc_1S_1I]>947]>;948def A57WriteVSTMd_Upd : SchedWriteVariant<[949 SchedVar<A57LMAddrPred1, [A57Write_2cyc_1S_1I]>,950 SchedVar<A57LMAddrPred2, [A57Write_4cyc_1S_1I]>,951 SchedVar<A57LMAddrPred3, [A57Write_6cyc_1S_1I]>,952 SchedVar<A57LMAddrPred4, [A57Write_8cyc_1S_1I]>,953 SchedVar<A57LMAddrPred5, [A57Write_10cyc_1S_1I]>,954 SchedVar<A57LMAddrPred6, [A57Write_12cyc_1S_1I]>,955 SchedVar<A57LMAddrPred7, [A57Write_14cyc_1S_1I]>,956 SchedVar<A57LMAddrPred8, [A57Write_16cyc_1S_1I]>,957 SchedVar<NoSchedPred, [A57Write_2cyc_1S_1I]>958]>;959 960def : InstRW<[A57WriteVSTMs], (instregex "VSTMSIA$")>;961def : InstRW<[A57WriteVSTMd], (instregex "VSTMDIA$")>;962def : InstRW<[A57WrBackOne, A57WriteVSTMs_Upd],963 (instregex "VSTM(SIA_UPD|SDB_UPD)")>;964def : InstRW<[A57WrBackOne, A57WriteVSTMd_Upd],965 (instregex "VSTM(DIA_UPD|DDB_UPD)")>;966 967// --- 3.14 ASIMD Integer Instructions ---968 969// ASIMD absolute diff, 3cyc F0/F1 for integer VABD970def : InstRW<[A57Write_3cyc_1V], (instregex "VABD(s|u)")>;971 972// ASIMD absolute diff accum: 4(1) F1 for D-form, 5(2) F1 for Q-form973def A57WriteVABAD : SchedWriteRes<[A57UnitX]> { let Latency = 4; }974def A57ReadVABAD : SchedReadAdvance<3, [A57WriteVABAD]>;975def : InstRW<[A57WriteVABAD, A57ReadVABAD],976 (instregex "VABA(s|u)(v8i8|v4i16|v2i32)")>;977def A57WriteVABAQ : SchedWriteRes<[A57UnitX]> { let Latency = 5; }978def A57ReadVABAQ : SchedReadAdvance<3, [A57WriteVABAQ]>;979def : InstRW<[A57WriteVABAQ, A57ReadVABAQ],980 (instregex "VABA(s|u)(v16i8|v8i16|v4i32)")>;981 982// ASIMD absolute diff accum long: 4(1) F1 for VABAL983def A57WriteVABAL : SchedWriteRes<[A57UnitX]> { let Latency = 4; }984def A57ReadVABAL : SchedReadAdvance<3, [A57WriteVABAL]>;985def : InstRW<[A57WriteVABAL, A57ReadVABAL], (instregex "VABAL(s|u)")>;986 987// ASIMD absolute diff long: 3cyc F0/F1 for VABDL988def : InstRW<[A57Write_3cyc_1V], (instregex "VABDL(s|u)")>;989 990// ASIMD arith, basic991def : InstRW<[A57Write_3cyc_1V], (instregex "VADDv", "VADDL", "VADDW",992 "VNEG(s8d|s16d|s32d|s8q|s16q|s32q|d|q)",993 "VPADDi", "VPADDL", "VSUBv", "VSUBL", "VSUBW")>;994 995// ASIMD arith, complex996def : InstRW<[A57Write_3cyc_1V], (instregex "VABS", "VADDHN", "VHADD", "VHSUB",997 "VQABS", "VQADD", "VQNEG", "VQSUB",998 "VRADDHN", "VRHADD", "VRSUBHN", "VSUBHN")>;999 1000// ASIMD compare1001def : InstRW<[A57Write_3cyc_1V],1002 (instregex "VCEQ", "VCGE", "VCGT", "VCLE", "VTST", "VCLT")>;1003 1004// ASIMD logical1005def : InstRW<[A57Write_3cyc_1V],1006 (instregex "VAND", "VBIC", "VMVN", "VORR", "VORN", "VEOR")>;1007 1008// ASIMD max/min1009def : InstRW<[A57Write_3cyc_1V],1010 (instregex "(VMAX|VMIN)(s|u)", "(VPMAX|VPMIN)(s8|s16|s32|u8|u16|u32)")>;1011 1012// ASIMD multiply, D-form: 5cyc F0 for r0px, 4cyc F0 for r1p0 and later1013// Cortex-A57 r1p0 and later reduce the latency of ASIMD multiply1014// and multiply-with-accumulate instructions relative to r0pX.1015def A57WriteVMULD_VecInt : SchedWriteVariant<[1016 SchedVar<IsR1P0AndLaterPred, [A57Write_4cyc_1W]>,1017 SchedVar<NoSchedPred, [A57Write_5cyc_1W]>]>;1018def : InstRW<[A57WriteVMULD_VecInt], (instregex1019 "VMUL(v8i8|v4i16|v2i32|pd)", "VMULsl(v4i16|v2i32)",1020 "VQDMULH(sl)?(v4i16|v2i32)", "VQRDMULH(sl)?(v4i16|v2i32)")>;1021 1022// ASIMD multiply, Q-form: 6cyc F0 for r0px, 5cyc F0 for r1p0 and later1023def A57WriteVMULQ_VecInt : SchedWriteVariant<[1024 SchedVar<IsR1P0AndLaterPred, [A57Write_5cyc_1W]>,1025 SchedVar<NoSchedPred, [A57Write_6cyc_1W]>]>;1026def : InstRW<[A57WriteVMULQ_VecInt], (instregex1027 "VMUL(v16i8|v8i16|v4i32|pq)", "VMULsl(v8i16|v4i32)",1028 "VQDMULH(sl)?(v8i16|v4i32)", "VQRDMULH(sl)?(v8i16|v4i32)")>;1029 1030// ASIMD multiply accumulate, D-form1031// 5cyc F0 for r0px, 4cyc F0 for r1p0 and later, 1cyc for accumulate sequence1032// (4 or 3 ReadAdvance)1033def A57WriteVMLAD_VecInt : SchedWriteVariant<[1034 SchedVar<IsR1P0AndLaterPred, [A57Write_4cyc_1W]>,1035 SchedVar<NoSchedPred, [A57Write_5cyc_1W]>]>;1036def A57ReadVMLAD_VecInt : SchedReadVariant<[1037 SchedVar<IsR1P0AndLaterPred, [SchedReadAdvance<3, [A57WriteVMLAD_VecInt]>]>,1038 SchedVar<NoSchedPred, [SchedReadAdvance<4, [A57WriteVMLAD_VecInt]>]>1039]>;1040def : InstRW<[A57WriteVMLAD_VecInt, A57ReadVMLAD_VecInt],1041 (instregex "VMLA(sl)?(v8i8|v4i16|v2i32)", "VMLS(sl)?(v8i8|v4i16|v2i32)")>;1042 1043// ASIMD multiply accumulate, Q-form1044// 6cyc F0 for r0px, 5cyc F0 for r1p0 and later, 2cyc for accumulate sequence1045// (4 or 3 ReadAdvance)1046def A57WriteVMLAQ_VecInt : SchedWriteVariant<[1047 SchedVar<IsR1P0AndLaterPred, [A57Write_5cyc_1W]>,1048 SchedVar<NoSchedPred, [A57Write_6cyc_1W]>]>;1049def A57ReadVMLAQ_VecInt : SchedReadVariant<[1050 SchedVar<IsR1P0AndLaterPred, [SchedReadAdvance<3, [A57WriteVMLAQ_VecInt]>]>,1051 SchedVar<NoSchedPred, [SchedReadAdvance<4, [A57WriteVMLAQ_VecInt]>]>1052]>;1053def : InstRW<[A57WriteVMLAQ_VecInt, A57ReadVMLAQ_VecInt],1054 (instregex "VMLA(sl)?(v16i8|v8i16|v4i32)", "VMLS(sl)?(v16i8|v8i16|v4i32)")>;1055 1056// ASIMD multiply accumulate long1057// 5cyc F0 for r0px, 4cyc F0 for r1p0 and later, 1cyc for accumulate sequence1058// (4 or 3 ReadAdvance)1059def A57WriteVMLAL_VecInt : SchedWriteVariant<[1060 SchedVar<IsR1P0AndLaterPred, [A57Write_4cyc_1W]>,1061 SchedVar<NoSchedPred, [A57Write_5cyc_1W]>]>;1062def A57ReadVMLAL_VecInt : SchedReadVariant<[1063 SchedVar<IsR1P0AndLaterPred, [SchedReadAdvance<3, [A57WriteVMLAL_VecInt]>]>,1064 SchedVar<NoSchedPred, [SchedReadAdvance<4, [A57WriteVMLAL_VecInt]>]>1065]>;1066def : InstRW<[A57WriteVMLAL_VecInt, A57ReadVMLAL_VecInt],1067 (instregex "VMLAL(s|u)", "VMLSL(s|u)")>;1068 1069// ASIMD multiply accumulate saturating long1070// 5cyc F0 for r0px, 4cyc F0 for r1p0 and later, 2cyc for accumulate sequence1071// (3 or 2 ReadAdvance)1072def A57WriteVQDMLAL_VecInt : SchedWriteVariant<[1073 SchedVar<IsR1P0AndLaterPred, [A57Write_4cyc_1W]>,1074 SchedVar<NoSchedPred, [A57Write_5cyc_1W]>]>;1075def A57ReadVQDMLAL_VecInt : SchedReadVariant<[1076 SchedVar<IsR1P0AndLaterPred, [SchedReadAdvance<2, [A57WriteVQDMLAL_VecInt]>]>,1077 SchedVar<NoSchedPred, [SchedReadAdvance<3, [A57WriteVQDMLAL_VecInt]>]>1078]>;1079def : InstRW<[A57WriteVQDMLAL_VecInt, A57ReadVQDMLAL_VecInt],1080 (instregex "VQDMLAL", "VQDMLSL")>;1081 1082// Vector Saturating Rounding Doubling Multiply Accumulate/Subtract Long1083// Scheduling info from VQDMLAL/VQDMLSL1084def : InstRW<[A57WriteVQDMLAL_VecInt, A57ReadVQDMLAL_VecInt],1085 (instregex "VQRDMLAH", "VQRDMLSH")>;1086 1087// ASIMD multiply long1088// 5cyc F0 for r0px, 4cyc F0 for r1p0 and later1089def A57WriteVMULL_VecInt : SchedWriteVariant<[1090 SchedVar<IsR1P0AndLaterPred, [A57Write_4cyc_1W]>,1091 SchedVar<NoSchedPred, [A57Write_5cyc_1W]>]>;1092def : InstRW<[A57WriteVMULL_VecInt],1093 (instregex "VMULL(s|u|p8|sls|slu)", "VQDMULL")>;1094 1095// ASIMD pairwise add and accumulate1096// 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)1097def A57WriteVPADAL : SchedWriteRes<[A57UnitX]> { let Latency = 4; }1098def A57ReadVPADAL : SchedReadAdvance<3, [A57WriteVPADAL]>;1099def : InstRW<[A57WriteVPADAL, A57ReadVPADAL], (instregex "VPADAL(s|u)")>;1100 1101// ASIMD shift accumulate1102// 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)1103def A57WriteVSRA : SchedWriteRes<[A57UnitX]> { let Latency = 4; }1104def A57ReadVSRA : SchedReadAdvance<3, [A57WriteVSRA]>;1105def : InstRW<[A57WriteVSRA, A57ReadVSRA], (instregex "VSRA", "VRSRA")>;1106 1107// ASIMD shift by immed, basic1108def : InstRW<[A57Write_3cyc_1X],1109 (instregex "VMOVL", "VSHLi", "VSHLL", "VSHR(s|u)", "VSHRN")>;1110 1111// ASIMD shift by immed, complex1112def : InstRW<[A57Write_4cyc_1X], (instregex1113 "VQRSHRN", "VQRSHRUN", "VQSHL(si|ui|su)", "VQSHRN", "VQSHRUN", "VRSHR(s|u)",1114 "VRSHRN")>;1115 1116// ASIMD shift by immed and insert, basic, D-form1117def : InstRW<[A57Write_4cyc_1X], (instregex1118 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;1119 1120// ASIMD shift by immed and insert, basic, Q-form1121def : InstRW<[A57Write_5cyc_1X], (instregex1122 "VSLI(v16i8|v8i16|v4i32|v2i64)", "VSRI(v16i8|v8i16|v4i32|v2i64)")>;1123 1124// ASIMD shift by register, basic, D-form1125def : InstRW<[A57Write_3cyc_1X], (instregex1126 "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;1127 1128// ASIMD shift by register, basic, Q-form1129def : InstRW<[A57Write_4cyc_1X], (instregex1130 "VSHL(s|u)(v16i8|v8i16|v4i32|v2i64)")>;1131 1132// ASIMD shift by register, complex, D-form1133// VQRSHL, VQSHL, VRSHL1134def : InstRW<[A57Write_4cyc_1X], (instregex1135 "VQRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)", "VQSHL(s|u)(v8i8|v4i16|v2i32|v1i64)",1136 "VRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;1137 1138// ASIMD shift by register, complex, Q-form1139def : InstRW<[A57Write_5cyc_1X], (instregex1140 "VQRSHL(s|u)(v16i8|v8i16|v4i32|v2i64)", "VQSHL(s|u)(v16i8|v8i16|v4i32|v2i64)",1141 "VRSHL(s|u)(v16i8|v8i16|v4i32|v2i64)")>;1142 1143// --- 3.15 ASIMD Floating-Point Instructions ---1144// ASIMD FP absolute value1145def : InstRW<[A57Write_3cyc_1V], (instregex "VABS(fd|fq|hd|hq)")>;1146 1147// ASIMD FP arith1148def : InstRW<[A57Write_5cyc_1V], (instregex "VABD(fd|fq|hd|hq)",1149 "VADD(fd|fq|hd|hq)", "VPADD(f|h)", "VSUB(fd|fq|hd|hq)")>;1150 1151def : InstRW<[A57Write_5cyc_1V], (instregex "VCADD", "VCMLA")>;1152 1153// ASIMD FP compare1154def : InstRW<[A57Write_5cyc_1V], (instregex "VAC(GE|GT|LE|LT)",1155 "VC(EQ|GE|GT|LE)(fd|fq|hd|hq)")>;1156 1157// ASIMD FP convert, integer1158def : InstRW<[A57Write_5cyc_1V], (instregex1159 "VCVT(f2sd|f2ud|s2fd|u2fd|f2sq|f2uq|s2fq|u2fq|f2xsd|f2xud|xs2fd|xu2fd)",1160 "VCVT(f2xsq|f2xuq|xs2fq|xu2fq)",1161 "VCVT(AN|MN|NN|PN)(SDf|SQf|UDf|UQf|SDh|SQh|UDh|UQh)")>;1162 1163// ASIMD FP convert, half-precision: 8cyc F0/F11164def : InstRW<[A57Write_8cyc_1V], (instregex1165 "VCVT(h2sd|h2ud|s2hd|u2hd|h2sq|h2uq|s2hq|u2hq|h2xsd|h2xud|xs2hd|xu2hd)",1166 "VCVT(h2xsq|h2xuq|xs2hq|xu2hq)",1167 "VCVT(f2h|h2f)")>;1168 1169// ASIMD FP max/min1170def : InstRW<[A57Write_5cyc_1V], (instregex1171 "(VMAX|VMIN)(fd|fq|hd|hq)", "(VPMAX|VPMIN)(f|h)", "(NEON|VFP)_VMAXNM",1172 "(NEON|VFP)_VMINNM")>;1173 1174// ASIMD FP multiply1175def A57WriteVMUL_VecFP : SchedWriteRes<[A57UnitV]> { let Latency = 5; }1176def : InstRW<[A57WriteVMUL_VecFP], (instregex "VMUL(sl)?(fd|fq|hd|hq)")>;1177 1178// ASIMD FP multiply accumulate: 9cyc F0/F1, 4cyc for accumulate sequence1179def A57WriteVMLA_VecFP : SchedWriteRes<[A57UnitV]> { let Latency = 9; }1180def A57ReadVMLA_VecFP :1181 SchedReadAdvance<5, [A57WriteVMLA_VecFP, A57WriteVMUL_VecFP]>;1182def : InstRW<[A57WriteVMLA_VecFP, A57ReadVMLA_VecFP],1183 (instregex "(VMLA|VMLS)(sl)?(fd|fq|hd|hq)", "(VFMA|VFMS)(fd|fq|hd|hq)")>;1184 1185// ASIMD FP negate1186def : InstRW<[A57Write_3cyc_1V], (instregex "VNEG(fd|f32q|hd|hq)")>;1187 1188// ASIMD FP round to integral1189def : InstRW<[A57Write_5cyc_1V], (instregex1190 "VRINT(AN|MN|NN|PN|XN|ZN)(Df|Qf|Dh|Qh)")>;1191 1192// --- 3.16 ASIMD Miscellaneous Instructions ---1193 1194// ASIMD bitwise insert1195def : InstRW<[A57Write_3cyc_1V], (instregex "VBIF", "VBIT", "VBSL", "VBSP")>;1196 1197// ASIMD count1198def : InstRW<[A57Write_3cyc_1V], (instregex "VCLS", "VCLZ", "VCNT")>;1199 1200// ASIMD duplicate, core reg: 8cyc "L, F0/F1"1201def : InstRW<[A57Write_8cyc_1L_1V], (instregex "VDUP(8|16|32)(d|q)")>;1202 1203// ASIMD duplicate, scalar: 3cyc "F0/F1"1204def : InstRW<[A57Write_3cyc_1V], (instregex "VDUPLN(8|16|32)(d|q)")>;1205 1206// ASIMD extract1207def : InstRW<[A57Write_3cyc_1V], (instregex "VEXT(d|q)(8|16|32|64)")>;1208 1209// ASIMD move, immed1210def : InstRW<[A57Write_3cyc_1V], (instregex1211 "VMOV(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v1i64|v2i64|v2f32|v4f32)",1212 "VMOVD0", "VMOVQ0")>;1213 1214// ASIMD move, narrowing1215def : InstRW<[A57Write_3cyc_1V], (instregex "VMOVN")>;1216 1217// ASIMD move, saturating1218def : InstRW<[A57Write_4cyc_1X], (instregex "VQMOVN")>;1219 1220// ASIMD reciprocal estimate1221def : InstRW<[A57Write_5cyc_1V], (instregex "VRECPE", "VRSQRTE")>;1222 1223// ASIMD reciprocal step, FZ1224def : InstRW<[A57Write_9cyc_1V], (instregex "VRECPS", "VRSQRTS")>;1225 1226// ASIMD reverse, swap, table lookup (1-2 reg)1227def : InstRW<[A57Write_3cyc_1V], (instregex "VREV", "VSWP", "VTB(L|X)(1|2)")>;1228 1229// ASIMD table lookup (3-4 reg)1230def : InstRW<[A57Write_6cyc_1V], (instregex "VTBL(3|4)", "VTBX(3|4)")>;1231 1232// ASIMD transfer, scalar to core reg: 6cyc "L, I0/I1"1233def : InstRW<[A57Write_6cyc_1L_1I], (instregex "VGETLN")>;1234 1235// ASIMD transfer, core reg to scalar: 8cyc "L, F0/F1"1236def : InstRW<[A57Write_8cyc_1L_1V], (instregex "VSETLN")>;1237 1238// ASIMD transpose1239def : InstRW<[A57Write_3cyc_1V, A57Write_3cyc_1V], (instregex "VTRN")>;1240 1241// ASIMD unzip/zip, D-form1242def : InstRW<[A57Write_3cyc_1V, A57Write_3cyc_1V],1243 (instregex "VUZPd", "VZIPd")>;1244 1245// ASIMD unzip/zip, Q-form1246def : InstRW<[A57Write_6cyc_1V, A57Write_6cyc_1V],1247 (instregex "VUZPq", "VZIPq")>;1248 1249// --- 3.17 ASIMD Load Instructions ---1250 1251// Overriden via InstRW for this processor.1252def : WriteRes<WriteVLD1, []>;1253def : WriteRes<WriteVLD2, []>;1254def : WriteRes<WriteVLD3, []>;1255def : WriteRes<WriteVLD4, []>;1256def : WriteRes<WriteVST1, []>;1257def : WriteRes<WriteVST2, []>;1258def : WriteRes<WriteVST3, []>;1259def : WriteRes<WriteVST4, []>;1260 1261// 1-2 reg: 5cyc L, +I for writeback, 1 cyc wb latency1262def : InstRW<[A57Write_5cyc_1L], (instregex "VLD1(d|q)(8|16|32|64)$")>;1263def : InstRW<[A57Write_5cyc_1L_1I, A57WrBackOne],1264 (instregex "VLD1(d|q)(8|16|32|64)wb")>;1265 1266// 3-4 reg: 6cyc L, +I for writeback, 1 cyc wb latency1267def : InstRW<[A57Write_6cyc_1L],1268 (instregex "VLD1(d|q)(8|16|32|64)(T|Q)$", "VLD1d64(T|Q)Pseudo")>;1269 1270def : InstRW<[A57Write_6cyc_1L_1I, A57WrBackOne],1271 (instregex "VLD1(d|q)(8|16|32|64)(T|Q)wb")>;1272 1273// ASIMD load, 1 element, one lane and all lanes: 8cyc "L, F0/F1"1274def : InstRW<[A57Write_8cyc_1L_1V], (instregex1275 "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;1276def : InstRW<[A57Write_8cyc_1L_1V_1I, A57WrBackOne], (instregex1277 "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)", "VLD1LNq(8|16|32)Pseudo_UPD")>;1278 1279// ASIMD load, 2 element, multiple, 2 reg: 8cyc "L, F0/F1"1280def : InstRW<[A57Write_8cyc_1L_1V],1281 (instregex "VLD2(d|q)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>;1282def : InstRW<[A57Write_8cyc_1L_1V_1I, A57WrBackOne],1283 (instregex "VLD2(d|q)(8|16|32)wb", "VLD2q(8|16|32)PseudoWB")>;1284 1285// ASIMD load, 2 element, multiple, 4 reg: 9cyc "L, F0/F1"1286def : InstRW<[A57Write_9cyc_1L_1V], (instregex "VLD2b(8|16|32)$")>;1287def : InstRW<[A57Write_9cyc_1L_1V_1I, A57WrBackOne],1288 (instregex "VLD2b(8|16|32)wb")>;1289 1290// ASIMD load, 2 element, one lane and all lanes: 8cyc "L, F0/F1"1291def : InstRW<[A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V],1292 (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$",1293 "VLD2LN(d|q)(8|16|32)Pseudo$")>;1294// 2 results + wb result1295def : InstRW<[A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V, A57WrBackOne],1296 (instregex "VLD2LN(d|q)(8|16|32)_UPD$")>;1297// 1 result + wb result1298def : InstRW<[A57Write_8cyc_1L_1V_1I, A57WrBackOne],1299 (instregex "VLD2DUPd(8|16|32|8x2|16x2|32x2)wb",1300 "VLD2LN(d|q)(8|16|32)Pseudo_UPD")>;1301 1302// ASIMD load, 3 element, multiple, 3 reg: 9cyc "L, F0/F1"1303// 3 results1304def : InstRW<[A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V],1305 (instregex "VLD3(d|q)(8|16|32)$")>;1306// 1 result1307def : InstRW<[A57Write_9cyc_1L_1V],1308 (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo$")>;1309// 3 results + wb1310def : InstRW<[A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I,1311 A57Write_9cyc_1L_1V_1I, A57WrBackOne],1312 (instregex "VLD3(d|q)(8|16|32)_UPD$")>;1313// 1 result + wb1314def : InstRW<[A57Write_9cyc_1L_1V_1I, A57WrBackOne],1315 (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD")>;1316 1317// ASIMD load, 3 element, one lane, size 32: 8cyc "L, F0/F1"1318def : InstRW<[A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V],1319 (instregex "VLD3LN(d|q)32$",1320 "VLD3LN(d|q)32Pseudo$")>;1321def : InstRW<[A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I,1322 A57Write_8cyc_1L_1V_1I, A57WrBackOne],1323 (instregex "VLD3LN(d|q)32_UPD")>;1324def : InstRW<[A57Write_8cyc_1L_1V_1I, A57WrBackOne],1325 (instregex "VLD3LN(d|q)32Pseudo_UPD")>;1326 1327// ASIMD load, 3 element, one lane, size 8/16: 9cyc "L, F0/F1"1328def : InstRW<[A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V],1329 (instregex "VLD3LN(d|q)(8|16)$",1330 "VLD3LN(d|q)(8|16)Pseudo$")>;1331def : InstRW<[A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I,1332 A57Write_9cyc_1L_1V_1I, A57WrBackOne],1333 (instregex "VLD3LN(d|q)(8|16)_UPD")>;1334def : InstRW<[A57Write_9cyc_1L_1V_1I, A57WrBackOne],1335 (instregex "VLD3LN(d|q)(8|16)Pseudo_UPD")>;1336 1337// ASIMD load, 3 element, all lanes: 8cyc "L, F0/F1"1338def : InstRW<[A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V],1339 (instregex "VLD3DUP(d|q)(8|16|32)$",1340 "VLD3DUP(d|q)(8|16|32)Pseudo$")>;1341def : InstRW<[A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I,1342 A57Write_8cyc_1L_1V_1I, A57WrBackOne],1343 (instregex "VLD3DUP(d|q)(8|16|32)_UPD")>;1344def : InstRW<[A57Write_8cyc_1L_1V_1I, A57WrBackOne],1345 (instregex "VLD3DUP(d|q)(8|16|32)Pseudo_UPD")>;1346 1347// ASIMD load, 4 element, multiple, 4 reg: 9cyc "L, F0/F1"1348def : InstRW<[A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V,1349 A57Write_9cyc_1L_1V],1350 (instregex "VLD4(d|q)(8|16|32)$")>;1351def : InstRW<[A57Write_9cyc_1L_1V],1352 (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo$")>;1353def : InstRW<[A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I,1354 A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I, A57WrBackOne],1355 (instregex "VLD4(d|q)(8|16|32)_UPD")>;1356def : InstRW<[A57Write_9cyc_1L_1V_1I, A57WrBackOne],1357 (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD")>;1358 1359// ASIMD load, 4 element, one lane, size 32: 8cyc "L, F0/F1"1360def : InstRW<[A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V,1361 A57Write_8cyc_1L_1V],1362 (instregex "VLD4LN(d|q)32$",1363 "VLD4LN(d|q)32Pseudo$")>;1364def : InstRW<[A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I,1365 A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I,1366 A57WrBackOne],1367 (instregex "VLD4LN(d|q)32_UPD")>;1368def : InstRW<[A57Write_8cyc_1L_1V_1I, A57WrBackOne],1369 (instregex "VLD4LN(d|q)32Pseudo_UPD")>;1370 1371// ASIMD load, 4 element, one lane, size 8/16: 9cyc "L, F0/F1"1372def : InstRW<[A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V, A57Write_9cyc_1L_1V,1373 A57Write_9cyc_1L_1V],1374 (instregex "VLD4LN(d|q)(8|16)$",1375 "VLD4LN(d|q)(8|16)Pseudo$")>;1376def : InstRW<[A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I,1377 A57Write_9cyc_1L_1V_1I, A57Write_9cyc_1L_1V_1I,1378 A57WrBackOne],1379 (instregex "VLD4LN(d|q)(8|16)_UPD")>;1380def : InstRW<[A57Write_9cyc_1L_1V_1I, A57WrBackOne],1381 (instregex "VLD4LN(d|q)(8|16)Pseudo_UPD")>;1382 1383// ASIMD load, 4 element, all lanes: 8cyc "L, F0/F1"1384def : InstRW<[A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V, A57Write_8cyc_1L_1V,1385 A57Write_8cyc_1L_1V],1386 (instregex "VLD4DUP(d|q)(8|16|32)$",1387 "VLD4DUP(d|q)(8|16|32)Pseudo$")>;1388def : InstRW<[A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I,1389 A57Write_8cyc_1L_1V_1I, A57Write_8cyc_1L_1V_1I,1390 A57WrBackOne],1391 (instregex "VLD4DUP(d|q)(8|16|32)_UPD")>;1392def : InstRW<[A57Write_8cyc_1L_1V_1I, A57WrBackOne],1393 (instregex "VLD4DUP(d|q)(8|16|32)Pseudo_UPD")>;1394 1395// --- 3.18 ASIMD Store Instructions ---1396 1397// ASIMD store, 1 element, multiple, 1 reg: 1cyc S1398def : InstRW<[A57Write_1cyc_1S], (instregex "VST1d(8|16|32|64)$")>;1399def : InstRW<[A57WrBackOne, A57Write_1cyc_1S_1I],1400 (instregex "VST1d(8|16|32|64)wb")>;1401// ASIMD store, 1 element, multiple, 2 reg: 2cyc S1402def : InstRW<[A57Write_2cyc_1S], (instregex "VST1q(8|16|32|64)$")>;1403def : InstRW<[A57WrBackOne, A57Write_2cyc_1S_1I],1404 (instregex "VST1q(8|16|32|64)wb")>;1405// ASIMD store, 1 element, multiple, 3 reg: 3cyc S1406def : InstRW<[A57Write_3cyc_1S],1407 (instregex "VST1d(8|16|32|64)T$", "VST1d64TPseudo$")>;1408def : InstRW<[A57WrBackOne, A57Write_3cyc_1S_1I],1409 (instregex "VST1d(8|16|32|64)Twb", "VST1d64TPseudoWB")>;1410// ASIMD store, 1 element, multiple, 4 reg: 4cyc S1411def : InstRW<[A57Write_4cyc_1S],1412 (instregex "VST1d(8|16|32|64)(Q|QPseudo)$")>;1413def : InstRW<[A57WrBackOne, A57Write_4cyc_1S_1I],1414 (instregex "VST1d(8|16|32|64)(Qwb|QPseudoWB)")>;1415// ASIMD store, 1 element, one lane: 3cyc "F0/F1, S"1416def : InstRW<[A57Write_3cyc_1S_1V],1417 (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>;1418def : InstRW<[A57WrBackOne, A57Write_3cyc_1S_1V_1I],1419 (instregex "VST1LNd(8|16|32)_UPD", "VST1LNq(8|16|32)Pseudo_UPD")>;1420// ASIMD store, 2 element, multiple, 2 reg: 3cyc "F0/F1, S"1421def : InstRW<[A57Write_3cyc_1S_1V],1422 (instregex "VST2(d|b)(8|16|32)$")>;1423def : InstRW<[A57WrBackOne, A57Write_3cyc_1S_1V_1I],1424 (instregex "VST2(b|d)(8|16|32)wb")>;1425// ASIMD store, 2 element, multiple, 4 reg: 4cyc "F0/F1, S"1426def : InstRW<[A57Write_4cyc_1S_1V],1427 (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>;1428def : InstRW<[A57WrBackOne, A57Write_4cyc_1S_1V_1I],1429 (instregex "VST2q(8|16|32)wb", "VST2q(8|16|32)PseudoWB")>;1430// ASIMD store, 2 element, one lane: 3cyc "F0/F1, S"1431def : InstRW<[A57Write_3cyc_1S_1V],1432 (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>;1433def : InstRW<[A57WrBackOne, A57Write_3cyc_1S_1V_1I],1434 (instregex "VST2LN(d|q)(8|16|32)_UPD",1435 "VST2LN(d|q)(8|16|32)Pseudo_UPD")>;1436// ASIMD store, 3 element, multiple, 3 reg1437def : InstRW<[A57Write_3cyc_1S_1V],1438 (instregex "VST3(d|q)(8|16|32)$", "VST3(d|q)(8|16|32)(oddP|P)seudo$")>;1439def : InstRW<[A57WrBackOne, A57Write_3cyc_1S_1V_1I],1440 (instregex "VST3(d|q)(8|16|32)_UPD",1441 "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;1442// ASIMD store, 3 element, one lane1443def : InstRW<[A57Write_3cyc_1S_1V],1444 (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>;1445def : InstRW<[A57WrBackOne, A57Write_3cyc_1S_1V_1I],1446 (instregex "VST3LN(d|q)(8|16|32)_UPD",1447 "VST3LN(d|q)(8|16|32)Pseudo_UPD")>;1448// ASIMD store, 4 element, multiple, 4 reg1449def : InstRW<[A57Write_4cyc_1S_1V],1450 (instregex "VST4(d|q)(8|16|32)$", "VST4(d|q)(8|16|32)(oddP|P)seudo$")>;1451def : InstRW<[A57WrBackOne, A57Write_4cyc_1S_1V_1I],1452 (instregex "VST4(d|q)(8|16|32)_UPD",1453 "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;1454// ASIMD store, 4 element, one lane1455def : InstRW<[A57Write_3cyc_1S_1V],1456 (instregex "VST4LN(d|q)(8|16|32)$", "VST4LN(d|q)(8|16|32)Pseudo$")>;1457def : InstRW<[A57WrBackOne, A57Write_3cyc_1S_1V_1I],1458 (instregex "VST4LN(d|q)(8|16|32)_UPD",1459 "VST4LN(d|q)(8|16|32)Pseudo_UPD")>;1460 1461// --- 3.19 Cryptography Extensions ---1462// Crypto AES ops1463// AESD, AESE, AESIMC, AESMC: 3cyc F01464def : InstRW<[A57Write_3cyc_1W], (instregex "^AES")>;1465// Crypto polynomial (64x64) multiply long (VMULL.P64): 3cyc F01466def : InstRW<[A57Write_3cyc_1W], (instregex "^VMULLp64")>;1467// Crypto SHA1 xor ops: 6cyc F0/F11468def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>;1469// Crypto SHA1 fast ops: 3cyc F01470def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>;1471// Crypto SHA1 slow ops: 6cyc F01472def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>;1473// Crypto SHA256 fast ops: 3cyc F01474def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>;1475// Crypto SHA256 slow ops: 6cyc F01476def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>;1477 1478// --- 3.20 CRC ---1479def : InstRW<[A57Write_3cyc_1W], (instregex "^(t2)?CRC32")>;1480 1481// -----------------------------------------------------------------------------1482// Common definitions1483def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }1484def : SchedAlias<WriteALU, CheckBranchForm<0, A57BranchForm<A57Write_1cyc_1I>>>;1485 1486def : SchedAlias<WriteBr, A57Write_1cyc_1B>;1487def : SchedAlias<WriteBrL, A57Write_1cyc_1B_1I>;1488def : SchedAlias<WriteBrTbl, A57Write_1cyc_1B_1I>;1489def : SchedAlias<WritePreLd, A57Write_4cyc_1L>;1490 1491def : SchedAlias<WriteLd, A57Write_4cyc_1L>;1492def : SchedAlias<WriteST, A57Write_1cyc_1S>;1493def : ReadAdvance<ReadALU, 0>;1494 1495} // SchedModel = CortexA57Model1496 1497