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1//=- ARMScheduleA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// Contains all of the Cortex-A57 specific SchedWriteRes types. The approach10// below is to define a generic SchedWriteRes for every combination of11// latency and microOps. The naming conventions is to use a prefix, one field12// for latency, and one or more microOp count/type designators.13// Prefix: A57Write14// Latency: #cyc15// MicroOp Count/Types: #(B|I|M|L|S|X|W|V)16//17// e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are18// 11 micro-ops to be issued as follows: one to I pipe, six to S pipes and19// four to V pipes.20//21//===----------------------------------------------------------------------===//22 23//===----------------------------------------------------------------------===//24// Define Generic 1 micro-op types25 26def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }27def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }28def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }29def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }30def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;31 let ReleaseAtCycles = [17]; }32def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;33 let ReleaseAtCycles = [18]; }34def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;35 let ReleaseAtCycles = [19]; }36def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;37 let ReleaseAtCycles = [20]; }38def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }39def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1;40 let ReleaseAtCycles = [1]; }41def A57Write_2cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 2;42 let ReleaseAtCycles = [1]; }43def A57Write_3cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 3; }44def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }45def A57Write_2cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 2; }46def A57Write_3cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 3; }47def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2;48 let ReleaseAtCycles = [1]; }49def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;50 let ReleaseAtCycles = [32]; }51def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;52 let ReleaseAtCycles = [32]; }53def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;54 let ReleaseAtCycles = [35]; }55def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }56def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }57def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }58def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }59 60// A57Write_3cyc_1L - A57Write_20cyc_1L61foreach Lat = 3-20 in {62 def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {63 let Latency = Lat;64 }65}66 67// A57Write_4cyc_1S - A57Write_16cyc_1S68foreach Lat = 4-16 in {69 def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {70 let Latency = Lat;71 }72}73 74def A57Write_4cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 4; }75def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }76def A57Write_4cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 4; }77def A57Write_5cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 5; }78def A57Write_6cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 6; }79def A57Write_6cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 6; }80def A57Write_8cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 8; }81def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }82def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }83def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }84 85 86//===----------------------------------------------------------------------===//87// Define Generic 2 micro-op types88 89def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {90 let Latency = 64;91 let NumMicroOps = 2;92 let ReleaseAtCycles = [32, 32];93}94def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,95 A57UnitL]> {96 let Latency = 6;97 let NumMicroOps = 2;98}99def A57Write_6cyc_1V_1X : SchedWriteRes<[A57UnitV,100 A57UnitX]> {101 let Latency = 6;102 let NumMicroOps = 2;103}104def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,105 A57UnitX]> {106 let Latency = 7;107 let NumMicroOps = 2;108}109def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL,110 A57UnitV]> {111 let Latency = 8;112 let NumMicroOps = 2;113}114def A57Write_9cyc_1L_1V : SchedWriteRes<[A57UnitL,115 A57UnitV]> {116 let Latency = 9;117 let NumMicroOps = 2;118}119def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {120 let Latency = 9;121 let NumMicroOps = 2;122}123def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {124 let Latency = 8;125 let NumMicroOps = 2;126}127def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> {128 let Latency = 6;129 let NumMicroOps = 2;130}131def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {132 let Latency = 6;133 let NumMicroOps = 2;134}135def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {136 let Latency = 6;137 let NumMicroOps = 2;138}139def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI,140 A57UnitL]> {141 let Latency = 5;142 let NumMicroOps = 2;143}144def A57Write_5cyc_1I_1M : SchedWriteRes<[A57UnitI,145 A57UnitM]> {146 let Latency = 5;147 let NumMicroOps = 2;148}149def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {150 let Latency = 5;151 let NumMicroOps = 2;152}153def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {154 let Latency = 5;155 let NumMicroOps = 2;156}157def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,158 A57UnitV]> {159 let Latency = 10;160 let NumMicroOps = 2;161}162def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {163 let Latency = 10;164 let NumMicroOps = 2;165}166def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB,167 A57UnitI]> {168 let Latency = 1;169 let NumMicroOps = 2;170}171def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI,172 A57UnitS]> {173 let Latency = 1;174 let NumMicroOps = 2;175}176def A57Write_1cyc_1S_1I : SchedWriteRes<[A57UnitS,177 A57UnitI]> {178 let Latency = 1;179 let NumMicroOps = 2;180}181def A57Write_2cyc_1S_1I : SchedWriteRes<[A57UnitS,182 A57UnitI]> {183 let Latency = 2;184 let NumMicroOps = 2;185}186def A57Write_3cyc_1S_1I : SchedWriteRes<[A57UnitS,187 A57UnitI]> {188 let Latency = 3;189 let NumMicroOps = 2;190}191def A57Write_1cyc_1S_1M : SchedWriteRes<[A57UnitS,192 A57UnitM]> {193 let Latency = 1;194 let NumMicroOps = 2;195}196def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB,197 A57UnitI]> {198 let Latency = 2;199 let NumMicroOps = 2;200}201def A57Write_3cyc_1B_1I : SchedWriteRes<[A57UnitB,202 A57UnitI]> {203 let Latency = 3;204 let NumMicroOps = 2;205}206def A57Write_6cyc_1B_1L : SchedWriteRes<[A57UnitB,207 A57UnitI]> {208 let Latency = 6;209 let NumMicroOps = 2;210}211def A57Write_2cyc_1I_1M : SchedWriteRes<[A57UnitI,212 A57UnitM]> {213 let Latency = 2;214 let NumMicroOps = 2;215}216def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> {217 let Latency = 2;218 let NumMicroOps = 2;219}220def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {221 let Latency = 2;222 let NumMicroOps = 2;223}224def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {225 let Latency = 36;226 let NumMicroOps = 2;227 let ReleaseAtCycles = [18, 18];228}229def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,230 A57UnitM]> {231 let Latency = 3;232 let NumMicroOps = 2;233}234def A57Write_4cyc_1I_1M : SchedWriteRes<[A57UnitI,235 A57UnitM]> {236 let Latency = 4;237 let NumMicroOps = 2;238}239 240// A57Write_3cyc_1L_1I - A57Write_20cyc_1L_1I241foreach Lat = 3-20 in {242 def A57Write_#Lat#cyc_1L_1I : SchedWriteRes<[A57UnitL, A57UnitI]> {243 let Latency = Lat; let NumMicroOps = 2;244 }245}246 247def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,248 A57UnitS]> {249 let Latency = 3;250 let NumMicroOps = 2;251}252def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,253 A57UnitV]> {254 let Latency = 3;255 let NumMicroOps = 2;256}257def A57Write_4cyc_1S_1V : SchedWriteRes<[A57UnitS,258 A57UnitV]> {259 let Latency = 4;260 let NumMicroOps = 2;261}262def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {263 let Latency = 3;264 let NumMicroOps = 2;265}266 267// A57Write_4cyc_1S_1I - A57Write_16cyc_1S_1I268foreach Lat = 4-16 in {269 def A57Write_#Lat#cyc_1S_1I : SchedWriteRes<[A57UnitS, A57UnitI]> {270 let Latency = Lat; let NumMicroOps = 2;271 }272}273 274def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {275 let Latency = 4;276 let NumMicroOps = 2;277}278 279 280//===----------------------------------------------------------------------===//281// Define Generic 3 micro-op types282 283def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {284 let Latency = 10;285 let NumMicroOps = 3;286}287def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI,288 A57UnitS, A57UnitS]> {289 let Latency = 2;290 let NumMicroOps = 3;291}292def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI,293 A57UnitS,294 A57UnitV]> {295 let Latency = 3;296 let NumMicroOps = 3;297}298def A57Write_3cyc_1S_1V_1I : SchedWriteRes<[A57UnitS,299 A57UnitV,300 A57UnitI]> {301 let Latency = 3;302 let NumMicroOps = 3;303}304def A57Write_4cyc_1S_1V_1I : SchedWriteRes<[A57UnitS,305 A57UnitV,306 A57UnitI]> {307 let Latency = 4;308 let NumMicroOps = 3;309}310def A57Write_4cyc_1I_1L_1M : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitM]> {311 let Latency = 4;312 let NumMicroOps = 3;313}314def A57Write_8cyc_1L_1V_1I : SchedWriteRes<[A57UnitL,315 A57UnitV,316 A57UnitI]> {317 let Latency = 8;318 let NumMicroOps = 3;319}320def A57Write_9cyc_1L_1V_1I : SchedWriteRes<[A57UnitL,321 A57UnitV,322 A57UnitI]> {323 let Latency = 9;324 let NumMicroOps = 3;325}326