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1//===-- ARMScheduleV6.td - ARM v6 Scheduling Definitions ---*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the itinerary class data for the ARM v6 processors.10//11//===----------------------------------------------------------------------===//12 13// Model based on ARM117614//15// Functional Units16def V6_Pipe : FuncUnit; // pipeline17 18// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual"19//20def ARMV6Itineraries : ProcessorItineraries<21 [V6_Pipe], [], [22 //23 // No operand cycles24 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,25 //26 // Binary Instructions that produce a result27 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,28 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,29 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,30 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,31 //32 // Bitwise Instructions that produce a result33 InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>,34 InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,35 InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,36 InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,37 //38 // Unary Instructions that produce a result39 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,40 InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,41 //42 // Zero and sign extension instructions43 InstrItinData<IIC_iEXTr , [InstrStage<1, [V6_Pipe]>], [1, 1]>,44 InstrItinData<IIC_iEXTAr , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,45 InstrItinData<IIC_iEXTAsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>,46 //47 // Compare instructions48 InstrItinData<IIC_iCMPi , [InstrStage<1, [V6_Pipe]>], [2]>,49 InstrItinData<IIC_iCMPr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,50 InstrItinData<IIC_iCMPsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,51 InstrItinData<IIC_iCMPsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,52 //53 // Test instructions54 InstrItinData<IIC_iTSTi , [InstrStage<1, [V6_Pipe]>], [2]>,55 InstrItinData<IIC_iTSTr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,56 InstrItinData<IIC_iTSTsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,57 InstrItinData<IIC_iTSTsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,58 //59 // Move instructions, unconditional60 InstrItinData<IIC_iMOVi , [InstrStage<1, [V6_Pipe]>], [2]>,61 InstrItinData<IIC_iMOVr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,62 InstrItinData<IIC_iMOVsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,63 InstrItinData<IIC_iMOVsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,64 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [V6_Pipe]>,65 InstrStage<1, [V6_Pipe]>], [2]>,66 InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [V6_Pipe]>,67 InstrStage<1, [V6_Pipe]>,68 InstrStage<1, [V6_Pipe]>], [3]>,69 InstrItinData<IIC_iMOVix2ld , [InstrStage<1, [V6_Pipe]>,70 InstrStage<1, [V6_Pipe]>,71 InstrStage<1, [V6_Pipe]>], [5]>,72 //73 // Move instructions, conditional74 InstrItinData<IIC_iCMOVi , [InstrStage<1, [V6_Pipe]>], [3]>,75 InstrItinData<IIC_iCMOVr , [InstrStage<1, [V6_Pipe]>], [3, 2]>,76 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [V6_Pipe]>], [3, 1]>,77 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>,78 InstrItinData<IIC_iCMOVix2 , [InstrStage<1, [V6_Pipe]>,79 InstrStage<1, [V6_Pipe]>], [4]>,80 //81 // MVN instructions82 InstrItinData<IIC_iMVNi , [InstrStage<1, [V6_Pipe]>], [2]>,83 InstrItinData<IIC_iMVNr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,84 InstrItinData<IIC_iMVNsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,85 InstrItinData<IIC_iMVNsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,86 87 // Integer multiply pipeline88 //89 InstrItinData<IIC_iMUL16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,90 InstrItinData<IIC_iMAC16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1, 2]>,91 InstrItinData<IIC_iMUL32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1]>,92 InstrItinData<IIC_iMAC32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1, 2]>,93 InstrItinData<IIC_iMUL64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1]>,94 InstrItinData<IIC_iMAC64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1, 2]>,95 96 // Integer load pipeline97 //98 // Immediate offset99 InstrItinData<IIC_iLoad_i , [InstrStage<1, [V6_Pipe]>], [4, 1]>,100 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [V6_Pipe]>], [4, 1]>,101 InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [V6_Pipe]>], [4, 1]>,102 //103 // Register offset104 InstrItinData<IIC_iLoad_r , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,105 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,106 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>,107 //108 // Scaled register offset, issues over 2 cycles109 InstrItinData<IIC_iLoad_si , [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>,110 InstrItinData<IIC_iLoad_bh_si, [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>,111 //112 // Immediate offset with update113 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>,114 InstrItinData<IIC_iLoad_bh_iu, [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>,115 //116 // Register offset with update117 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>,118 InstrItinData<IIC_iLoad_bh_ru, [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>,119 InstrItinData<IIC_iLoad_d_ru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>,120 //121 // Scaled register offset with update, issues over 2 cycles122 InstrItinData<IIC_iLoad_siu, [InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>,123 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>,124 125 //126 // Load multiple, def is the 5th operand.127 InstrItinData<IIC_iLoad_m , [InstrStage<3, [V6_Pipe]>], [1, 1, 1, 1, 4]>,128 //129 // Load multiple + update, defs are the 1st and 5th operands.130 InstrItinData<IIC_iLoad_mu , [InstrStage<3, [V6_Pipe]>], [2, 1, 1, 1, 4]>,131 //132 // Load multiple plus branch133 InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [V6_Pipe]>,134 InstrStage<1, [V6_Pipe]>], [1, 2, 1, 1, 4]>,135 136 //137 // iLoadi + iALUr for t2LDRpci_pic.138 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>,139 InstrStage<1, [V6_Pipe]>], [3, 1]>,140 141 //142 // Pop, def is the 3rd operand.143 InstrItinData<IIC_iPop , [InstrStage<3, [V6_Pipe]>], [1, 1, 4]>,144 //145 // Pop + branch, def is the 3rd operand.146 InstrItinData<IIC_iPop_Br, [InstrStage<3, [V6_Pipe]>,147 InstrStage<1, [V6_Pipe]>], [1, 2, 4]>,148 149 // Integer store pipeline150 //151 // Immediate offset152 InstrItinData<IIC_iStore_i , [InstrStage<1, [V6_Pipe]>], [2, 1]>,153 InstrItinData<IIC_iStore_bh_i, [InstrStage<1, [V6_Pipe]>], [2, 1]>,154 InstrItinData<IIC_iStore_d_i , [InstrStage<1, [V6_Pipe]>], [2, 1]>,155 //156 // Register offset157 InstrItinData<IIC_iStore_r , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>,158 InstrItinData<IIC_iStore_bh_r, [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>,159 InstrItinData<IIC_iStore_d_r , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>,160 //161 // Scaled register offset, issues over 2 cycles162 InstrItinData<IIC_iStore_si , [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>,163 InstrItinData<IIC_iStore_bh_si, [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>,164 //165 // Immediate offset with update166 InstrItinData<IIC_iStore_iu , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,167 InstrItinData<IIC_iStore_bh_iu, [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>,168 //169 // Register offset with update170 InstrItinData<IIC_iStore_ru, [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>,171 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>,172 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>,173 //174 // Scaled register offset with update, issues over 2 cycles175 InstrItinData<IIC_iStore_siu, [InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>,176 InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>,177 //178 // Store multiple179 InstrItinData<IIC_iStore_m , [InstrStage<3, [V6_Pipe]>]>,180 //181 // Store multiple + update182 InstrItinData<IIC_iStore_mu , [InstrStage<3, [V6_Pipe]>], [2]>,183 184 // Branch185 //186 // no delay slots, so the latency of a branch is unimportant187 InstrItinData<IIC_Br , [InstrStage<1, [V6_Pipe]>]>,188 189 // VFP190 // Issue through integer pipeline, and execute in NEON unit. We assume191 // RunFast mode so that NFP pipeline is used for single-precision when192 // possible.193 //194 // FP Special Register to Integer Register File Move195 InstrItinData<IIC_fpSTAT , [InstrStage<1, [V6_Pipe]>], [3]>,196 //197 // Single-precision FP Unary198 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [V6_Pipe]>], [5, 2]>,199 //200 // Double-precision FP Unary201 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [V6_Pipe]>], [5, 2]>,202 //203 // Single-precision FP Compare204 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [V6_Pipe]>], [2, 2]>,205 //206 // Double-precision FP Compare207 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [V6_Pipe]>], [2, 2]>,208 //209 // Single to Double FP Convert210 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [V6_Pipe]>], [5, 2]>,211 //212 // Double to Single FP Convert213 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [V6_Pipe]>], [5, 2]>,214 //215 // Single-Precision FP to Integer Convert216 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [V6_Pipe]>], [9, 2]>,217 //218 // Double-Precision FP to Integer Convert219 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [V6_Pipe]>], [9, 2]>,220 //221 // Integer to Single-Precision FP Convert222 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [V6_Pipe]>], [9, 2]>,223 //224 // Integer to Double-Precision FP Convert225 InstrItinData<IIC_fpCVTID , [InstrStage<1, [V6_Pipe]>], [9, 2]>,226 //227 // Single-precision FP ALU228 InstrItinData<IIC_fpALU32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>,229 //230 // Double-precision FP ALU231 InstrItinData<IIC_fpALU64 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>,232 //233 // Single-precision FP Multiply234 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>,235 //236 // Double-precision FP Multiply237 InstrItinData<IIC_fpMUL64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2]>,238 //239 // Single-precision FP MAC240 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>,241 //242 // Double-precision FP MAC243 InstrItinData<IIC_fpMAC64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>,244 //245 // Single-precision Fused FP MAC246 InstrItinData<IIC_fpFMAC32, [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>,247 //248 // Double-precision Fused FP MAC249 InstrItinData<IIC_fpFMAC64, [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>,250 //251 // Single-precision FP DIV252 InstrItinData<IIC_fpDIV32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>,253 //254 // Double-precision FP DIV255 InstrItinData<IIC_fpDIV64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,256 //257 // Single-precision FP SQRT258 InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>,259 //260 // Double-precision FP SQRT261 InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,262 //263 // Integer to Single-precision Move264 InstrItinData<IIC_fpMOVIS, [InstrStage<1, [V6_Pipe]>], [10, 1]>,265 //266 // Integer to Double-precision Move267 InstrItinData<IIC_fpMOVID, [InstrStage<1, [V6_Pipe]>], [10, 1, 1]>,268 //269 // Single-precision to Integer Move270 InstrItinData<IIC_fpMOVSI, [InstrStage<1, [V6_Pipe]>], [10, 1]>,271 //272 // Double-precision to Integer Move273 InstrItinData<IIC_fpMOVDI, [InstrStage<1, [V6_Pipe]>], [10, 10, 1]>,274 //275 // Single-precision FP Load276 InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,277 //278 // Double-precision FP Load279 InstrItinData<IIC_fpLoad64 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,280 //281 // FP Load Multiple282 InstrItinData<IIC_fpLoad_m , [InstrStage<3, [V6_Pipe]>], [2, 1, 1, 5]>,283 //284 // FP Load Multiple + update285 InstrItinData<IIC_fpLoad_mu, [InstrStage<3, [V6_Pipe]>], [3, 2, 1, 1, 5]>,286 //287 // Single-precision FP Store288 InstrItinData<IIC_fpStore32 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,289 //290 // Double-precision FP Store291 // use FU_Issue to enforce the 1 load/store per cycle limit292 InstrItinData<IIC_fpStore64 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>,293 //294 // FP Store Multiple295 InstrItinData<IIC_fpStore_m, [InstrStage<3, [V6_Pipe]>], [2, 2, 2, 2]>,296 //297 // FP Store Multiple + update298 InstrItinData<IIC_fpStore_mu,[InstrStage<3, [V6_Pipe]>], [3, 2, 2, 2, 2]>299]>;300