513 lines · c
1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file declares the ARM specific subclass of TargetSubtargetInfo.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H14#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H15 16#include "ARMBaseInstrInfo.h"17#include "ARMBaseRegisterInfo.h"18#include "ARMConstantPoolValue.h"19#include "ARMFrameLowering.h"20#include "ARMISelLowering.h"21#include "ARMMachineFunctionInfo.h"22#include "ARMSelectionDAGInfo.h"23#include "llvm/Analysis/TargetTransformInfo.h"24#include "llvm/CodeGen/GlobalISel/CallLowering.h"25#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"26#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"27#include "llvm/CodeGen/MachineFunction.h"28#include "llvm/CodeGen/RegisterBankInfo.h"29#include "llvm/CodeGen/TargetSubtargetInfo.h"30#include "llvm/MC/MCInstrItineraries.h"31#include "llvm/MC/MCSchedule.h"32#include "llvm/Target/TargetMachine.h"33#include "llvm/Target/TargetOptions.h"34#include "llvm/TargetParser/Triple.h"35#include <bitset>36#include <memory>37#include <string>38 39#define GET_SUBTARGETINFO_HEADER40#include "ARMGenSubtargetInfo.inc"41 42namespace llvm {43 44class ARMBaseTargetMachine;45class GlobalValue;46class StringRef;47 48class ARMSubtarget : public ARMGenSubtargetInfo {49protected:50 enum ARMProcFamilyEnum {51 Others,52#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,53#include "llvm/TargetParser/ARMTargetParserDef.inc"54#undef ARM_PROCESSOR_FAMILY55 };56 enum ARMProcClassEnum {57 None,58 59 AClass,60 MClass,61 RClass62 };63 enum ARMArchEnum {64#define ARM_ARCHITECTURE(ENUM) ENUM,65#include "llvm/TargetParser/ARMTargetParserDef.inc"66#undef ARM_ARCHITECTURE67 };68 69public:70 /// What kind of timing do load multiple/store multiple instructions have.71 enum ARMLdStMultipleTiming {72 /// Can load/store 2 registers/cycle.73 DoubleIssue,74 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access75 /// is not 64-bit aligned.76 DoubleIssueCheckUnalignedAccess,77 /// Can load/store 1 register/cycle.78 SingleIssue,79 /// Can load/store 1 register/cycle, but needs an extra cycle for address80 /// computation and potentially also for register writeback.81 SingleIssuePlusExtras,82 };83 84 /// How the push and pop instructions of callee saved general-purpose85 /// registers should be split.86 enum PushPopSplitVariation {87 /// All GPRs can be pushed in a single instruction.88 /// push {r0-r12, lr}89 /// vpush {d8-d15}90 NoSplit,91 92 /// R7 and LR must be adjacent, because R7 is the frame pointer, and must93 /// point to a frame record consisting of the previous frame pointer and the94 /// return address.95 /// push {r0-r7, lr}96 /// push {r8-r12}97 /// vpush {d8-d15}98 /// Note that Thumb1 changes this layout when the frame pointer is R11,99 /// using a longer sequence of instructions because R11 can't be used by a100 /// Thumb1 push instruction. This doesn't currently have a separate enum101 /// value, and is handled entriely within Thumb1FrameLowering::emitPrologue.102 SplitR7,103 104 /// When the stack frame size is not known (because of variable-sized105 /// objects or realignment), Windows SEH requires the callee-saved registers106 /// to be stored in three regions, with R11 and LR below the floating-point107 /// registers.108 /// push {r0-r10, r12}109 /// vpush {d8-d15}110 /// push {r11, lr}111 SplitR11WindowsSEH,112 113 /// When generating AAPCS-compilant frame chains, R11 is the frame pointer,114 /// and must be pushed adjacent to the return address (LR). Normally this115 /// isn't a problem, because the only register between them is r12, which is116 /// the intra-procedure-call scratch register, so doesn't need to be saved.117 /// However, when PACBTI is in use, r12 contains the authentication code, so118 /// does need to be saved. This means that we need a separate push for R11119 /// and LR.120 /// push {r0-r10, r12}121 /// push {r11, lr}122 /// vpush {d8-d15}123 SplitR11AAPCSSignRA,124 };125 126protected:127// Bool members corresponding to the SubtargetFeatures defined in tablegen128#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \129 bool ATTRIBUTE = DEFAULT;130#include "ARMGenSubtargetInfo.inc"131 132 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.133 ARMProcFamilyEnum ARMProcFamily = Others;134 135 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.136 ARMProcClassEnum ARMProcClass = None;137 138 /// ARMArch - ARM architecture139 ARMArchEnum ARMArch = ARMv4t;140 141 /// UseMulOps - True if non-microcoded fused integer multiply-add and142 /// multiply-subtract instructions should be used.143 bool UseMulOps = false;144 145 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker146 /// must be able to synthesize call stubs for interworking between ARM and147 /// Thumb.148 bool SupportsTailCall = false;149 150 /// RestrictIT - If true, the subtarget disallows generation of complex IT151 /// blocks.152 bool RestrictIT = false;153 154 /// stackAlignment - The minimum alignment known to hold of the stack frame on155 /// entry to the function and which must be maintained by every function.156 Align stackAlignment = Align(4);157 158 /// CPUString - String name of used CPU.159 std::string CPUString;160 161 unsigned MaxInterleaveFactor = 1;162 163 /// Clearance before partial register updates (in number of instructions)164 unsigned PartialUpdateClearance = 0;165 166 /// What kind of timing do load multiple/store multiple have (double issue,167 /// single issue etc).168 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;169 170 /// The adjustment that we need to apply to get the operand latency from the171 /// operand cycle returned by the itinerary data for pre-ISel operands.172 int PreISelOperandLatencyAdjustment = 2;173 174 /// What alignment is preferred for loop bodies and functions, in log2(bytes).175 unsigned PreferBranchLogAlignment = 0;176 177 /// The cost factor for MVE instructions, representing the multiple beats an178 // instruction can take. The default is 2, (set in initSubtargetFeatures so179 // that we can use subtarget features less than 2).180 unsigned MVEVectorCostFactor = 0;181 182 /// OptMinSize - True if we're optimising for minimum code size, equal to183 /// the function attribute.184 bool OptMinSize = false;185 186 /// IsLittle - The target is Little Endian187 bool IsLittle;188 189 /// DM - Denormal mode190 /// NEON and VFP RunFast mode are not IEEE 754 compliant,191 /// use this field to determine whether to generate NEON/VFP192 /// instructions in related function.193 DenormalMode DM;194 195 /// TargetTriple - What processor and OS we're targeting.196 Triple TargetTriple;197 198 /// SchedModel - Processor specific instruction costs.199 MCSchedModel SchedModel;200 201 /// Selected instruction itineraries (one entry per itinerary class.)202 InstrItineraryData InstrItins;203 204 /// Options passed via command line that could influence the target205 const TargetOptions &Options;206 207 const ARMBaseTargetMachine &TM;208 209public:210 /// This constructor initializes the data members to match that211 /// of the specified triple.212 ///213 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,214 const ARMBaseTargetMachine &TM, bool IsLittle,215 bool MinSize = false, DenormalMode DM = DenormalMode::getIEEE());216 217 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size218 /// that still makes it profitable to inline the call.219 unsigned getMaxInlineSizeThreshold() const {220 return 64;221 }222 223 /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size224 /// that still makes it profitable to inline a llvm.memcpy as a Tail225 /// Predicated loop.226 /// This threshold should only be used for constant size inputs.227 unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; }228 229 /// ParseSubtargetFeatures - Parses features string setting specified230 /// subtarget options. Definition of function is auto generated by tblgen.231 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);232 233 /// initializeSubtargetDependencies - Initializes using a CPU and feature string234 /// so that we can use initializer lists for subtarget initialization.235 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);236 237 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {238 return &TSInfo;239 }240 241 const ARMBaseInstrInfo *getInstrInfo() const override {242 return InstrInfo.get();243 }244 245 const ARMTargetLowering *getTargetLowering() const override {246 return &TLInfo;247 }248 249 const ARMFrameLowering *getFrameLowering() const override {250 return FrameLowering.get();251 }252 253 const ARMBaseRegisterInfo *getRegisterInfo() const override {254 return &InstrInfo->getRegisterInfo();255 }256 257 const CallLowering *getCallLowering() const override;258 InstructionSelector *getInstructionSelector() const override;259 const LegalizerInfo *getLegalizerInfo() const override;260 const RegisterBankInfo *getRegBankInfo() const override;261 void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override;262 263private:264 ARMSelectionDAGInfo TSInfo;265 // Either Thumb1FrameLowering or ARMFrameLowering.266 std::unique_ptr<ARMFrameLowering> FrameLowering;267 // Either Thumb1InstrInfo or Thumb2InstrInfo.268 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;269 ARMTargetLowering TLInfo;270 271 /// GlobalISel related APIs.272 std::unique_ptr<CallLowering> CallLoweringInfo;273 std::unique_ptr<InstructionSelector> InstSelector;274 std::unique_ptr<LegalizerInfo> Legalizer;275 std::unique_ptr<RegisterBankInfo> RegBankInfo;276 277 void initSubtargetFeatures(StringRef CPU, StringRef FS);278 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);279 280 std::bitset<8> CoprocCDE = {};281public:282// Getters for SubtargetFeatures defined in tablegen283#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \284 bool GETTER() const { return ATTRIBUTE; }285#include "ARMGenSubtargetInfo.inc"286 287 /// @{288 /// These functions are obsolete, please consider adding subtarget features289 /// or properties instead of calling them.290 bool isCortexA5() const { return ARMProcFamily == CortexA5; }291 bool isCortexA7() const { return ARMProcFamily == CortexA7; }292 bool isCortexA8() const { return ARMProcFamily == CortexA8; }293 bool isCortexA9() const { return ARMProcFamily == CortexA9; }294 bool isCortexA15() const { return ARMProcFamily == CortexA15; }295 bool isSwift() const { return ARMProcFamily == Swift; }296 bool isCortexM3() const { return ARMProcFamily == CortexM3; }297 bool isCortexM55() const { return ARMProcFamily == CortexM55; }298 bool isCortexM7() const { return ARMProcFamily == CortexM7; }299 bool isCortexM85() const { return ARMProcFamily == CortexM85; }300 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }301 bool isCortexR5() const { return ARMProcFamily == CortexR5; }302 bool isKrait() const { return ARMProcFamily == Krait; }303 /// @}304 305 bool hasARMOps() const { return !NoARM; }306 307 bool useNEONForSinglePrecisionFP() const {308 return hasNEON() && hasNEONForFP();309 }310 311 bool hasVFP2Base() const { return hasVFPv2SP(); }312 bool hasVFP3Base() const { return hasVFPv3D16SP(); }313 bool hasVFP4Base() const { return hasVFPv4D16SP(); }314 bool hasFPARMv8Base() const { return hasFPARMv8D16SP(); }315 316 bool hasAnyDataBarrier() const {317 return HasDataBarrier || (hasV6Ops() && !isThumb());318 }319 320 bool useMulOps() const { return UseMulOps; }321 bool useFPVMLx() const { return !SlowFPVMLx; }322 bool useFPVFMx() const {323 return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx;324 }325 bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); }326 bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); }327 bool hasBaseDSP() const {328 if (isThumb())329 return hasThumb2() && hasDSP();330 else331 return hasV5TEOps();332 }333 334 /// Return true if the CPU supports any kind of instruction fusion.335 bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }336 337 const Triple &getTargetTriple() const { return TargetTriple; }338 339 /// @{340 /// These properties are per-module, please use the TargetMachine341 /// TargetTriple.342 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }343 bool isTargetIOS() const { return TargetTriple.isiOS(); }344 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }345 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }346 bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); }347 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }348 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }349 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }350 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }351 352 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }353 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }354 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }355 356 bool isTargetAEABI() const { return TargetTriple.isTargetAEABI(); }357 358 bool isTargetGNUAEABI() const { return TargetTriple.isTargetGNUAEABI(); }359 360 bool isTargetMuslAEABI() const { return TargetTriple.isTargetMuslAEABI(); }361 362 // ARM Targets that support EHABI exception handling standard363 // Darwin uses SjLj. Other targets might need more checks.364 bool isTargetEHABICompatible() const {365 return TargetTriple.isTargetEHABICompatible();366 }367 /// @}368 369 bool isReadTPSoft() const {370 return !(isReadTPTPIDRURW() || isReadTPTPIDRURO() || isReadTPTPIDRPRW());371 }372 373 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }374 375 bool isXRaySupported() const override;376 377 bool isROPI() const;378 bool isRWPI() const;379 380 bool useMachineScheduler() const { return UseMISched; }381 bool useMachinePipeliner() const { return UseMIPipeliner; }382 bool hasMinSize() const { return OptMinSize; }383 bool isThumb1Only() const { return isThumb() && !hasThumb2(); }384 bool isThumb2() const { return isThumb() && hasThumb2(); }385 bool isMClass() const { return ARMProcClass == MClass; }386 bool isRClass() const { return ARMProcClass == RClass; }387 bool isAClass() const { return ARMProcClass == AClass; }388 389 bool isR9Reserved() const {390 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;391 }392 393 MCPhysReg getFramePointerReg() const {394 if (isTargetDarwin() ||395 (!isTargetWindows() && isThumb() && !createAAPCSFrameChain()))396 return ARM::R7;397 return ARM::R11;398 }399 400 enum PushPopSplitVariation401 getPushPopSplitVariation(const MachineFunction &MF) const;402 403 bool useStride4VFPs() const;404 405 bool useMovt() const;406 407 bool supportsTailCall() const { return SupportsTailCall; }408 409 bool allowsUnalignedMem() const { return !StrictAlign; }410 411 bool restrictIT() const { return RestrictIT; }412 413 const std::string & getCPUString() const { return CPUString; }414 415 bool isLittle() const { return IsLittle; }416 417 unsigned getMispredictionPenalty() const;418 419 /// Returns true if machine scheduler should be enabled.420 bool enableMachineScheduler() const override;421 422 /// Returns true if machine pipeliner should be enabled.423 bool enableMachinePipeliner() const override;424 bool useDFAforSMS() const override;425 426 /// True for some subtargets at > -O0.427 bool enablePostRAScheduler() const override;428 429 /// True for some subtargets at > -O0.430 bool enablePostRAMachineScheduler() const override;431 432 /// Check whether this subtarget wants to use subregister liveness.433 bool enableSubRegLiveness() const override;434 435 /// Enable use of alias analysis during code generation (during MI436 /// scheduling, DAGCombine, etc.).437 bool useAA() const override { return true; }438 439 /// getInstrItins - Return the instruction itineraries based on subtarget440 /// selection.441 const InstrItineraryData *getInstrItineraryData() const override {442 return &InstrItins;443 }444 445 /// getStackAlignment - Returns the minimum alignment known to hold of the446 /// stack frame on entry to the function and which must be maintained by every447 /// function for this subtarget.448 Align getStackAlignment() const { return stackAlignment; }449 450 // Returns the required alignment for LDRD/STRD instructions451 Align getDualLoadStoreAlignment() const {452 return Align(hasV7Ops() || allowsUnalignedMem() ? 4 : 8);453 }454 455 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }456 457 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }458 459 ARMLdStMultipleTiming getLdStMultipleTiming() const {460 return LdStMultipleTiming;461 }462 463 int getPreISelOperandLatencyAdjustment() const {464 return PreISelOperandLatencyAdjustment;465 }466 467 /// True if the GV will be accessed via an indirect symbol.468 bool isGVIndirectSymbol(const GlobalValue *GV) const;469 470 /// Returns the constant pool modifier needed to access the GV.471 bool isGVInGOT(const GlobalValue *GV) const;472 473 /// True if fast-isel is used.474 bool useFastISel() const;475 476 /// Returns the correct return opcode for the current feature set.477 /// Use BX if available to allow mixing thumb/arm code, but fall back478 /// to plain mov pc,lr on ARMv4.479 unsigned getReturnOpcode() const {480 if (isThumb())481 return ARM::tBX_RET;482 if (hasV4TOps())483 return ARM::BX_RET;484 return ARM::MOVPCLR;485 }486 487 /// Allow movt+movw for PIC global address calculation.488 /// ELF does not have GOT relocations for movt+movw.489 /// ROPI does not use GOT.490 bool allowPositionIndependentMovt() const {491 return isROPI() || !isTargetELF();492 }493 494 unsigned getPreferBranchLogAlignment() const {495 return PreferBranchLogAlignment;496 }497 498 unsigned499 getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const {500 if (CostKind == TargetTransformInfo::TCK_CodeSize)501 return 1;502 return MVEVectorCostFactor;503 }504 505 bool ignoreCSRForAllocationOrder(const MachineFunction &MF,506 MCRegister PhysReg) const override;507 unsigned getGPRAllocationOrder(const MachineFunction &MF) const;508};509 510} // end namespace llvm511 512#endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H513