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1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file declares the ARM specific subclass of TargetMachine.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H14#define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H15 16#include "ARMSubtarget.h"17#include "llvm/ADT/StringMap.h"18#include "llvm/ADT/StringRef.h"19#include "llvm/Analysis/TargetTransformInfo.h"20#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"21#include "llvm/Support/CodeGen.h"22#include "llvm/Target/TargetMachine.h"23#include "llvm/TargetParser/ARMTargetParser.h"24#include <memory>25#include <optional>26 27namespace llvm {28 29class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {30public:31 ARM::ARMABI TargetABI;32 33protected:34 std::unique_ptr<TargetLoweringObjectFile> TLOF;35 bool isLittle;36 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;37 38 /// Reset internal state.39 void reset() override;40 41public:42 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,43 StringRef FS, const TargetOptions &Options,44 std::optional<Reloc::Model> RM,45 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL);46 ~ARMBaseTargetMachine() override;47 48 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;49 // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,50 // subtargets are per-function entities based on the target-specific51 // attributes of each function.52 const ARMSubtarget *getSubtargetImpl() const = delete;53 bool isLittleEndian() const { return isLittle; }54 55 TargetTransformInfo getTargetTransformInfo(const Function &F) const override;56 57 // Pass Pipeline Configuration58 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;59 60 TargetLoweringObjectFile *getObjFileLowering() const override {61 return TLOF.get();62 }63 64 bool isAPCS_ABI() const {65 assert(TargetABI != ARM::ARM_ABI_UNKNOWN);66 return TargetABI == ARM::ARM_ABI_APCS;67 }68 69 bool isAAPCS_ABI() const {70 assert(TargetABI != ARM::ARM_ABI_UNKNOWN);71 return TargetABI == ARM::ARM_ABI_AAPCS || TargetABI == ARM::ARM_ABI_AAPCS16;72 }73 74 bool isAAPCS16_ABI() const {75 assert(TargetABI != ARM::ARM_ABI_UNKNOWN);76 return TargetABI == ARM::ARM_ABI_AAPCS16;77 }78 79 bool isTargetHardFloat() const {80 return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||81 TargetTriple.getEnvironment() == Triple::GNUEABIHFT64 ||82 TargetTriple.getEnvironment() == Triple::MuslEABIHF ||83 TargetTriple.getEnvironment() == Triple::EABIHF ||84 (TargetTriple.isOSBinFormatMachO() &&85 TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) ||86 TargetTriple.isOSWindows() || TargetABI == ARM::ARM_ABI_AAPCS16;87 }88 89 bool targetSchedulesPostRAScheduling() const override { return true; };90 91 MachineFunctionInfo *92 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,93 const TargetSubtargetInfo *STI) const override;94 95 /// Returns true if a cast between SrcAS and DestAS is a noop.96 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {97 // Addrspacecasts are always noops.98 return true;99 }100 101 bool isGVIndirectSymbol(const GlobalValue *GV) const {102 if (!shouldAssumeDSOLocal(GV))103 return true;104 105 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in106 // the section that is being relocated. This means we have to use o load107 // even for GVs that are known to be local to the dso.108 if (getTargetTriple().isOSBinFormatMachO() && isPositionIndependent() &&109 (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))110 return true;111 112 return false;113 }114 115 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;116 yaml::MachineFunctionInfo *117 convertFuncInfoToYAML(const MachineFunction &MF) const override;118 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,119 PerFunctionMIParsingState &PFS,120 SMDiagnostic &Error,121 SMRange &SourceRange) const override;122 ScheduleDAGInstrs *123 createMachineScheduler(MachineSchedContext *C) const override;124 ScheduleDAGInstrs *125 createPostMachineScheduler(MachineSchedContext *C) const override;126};127 128/// ARM/Thumb little endian target machine.129///130class ARMLETargetMachine : public ARMBaseTargetMachine {131public:132 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,133 StringRef FS, const TargetOptions &Options,134 std::optional<Reloc::Model> RM,135 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,136 bool JIT);137};138 139/// ARM/Thumb big endian target machine.140///141class ARMBETargetMachine : public ARMBaseTargetMachine {142public:143 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,144 StringRef FS, const TargetOptions &Options,145 std::optional<Reloc::Model> RM,146 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,147 bool JIT);148};149 150} // end namespace llvm151 152#endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H153