6569 lines · cpp
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "ARMBaseInstrInfo.h"10#include "MCTargetDesc/ARMAddressingModes.h"11#include "MCTargetDesc/ARMBaseInfo.h"12#include "MCTargetDesc/ARMMCTargetDesc.h"13#include "TargetInfo/ARMTargetInfo.h"14#include "Utils/ARMBaseInfo.h"15#include "llvm/MC/MCContext.h"16#include "llvm/MC/MCDecoder.h"17#include "llvm/MC/MCDecoderOps.h"18#include "llvm/MC/MCDisassembler/MCDisassembler.h"19#include "llvm/MC/MCInst.h"20#include "llvm/MC/MCInstrDesc.h"21#include "llvm/MC/MCInstrInfo.h"22#include "llvm/MC/MCSubtargetInfo.h"23#include "llvm/MC/TargetRegistry.h"24#include "llvm/Support/Compiler.h"25#include "llvm/Support/ErrorHandling.h"26#include "llvm/Support/MathExtras.h"27#include "llvm/Support/raw_ostream.h"28#include "llvm/TargetParser/SubtargetFeature.h"29#include <algorithm>30#include <cassert>31#include <cstdint>32#include <vector>33 34using namespace llvm;35using namespace llvm::MCD;36 37#define DEBUG_TYPE "arm-disassembler"38 39using DecodeStatus = MCDisassembler::DecodeStatus;40 41namespace {42 43// Handles the condition code status of instructions in IT blocks44class ITStatus {45public:46 // Returns the condition code for instruction in IT block47 unsigned getITCC() {48 unsigned CC = ARMCC::AL;49 if (instrInITBlock())50 CC = ITStates.back();51 return CC;52 }53 54 // Advances the IT block state to the next T or E55 void advanceITState() { ITStates.pop_back(); }56 57 // Returns true if the current instruction is in an IT block58 bool instrInITBlock() { return !ITStates.empty(); }59 60 // Returns true if current instruction is the last instruction in an IT block61 bool instrLastInITBlock() { return ITStates.size() == 1; }62 63 // Called when decoding an IT instruction. Sets the IT state for64 // the following instructions that for the IT block. Firstcond65 // corresponds to the field in the IT instruction encoding; Mask66 // is in the MCOperand format in which 1 means 'else' and 0 'then'.67 void setITState(char Firstcond, char Mask) {68 // (3 - the number of trailing zeros) is the number of then / else.69 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);71 assert(NumTZ <= 3 && "Invalid IT mask!");72 // push condition codes onto the stack the correct order for the pops73 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {74 unsigned Else = (Mask >> Pos) & 1;75 ITStates.push_back(CCBits ^ Else);76 }77 ITStates.push_back(CCBits);78 }79 80private:81 std::vector<unsigned char> ITStates;82};83 84class VPTStatus {85public:86 unsigned getVPTPred() {87 unsigned Pred = ARMVCC::None;88 if (instrInVPTBlock())89 Pred = VPTStates.back();90 return Pred;91 }92 93 void advanceVPTState() { VPTStates.pop_back(); }94 95 bool instrInVPTBlock() { return !VPTStates.empty(); }96 97 bool instrLastInVPTBlock() { return VPTStates.size() == 1; }98 99 void setVPTState(char Mask) {100 // (3 - the number of trailing zeros) is the number of then / else.101 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask);102 assert(NumTZ <= 3 && "Invalid VPT mask!");103 // push predicates onto the stack the correct order for the pops104 for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {105 bool T = ((Mask >> Pos) & 1) == 0;106 if (T)107 VPTStates.push_back(ARMVCC::Then);108 else109 VPTStates.push_back(ARMVCC::Else);110 }111 VPTStates.push_back(ARMVCC::Then);112 }113 114private:115 SmallVector<unsigned char, 4> VPTStates;116};117 118/// ARM disassembler for all ARM platforms.119class ARMDisassembler : public MCDisassembler {120public:121 std::unique_ptr<const MCInstrInfo> MCII;122 mutable ITStatus ITBlock;123 mutable VPTStatus VPTBlock;124 125 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,126 const MCInstrInfo *MCII)127 : MCDisassembler(STI, Ctx), MCII(MCII) {128 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions)129 ? llvm::endianness::big130 : llvm::endianness::little;131 }132 133 ~ARMDisassembler() override = default;134 135 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,136 ArrayRef<uint8_t> Bytes, uint64_t Address,137 raw_ostream &CStream) const override;138 139 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes,140 uint64_t Address) const override;141 142private:143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,144 ArrayRef<uint8_t> Bytes, uint64_t Address,145 raw_ostream &CStream) const;146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,148 ArrayRef<uint8_t> Bytes, uint64_t Address,149 raw_ostream &CStream) const;150 151 bool isVectorPredicable(const MCInst &MI) const;152 DecodeStatus checkThumbPredicate(MCInst &) const;153 void UpdateThumbPredicate(DecodeStatus &S, MCInst &MI) const;154 155 llvm::endianness InstructionEndianness;156};157 158} // end anonymous namespace159 160typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,161 uint64_t Address,162 const MCDisassembler *Decoder);163 164/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the165/// immediate Value in the MCInst. The immediate Value has had any PC166/// adjustment made by the caller. If the instruction is a branch instruction167/// then isBranch is true, else false. If the getOpInfo() function was set as168/// part of the setupForSymbolicDisassembly() call then that function is called169/// to get any symbolic information at the Address for this instruction. If170/// that returns non-zero then the symbolic information it returns is used to171/// create an MCExpr and that is added as an operand to the MCInst. If172/// getOpInfo() returns zero and isBranch is true then a symbol look up for173/// Value is done and if a symbol is found an MCExpr is created with that, else174/// an MCExpr with Value is created. This function returns true if it adds an175/// operand to the MCInst and false otherwise.176static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,177 bool isBranch, uint64_t InstSize,178 MCInst &MI,179 const MCDisassembler *Decoder) {180 // FIXME: Does it make sense for value to be negative?181 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,182 isBranch, /*Offset=*/0, /*OpSize=*/0,183 InstSize);184}185 186/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being187/// referenced by a load instruction with the base register that is the Pc.188/// These can often be values in a literal pool near the Address of the189/// instruction. The Address of the instruction and its immediate Value are190/// used as a possible literal pool entry. The SymbolLookUp call back will191/// return the name of a symbol referenced by the literal pool's entry if192/// the referenced address is that of a symbol. Or it will return a pointer to193/// a literal 'C' string if the referenced address of the literal pool's entry194/// is an address into a section with 'C' string literals.195static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,196 const MCDisassembler *Decoder) {197 Decoder->tryAddingPcLoadReferenceComment(Value, Address);198}199 200// Register class decoding functions.201 202static const uint16_t GPRDecoderTable[] = {203 ARM::R0, ARM::R1, ARM::R2, ARM::R3,204 ARM::R4, ARM::R5, ARM::R6, ARM::R7,205 ARM::R8, ARM::R9, ARM::R10, ARM::R11,206 ARM::R12, ARM::SP, ARM::LR, ARM::PC207};208 209static const uint16_t CLRMGPRDecoderTable[] = {210 ARM::R0, ARM::R1, ARM::R2, ARM::R3,211 ARM::R4, ARM::R5, ARM::R6, ARM::R7,212 ARM::R8, ARM::R9, ARM::R10, ARM::R11,213 ARM::R12, 0, ARM::LR, ARM::APSR214};215 216static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,217 uint64_t Address,218 const MCDisassembler *Decoder) {219 if (RegNo > 15)220 return MCDisassembler::Fail;221 222 unsigned Register = GPRDecoderTable[RegNo];223 Inst.addOperand(MCOperand::createReg(Register));224 return MCDisassembler::Success;225}226 227static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,228 uint64_t Address,229 const MCDisassembler *Decoder) {230 if (RegNo > 15)231 return MCDisassembler::Fail;232 233 unsigned Register = CLRMGPRDecoderTable[RegNo];234 if (Register == 0)235 return MCDisassembler::Fail;236 237 Inst.addOperand(MCOperand::createReg(Register));238 return MCDisassembler::Success;239}240 241static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,242 uint64_t Address,243 const MCDisassembler *Decoder) {244 DecodeStatus S = MCDisassembler::Success;245 246 if (RegNo == 15)247 S = MCDisassembler::SoftFail;248 249 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));250 251 return S;252}253 254static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,255 uint64_t Address,256 const MCDisassembler *Decoder) {257 DecodeStatus S = MCDisassembler::Success;258 259 if (RegNo == 13)260 S = MCDisassembler::SoftFail;261 262 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));263 264 return S;265}266 267static DecodeStatus268DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,269 const MCDisassembler *Decoder) {270 DecodeStatus S = MCDisassembler::Success;271 272 if (RegNo == 15)273 {274 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));275 return MCDisassembler::Success;276 }277 278 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));279 return S;280}281 282static DecodeStatus283DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,284 const MCDisassembler *Decoder) {285 DecodeStatus S = MCDisassembler::Success;286 287 if (RegNo == 15)288 {289 Inst.addOperand(MCOperand::createReg(ARM::ZR));290 return MCDisassembler::Success;291 }292 293 if (RegNo == 13)294 Check(S, MCDisassembler::SoftFail);295 296 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));297 return S;298}299 300static DecodeStatus301DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,302 const MCDisassembler *Decoder) {303 DecodeStatus S = MCDisassembler::Success;304 if (RegNo == 13)305 return MCDisassembler::Fail;306 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));307 return S;308}309 310static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,311 uint64_t Address,312 const MCDisassembler *Decoder) {313 if (RegNo > 7)314 return MCDisassembler::Fail;315 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);316}317 318static const uint16_t GPRPairDecoderTable[] = {319 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,320 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP321};322 323static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,324 uint64_t Address,325 const MCDisassembler *Decoder) {326 DecodeStatus S = MCDisassembler::Success;327 328 // According to the Arm ARM RegNo = 14 is undefined, but we return fail329 // rather than SoftFail as there is no GPRPair table entry for index 7.330 if (RegNo > 13)331 return MCDisassembler::Fail;332 333 if (RegNo & 1)334 S = MCDisassembler::SoftFail;335 336 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];337 Inst.addOperand(MCOperand::createReg(RegisterPair));338 return S;339}340 341static DecodeStatus342DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,343 const MCDisassembler *Decoder) {344 if (RegNo > 13)345 return MCDisassembler::Fail;346 347 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];348 Inst.addOperand(MCOperand::createReg(RegisterPair));349 350 if ((RegNo & 1) || RegNo > 10)351 return MCDisassembler::SoftFail;352 return MCDisassembler::Success;353}354 355static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,356 uint64_t Address,357 const MCDisassembler *Decoder) {358 if (RegNo != 13)359 return MCDisassembler::Fail;360 361 unsigned Register = GPRDecoderTable[RegNo];362 Inst.addOperand(MCOperand::createReg(Register));363 return MCDisassembler::Success;364}365 366static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,367 uint64_t Address,368 const MCDisassembler *Decoder) {369 unsigned Register = 0;370 switch (RegNo) {371 case 0:372 Register = ARM::R0;373 break;374 case 1:375 Register = ARM::R1;376 break;377 case 2:378 Register = ARM::R2;379 break;380 case 3:381 Register = ARM::R3;382 break;383 case 9:384 Register = ARM::R9;385 break;386 case 12:387 Register = ARM::R12;388 break;389 default:390 return MCDisassembler::Fail;391 }392 393 Inst.addOperand(MCOperand::createReg(Register));394 return MCDisassembler::Success;395}396 397static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,398 uint64_t Address,399 const MCDisassembler *Decoder) {400 DecodeStatus S = MCDisassembler::Success;401 402 const FeatureBitset &featureBits =403 Decoder->getSubtargetInfo().getFeatureBits();404 405 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)406 S = MCDisassembler::SoftFail;407 408 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));409 return S;410}411 412static const MCPhysReg SPRDecoderTable[] = {413 ARM::S0, ARM::S1, ARM::S2, ARM::S3,414 ARM::S4, ARM::S5, ARM::S6, ARM::S7,415 ARM::S8, ARM::S9, ARM::S10, ARM::S11,416 ARM::S12, ARM::S13, ARM::S14, ARM::S15,417 ARM::S16, ARM::S17, ARM::S18, ARM::S19,418 ARM::S20, ARM::S21, ARM::S22, ARM::S23,419 ARM::S24, ARM::S25, ARM::S26, ARM::S27,420 ARM::S28, ARM::S29, ARM::S30, ARM::S31421};422 423static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,424 uint64_t Address,425 const MCDisassembler *Decoder) {426 if (RegNo > 31)427 return MCDisassembler::Fail;428 429 unsigned Register = SPRDecoderTable[RegNo];430 Inst.addOperand(MCOperand::createReg(Register));431 return MCDisassembler::Success;432}433 434static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,435 uint64_t Address,436 const MCDisassembler *Decoder) {437 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);438}439 440static const MCPhysReg DPRDecoderTable[] = {441 ARM::D0, ARM::D1, ARM::D2, ARM::D3,442 ARM::D4, ARM::D5, ARM::D6, ARM::D7,443 ARM::D8, ARM::D9, ARM::D10, ARM::D11,444 ARM::D12, ARM::D13, ARM::D14, ARM::D15,445 ARM::D16, ARM::D17, ARM::D18, ARM::D19,446 ARM::D20, ARM::D21, ARM::D22, ARM::D23,447 ARM::D24, ARM::D25, ARM::D26, ARM::D27,448 ARM::D28, ARM::D29, ARM::D30, ARM::D31449};450 451// Does this instruction/subtarget permit use of registers d16-d31?452static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder) {453 if (Inst.getOpcode() == ARM::VSCCLRMD || Inst.getOpcode() == ARM::VSCCLRMS)454 return true;455 const FeatureBitset &featureBits =456 Decoder->getSubtargetInfo().getFeatureBits();457 return featureBits[ARM::FeatureD32];458}459 460static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,461 uint64_t Address,462 const MCDisassembler *Decoder) {463 if (RegNo > (PermitsD32(Inst, Decoder) ? 31u : 15u))464 return MCDisassembler::Fail;465 466 unsigned Register = DPRDecoderTable[RegNo];467 Inst.addOperand(MCOperand::createReg(Register));468 return MCDisassembler::Success;469}470 471static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,472 uint64_t Address,473 const MCDisassembler *Decoder) {474 if (RegNo > 7)475 return MCDisassembler::Fail;476 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);477}478 479static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,480 uint64_t Address,481 const MCDisassembler *Decoder) {482 if (RegNo > 15)483 return MCDisassembler::Fail;484 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);485}486 487static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,488 uint64_t Address,489 const MCDisassembler *Decoder) {490 if (RegNo > 15)491 return MCDisassembler::Fail;492 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);493}494 495static const MCPhysReg QPRDecoderTable[] = {496 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,497 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,498 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,499 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15500};501 502static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,503 uint64_t Address,504 const MCDisassembler *Decoder) {505 if (RegNo > 31 || (RegNo & 1) != 0)506 return MCDisassembler::Fail;507 RegNo >>= 1;508 509 unsigned Register = QPRDecoderTable[RegNo];510 Inst.addOperand(MCOperand::createReg(Register));511 return MCDisassembler::Success;512}513 514static const MCPhysReg DPairDecoderTable[] = {515 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,516 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,517 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,518 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,519 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,520 ARM::Q15521};522 523static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,524 uint64_t Address,525 const MCDisassembler *Decoder) {526 if (RegNo > 30)527 return MCDisassembler::Fail;528 529 unsigned Register = DPairDecoderTable[RegNo];530 Inst.addOperand(MCOperand::createReg(Register));531 return MCDisassembler::Success;532}533 534static const MCPhysReg DPairSpacedDecoderTable[] = {535 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,536 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,537 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,538 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,539 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,540 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,541 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,542 ARM::D28_D30, ARM::D29_D31543};544 545static DecodeStatus546DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,547 const MCDisassembler *Decoder) {548 if (RegNo > 29)549 return MCDisassembler::Fail;550 551 unsigned Register = DPairSpacedDecoderTable[RegNo];552 Inst.addOperand(MCOperand::createReg(Register));553 return MCDisassembler::Success;554}555 556static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,557 uint64_t Address,558 const MCDisassembler *Decoder) {559 if (RegNo > 7)560 return MCDisassembler::Fail;561 562 unsigned Register = QPRDecoderTable[RegNo];563 Inst.addOperand(MCOperand::createReg(Register));564 return MCDisassembler::Success;565}566 567static const MCPhysReg QQPRDecoderTable[] = {568 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,569 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7570};571 572static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,573 uint64_t Address,574 const MCDisassembler *Decoder) {575 if (RegNo > 6)576 return MCDisassembler::Fail;577 578 unsigned Register = QQPRDecoderTable[RegNo];579 Inst.addOperand(MCOperand::createReg(Register));580 return MCDisassembler::Success;581}582 583static const MCPhysReg QQQQPRDecoderTable[] = {584 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,585 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7586};587 588static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,589 uint64_t Address,590 const MCDisassembler *Decoder) {591 if (RegNo > 4)592 return MCDisassembler::Fail;593 594 unsigned Register = QQQQPRDecoderTable[RegNo];595 Inst.addOperand(MCOperand::createReg(Register));596 return MCDisassembler::Success;597}598 599// Operand decoding functions.600 601static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,602 uint64_t Address,603 const MCDisassembler *Decoder) {604 DecodeStatus S = MCDisassembler::Success;605 if (Val == 0xF) return MCDisassembler::Fail;606 // AL predicate is not allowed on Thumb1 branches.607 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)608 return MCDisassembler::Fail;609 const MCInstrInfo *MCII =610 static_cast<const ARMDisassembler *>(Decoder)->MCII.get();611 if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable())612 Check(S, MCDisassembler::SoftFail);613 Inst.addOperand(MCOperand::createImm(Val));614 if (Val == ARMCC::AL) {615 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));616 } else617 Inst.addOperand(MCOperand::createReg(ARM::CPSR));618 return S;619}620 621// This overload is used to decode a `pred` operand that is not encoded into622// instruction. This is the case for almost all predicable Thumb instructions623// (exceptions are tBcc and t2Bcc). Some predicable Thumb instructions have ARM624// equivalents where they are not predicable (always executed). This function625// is used to decode `pred` operand of these ARM instructions, too.626static DecodeStatus DecodePredicateOperand(MCInst &Inst,627 const MCDisassembler *Decoder) {628 const auto *D = static_cast<const ARMDisassembler *>(Decoder);629 unsigned CC = ARMCC::AL;630 if (D->getSubtargetInfo().hasFeature(ARM::ModeThumb))631 CC = D->ITBlock.getITCC();632 MCRegister CondReg = CC == ARMCC::AL ? ARM::NoRegister : ARM::CPSR;633 Inst.addOperand(MCOperand::createImm(CC));634 Inst.addOperand(MCOperand::createReg(CondReg));635 return MCDisassembler::Success;636}637 638static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,639 uint64_t Address,640 const MCDisassembler *Decoder) {641 if (Val)642 Inst.addOperand(MCOperand::createReg(ARM::CPSR));643 else644 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));645 return MCDisassembler::Success;646}647 648// This overload is called when decoding `s_cc_out` operand, which is not649// encoded into instruction. It is only used in Thumb1 instructions.650static DecodeStatus DecodeCCOutOperand(MCInst &Inst,651 const MCDisassembler *Decoder) {652 const auto *D = static_cast<const ARMDisassembler *>(Decoder);653 // Thumb1 instructions define CPSR unless they are inside an IT block.654 MCRegister CCR = D->ITBlock.instrInITBlock() ? ARM::NoRegister : ARM::CPSR;655 Inst.addOperand(MCOperand::createReg(CCR));656 return MCDisassembler::Success;657}658 659static DecodeStatus DecodeVpredNOperand(MCInst &Inst,660 const MCDisassembler *Decoder) {661 const auto *D = static_cast<const ARMDisassembler *>(Decoder);662 unsigned VCC = D->VPTBlock.getVPTPred();663 MCRegister CondReg = VCC == ARMVCC::None ? ARM::NoRegister : ARM::P0;664 665 Inst.addOperand(MCOperand::createImm(VCC)); // $cond666 Inst.addOperand(MCOperand::createReg(CondReg)); // $cond_reg667 Inst.addOperand(MCOperand::createReg(ARM::NoRegister)); // $tp_reg668 669 return MCDisassembler::Success;670}671 672static DecodeStatus DecodeVpredROperand(MCInst &Inst,673 const MCDisassembler *Decoder) {674 const auto *D = static_cast<const ARMDisassembler *>(Decoder);675 unsigned VCC = D->VPTBlock.getVPTPred();676 MCRegister CondReg = VCC == ARMVCC::None ? ARM::NoRegister : ARM::P0;677 678 Inst.addOperand(MCOperand::createImm(VCC)); // $cond679 Inst.addOperand(MCOperand::createReg(CondReg)); // $cond_reg680 Inst.addOperand(MCOperand::createReg(ARM::NoRegister)); // $tp_reg681 682 // The last sub-operand ($inactive) is tied to an output operand.683 // The output operand has already been decoded, so just copy it.684 const MCInstrDesc &MCID = D->MCII->get(Inst.getOpcode());685 unsigned InactiveOpIdx = Inst.getNumOperands();686 int TiedOpIdx = MCID.getOperandConstraint(InactiveOpIdx, MCOI::TIED_TO);687 assert(TiedOpIdx >= 0 &&688 "Inactive register in vpred_r is not tied to an output!");689 690 // Make a copy of the operand to ensure it is not invalidated when MI grows.691 Inst.addOperand(MCOperand(Inst.getOperand(TiedOpIdx))); // $inactive692 693 return MCDisassembler::Success;694}695 696static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,697 uint64_t Address,698 const MCDisassembler *Decoder) {699 DecodeStatus S = MCDisassembler::Success;700 701 unsigned Rm = fieldFromInstruction(Val, 0, 4);702 unsigned type = fieldFromInstruction(Val, 5, 2);703 unsigned imm = fieldFromInstruction(Val, 7, 5);704 705 // Register-immediate706 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))707 return MCDisassembler::Fail;708 709 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;710 switch (type) {711 case 0:712 Shift = ARM_AM::lsl;713 break;714 case 1:715 Shift = ARM_AM::lsr;716 break;717 case 2:718 Shift = ARM_AM::asr;719 break;720 case 3:721 Shift = ARM_AM::ror;722 break;723 }724 725 if (Shift == ARM_AM::ror && imm == 0)726 Shift = ARM_AM::rrx;727 728 unsigned Op = Shift | (imm << 3);729 Inst.addOperand(MCOperand::createImm(Op));730 731 return S;732}733 734static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,735 uint64_t Address,736 const MCDisassembler *Decoder) {737 DecodeStatus S = MCDisassembler::Success;738 739 unsigned Rm = fieldFromInstruction(Val, 0, 4);740 unsigned type = fieldFromInstruction(Val, 5, 2);741 unsigned Rs = fieldFromInstruction(Val, 8, 4);742 743 // Register-register744 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))745 return MCDisassembler::Fail;746 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))747 return MCDisassembler::Fail;748 749 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;750 switch (type) {751 case 0:752 Shift = ARM_AM::lsl;753 break;754 case 1:755 Shift = ARM_AM::lsr;756 break;757 case 2:758 Shift = ARM_AM::asr;759 break;760 case 3:761 Shift = ARM_AM::ror;762 break;763 }764 765 Inst.addOperand(MCOperand::createImm(Shift));766 767 return S;768}769 770static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,771 uint64_t Address,772 const MCDisassembler *Decoder) {773 DecodeStatus S = MCDisassembler::Success;774 775 bool NeedDisjointWriteback = false;776 MCRegister WritebackReg;777 bool CLRM = false;778 switch (Inst.getOpcode()) {779 default:780 break;781 case ARM::LDMIA_UPD:782 case ARM::LDMDB_UPD:783 case ARM::LDMIB_UPD:784 case ARM::LDMDA_UPD:785 case ARM::t2LDMIA_UPD:786 case ARM::t2LDMDB_UPD:787 case ARM::t2STMIA_UPD:788 case ARM::t2STMDB_UPD:789 NeedDisjointWriteback = true;790 WritebackReg = Inst.getOperand(0).getReg();791 break;792 case ARM::t2CLRM:793 CLRM = true;794 break;795 }796 797 // Empty register lists are not allowed.798 if (Val == 0) return MCDisassembler::Fail;799 for (unsigned i = 0; i < 16; ++i) {800 if (Val & (1 << i)) {801 if (CLRM) {802 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {803 return MCDisassembler::Fail;804 }805 } else {806 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))807 return MCDisassembler::Fail;808 // Writeback not allowed if Rn is in the target list.809 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())810 Check(S, MCDisassembler::SoftFail);811 }812 }813 }814 815 return S;816}817 818static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,819 uint64_t Address,820 const MCDisassembler *Decoder) {821 DecodeStatus S = MCDisassembler::Success;822 823 unsigned Vd = fieldFromInstruction(Val, 8, 5);824 unsigned regs = fieldFromInstruction(Val, 0, 8);825 826 // In case of unpredictable encoding, tweak the operands.827 if (regs == 0 || (Vd + regs) > 32) {828 regs = Vd + regs > 32 ? 32 - Vd : regs;829 regs = std::max( 1u, regs);830 S = MCDisassembler::SoftFail;831 }832 833 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))834 return MCDisassembler::Fail;835 for (unsigned i = 0; i < (regs - 1); ++i) {836 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))837 return MCDisassembler::Fail;838 }839 840 return S;841}842 843static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,844 uint64_t Address,845 const MCDisassembler *Decoder) {846 DecodeStatus S = MCDisassembler::Success;847 848 unsigned Vd = fieldFromInstruction(Val, 8, 5);849 unsigned regs = fieldFromInstruction(Val, 1, 7);850 851 // In case of unpredictable encoding, tweak the operands.852 unsigned MaxReg = PermitsD32(Inst, Decoder) ? 32 : 16;853 if (regs == 0 || (Vd + regs) > MaxReg) {854 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs;855 regs = std::max( 1u, regs);856 regs = std::min(MaxReg, regs);857 S = MCDisassembler::SoftFail;858 }859 860 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))861 return MCDisassembler::Fail;862 for (unsigned i = 0; i < (regs - 1); ++i) {863 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))864 return MCDisassembler::Fail;865 }866 867 return S;868}869 870static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,871 uint64_t Address,872 const MCDisassembler *Decoder) {873 // This operand encodes a mask of contiguous zeros between a specified MSB874 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,875 // the mask of all bits LSB-and-lower, and then xor them to create876 // the mask of that's all ones on [msb, lsb]. Finally we not it to877 // create the final mask.878 unsigned msb = fieldFromInstruction(Val, 5, 5);879 unsigned lsb = fieldFromInstruction(Val, 0, 5);880 881 DecodeStatus S = MCDisassembler::Success;882 if (lsb > msb) {883 Check(S, MCDisassembler::SoftFail);884 // The check above will cause the warning for the "potentially undefined885 // instruction encoding" but we can't build a bad MCOperand value here886 // with a lsb > msb or else printing the MCInst will cause a crash.887 lsb = msb;888 }889 890 uint32_t msb_mask = 0xFFFFFFFF;891 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;892 uint32_t lsb_mask = (1U << lsb) - 1;893 894 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));895 return S;896}897 898static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,899 uint64_t Address,900 const MCDisassembler *Decoder) {901 DecodeStatus S = MCDisassembler::Success;902 903 unsigned pred = fieldFromInstruction(Insn, 28, 4);904 unsigned CRd = fieldFromInstruction(Insn, 12, 4);905 unsigned coproc = fieldFromInstruction(Insn, 8, 4);906 unsigned imm = fieldFromInstruction(Insn, 0, 8);907 unsigned Rn = fieldFromInstruction(Insn, 16, 4);908 unsigned U = fieldFromInstruction(Insn, 23, 1);909 const FeatureBitset &featureBits =910 Decoder->getSubtargetInfo().getFeatureBits();911 912 switch (Inst.getOpcode()) {913 case ARM::LDC_OFFSET:914 case ARM::LDC_PRE:915 case ARM::LDC_POST:916 case ARM::LDC_OPTION:917 case ARM::LDCL_OFFSET:918 case ARM::LDCL_PRE:919 case ARM::LDCL_POST:920 case ARM::LDCL_OPTION:921 case ARM::STC_OFFSET:922 case ARM::STC_PRE:923 case ARM::STC_POST:924 case ARM::STC_OPTION:925 case ARM::STCL_OFFSET:926 case ARM::STCL_PRE:927 case ARM::STCL_POST:928 case ARM::STCL_OPTION:929 case ARM::t2LDC_OFFSET:930 case ARM::t2LDC_PRE:931 case ARM::t2LDC_POST:932 case ARM::t2LDC_OPTION:933 case ARM::t2LDCL_OFFSET:934 case ARM::t2LDCL_PRE:935 case ARM::t2LDCL_POST:936 case ARM::t2LDCL_OPTION:937 case ARM::t2STC_OFFSET:938 case ARM::t2STC_PRE:939 case ARM::t2STC_POST:940 case ARM::t2STC_OPTION:941 case ARM::t2STCL_OFFSET:942 case ARM::t2STCL_PRE:943 case ARM::t2STCL_POST:944 case ARM::t2STCL_OPTION:945 case ARM::t2LDC2_OFFSET:946 case ARM::t2LDC2L_OFFSET:947 case ARM::t2LDC2_PRE:948 case ARM::t2LDC2L_PRE:949 case ARM::t2STC2_OFFSET:950 case ARM::t2STC2L_OFFSET:951 case ARM::t2STC2_PRE:952 case ARM::t2STC2L_PRE:953 case ARM::LDC2_OFFSET:954 case ARM::LDC2L_OFFSET:955 case ARM::LDC2_PRE:956 case ARM::LDC2L_PRE:957 case ARM::STC2_OFFSET:958 case ARM::STC2L_OFFSET:959 case ARM::STC2_PRE:960 case ARM::STC2L_PRE:961 case ARM::t2LDC2_OPTION:962 case ARM::t2STC2_OPTION:963 case ARM::t2LDC2_POST:964 case ARM::t2LDC2L_POST:965 case ARM::t2STC2_POST:966 case ARM::t2STC2L_POST:967 case ARM::LDC2_POST:968 case ARM::LDC2L_POST:969 case ARM::STC2_POST:970 case ARM::STC2L_POST:971 if (coproc == 0xA || coproc == 0xB ||972 (featureBits[ARM::HasV8_1MMainlineOps] &&973 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||974 coproc == 0xE || coproc == 0xF)))975 return MCDisassembler::Fail;976 break;977 default:978 break;979 }980 981 if (featureBits[ARM::HasV8Ops] && (coproc != 14))982 return MCDisassembler::Fail;983 984 Inst.addOperand(MCOperand::createImm(coproc));985 Inst.addOperand(MCOperand::createImm(CRd));986 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))987 return MCDisassembler::Fail;988 989 switch (Inst.getOpcode()) {990 case ARM::t2LDC2_OFFSET:991 case ARM::t2LDC2L_OFFSET:992 case ARM::t2LDC2_PRE:993 case ARM::t2LDC2L_PRE:994 case ARM::t2STC2_OFFSET:995 case ARM::t2STC2L_OFFSET:996 case ARM::t2STC2_PRE:997 case ARM::t2STC2L_PRE:998 case ARM::LDC2_OFFSET:999 case ARM::LDC2L_OFFSET:1000 case ARM::LDC2_PRE:1001 case ARM::LDC2L_PRE:1002 case ARM::STC2_OFFSET:1003 case ARM::STC2L_OFFSET:1004 case ARM::STC2_PRE:1005 case ARM::STC2L_PRE:1006 case ARM::t2LDC_OFFSET:1007 case ARM::t2LDCL_OFFSET:1008 case ARM::t2LDC_PRE:1009 case ARM::t2LDCL_PRE:1010 case ARM::t2STC_OFFSET:1011 case ARM::t2STCL_OFFSET:1012 case ARM::t2STC_PRE:1013 case ARM::t2STCL_PRE:1014 case ARM::LDC_OFFSET:1015 case ARM::LDCL_OFFSET:1016 case ARM::LDC_PRE:1017 case ARM::LDCL_PRE:1018 case ARM::STC_OFFSET:1019 case ARM::STCL_OFFSET:1020 case ARM::STC_PRE:1021 case ARM::STCL_PRE:1022 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);1023 Inst.addOperand(MCOperand::createImm(imm));1024 break;1025 case ARM::t2LDC2_POST:1026 case ARM::t2LDC2L_POST:1027 case ARM::t2STC2_POST:1028 case ARM::t2STC2L_POST:1029 case ARM::LDC2_POST:1030 case ARM::LDC2L_POST:1031 case ARM::STC2_POST:1032 case ARM::STC2L_POST:1033 case ARM::t2LDC_POST:1034 case ARM::t2LDCL_POST:1035 case ARM::t2STC_POST:1036 case ARM::t2STCL_POST:1037 case ARM::LDC_POST:1038 case ARM::LDCL_POST:1039 case ARM::STC_POST:1040 case ARM::STCL_POST:1041 imm |= U << 8;1042 [[fallthrough]];1043 default:1044 // The 'option' variant doesn't encode 'U' in the immediate since1045 // the immediate is unsigned [0,255].1046 Inst.addOperand(MCOperand::createImm(imm));1047 break;1048 }1049 1050 switch (Inst.getOpcode()) {1051 case ARM::LDC_OFFSET:1052 case ARM::LDC_PRE:1053 case ARM::LDC_POST:1054 case ARM::LDC_OPTION:1055 case ARM::LDCL_OFFSET:1056 case ARM::LDCL_PRE:1057 case ARM::LDCL_POST:1058 case ARM::LDCL_OPTION:1059 case ARM::STC_OFFSET:1060 case ARM::STC_PRE:1061 case ARM::STC_POST:1062 case ARM::STC_OPTION:1063 case ARM::STCL_OFFSET:1064 case ARM::STCL_PRE:1065 case ARM::STCL_POST:1066 case ARM::STCL_OPTION:1067 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))1068 return MCDisassembler::Fail;1069 break;1070 case ARM::t2LDC2L_OFFSET:1071 case ARM::t2LDC2L_OPTION:1072 case ARM::t2LDC2L_POST:1073 case ARM::t2LDC2L_PRE:1074 case ARM::t2LDC2_OFFSET:1075 case ARM::t2LDC2_OPTION:1076 case ARM::t2LDC2_POST:1077 case ARM::t2LDC2_PRE:1078 case ARM::t2LDCL_OFFSET:1079 case ARM::t2LDCL_OPTION:1080 case ARM::t2LDCL_POST:1081 case ARM::t2LDCL_PRE:1082 case ARM::t2LDC_OFFSET:1083 case ARM::t2LDC_OPTION:1084 case ARM::t2LDC_POST:1085 case ARM::t2LDC_PRE:1086 case ARM::t2STC2L_OFFSET:1087 case ARM::t2STC2L_OPTION:1088 case ARM::t2STC2L_POST:1089 case ARM::t2STC2L_PRE:1090 case ARM::t2STC2_OFFSET:1091 case ARM::t2STC2_OPTION:1092 case ARM::t2STC2_POST:1093 case ARM::t2STC2_PRE:1094 case ARM::t2STCL_OFFSET:1095 case ARM::t2STCL_OPTION:1096 case ARM::t2STCL_POST:1097 case ARM::t2STCL_PRE:1098 case ARM::t2STC_OFFSET:1099 case ARM::t2STC_OPTION:1100 case ARM::t2STC_POST:1101 case ARM::t2STC_PRE:1102 DecodePredicateOperand(Inst, Decoder);1103 break;1104 default:1105 break;1106 }1107 1108 return S;1109}1110 1111static DecodeStatus1112DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,1113 const MCDisassembler *Decoder) {1114 DecodeStatus S = MCDisassembler::Success;1115 1116 unsigned Rn = fieldFromInstruction(Insn, 16, 4);1117 unsigned Rt = fieldFromInstruction(Insn, 12, 4);1118 unsigned Rm = fieldFromInstruction(Insn, 0, 4);1119 unsigned imm = fieldFromInstruction(Insn, 0, 12);1120 unsigned pred = fieldFromInstruction(Insn, 28, 4);1121 unsigned reg = fieldFromInstruction(Insn, 25, 1);1122 unsigned P = fieldFromInstruction(Insn, 24, 1);1123 unsigned W = fieldFromInstruction(Insn, 21, 1);1124 1125 // On stores, the writeback operand precedes Rt.1126 switch (Inst.getOpcode()) {1127 case ARM::STR_POST_IMM:1128 case ARM::STR_POST_REG:1129 case ARM::STRB_POST_IMM:1130 case ARM::STRB_POST_REG:1131 case ARM::STRT_POST_REG:1132 case ARM::STRT_POST_IMM:1133 case ARM::STRBT_POST_REG:1134 case ARM::STRBT_POST_IMM:1135 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1136 return MCDisassembler::Fail;1137 break;1138 default:1139 break;1140 }1141 1142 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))1143 return MCDisassembler::Fail;1144 1145 // On loads, the writeback operand comes after Rt.1146 switch (Inst.getOpcode()) {1147 case ARM::LDR_POST_IMM:1148 case ARM::LDR_POST_REG:1149 case ARM::LDRB_POST_IMM:1150 case ARM::LDRB_POST_REG:1151 case ARM::LDRBT_POST_REG:1152 case ARM::LDRBT_POST_IMM:1153 case ARM::LDRT_POST_REG:1154 case ARM::LDRT_POST_IMM:1155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1156 return MCDisassembler::Fail;1157 break;1158 default:1159 break;1160 }1161 1162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1163 return MCDisassembler::Fail;1164 1165 ARM_AM::AddrOpc Op = ARM_AM::add;1166 if (!fieldFromInstruction(Insn, 23, 1))1167 Op = ARM_AM::sub;1168 1169 bool writeback = (P == 0) || (W == 1);1170 unsigned idx_mode = 0;1171 if (P && writeback)1172 idx_mode = ARMII::IndexModePre;1173 else if (!P && writeback)1174 idx_mode = ARMII::IndexModePost;1175 1176 if (writeback && (Rn == 15 || Rn == Rt))1177 S = MCDisassembler::SoftFail; // UNPREDICTABLE1178 1179 if (reg) {1180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))1181 return MCDisassembler::Fail;1182 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;1183 switch( fieldFromInstruction(Insn, 5, 2)) {1184 case 0:1185 Opc = ARM_AM::lsl;1186 break;1187 case 1:1188 Opc = ARM_AM::lsr;1189 break;1190 case 2:1191 Opc = ARM_AM::asr;1192 break;1193 case 3:1194 Opc = ARM_AM::ror;1195 break;1196 default:1197 return MCDisassembler::Fail;1198 }1199 unsigned amt = fieldFromInstruction(Insn, 7, 5);1200 if (Opc == ARM_AM::ror && amt == 0)1201 Opc = ARM_AM::rrx;1202 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);1203 1204 Inst.addOperand(MCOperand::createImm(imm));1205 } else {1206 Inst.addOperand(MCOperand::createReg(0));1207 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);1208 Inst.addOperand(MCOperand::createImm(tmp));1209 }1210 1211 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))1212 return MCDisassembler::Fail;1213 1214 return S;1215}1216 1217static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,1218 uint64_t Address,1219 const MCDisassembler *Decoder) {1220 DecodeStatus S = MCDisassembler::Success;1221 1222 unsigned Rn = fieldFromInstruction(Val, 13, 4);1223 unsigned Rm = fieldFromInstruction(Val, 0, 4);1224 unsigned type = fieldFromInstruction(Val, 5, 2);1225 unsigned imm = fieldFromInstruction(Val, 7, 5);1226 unsigned U = fieldFromInstruction(Val, 12, 1);1227 1228 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;1229 switch (type) {1230 case 0:1231 ShOp = ARM_AM::lsl;1232 break;1233 case 1:1234 ShOp = ARM_AM::lsr;1235 break;1236 case 2:1237 ShOp = ARM_AM::asr;1238 break;1239 case 3:1240 ShOp = ARM_AM::ror;1241 break;1242 }1243 1244 if (ShOp == ARM_AM::ror && imm == 0)1245 ShOp = ARM_AM::rrx;1246 1247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1248 return MCDisassembler::Fail;1249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))1250 return MCDisassembler::Fail;1251 unsigned shift;1252 if (U)1253 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);1254 else1255 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);1256 Inst.addOperand(MCOperand::createImm(shift));1257 1258 return S;1259}1260 1261static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,1262 uint64_t Address,1263 const MCDisassembler *Decoder) {1264 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)1265 return MCDisassembler::Fail;1266 1267 // The "csync" operand is not encoded into the "tsb" instruction (as this is1268 // the only available operand), but LLVM expects the instruction to have one1269 // operand, so we need to add the csync when decoding.1270 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC));1271 if (Inst.getOpcode() == ARM::t2TSB)1272 DecodePredicateOperand(Inst, Decoder);1273 return MCDisassembler::Success;1274}1275 1276static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,1277 uint64_t Address,1278 const MCDisassembler *Decoder) {1279 DecodeStatus S = MCDisassembler::Success;1280 1281 unsigned Rt = fieldFromInstruction(Insn, 12, 4);1282 unsigned Rn = fieldFromInstruction(Insn, 16, 4);1283 unsigned Rm = fieldFromInstruction(Insn, 0, 4);1284 unsigned type = fieldFromInstruction(Insn, 22, 1);1285 unsigned imm = fieldFromInstruction(Insn, 8, 4);1286 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;1287 unsigned pred = fieldFromInstruction(Insn, 28, 4);1288 unsigned W = fieldFromInstruction(Insn, 21, 1);1289 unsigned P = fieldFromInstruction(Insn, 24, 1);1290 unsigned Rt2 = Rt + 1;1291 1292 bool writeback = (W == 1) | (P == 0);1293 1294 // For {LD,ST}RD, Rt must be even, else undefined.1295 switch (Inst.getOpcode()) {1296 case ARM::STRD:1297 case ARM::STRD_PRE:1298 case ARM::STRD_POST:1299 case ARM::LDRD:1300 case ARM::LDRD_PRE:1301 case ARM::LDRD_POST:1302 if (Rt & 0x1) S = MCDisassembler::SoftFail;1303 break;1304 default:1305 break;1306 }1307 switch (Inst.getOpcode()) {1308 case ARM::STRD:1309 case ARM::STRD_PRE:1310 case ARM::STRD_POST:1311 if (P == 0 && W == 1)1312 S = MCDisassembler::SoftFail;1313 1314 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))1315 S = MCDisassembler::SoftFail;1316 if (type && Rm == 15)1317 S = MCDisassembler::SoftFail;1318 if (Rt2 == 15)1319 S = MCDisassembler::SoftFail;1320 if (!type && fieldFromInstruction(Insn, 8, 4))1321 S = MCDisassembler::SoftFail;1322 break;1323 case ARM::STRH:1324 case ARM::STRH_PRE:1325 case ARM::STRH_POST:1326 if (Rt == 15)1327 S = MCDisassembler::SoftFail;1328 if (writeback && (Rn == 15 || Rn == Rt))1329 S = MCDisassembler::SoftFail;1330 if (!type && Rm == 15)1331 S = MCDisassembler::SoftFail;1332 break;1333 case ARM::LDRD:1334 case ARM::LDRD_PRE:1335 case ARM::LDRD_POST:1336 if (type && Rn == 15) {1337 if (Rt2 == 15)1338 S = MCDisassembler::SoftFail;1339 break;1340 }1341 if (P == 0 && W == 1)1342 S = MCDisassembler::SoftFail;1343 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))1344 S = MCDisassembler::SoftFail;1345 if (!type && writeback && Rn == 15)1346 S = MCDisassembler::SoftFail;1347 if (writeback && (Rn == Rt || Rn == Rt2))1348 S = MCDisassembler::SoftFail;1349 break;1350 case ARM::LDRH:1351 case ARM::LDRH_PRE:1352 case ARM::LDRH_POST:1353 if (type && Rn == 15) {1354 if (Rt == 15)1355 S = MCDisassembler::SoftFail;1356 break;1357 }1358 if (Rt == 15)1359 S = MCDisassembler::SoftFail;1360 if (!type && Rm == 15)1361 S = MCDisassembler::SoftFail;1362 if (!type && writeback && (Rn == 15 || Rn == Rt))1363 S = MCDisassembler::SoftFail;1364 break;1365 case ARM::LDRSH:1366 case ARM::LDRSH_PRE:1367 case ARM::LDRSH_POST:1368 case ARM::LDRSB:1369 case ARM::LDRSB_PRE:1370 case ARM::LDRSB_POST:1371 if (type && Rn == 15) {1372 if (Rt == 15)1373 S = MCDisassembler::SoftFail;1374 break;1375 }1376 if (type && (Rt == 15 || (writeback && Rn == Rt)))1377 S = MCDisassembler::SoftFail;1378 if (!type && (Rt == 15 || Rm == 15))1379 S = MCDisassembler::SoftFail;1380 if (!type && writeback && (Rn == 15 || Rn == Rt))1381 S = MCDisassembler::SoftFail;1382 break;1383 default:1384 break;1385 }1386 1387 if (writeback) { // Writeback1388 if (P)1389 U |= ARMII::IndexModePre << 9;1390 else1391 U |= ARMII::IndexModePost << 9;1392 1393 // On stores, the writeback operand precedes Rt.1394 switch (Inst.getOpcode()) {1395 case ARM::STRD:1396 case ARM::STRD_PRE:1397 case ARM::STRD_POST:1398 case ARM::STRH:1399 case ARM::STRH_PRE:1400 case ARM::STRH_POST:1401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1402 return MCDisassembler::Fail;1403 break;1404 default:1405 break;1406 }1407 }1408 1409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))1410 return MCDisassembler::Fail;1411 switch (Inst.getOpcode()) {1412 case ARM::STRD:1413 case ARM::STRD_PRE:1414 case ARM::STRD_POST:1415 case ARM::LDRD:1416 case ARM::LDRD_PRE:1417 case ARM::LDRD_POST:1418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))1419 return MCDisassembler::Fail;1420 break;1421 default:1422 break;1423 }1424 1425 if (writeback) {1426 // On loads, the writeback operand comes after Rt.1427 switch (Inst.getOpcode()) {1428 case ARM::LDRD:1429 case ARM::LDRD_PRE:1430 case ARM::LDRD_POST:1431 case ARM::LDRH:1432 case ARM::LDRH_PRE:1433 case ARM::LDRH_POST:1434 case ARM::LDRSH:1435 case ARM::LDRSH_PRE:1436 case ARM::LDRSH_POST:1437 case ARM::LDRSB:1438 case ARM::LDRSB_PRE:1439 case ARM::LDRSB_POST:1440 case ARM::LDRHTr:1441 case ARM::LDRSBTr:1442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1443 return MCDisassembler::Fail;1444 break;1445 default:1446 break;1447 }1448 }1449 1450 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1451 return MCDisassembler::Fail;1452 1453 if (type) {1454 Inst.addOperand(MCOperand::createReg(0));1455 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));1456 } else {1457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))1458 return MCDisassembler::Fail;1459 Inst.addOperand(MCOperand::createImm(U));1460 }1461 1462 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))1463 return MCDisassembler::Fail;1464 1465 return S;1466}1467 1468static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,1469 uint64_t Address,1470 const MCDisassembler *Decoder) {1471 DecodeStatus S = MCDisassembler::Success;1472 1473 unsigned Rn = fieldFromInstruction(Insn, 16, 4);1474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1475 return MCDisassembler::Fail;1476 1477 return S;1478}1479 1480static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,1481 uint64_t Address,1482 const MCDisassembler *Decoder) {1483 unsigned imod = fieldFromInstruction(Insn, 18, 2);1484 unsigned M = fieldFromInstruction(Insn, 17, 1);1485 unsigned iflags = fieldFromInstruction(Insn, 6, 3);1486 unsigned mode = fieldFromInstruction(Insn, 0, 5);1487 1488 DecodeStatus S = MCDisassembler::Success;1489 1490 // This decoder is called from multiple location that do not check1491 // the full encoding is valid before they do.1492 if (fieldFromInstruction(Insn, 5, 1) != 0 ||1493 fieldFromInstruction(Insn, 16, 1) != 0 ||1494 fieldFromInstruction(Insn, 20, 8) != 0x10)1495 return MCDisassembler::Fail;1496 1497 // imod == '01' --> UNPREDICTABLE1498 // NOTE: Even though this is technically UNPREDICTABLE, we choose to1499 // return failure here. The '01' imod value is unprintable, so there's1500 // nothing useful we could do even if we returned UNPREDICTABLE.1501 1502 if (imod == 1) return MCDisassembler::Fail;1503 1504 if (imod && M) {1505 Inst.setOpcode(ARM::CPS3p);1506 Inst.addOperand(MCOperand::createImm(imod));1507 Inst.addOperand(MCOperand::createImm(iflags));1508 Inst.addOperand(MCOperand::createImm(mode));1509 } else if (imod && !M) {1510 Inst.setOpcode(ARM::CPS2p);1511 Inst.addOperand(MCOperand::createImm(imod));1512 Inst.addOperand(MCOperand::createImm(iflags));1513 if (mode) S = MCDisassembler::SoftFail;1514 } else if (!imod && M) {1515 Inst.setOpcode(ARM::CPS1p);1516 Inst.addOperand(MCOperand::createImm(mode));1517 if (iflags) S = MCDisassembler::SoftFail;1518 } else {1519 // imod == '00' && M == '0' --> UNPREDICTABLE1520 Inst.setOpcode(ARM::CPS1p);1521 Inst.addOperand(MCOperand::createImm(mode));1522 S = MCDisassembler::SoftFail;1523 }1524 1525 return S;1526}1527 1528static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,1529 uint64_t Address,1530 const MCDisassembler *Decoder) {1531 DecodeStatus S = MCDisassembler::Success;1532 1533 unsigned Rd = fieldFromInstruction(Insn, 12, 4);1534 unsigned Rm = fieldFromInstruction(Insn, 0, 4);1535 unsigned Rn = fieldFromInstruction(Insn, 16, 4);1536 unsigned pred = fieldFromInstruction(Insn, 28, 4);1537 1538 if (pred == 0xF)1539 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);1540 1541 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))1542 return MCDisassembler::Fail;1543 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))1544 return MCDisassembler::Fail;1545 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))1546 return MCDisassembler::Fail;1547 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))1548 return MCDisassembler::Fail;1549 return S;1550}1551 1552static DecodeStatus1553DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,1554 uint64_t Address,1555 const MCDisassembler *Decoder) {1556 DecodeStatus S = MCDisassembler::Success;1557 1558 unsigned Rn = fieldFromInstruction(Insn, 16, 4);1559 unsigned pred = fieldFromInstruction(Insn, 28, 4);1560 unsigned reglist = fieldFromInstruction(Insn, 0, 16);1561 1562 if (pred == 0xF) {1563 // Ambiguous with RFE and SRS1564 switch (Inst.getOpcode()) {1565 case ARM::LDMDA:1566 Inst.setOpcode(ARM::RFEDA);1567 break;1568 case ARM::LDMDA_UPD:1569 Inst.setOpcode(ARM::RFEDA_UPD);1570 break;1571 case ARM::LDMDB:1572 Inst.setOpcode(ARM::RFEDB);1573 break;1574 case ARM::LDMDB_UPD:1575 Inst.setOpcode(ARM::RFEDB_UPD);1576 break;1577 case ARM::LDMIA:1578 Inst.setOpcode(ARM::RFEIA);1579 break;1580 case ARM::LDMIA_UPD:1581 Inst.setOpcode(ARM::RFEIA_UPD);1582 break;1583 case ARM::LDMIB:1584 Inst.setOpcode(ARM::RFEIB);1585 break;1586 case ARM::LDMIB_UPD:1587 Inst.setOpcode(ARM::RFEIB_UPD);1588 break;1589 case ARM::STMDA:1590 Inst.setOpcode(ARM::SRSDA);1591 break;1592 case ARM::STMDA_UPD:1593 Inst.setOpcode(ARM::SRSDA_UPD);1594 break;1595 case ARM::STMDB:1596 Inst.setOpcode(ARM::SRSDB);1597 break;1598 case ARM::STMDB_UPD:1599 Inst.setOpcode(ARM::SRSDB_UPD);1600 break;1601 case ARM::STMIA:1602 Inst.setOpcode(ARM::SRSIA);1603 break;1604 case ARM::STMIA_UPD:1605 Inst.setOpcode(ARM::SRSIA_UPD);1606 break;1607 case ARM::STMIB:1608 Inst.setOpcode(ARM::SRSIB);1609 break;1610 case ARM::STMIB_UPD:1611 Inst.setOpcode(ARM::SRSIB_UPD);1612 break;1613 default:1614 return MCDisassembler::Fail;1615 }1616 1617 // For stores (which become SRS's, the only operand is the mode.1618 if (fieldFromInstruction(Insn, 20, 1) == 0) {1619 // Check SRS encoding constraints1620 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&1621 fieldFromInstruction(Insn, 20, 1) == 0))1622 return MCDisassembler::Fail;1623 1624 Inst.addOperand(1625 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));1626 return S;1627 }1628 1629 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);1630 }1631 1632 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1633 return MCDisassembler::Fail;1634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1635 return MCDisassembler::Fail; // Tied1636 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))1637 return MCDisassembler::Fail;1638 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))1639 return MCDisassembler::Fail;1640 1641 return S;1642}1643 1644// Check for UNPREDICTABLE predicated ESB instruction1645static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,1646 uint64_t Address,1647 const MCDisassembler *Decoder) {1648 unsigned pred = fieldFromInstruction(Insn, 28, 4);1649 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);1650 const FeatureBitset &FeatureBits =1651 Decoder->getSubtargetInfo().getFeatureBits();1652 1653 DecodeStatus S = MCDisassembler::Success;1654 1655 Inst.addOperand(MCOperand::createImm(imm8));1656 1657 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))1658 return MCDisassembler::Fail;1659 1660 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,1661 // so all predicates should be allowed.1662 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))1663 S = MCDisassembler::SoftFail;1664 1665 return S;1666}1667 1668static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,1669 uint64_t Address,1670 const MCDisassembler *Decoder) {1671 unsigned imod = fieldFromInstruction(Insn, 9, 2);1672 unsigned M = fieldFromInstruction(Insn, 8, 1);1673 unsigned iflags = fieldFromInstruction(Insn, 5, 3);1674 unsigned mode = fieldFromInstruction(Insn, 0, 5);1675 1676 DecodeStatus S = MCDisassembler::Success;1677 1678 // imod == '01' --> UNPREDICTABLE1679 // NOTE: Even though this is technically UNPREDICTABLE, we choose to1680 // return failure here. The '01' imod value is unprintable, so there's1681 // nothing useful we could do even if we returned UNPREDICTABLE.1682 1683 if (imod == 1) return MCDisassembler::Fail;1684 1685 if (imod && M) {1686 Inst.setOpcode(ARM::t2CPS3p);1687 Inst.addOperand(MCOperand::createImm(imod));1688 Inst.addOperand(MCOperand::createImm(iflags));1689 Inst.addOperand(MCOperand::createImm(mode));1690 } else if (imod && !M) {1691 Inst.setOpcode(ARM::t2CPS2p);1692 Inst.addOperand(MCOperand::createImm(imod));1693 Inst.addOperand(MCOperand::createImm(iflags));1694 if (mode) S = MCDisassembler::SoftFail;1695 } else if (!imod && M) {1696 Inst.setOpcode(ARM::t2CPS1p);1697 Inst.addOperand(MCOperand::createImm(mode));1698 if (iflags) S = MCDisassembler::SoftFail;1699 } else {1700 // imod == '00' && M == '0' --> this is a HINT instruction1701 int imm = fieldFromInstruction(Insn, 0, 8);1702 // HINT are defined only for immediate in [0..4]1703 if(imm > 4) return MCDisassembler::Fail;1704 Inst.setOpcode(ARM::t2HINT);1705 Inst.addOperand(MCOperand::createImm(imm));1706 DecodePredicateOperand(Inst, Decoder);1707 }1708 1709 return S;1710}1711 1712static DecodeStatus1713DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,1714 const MCDisassembler *Decoder) {1715 unsigned imm = fieldFromInstruction(Insn, 0, 8);1716 1717 unsigned Opcode = ARM::t2HINT;1718 1719 if (imm == 0x0D) {1720 Opcode = ARM::t2PACBTI;1721 } else if (imm == 0x1D) {1722 Opcode = ARM::t2PAC;1723 } else if (imm == 0x2D) {1724 Opcode = ARM::t2AUT;1725 } else if (imm == 0x0F) {1726 Opcode = ARM::t2BTI;1727 }1728 1729 Inst.setOpcode(Opcode);1730 if (Opcode == ARM::t2HINT) {1731 Inst.addOperand(MCOperand::createImm(imm));1732 DecodePredicateOperand(Inst, Decoder);1733 }1734 1735 return MCDisassembler::Success;1736}1737 1738static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,1739 uint64_t Address,1740 const MCDisassembler *Decoder) {1741 DecodeStatus S = MCDisassembler::Success;1742 1743 unsigned Rd = fieldFromInstruction(Insn, 8, 4);1744 unsigned imm = 0;1745 1746 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);1747 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);1748 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);1749 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);1750 1751 if (Inst.getOpcode() == ARM::t2MOVTi16)1752 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))1753 return MCDisassembler::Fail;1754 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))1755 return MCDisassembler::Fail;1756 1757 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))1758 Inst.addOperand(MCOperand::createImm(imm));1759 1760 DecodePredicateOperand(Inst, Decoder);1761 return S;1762}1763 1764static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,1765 uint64_t Address,1766 const MCDisassembler *Decoder) {1767 DecodeStatus S = MCDisassembler::Success;1768 1769 unsigned Rd = fieldFromInstruction(Insn, 12, 4);1770 unsigned pred = fieldFromInstruction(Insn, 28, 4);1771 unsigned imm = 0;1772 1773 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);1774 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);1775 1776 if (Inst.getOpcode() == ARM::MOVTi16)1777 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))1778 return MCDisassembler::Fail;1779 1780 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))1781 return MCDisassembler::Fail;1782 1783 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))1784 Inst.addOperand(MCOperand::createImm(imm));1785 1786 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))1787 return MCDisassembler::Fail;1788 1789 return S;1790}1791 1792static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,1793 uint64_t Address,1794 const MCDisassembler *Decoder) {1795 DecodeStatus S = MCDisassembler::Success;1796 1797 unsigned Rd = fieldFromInstruction(Insn, 16, 4);1798 unsigned Rn = fieldFromInstruction(Insn, 0, 4);1799 unsigned Rm = fieldFromInstruction(Insn, 8, 4);1800 unsigned Ra = fieldFromInstruction(Insn, 12, 4);1801 unsigned pred = fieldFromInstruction(Insn, 28, 4);1802 1803 if (pred == 0xF)1804 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);1805 1806 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))1807 return MCDisassembler::Fail;1808 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))1809 return MCDisassembler::Fail;1810 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))1811 return MCDisassembler::Fail;1812 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))1813 return MCDisassembler::Fail;1814 1815 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))1816 return MCDisassembler::Fail;1817 1818 return S;1819}1820 1821static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,1822 uint64_t Address,1823 const MCDisassembler *Decoder) {1824 DecodeStatus S = MCDisassembler::Success;1825 1826 unsigned Imm = fieldFromInstruction(Insn, 9, 1);1827 1828 const FeatureBitset &FeatureBits =1829 Decoder->getSubtargetInfo().getFeatureBits();1830 1831 if (!FeatureBits[ARM::HasV8_1aOps] ||1832 !FeatureBits[ARM::HasV8Ops])1833 return MCDisassembler::Fail;1834 1835 // Decoder can be called from DecodeTST, which does not check the full1836 // encoding is valid.1837 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||1838 fieldFromInstruction(Insn, 4,4) != 0)1839 return MCDisassembler::Fail;1840 if (fieldFromInstruction(Insn, 10,10) != 0 ||1841 fieldFromInstruction(Insn, 0,4) != 0)1842 S = MCDisassembler::SoftFail;1843 1844 Inst.setOpcode(ARM::SETPAN);1845 Inst.addOperand(MCOperand::createImm(Imm));1846 1847 return S;1848}1849 1850static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,1851 uint64_t Address,1852 const MCDisassembler *Decoder) {1853 DecodeStatus S = MCDisassembler::Success;1854 1855 unsigned Pred = fieldFromInstruction(Insn, 28, 4);1856 unsigned Rn = fieldFromInstruction(Insn, 16, 4);1857 unsigned Rm = fieldFromInstruction(Insn, 0, 4);1858 1859 if (Pred == 0xF)1860 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);1861 1862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1863 return MCDisassembler::Fail;1864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))1865 return MCDisassembler::Fail;1866 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))1867 return MCDisassembler::Fail;1868 1869 return S;1870}1871 1872static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,1873 uint64_t Address,1874 const MCDisassembler *Decoder) {1875 DecodeStatus S = MCDisassembler::Success;1876 1877 unsigned add = fieldFromInstruction(Val, 12, 1);1878 unsigned imm = fieldFromInstruction(Val, 0, 12);1879 unsigned Rn = fieldFromInstruction(Val, 13, 4);1880 1881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1882 return MCDisassembler::Fail;1883 1884 if (!add) imm *= -1;1885 if (imm == 0 && !add) imm = INT32_MIN;1886 Inst.addOperand(MCOperand::createImm(imm));1887 if (Rn == 15)1888 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);1889 1890 return S;1891}1892 1893static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,1894 uint64_t Address,1895 const MCDisassembler *Decoder) {1896 DecodeStatus S = MCDisassembler::Success;1897 1898 unsigned Rn = fieldFromInstruction(Val, 9, 4);1899 // U == 1 to add imm, 0 to subtract it.1900 unsigned U = fieldFromInstruction(Val, 8, 1);1901 unsigned imm = fieldFromInstruction(Val, 0, 8);1902 1903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1904 return MCDisassembler::Fail;1905 1906 if (U)1907 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));1908 else1909 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));1910 1911 return S;1912}1913 1914static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,1915 uint64_t Address,1916 const MCDisassembler *Decoder) {1917 DecodeStatus S = MCDisassembler::Success;1918 1919 unsigned Rn = fieldFromInstruction(Val, 9, 4);1920 // U == 1 to add imm, 0 to subtract it.1921 unsigned U = fieldFromInstruction(Val, 8, 1);1922 unsigned imm = fieldFromInstruction(Val, 0, 8);1923 1924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))1925 return MCDisassembler::Fail;1926 1927 if (U)1928 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));1929 else1930 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));1931 1932 return S;1933}1934 1935static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,1936 uint64_t Address,1937 const MCDisassembler *Decoder) {1938 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);1939}1940 1941static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,1942 uint64_t Address,1943 const MCDisassembler *Decoder) {1944 DecodeStatus Status = MCDisassembler::Success;1945 1946 // Note the J1 and J2 values are from the encoded instruction. So here1947 // change them to I1 and I2 values via as documented:1948 // I1 = NOT(J1 EOR S);1949 // I2 = NOT(J2 EOR S);1950 // and build the imm32 with one trailing zero as documented:1951 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);1952 unsigned S = fieldFromInstruction(Insn, 26, 1);1953 unsigned J1 = fieldFromInstruction(Insn, 13, 1);1954 unsigned J2 = fieldFromInstruction(Insn, 11, 1);1955 unsigned I1 = !(J1 ^ S);1956 unsigned I2 = !(J2 ^ S);1957 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);1958 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);1959 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;1960 int imm32 = SignExtend32<25>(tmp << 1);1961 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,1962 true, 4, Inst, Decoder))1963 Inst.addOperand(MCOperand::createImm(imm32));1964 1965 DecodePredicateOperand(Inst, Decoder);1966 return Status;1967}1968 1969static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,1970 uint64_t Address,1971 const MCDisassembler *Decoder) {1972 DecodeStatus S = MCDisassembler::Success;1973 1974 unsigned pred = fieldFromInstruction(Insn, 28, 4);1975 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;1976 1977 if (pred == 0xF) {1978 Inst.setOpcode(ARM::BLXi);1979 imm |= fieldFromInstruction(Insn, 24, 1) << 1;1980 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,1981 true, 4, Inst, Decoder))1982 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));1983 return S;1984 }1985 1986 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,1987 true, 4, Inst, Decoder))1988 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));1989 1990 // We already have BL_pred for BL w/ predicate, no need to add addition1991 // predicate opreands for BL1992 if (Inst.getOpcode() != ARM::BL)1993 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))1994 return MCDisassembler::Fail;1995 1996 return S;1997}1998 1999static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,2000 uint64_t Address,2001 const MCDisassembler *Decoder) {2002 DecodeStatus S = MCDisassembler::Success;2003 2004 unsigned Rm = fieldFromInstruction(Val, 0, 4);2005 unsigned align = fieldFromInstruction(Val, 4, 2);2006 2007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))2008 return MCDisassembler::Fail;2009 if (!align)2010 Inst.addOperand(MCOperand::createImm(0));2011 else2012 Inst.addOperand(MCOperand::createImm(4 << align));2013 2014 return S;2015}2016 2017static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,2018 uint64_t Address,2019 const MCDisassembler *Decoder) {2020 DecodeStatus S = MCDisassembler::Success;2021 2022 unsigned Rd = fieldFromInstruction(Insn, 12, 4);2023 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;2024 unsigned wb = fieldFromInstruction(Insn, 16, 4);2025 unsigned Rn = fieldFromInstruction(Insn, 16, 4);2026 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;2027 unsigned Rm = fieldFromInstruction(Insn, 0, 4);2028 2029 // First output register2030 switch (Inst.getOpcode()) {2031 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:2032 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:2033 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:2034 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:2035 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:2036 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:2037 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:2038 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:2039 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:2040 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))2041 return MCDisassembler::Fail;2042 break;2043 case ARM::VLD2b16:2044 case ARM::VLD2b32:2045 case ARM::VLD2b8:2046 case ARM::VLD2b16wb_fixed:2047 case ARM::VLD2b16wb_register:2048 case ARM::VLD2b32wb_fixed:2049 case ARM::VLD2b32wb_register:2050 case ARM::VLD2b8wb_fixed:2051 case ARM::VLD2b8wb_register:2052 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))2053 return MCDisassembler::Fail;2054 break;2055 default:2056 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2057 return MCDisassembler::Fail;2058 }2059 2060 // Second output register2061 switch (Inst.getOpcode()) {2062 case ARM::VLD3d8:2063 case ARM::VLD3d16:2064 case ARM::VLD3d32:2065 case ARM::VLD3d8_UPD:2066 case ARM::VLD3d16_UPD:2067 case ARM::VLD3d32_UPD:2068 case ARM::VLD4d8:2069 case ARM::VLD4d16:2070 case ARM::VLD4d32:2071 case ARM::VLD4d8_UPD:2072 case ARM::VLD4d16_UPD:2073 case ARM::VLD4d32_UPD:2074 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))2075 return MCDisassembler::Fail;2076 break;2077 case ARM::VLD3q8:2078 case ARM::VLD3q16:2079 case ARM::VLD3q32:2080 case ARM::VLD3q8_UPD:2081 case ARM::VLD3q16_UPD:2082 case ARM::VLD3q32_UPD:2083 case ARM::VLD4q8:2084 case ARM::VLD4q16:2085 case ARM::VLD4q32:2086 case ARM::VLD4q8_UPD:2087 case ARM::VLD4q16_UPD:2088 case ARM::VLD4q32_UPD:2089 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))2090 return MCDisassembler::Fail;2091 break;2092 default:2093 break;2094 }2095 2096 // Third output register2097 switch(Inst.getOpcode()) {2098 case ARM::VLD3d8:2099 case ARM::VLD3d16:2100 case ARM::VLD3d32:2101 case ARM::VLD3d8_UPD:2102 case ARM::VLD3d16_UPD:2103 case ARM::VLD3d32_UPD:2104 case ARM::VLD4d8:2105 case ARM::VLD4d16:2106 case ARM::VLD4d32:2107 case ARM::VLD4d8_UPD:2108 case ARM::VLD4d16_UPD:2109 case ARM::VLD4d32_UPD:2110 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))2111 return MCDisassembler::Fail;2112 break;2113 case ARM::VLD3q8:2114 case ARM::VLD3q16:2115 case ARM::VLD3q32:2116 case ARM::VLD3q8_UPD:2117 case ARM::VLD3q16_UPD:2118 case ARM::VLD3q32_UPD:2119 case ARM::VLD4q8:2120 case ARM::VLD4q16:2121 case ARM::VLD4q32:2122 case ARM::VLD4q8_UPD:2123 case ARM::VLD4q16_UPD:2124 case ARM::VLD4q32_UPD:2125 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))2126 return MCDisassembler::Fail;2127 break;2128 default:2129 break;2130 }2131 2132 // Fourth output register2133 switch (Inst.getOpcode()) {2134 case ARM::VLD4d8:2135 case ARM::VLD4d16:2136 case ARM::VLD4d32:2137 case ARM::VLD4d8_UPD:2138 case ARM::VLD4d16_UPD:2139 case ARM::VLD4d32_UPD:2140 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))2141 return MCDisassembler::Fail;2142 break;2143 case ARM::VLD4q8:2144 case ARM::VLD4q16:2145 case ARM::VLD4q32:2146 case ARM::VLD4q8_UPD:2147 case ARM::VLD4q16_UPD:2148 case ARM::VLD4q32_UPD:2149 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))2150 return MCDisassembler::Fail;2151 break;2152 default:2153 break;2154 }2155 2156 // Writeback operand2157 switch (Inst.getOpcode()) {2158 case ARM::VLD1d8wb_fixed:2159 case ARM::VLD1d16wb_fixed:2160 case ARM::VLD1d32wb_fixed:2161 case ARM::VLD1d64wb_fixed:2162 case ARM::VLD1d8wb_register:2163 case ARM::VLD1d16wb_register:2164 case ARM::VLD1d32wb_register:2165 case ARM::VLD1d64wb_register:2166 case ARM::VLD1q8wb_fixed:2167 case ARM::VLD1q16wb_fixed:2168 case ARM::VLD1q32wb_fixed:2169 case ARM::VLD1q64wb_fixed:2170 case ARM::VLD1q8wb_register:2171 case ARM::VLD1q16wb_register:2172 case ARM::VLD1q32wb_register:2173 case ARM::VLD1q64wb_register:2174 case ARM::VLD1d8Twb_fixed:2175 case ARM::VLD1d8Twb_register:2176 case ARM::VLD1d16Twb_fixed:2177 case ARM::VLD1d16Twb_register:2178 case ARM::VLD1d32Twb_fixed:2179 case ARM::VLD1d32Twb_register:2180 case ARM::VLD1d64Twb_fixed:2181 case ARM::VLD1d64Twb_register:2182 case ARM::VLD1d8Qwb_fixed:2183 case ARM::VLD1d8Qwb_register:2184 case ARM::VLD1d16Qwb_fixed:2185 case ARM::VLD1d16Qwb_register:2186 case ARM::VLD1d32Qwb_fixed:2187 case ARM::VLD1d32Qwb_register:2188 case ARM::VLD1d64Qwb_fixed:2189 case ARM::VLD1d64Qwb_register:2190 case ARM::VLD2d8wb_fixed:2191 case ARM::VLD2d16wb_fixed:2192 case ARM::VLD2d32wb_fixed:2193 case ARM::VLD2q8wb_fixed:2194 case ARM::VLD2q16wb_fixed:2195 case ARM::VLD2q32wb_fixed:2196 case ARM::VLD2d8wb_register:2197 case ARM::VLD2d16wb_register:2198 case ARM::VLD2d32wb_register:2199 case ARM::VLD2q8wb_register:2200 case ARM::VLD2q16wb_register:2201 case ARM::VLD2q32wb_register:2202 case ARM::VLD2b8wb_fixed:2203 case ARM::VLD2b16wb_fixed:2204 case ARM::VLD2b32wb_fixed:2205 case ARM::VLD2b8wb_register:2206 case ARM::VLD2b16wb_register:2207 case ARM::VLD2b32wb_register:2208 Inst.addOperand(MCOperand::createImm(0));2209 break;2210 case ARM::VLD3d8_UPD:2211 case ARM::VLD3d16_UPD:2212 case ARM::VLD3d32_UPD:2213 case ARM::VLD3q8_UPD:2214 case ARM::VLD3q16_UPD:2215 case ARM::VLD3q32_UPD:2216 case ARM::VLD4d8_UPD:2217 case ARM::VLD4d16_UPD:2218 case ARM::VLD4d32_UPD:2219 case ARM::VLD4q8_UPD:2220 case ARM::VLD4q16_UPD:2221 case ARM::VLD4q32_UPD:2222 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))2223 return MCDisassembler::Fail;2224 break;2225 default:2226 break;2227 }2228 2229 // AddrMode6 Base (register+alignment)2230 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))2231 return MCDisassembler::Fail;2232 2233 // AddrMode6 Offset (register)2234 switch (Inst.getOpcode()) {2235 default:2236 // The below have been updated to have explicit am6offset split2237 // between fixed and register offset. For those instructions not2238 // yet updated, we need to add an additional reg0 operand for the2239 // fixed variant.2240 //2241 // The fixed offset encodes as Rm == 0xd, so we check for that.2242 if (Rm == 0xd) {2243 Inst.addOperand(MCOperand::createReg(0));2244 break;2245 }2246 // Fall through to handle the register offset variant.2247 [[fallthrough]];2248 case ARM::VLD1d8wb_fixed:2249 case ARM::VLD1d16wb_fixed:2250 case ARM::VLD1d32wb_fixed:2251 case ARM::VLD1d64wb_fixed:2252 case ARM::VLD1d8Twb_fixed:2253 case ARM::VLD1d16Twb_fixed:2254 case ARM::VLD1d32Twb_fixed:2255 case ARM::VLD1d64Twb_fixed:2256 case ARM::VLD1d8Qwb_fixed:2257 case ARM::VLD1d16Qwb_fixed:2258 case ARM::VLD1d32Qwb_fixed:2259 case ARM::VLD1d64Qwb_fixed:2260 case ARM::VLD1d8wb_register:2261 case ARM::VLD1d16wb_register:2262 case ARM::VLD1d32wb_register:2263 case ARM::VLD1d64wb_register:2264 case ARM::VLD1q8wb_fixed:2265 case ARM::VLD1q16wb_fixed:2266 case ARM::VLD1q32wb_fixed:2267 case ARM::VLD1q64wb_fixed:2268 case ARM::VLD1q8wb_register:2269 case ARM::VLD1q16wb_register:2270 case ARM::VLD1q32wb_register:2271 case ARM::VLD1q64wb_register:2272 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback2273 // variant encodes Rm == 0xf. Anything else is a register offset post-2274 // increment and we need to add the register operand to the instruction.2275 if (Rm != 0xD && Rm != 0xF &&2276 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))2277 return MCDisassembler::Fail;2278 break;2279 case ARM::VLD2d8wb_fixed:2280 case ARM::VLD2d16wb_fixed:2281 case ARM::VLD2d32wb_fixed:2282 case ARM::VLD2b8wb_fixed:2283 case ARM::VLD2b16wb_fixed:2284 case ARM::VLD2b32wb_fixed:2285 case ARM::VLD2q8wb_fixed:2286 case ARM::VLD2q16wb_fixed:2287 case ARM::VLD2q32wb_fixed:2288 break;2289 }2290 2291 DecodePredicateOperand(Inst, Decoder);2292 return S;2293}2294 2295static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,2296 uint64_t Address,2297 const MCDisassembler *Decoder) {2298 DecodeStatus S = MCDisassembler::Success;2299 2300 unsigned Rd = fieldFromInstruction(Insn, 12, 4);2301 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;2302 unsigned wb = fieldFromInstruction(Insn, 16, 4);2303 unsigned Rn = fieldFromInstruction(Insn, 16, 4);2304 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;2305 unsigned Rm = fieldFromInstruction(Insn, 0, 4);2306 2307 // Writeback Operand2308 switch (Inst.getOpcode()) {2309 case ARM::VST1d8wb_fixed:2310 case ARM::VST1d16wb_fixed:2311 case ARM::VST1d32wb_fixed:2312 case ARM::VST1d64wb_fixed:2313 case ARM::VST1d8wb_register:2314 case ARM::VST1d16wb_register:2315 case ARM::VST1d32wb_register:2316 case ARM::VST1d64wb_register:2317 case ARM::VST1q8wb_fixed:2318 case ARM::VST1q16wb_fixed:2319 case ARM::VST1q32wb_fixed:2320 case ARM::VST1q64wb_fixed:2321 case ARM::VST1q8wb_register:2322 case ARM::VST1q16wb_register:2323 case ARM::VST1q32wb_register:2324 case ARM::VST1q64wb_register:2325 case ARM::VST1d8Twb_fixed:2326 case ARM::VST1d16Twb_fixed:2327 case ARM::VST1d32Twb_fixed:2328 case ARM::VST1d64Twb_fixed:2329 case ARM::VST1d8Twb_register:2330 case ARM::VST1d16Twb_register:2331 case ARM::VST1d32Twb_register:2332 case ARM::VST1d64Twb_register:2333 case ARM::VST1d8Qwb_fixed:2334 case ARM::VST1d16Qwb_fixed:2335 case ARM::VST1d32Qwb_fixed:2336 case ARM::VST1d64Qwb_fixed:2337 case ARM::VST1d8Qwb_register:2338 case ARM::VST1d16Qwb_register:2339 case ARM::VST1d32Qwb_register:2340 case ARM::VST1d64Qwb_register:2341 case ARM::VST2d8wb_fixed:2342 case ARM::VST2d16wb_fixed:2343 case ARM::VST2d32wb_fixed:2344 case ARM::VST2d8wb_register:2345 case ARM::VST2d16wb_register:2346 case ARM::VST2d32wb_register:2347 case ARM::VST2q8wb_fixed:2348 case ARM::VST2q16wb_fixed:2349 case ARM::VST2q32wb_fixed:2350 case ARM::VST2q8wb_register:2351 case ARM::VST2q16wb_register:2352 case ARM::VST2q32wb_register:2353 case ARM::VST2b8wb_fixed:2354 case ARM::VST2b16wb_fixed:2355 case ARM::VST2b32wb_fixed:2356 case ARM::VST2b8wb_register:2357 case ARM::VST2b16wb_register:2358 case ARM::VST2b32wb_register:2359 if (Rm == 0xF)2360 return MCDisassembler::Fail;2361 Inst.addOperand(MCOperand::createImm(0));2362 break;2363 case ARM::VST3d8_UPD:2364 case ARM::VST3d16_UPD:2365 case ARM::VST3d32_UPD:2366 case ARM::VST3q8_UPD:2367 case ARM::VST3q16_UPD:2368 case ARM::VST3q32_UPD:2369 case ARM::VST4d8_UPD:2370 case ARM::VST4d16_UPD:2371 case ARM::VST4d32_UPD:2372 case ARM::VST4q8_UPD:2373 case ARM::VST4q16_UPD:2374 case ARM::VST4q32_UPD:2375 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))2376 return MCDisassembler::Fail;2377 break;2378 default:2379 break;2380 }2381 2382 // AddrMode6 Base (register+alignment)2383 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))2384 return MCDisassembler::Fail;2385 2386 // AddrMode6 Offset (register)2387 switch (Inst.getOpcode()) {2388 default:2389 if (Rm == 0xD)2390 Inst.addOperand(MCOperand::createReg(0));2391 else if (Rm != 0xF) {2392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))2393 return MCDisassembler::Fail;2394 }2395 break;2396 case ARM::VST1d8wb_fixed:2397 case ARM::VST1d16wb_fixed:2398 case ARM::VST1d32wb_fixed:2399 case ARM::VST1d64wb_fixed:2400 case ARM::VST1q8wb_fixed:2401 case ARM::VST1q16wb_fixed:2402 case ARM::VST1q32wb_fixed:2403 case ARM::VST1q64wb_fixed:2404 case ARM::VST1d8Twb_fixed:2405 case ARM::VST1d16Twb_fixed:2406 case ARM::VST1d32Twb_fixed:2407 case ARM::VST1d64Twb_fixed:2408 case ARM::VST1d8Qwb_fixed:2409 case ARM::VST1d16Qwb_fixed:2410 case ARM::VST1d32Qwb_fixed:2411 case ARM::VST1d64Qwb_fixed:2412 case ARM::VST2d8wb_fixed:2413 case ARM::VST2d16wb_fixed:2414 case ARM::VST2d32wb_fixed:2415 case ARM::VST2q8wb_fixed:2416 case ARM::VST2q16wb_fixed:2417 case ARM::VST2q32wb_fixed:2418 case ARM::VST2b8wb_fixed:2419 case ARM::VST2b16wb_fixed:2420 case ARM::VST2b32wb_fixed:2421 break;2422 }2423 2424 // First input register2425 switch (Inst.getOpcode()) {2426 case ARM::VST1q16:2427 case ARM::VST1q32:2428 case ARM::VST1q64:2429 case ARM::VST1q8:2430 case ARM::VST1q16wb_fixed:2431 case ARM::VST1q16wb_register:2432 case ARM::VST1q32wb_fixed:2433 case ARM::VST1q32wb_register:2434 case ARM::VST1q64wb_fixed:2435 case ARM::VST1q64wb_register:2436 case ARM::VST1q8wb_fixed:2437 case ARM::VST1q8wb_register:2438 case ARM::VST2d16:2439 case ARM::VST2d32:2440 case ARM::VST2d8:2441 case ARM::VST2d16wb_fixed:2442 case ARM::VST2d16wb_register:2443 case ARM::VST2d32wb_fixed:2444 case ARM::VST2d32wb_register:2445 case ARM::VST2d8wb_fixed:2446 case ARM::VST2d8wb_register:2447 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))2448 return MCDisassembler::Fail;2449 break;2450 case ARM::VST2b16:2451 case ARM::VST2b32:2452 case ARM::VST2b8:2453 case ARM::VST2b16wb_fixed:2454 case ARM::VST2b16wb_register:2455 case ARM::VST2b32wb_fixed:2456 case ARM::VST2b32wb_register:2457 case ARM::VST2b8wb_fixed:2458 case ARM::VST2b8wb_register:2459 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))2460 return MCDisassembler::Fail;2461 break;2462 default:2463 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2464 return MCDisassembler::Fail;2465 }2466 2467 // Second input register2468 switch (Inst.getOpcode()) {2469 case ARM::VST3d8:2470 case ARM::VST3d16:2471 case ARM::VST3d32:2472 case ARM::VST3d8_UPD:2473 case ARM::VST3d16_UPD:2474 case ARM::VST3d32_UPD:2475 case ARM::VST4d8:2476 case ARM::VST4d16:2477 case ARM::VST4d32:2478 case ARM::VST4d8_UPD:2479 case ARM::VST4d16_UPD:2480 case ARM::VST4d32_UPD:2481 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))2482 return MCDisassembler::Fail;2483 break;2484 case ARM::VST3q8:2485 case ARM::VST3q16:2486 case ARM::VST3q32:2487 case ARM::VST3q8_UPD:2488 case ARM::VST3q16_UPD:2489 case ARM::VST3q32_UPD:2490 case ARM::VST4q8:2491 case ARM::VST4q16:2492 case ARM::VST4q32:2493 case ARM::VST4q8_UPD:2494 case ARM::VST4q16_UPD:2495 case ARM::VST4q32_UPD:2496 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))2497 return MCDisassembler::Fail;2498 break;2499 default:2500 break;2501 }2502 2503 // Third input register2504 switch (Inst.getOpcode()) {2505 case ARM::VST3d8:2506 case ARM::VST3d16:2507 case ARM::VST3d32:2508 case ARM::VST3d8_UPD:2509 case ARM::VST3d16_UPD:2510 case ARM::VST3d32_UPD:2511 case ARM::VST4d8:2512 case ARM::VST4d16:2513 case ARM::VST4d32:2514 case ARM::VST4d8_UPD:2515 case ARM::VST4d16_UPD:2516 case ARM::VST4d32_UPD:2517 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))2518 return MCDisassembler::Fail;2519 break;2520 case ARM::VST3q8:2521 case ARM::VST3q16:2522 case ARM::VST3q32:2523 case ARM::VST3q8_UPD:2524 case ARM::VST3q16_UPD:2525 case ARM::VST3q32_UPD:2526 case ARM::VST4q8:2527 case ARM::VST4q16:2528 case ARM::VST4q32:2529 case ARM::VST4q8_UPD:2530 case ARM::VST4q16_UPD:2531 case ARM::VST4q32_UPD:2532 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))2533 return MCDisassembler::Fail;2534 break;2535 default:2536 break;2537 }2538 2539 // Fourth input register2540 switch (Inst.getOpcode()) {2541 case ARM::VST4d8:2542 case ARM::VST4d16:2543 case ARM::VST4d32:2544 case ARM::VST4d8_UPD:2545 case ARM::VST4d16_UPD:2546 case ARM::VST4d32_UPD:2547 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))2548 return MCDisassembler::Fail;2549 break;2550 case ARM::VST4q8:2551 case ARM::VST4q16:2552 case ARM::VST4q32:2553 case ARM::VST4q8_UPD:2554 case ARM::VST4q16_UPD:2555 case ARM::VST4q32_UPD:2556 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))2557 return MCDisassembler::Fail;2558 break;2559 default:2560 break;2561 }2562 2563 DecodePredicateOperand(Inst, Decoder);2564 return S;2565}2566 2567static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,2568 uint64_t Address,2569 const MCDisassembler *Decoder) {2570 unsigned type = fieldFromInstruction(Insn, 8, 4);2571 unsigned align = fieldFromInstruction(Insn, 4, 2);2572 if (type == 6 && (align & 2)) return MCDisassembler::Fail;2573 if (type == 7 && (align & 2)) return MCDisassembler::Fail;2574 if (type == 10 && align == 3) return MCDisassembler::Fail;2575 2576 unsigned load = fieldFromInstruction(Insn, 21, 1);2577 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)2578 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);2579}2580 2581static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,2582 uint64_t Address,2583 const MCDisassembler *Decoder) {2584 unsigned size = fieldFromInstruction(Insn, 6, 2);2585 if (size == 3) return MCDisassembler::Fail;2586 2587 unsigned type = fieldFromInstruction(Insn, 8, 4);2588 unsigned align = fieldFromInstruction(Insn, 4, 2);2589 if (type == 8 && align == 3) return MCDisassembler::Fail;2590 if (type == 9 && align == 3) return MCDisassembler::Fail;2591 2592 unsigned load = fieldFromInstruction(Insn, 21, 1);2593 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)2594 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);2595}2596 2597static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,2598 uint64_t Address,2599 const MCDisassembler *Decoder) {2600 unsigned size = fieldFromInstruction(Insn, 6, 2);2601 if (size == 3) return MCDisassembler::Fail;2602 2603 unsigned align = fieldFromInstruction(Insn, 4, 2);2604 if (align & 2) return MCDisassembler::Fail;2605 2606 unsigned load = fieldFromInstruction(Insn, 21, 1);2607 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)2608 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);2609}2610 2611static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,2612 uint64_t Address,2613 const MCDisassembler *Decoder) {2614 unsigned size = fieldFromInstruction(Insn, 6, 2);2615 if (size == 3) return MCDisassembler::Fail;2616 2617 unsigned load = fieldFromInstruction(Insn, 21, 1);2618 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)2619 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);2620}2621 2622static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,2623 uint64_t Address,2624 const MCDisassembler *Decoder) {2625 DecodeStatus S = MCDisassembler::Success;2626 2627 unsigned Rd = fieldFromInstruction(Insn, 12, 4);2628 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;2629 unsigned Rn = fieldFromInstruction(Insn, 16, 4);2630 unsigned Rm = fieldFromInstruction(Insn, 0, 4);2631 unsigned align = fieldFromInstruction(Insn, 4, 1);2632 unsigned size = fieldFromInstruction(Insn, 6, 2);2633 2634 if (size == 0 && align == 1)2635 return MCDisassembler::Fail;2636 align *= (1 << size);2637 2638 switch (Inst.getOpcode()) {2639 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:2640 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:2641 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:2642 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:2643 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))2644 return MCDisassembler::Fail;2645 break;2646 default:2647 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2648 return MCDisassembler::Fail;2649 break;2650 }2651 if (Rm != 0xF) {2652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))2653 return MCDisassembler::Fail;2654 }2655 2656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))2657 return MCDisassembler::Fail;2658 Inst.addOperand(MCOperand::createImm(align));2659 2660 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback2661 // variant encodes Rm == 0xf. Anything else is a register offset post-2662 // increment and we need to add the register operand to the instruction.2663 if (Rm != 0xD && Rm != 0xF &&2664 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))2665 return MCDisassembler::Fail;2666 2667 DecodePredicateOperand(Inst, Decoder);2668 return S;2669}2670 2671static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,2672 uint64_t Address,2673 const MCDisassembler *Decoder) {2674 DecodeStatus S = MCDisassembler::Success;2675 2676 unsigned Rd = fieldFromInstruction(Insn, 12, 4);2677 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;2678 unsigned Rn = fieldFromInstruction(Insn, 16, 4);2679 unsigned Rm = fieldFromInstruction(Insn, 0, 4);2680 unsigned align = fieldFromInstruction(Insn, 4, 1);2681 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);2682 align *= 2*size;2683 2684 switch (Inst.getOpcode()) {2685 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:2686 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:2687 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:2688 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:2689 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))2690 return MCDisassembler::Fail;2691 break;2692 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:2693 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:2694 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:2695 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:2696 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))2697 return MCDisassembler::Fail;2698 break;2699 default:2700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2701 return MCDisassembler::Fail;2702 break;2703 }2704 2705 if (Rm != 0xF)2706 Inst.addOperand(MCOperand::createImm(0));2707 2708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))2709 return MCDisassembler::Fail;2710 Inst.addOperand(MCOperand::createImm(align));2711 2712 if (Rm != 0xD && Rm != 0xF) {2713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))2714 return MCDisassembler::Fail;2715 }2716 2717 DecodePredicateOperand(Inst, Decoder);2718 return S;2719}2720 2721static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,2722 uint64_t Address,2723 const MCDisassembler *Decoder) {2724 DecodeStatus S = MCDisassembler::Success;2725 2726 unsigned Rd = fieldFromInstruction(Insn, 12, 4);2727 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;2728 unsigned Rn = fieldFromInstruction(Insn, 16, 4);2729 unsigned Rm = fieldFromInstruction(Insn, 0, 4);2730 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;2731 2732 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2733 return MCDisassembler::Fail;2734 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))2735 return MCDisassembler::Fail;2736 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))2737 return MCDisassembler::Fail;2738 if (Rm != 0xF) {2739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))2740 return MCDisassembler::Fail;2741 }2742 2743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))2744 return MCDisassembler::Fail;2745 Inst.addOperand(MCOperand::createImm(0));2746 2747 if (Rm == 0xD)2748 Inst.addOperand(MCOperand::createReg(0));2749 else if (Rm != 0xF) {2750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))2751 return MCDisassembler::Fail;2752 }2753 2754 DecodePredicateOperand(Inst, Decoder);2755 return S;2756}2757 2758static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,2759 uint64_t Address,2760 const MCDisassembler *Decoder) {2761 DecodeStatus S = MCDisassembler::Success;2762 2763 unsigned Rd = fieldFromInstruction(Insn, 12, 4);2764 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;2765 unsigned Rn = fieldFromInstruction(Insn, 16, 4);2766 unsigned Rm = fieldFromInstruction(Insn, 0, 4);2767 unsigned size = fieldFromInstruction(Insn, 6, 2);2768 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;2769 unsigned align = fieldFromInstruction(Insn, 4, 1);2770 2771 if (size == 0x3) {2772 if (align == 0)2773 return MCDisassembler::Fail;2774 align = 16;2775 } else {2776 if (size == 2) {2777 align *= 8;2778 } else {2779 size = 1 << size;2780 align *= 4*size;2781 }2782 }2783 2784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2785 return MCDisassembler::Fail;2786 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))2787 return MCDisassembler::Fail;2788 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))2789 return MCDisassembler::Fail;2790 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))2791 return MCDisassembler::Fail;2792 if (Rm != 0xF) {2793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))2794 return MCDisassembler::Fail;2795 }2796 2797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))2798 return MCDisassembler::Fail;2799 Inst.addOperand(MCOperand::createImm(align));2800 2801 if (Rm == 0xD)2802 Inst.addOperand(MCOperand::createReg(0));2803 else if (Rm != 0xF) {2804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))2805 return MCDisassembler::Fail;2806 }2807 2808 DecodePredicateOperand(Inst, Decoder);2809 return S;2810}2811 2812static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,2813 uint64_t Address,2814 const MCDisassembler *Decoder) {2815 DecodeStatus S = MCDisassembler::Success;2816 2817 unsigned Rd = fieldFromInstruction(Insn, 12, 4);2818 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;2819 unsigned imm = fieldFromInstruction(Insn, 0, 4);2820 imm |= fieldFromInstruction(Insn, 16, 3) << 4;2821 imm |= fieldFromInstruction(Insn, 24, 1) << 7;2822 imm |= fieldFromInstruction(Insn, 8, 4) << 8;2823 imm |= fieldFromInstruction(Insn, 5, 1) << 12;2824 unsigned Q = fieldFromInstruction(Insn, 6, 1);2825 2826 if (Q) {2827 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))2828 return MCDisassembler::Fail;2829 } else {2830 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2831 return MCDisassembler::Fail;2832 }2833 2834 Inst.addOperand(MCOperand::createImm(imm));2835 2836 switch (Inst.getOpcode()) {2837 case ARM::VORRiv4i16:2838 case ARM::VORRiv2i32:2839 case ARM::VBICiv4i16:2840 case ARM::VBICiv2i32:2841 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2842 return MCDisassembler::Fail;2843 break;2844 case ARM::VORRiv8i16:2845 case ARM::VORRiv4i32:2846 case ARM::VBICiv8i16:2847 case ARM::VBICiv4i32:2848 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))2849 return MCDisassembler::Fail;2850 break;2851 default:2852 break;2853 }2854 2855 DecodePredicateOperand(Inst, Decoder);2856 return S;2857}2858 2859static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,2860 uint64_t Address,2861 const MCDisassembler *Decoder) {2862 DecodeStatus S = MCDisassembler::Success;2863 2864 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |2865 fieldFromInstruction(Insn, 13, 3));2866 unsigned cmode = fieldFromInstruction(Insn, 8, 4);2867 unsigned imm = fieldFromInstruction(Insn, 0, 4);2868 imm |= fieldFromInstruction(Insn, 16, 3) << 4;2869 imm |= fieldFromInstruction(Insn, 28, 1) << 7;2870 imm |= cmode << 8;2871 imm |= fieldFromInstruction(Insn, 5, 1) << 12;2872 2873 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)2874 return MCDisassembler::Fail;2875 2876 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))2877 return MCDisassembler::Fail;2878 2879 Inst.addOperand(MCOperand::createImm(imm));2880 2881 Check(S, DecodeVpredROperand(Inst, Decoder));2882 return S;2883}2884 2885static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,2886 uint64_t Address,2887 const MCDisassembler *Decoder) {2888 DecodeStatus S = MCDisassembler::Success;2889 2890 unsigned Qd = fieldFromInstruction(Insn, 13, 3);2891 Qd |= fieldFromInstruction(Insn, 22, 1) << 3;2892 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))2893 return MCDisassembler::Fail;2894 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));2895 2896 unsigned Qn = fieldFromInstruction(Insn, 17, 3);2897 Qn |= fieldFromInstruction(Insn, 7, 1) << 3;2898 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))2899 return MCDisassembler::Fail;2900 unsigned Qm = fieldFromInstruction(Insn, 1, 3);2901 Qm |= fieldFromInstruction(Insn, 5, 1) << 3;2902 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))2903 return MCDisassembler::Fail;2904 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR2905 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));2906 2907 Check(S, DecodeVpredROperand(Inst, Decoder));2908 return S;2909}2910 2911static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,2912 uint64_t Address,2913 const MCDisassembler *Decoder) {2914 DecodeStatus S = MCDisassembler::Success;2915 2916 unsigned Rd = fieldFromInstruction(Insn, 12, 4);2917 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;2918 unsigned Rm = fieldFromInstruction(Insn, 0, 4);2919 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;2920 unsigned size = fieldFromInstruction(Insn, 18, 2);2921 2922 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))2923 return MCDisassembler::Fail;2924 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))2925 return MCDisassembler::Fail;2926 Inst.addOperand(MCOperand::createImm(8 << size));2927 2928 DecodePredicateOperand(Inst, Decoder);2929 return S;2930}2931 2932static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,2933 uint64_t Address,2934 const MCDisassembler *Decoder) {2935 Inst.addOperand(MCOperand::createImm(8 - Val));2936 return MCDisassembler::Success;2937}2938 2939static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,2940 uint64_t Address,2941 const MCDisassembler *Decoder) {2942 Inst.addOperand(MCOperand::createImm(16 - Val));2943 return MCDisassembler::Success;2944}2945 2946static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,2947 uint64_t Address,2948 const MCDisassembler *Decoder) {2949 Inst.addOperand(MCOperand::createImm(32 - Val));2950 return MCDisassembler::Success;2951}2952 2953static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,2954 uint64_t Address,2955 const MCDisassembler *Decoder) {2956 Inst.addOperand(MCOperand::createImm(64 - Val));2957 return MCDisassembler::Success;2958}2959 2960static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,2961 uint64_t Address,2962 const MCDisassembler *Decoder) {2963 DecodeStatus S = MCDisassembler::Success;2964 2965 unsigned Rd = fieldFromInstruction(Insn, 12, 4);2966 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;2967 unsigned Rn = fieldFromInstruction(Insn, 16, 4);2968 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;2969 unsigned Rm = fieldFromInstruction(Insn, 0, 4);2970 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;2971 unsigned op = fieldFromInstruction(Insn, 6, 1);2972 2973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2974 return MCDisassembler::Fail;2975 if (op) {2976 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))2977 return MCDisassembler::Fail; // Writeback2978 }2979 2980 switch (Inst.getOpcode()) {2981 case ARM::VTBL2:2982 case ARM::VTBX2:2983 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))2984 return MCDisassembler::Fail;2985 break;2986 default:2987 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))2988 return MCDisassembler::Fail;2989 }2990 2991 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))2992 return MCDisassembler::Fail;2993 2994 DecodePredicateOperand(Inst, Decoder);2995 return S;2996}2997 2998static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,2999 uint64_t Address,3000 const MCDisassembler *Decoder) {3001 DecodeStatus S = MCDisassembler::Success;3002 3003 unsigned dst = fieldFromInstruction(Insn, 8, 3);3004 unsigned imm = fieldFromInstruction(Insn, 0, 8);3005 3006 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))3007 return MCDisassembler::Fail;3008 3009 switch(Inst.getOpcode()) {3010 default:3011 return MCDisassembler::Fail;3012 case ARM::tADR:3013 break; // tADR does not explicitly represent the PC as an operand.3014 case ARM::tADDrSPi:3015 Inst.addOperand(MCOperand::createReg(ARM::SP));3016 break;3017 }3018 3019 Inst.addOperand(MCOperand::createImm(imm));3020 DecodePredicateOperand(Inst, Decoder);3021 return S;3022}3023 3024static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,3025 uint64_t Address,3026 const MCDisassembler *Decoder) {3027 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,3028 true, 2, Inst, Decoder))3029 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));3030 return MCDisassembler::Success;3031}3032 3033static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,3034 uint64_t Address,3035 const MCDisassembler *Decoder) {3036 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,3037 true, 4, Inst, Decoder))3038 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));3039 return MCDisassembler::Success;3040}3041 3042static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,3043 uint64_t Address,3044 const MCDisassembler *Decoder) {3045 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,3046 true, 2, Inst, Decoder))3047 Inst.addOperand(MCOperand::createImm(Val << 1));3048 return MCDisassembler::Success;3049}3050 3051static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,3052 uint64_t Address,3053 const MCDisassembler *Decoder) {3054 DecodeStatus S = MCDisassembler::Success;3055 3056 unsigned Rn = fieldFromInstruction(Val, 0, 3);3057 unsigned Rm = fieldFromInstruction(Val, 3, 3);3058 3059 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))3060 return MCDisassembler::Fail;3061 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))3062 return MCDisassembler::Fail;3063 3064 return S;3065}3066 3067static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,3068 uint64_t Address,3069 const MCDisassembler *Decoder) {3070 DecodeStatus S = MCDisassembler::Success;3071 3072 unsigned Rn = fieldFromInstruction(Val, 0, 3);3073 unsigned imm = fieldFromInstruction(Val, 3, 5);3074 3075 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))3076 return MCDisassembler::Fail;3077 Inst.addOperand(MCOperand::createImm(imm));3078 3079 return S;3080}3081 3082static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,3083 uint64_t Address,3084 const MCDisassembler *Decoder) {3085 unsigned imm = Val << 2;3086 3087 Inst.addOperand(MCOperand::createImm(imm));3088 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);3089 3090 return MCDisassembler::Success;3091}3092 3093static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,3094 uint64_t Address,3095 const MCDisassembler *Decoder) {3096 Inst.addOperand(MCOperand::createReg(ARM::SP));3097 Inst.addOperand(MCOperand::createImm(Val));3098 3099 return MCDisassembler::Success;3100}3101 3102static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,3103 uint64_t Address,3104 const MCDisassembler *Decoder) {3105 DecodeStatus S = MCDisassembler::Success;3106 3107 unsigned Rn = fieldFromInstruction(Val, 6, 4);3108 unsigned Rm = fieldFromInstruction(Val, 2, 4);3109 unsigned imm = fieldFromInstruction(Val, 0, 2);3110 3111 // Thumb stores cannot use PC as dest register.3112 switch (Inst.getOpcode()) {3113 case ARM::t2STRHs:3114 case ARM::t2STRBs:3115 case ARM::t2STRs:3116 if (Rn == 15)3117 return MCDisassembler::Fail;3118 break;3119 default:3120 break;3121 }3122 3123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))3124 return MCDisassembler::Fail;3125 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))3126 return MCDisassembler::Fail;3127 Inst.addOperand(MCOperand::createImm(imm));3128 3129 return S;3130}3131 3132static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,3133 uint64_t Address,3134 const MCDisassembler *Decoder) {3135 DecodeStatus S = MCDisassembler::Success;3136 3137 unsigned Rt = fieldFromInstruction(Insn, 12, 4);3138 unsigned U = fieldFromInstruction(Insn, 23, 1);3139 int imm = fieldFromInstruction(Insn, 0, 12);3140 3141 const FeatureBitset &featureBits =3142 Decoder->getSubtargetInfo().getFeatureBits();3143 3144 bool hasV7Ops = featureBits[ARM::HasV7Ops];3145 3146 if (Rt == 15) {3147 switch (Inst.getOpcode()) {3148 case ARM::t2LDRBpci:3149 case ARM::t2LDRHpci:3150 Inst.setOpcode(ARM::t2PLDpci);3151 break;3152 case ARM::t2LDRSBpci:3153 Inst.setOpcode(ARM::t2PLIpci);3154 break;3155 case ARM::t2LDRSHpci:3156 return MCDisassembler::Fail;3157 default:3158 break;3159 }3160 }3161 3162 switch(Inst.getOpcode()) {3163 case ARM::t2PLDpci:3164 break;3165 case ARM::t2PLIpci:3166 if (!hasV7Ops)3167 return MCDisassembler::Fail;3168 break;3169 default:3170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))3171 return MCDisassembler::Fail;3172 }3173 3174 if (!U) {3175 // Special case for #-0.3176 if (imm == 0)3177 imm = INT32_MIN;3178 else3179 imm = -imm;3180 }3181 Inst.addOperand(MCOperand::createImm(imm));3182 3183 DecodePredicateOperand(Inst, Decoder);3184 return S;3185}3186 3187static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,3188 uint64_t Address,3189 const MCDisassembler *Decoder) {3190 DecodeStatus S = MCDisassembler::Success;3191 3192 unsigned Rt = fieldFromInstruction(Insn, 12, 4);3193 unsigned Rn = fieldFromInstruction(Insn, 16, 4);3194 3195 const FeatureBitset &featureBits =3196 Decoder->getSubtargetInfo().getFeatureBits();3197 3198 bool hasMP = featureBits[ARM::FeatureMP];3199 bool hasV7Ops = featureBits[ARM::HasV7Ops];3200 3201 if (Rn == 15) {3202 switch (Inst.getOpcode()) {3203 case ARM::t2LDRBs:3204 Inst.setOpcode(ARM::t2LDRBpci);3205 break;3206 case ARM::t2LDRHs:3207 Inst.setOpcode(ARM::t2LDRHpci);3208 break;3209 case ARM::t2LDRSHs:3210 Inst.setOpcode(ARM::t2LDRSHpci);3211 break;3212 case ARM::t2LDRSBs:3213 Inst.setOpcode(ARM::t2LDRSBpci);3214 break;3215 case ARM::t2LDRs:3216 Inst.setOpcode(ARM::t2LDRpci);3217 break;3218 case ARM::t2PLDs:3219 Inst.setOpcode(ARM::t2PLDpci);3220 break;3221 case ARM::t2PLIs:3222 Inst.setOpcode(ARM::t2PLIpci);3223 break;3224 default:3225 return MCDisassembler::Fail;3226 }3227 3228 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);3229 }3230 3231 if (Rt == 15) {3232 switch (Inst.getOpcode()) {3233 case ARM::t2LDRSHs:3234 return MCDisassembler::Fail;3235 case ARM::t2LDRHs:3236 Inst.setOpcode(ARM::t2PLDWs);3237 break;3238 case ARM::t2LDRSBs:3239 Inst.setOpcode(ARM::t2PLIs);3240 break;3241 default:3242 break;3243 }3244 }3245 3246 switch (Inst.getOpcode()) {3247 case ARM::t2PLDs:3248 break;3249 case ARM::t2PLIs:3250 if (!hasV7Ops)3251 return MCDisassembler::Fail;3252 break;3253 case ARM::t2PLDWs:3254 if (!hasV7Ops || !hasMP)3255 return MCDisassembler::Fail;3256 break;3257 default:3258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))3259 return MCDisassembler::Fail;3260 }3261 3262 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);3263 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;3264 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;3265 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))3266 return MCDisassembler::Fail;3267 3268 DecodePredicateOperand(Inst, Decoder);3269 return S;3270}3271 3272static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,3273 const MCDisassembler *Decoder) {3274 int imm = Val & 0xFF;3275 if (Val == 0)3276 imm = INT32_MIN;3277 else if (!(Val & 0x100))3278 imm *= -1;3279 Inst.addOperand(MCOperand::createImm(imm));3280 3281 return MCDisassembler::Success;3282}3283 3284static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,3285 uint64_t Address,3286 const MCDisassembler *Decoder) {3287 DecodeStatus S = MCDisassembler::Success;3288 3289 unsigned Rn = fieldFromInstruction(Val, 9, 4);3290 unsigned imm = fieldFromInstruction(Val, 0, 9);3291 3292 // Thumb stores cannot use PC as dest register.3293 switch (Inst.getOpcode()) {3294 case ARM::t2STRT:3295 case ARM::t2STRBT:3296 case ARM::t2STRHT:3297 case ARM::t2STRi8:3298 case ARM::t2STRHi8:3299 case ARM::t2STRBi8:3300 if (Rn == 15)3301 return MCDisassembler::Fail;3302 break;3303 default:3304 break;3305 }3306 3307 // Some instructions always use an additive offset.3308 switch (Inst.getOpcode()) {3309 case ARM::t2LDRT:3310 case ARM::t2LDRBT:3311 case ARM::t2LDRHT:3312 case ARM::t2LDRSBT:3313 case ARM::t2LDRSHT:3314 case ARM::t2STRT:3315 case ARM::t2STRBT:3316 case ARM::t2STRHT:3317 imm |= 0x100;3318 break;3319 default:3320 break;3321 }3322 3323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))3324 return MCDisassembler::Fail;3325 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))3326 return MCDisassembler::Fail;3327 3328 return S;3329}3330 3331static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,3332 uint64_t Address,3333 const MCDisassembler *Decoder) {3334 DecodeStatus S = MCDisassembler::Success;3335 3336 unsigned Rn = fieldFromInstruction(Insn, 16, 4);3337 unsigned Rt = fieldFromInstruction(Insn, 12, 4);3338 unsigned U = fieldFromInstruction(Insn, 9, 1);3339 unsigned imm = fieldFromInstruction(Insn, 0, 8);3340 imm |= (U << 8);3341 imm |= (Rn << 9);3342 unsigned add = fieldFromInstruction(Insn, 9, 1);3343 3344 const FeatureBitset &featureBits =3345 Decoder->getSubtargetInfo().getFeatureBits();3346 3347 bool hasMP = featureBits[ARM::FeatureMP];3348 bool hasV7Ops = featureBits[ARM::HasV7Ops];3349 3350 if (Rn == 15) {3351 switch (Inst.getOpcode()) {3352 case ARM::t2LDRi8:3353 Inst.setOpcode(ARM::t2LDRpci);3354 break;3355 case ARM::t2LDRBi8:3356 Inst.setOpcode(ARM::t2LDRBpci);3357 break;3358 case ARM::t2LDRSBi8:3359 Inst.setOpcode(ARM::t2LDRSBpci);3360 break;3361 case ARM::t2LDRHi8:3362 Inst.setOpcode(ARM::t2LDRHpci);3363 break;3364 case ARM::t2LDRSHi8:3365 Inst.setOpcode(ARM::t2LDRSHpci);3366 break;3367 case ARM::t2PLDi8:3368 Inst.setOpcode(ARM::t2PLDpci);3369 break;3370 case ARM::t2PLIi8:3371 Inst.setOpcode(ARM::t2PLIpci);3372 break;3373 default:3374 return MCDisassembler::Fail;3375 }3376 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);3377 }3378 3379 if (Rt == 15) {3380 switch (Inst.getOpcode()) {3381 case ARM::t2LDRSHi8:3382 return MCDisassembler::Fail;3383 case ARM::t2LDRHi8:3384 if (!add)3385 Inst.setOpcode(ARM::t2PLDWi8);3386 break;3387 case ARM::t2LDRSBi8:3388 Inst.setOpcode(ARM::t2PLIi8);3389 break;3390 default:3391 break;3392 }3393 }3394 3395 switch (Inst.getOpcode()) {3396 case ARM::t2PLDi8:3397 break;3398 case ARM::t2PLIi8:3399 if (!hasV7Ops)3400 return MCDisassembler::Fail;3401 break;3402 case ARM::t2PLDWi8:3403 if (!hasV7Ops || !hasMP)3404 return MCDisassembler::Fail;3405 break;3406 default:3407 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))3408 return MCDisassembler::Fail;3409 }3410 3411 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))3412 return MCDisassembler::Fail;3413 DecodePredicateOperand(Inst, Decoder);3414 return S;3415}3416 3417static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,3418 uint64_t Address,3419 const MCDisassembler *Decoder) {3420 DecodeStatus S = MCDisassembler::Success;3421 3422 unsigned Rn = fieldFromInstruction(Val, 13, 4);3423 unsigned imm = fieldFromInstruction(Val, 0, 12);3424 3425 // Thumb stores cannot use PC as dest register.3426 switch (Inst.getOpcode()) {3427 case ARM::t2STRi12:3428 case ARM::t2STRBi12:3429 case ARM::t2STRHi12:3430 if (Rn == 15)3431 return MCDisassembler::Fail;3432 break;3433 default:3434 break;3435 }3436 3437 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))3438 return MCDisassembler::Fail;3439 Inst.addOperand(MCOperand::createImm(imm));3440 3441 return S;3442}3443 3444static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,3445 uint64_t Address,3446 const MCDisassembler *Decoder) {3447 DecodeStatus S = MCDisassembler::Success;3448 3449 unsigned Rn = fieldFromInstruction(Insn, 16, 4);3450 unsigned Rt = fieldFromInstruction(Insn, 12, 4);3451 unsigned imm = fieldFromInstruction(Insn, 0, 12);3452 imm |= (Rn << 13);3453 3454 const FeatureBitset &featureBits =3455 Decoder->getSubtargetInfo().getFeatureBits();3456 3457 bool hasMP = featureBits[ARM::FeatureMP];3458 bool hasV7Ops = featureBits[ARM::HasV7Ops];3459 3460 if (Rn == 15) {3461 switch (Inst.getOpcode()) {3462 case ARM::t2LDRi12:3463 Inst.setOpcode(ARM::t2LDRpci);3464 break;3465 case ARM::t2LDRHi12:3466 Inst.setOpcode(ARM::t2LDRHpci);3467 break;3468 case ARM::t2LDRSHi12:3469 Inst.setOpcode(ARM::t2LDRSHpci);3470 break;3471 case ARM::t2LDRBi12:3472 Inst.setOpcode(ARM::t2LDRBpci);3473 break;3474 case ARM::t2LDRSBi12:3475 Inst.setOpcode(ARM::t2LDRSBpci);3476 break;3477 case ARM::t2PLDi12:3478 Inst.setOpcode(ARM::t2PLDpci);3479 break;3480 case ARM::t2PLIi12:3481 Inst.setOpcode(ARM::t2PLIpci);3482 break;3483 default:3484 return MCDisassembler::Fail;3485 }3486 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);3487 }3488 3489 if (Rt == 15) {3490 switch (Inst.getOpcode()) {3491 case ARM::t2LDRSHi12:3492 return MCDisassembler::Fail;3493 case ARM::t2LDRHi12:3494 Inst.setOpcode(ARM::t2PLDWi12);3495 break;3496 case ARM::t2LDRSBi12:3497 Inst.setOpcode(ARM::t2PLIi12);3498 break;3499 default:3500 break;3501 }3502 }3503 3504 switch (Inst.getOpcode()) {3505 case ARM::t2PLDi12:3506 break;3507 case ARM::t2PLIi12:3508 if (!hasV7Ops)3509 return MCDisassembler::Fail;3510 break;3511 case ARM::t2PLDWi12:3512 if (!hasV7Ops || !hasMP)3513 return MCDisassembler::Fail;3514 break;3515 default:3516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))3517 return MCDisassembler::Fail;3518 }3519 3520 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))3521 return MCDisassembler::Fail;3522 DecodePredicateOperand(Inst, Decoder);3523 return S;3524}3525 3526static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,3527 const MCDisassembler *Decoder) {3528 DecodeStatus S = MCDisassembler::Success;3529 3530 unsigned Rn = fieldFromInstruction(Insn, 16, 4);3531 unsigned Rt = fieldFromInstruction(Insn, 12, 4);3532 unsigned imm = fieldFromInstruction(Insn, 0, 8);3533 imm |= (Rn << 9);3534 3535 if (Rn == 15) {3536 switch (Inst.getOpcode()) {3537 case ARM::t2LDRT:3538 Inst.setOpcode(ARM::t2LDRpci);3539 break;3540 case ARM::t2LDRBT:3541 Inst.setOpcode(ARM::t2LDRBpci);3542 break;3543 case ARM::t2LDRHT:3544 Inst.setOpcode(ARM::t2LDRHpci);3545 break;3546 case ARM::t2LDRSBT:3547 Inst.setOpcode(ARM::t2LDRSBpci);3548 break;3549 case ARM::t2LDRSHT:3550 Inst.setOpcode(ARM::t2LDRSHpci);3551 break;3552 default:3553 return MCDisassembler::Fail;3554 }3555 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);3556 }3557 3558 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))3559 return MCDisassembler::Fail;3560 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))3561 return MCDisassembler::Fail;3562 DecodePredicateOperand(Inst, Decoder);3563 return S;3564}3565 3566static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,3567 const MCDisassembler *Decoder) {3568 if (Val == 0)3569 Inst.addOperand(MCOperand::createImm(INT32_MIN));3570 else {3571 int imm = Val & 0xFF;3572 3573 if (!(Val & 0x100)) imm *= -1;3574 Inst.addOperand(MCOperand::createImm(imm * 4));3575 }3576 3577 return MCDisassembler::Success;3578}3579 3580static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,3581 const MCDisassembler *Decoder) {3582 if (Val == 0)3583 Inst.addOperand(MCOperand::createImm(INT32_MIN));3584 else {3585 int imm = Val & 0x7F;3586 3587 if (!(Val & 0x80))3588 imm *= -1;3589 Inst.addOperand(MCOperand::createImm(imm * 4));3590 }3591 3592 return MCDisassembler::Success;3593}3594 3595static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,3596 uint64_t Address,3597 const MCDisassembler *Decoder) {3598 DecodeStatus S = MCDisassembler::Success;3599 3600 unsigned Rn = fieldFromInstruction(Val, 9, 4);3601 unsigned imm = fieldFromInstruction(Val, 0, 9);3602 3603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))3604 return MCDisassembler::Fail;3605 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))3606 return MCDisassembler::Fail;3607 3608 return S;3609}3610 3611static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,3612 uint64_t Address,3613 const MCDisassembler *Decoder) {3614 DecodeStatus S = MCDisassembler::Success;3615 3616 unsigned Rn = fieldFromInstruction(Val, 8, 4);3617 unsigned imm = fieldFromInstruction(Val, 0, 8);3618 3619 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))3620 return MCDisassembler::Fail;3621 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))3622 return MCDisassembler::Fail;3623 3624 return S;3625}3626 3627static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,3628 uint64_t Address,3629 const MCDisassembler *Decoder) {3630 DecodeStatus S = MCDisassembler::Success;3631 3632 unsigned Rn = fieldFromInstruction(Val, 8, 4);3633 unsigned imm = fieldFromInstruction(Val, 0, 8);3634 3635 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))3636 return MCDisassembler::Fail;3637 3638 Inst.addOperand(MCOperand::createImm(imm));3639 3640 return S;3641}3642 3643template <int shift>3644static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,3645 const MCDisassembler *Decoder) {3646 int imm = Val & 0x7F;3647 if (Val == 0)3648 imm = INT32_MIN;3649 else if (!(Val & 0x80))3650 imm *= -1;3651 if (imm != INT32_MIN)3652 imm *= (1U << shift);3653 Inst.addOperand(MCOperand::createImm(imm));3654 3655 return MCDisassembler::Success;3656}3657 3658template <int shift>3659static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,3660 uint64_t Address,3661 const MCDisassembler *Decoder) {3662 DecodeStatus S = MCDisassembler::Success;3663 3664 unsigned Rn = fieldFromInstruction(Val, 8, 3);3665 unsigned imm = fieldFromInstruction(Val, 0, 8);3666 3667 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))3668 return MCDisassembler::Fail;3669 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))3670 return MCDisassembler::Fail;3671 3672 return S;3673}3674 3675template <int shift, int WriteBack>3676static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,3677 uint64_t Address,3678 const MCDisassembler *Decoder) {3679 DecodeStatus S = MCDisassembler::Success;3680 3681 unsigned Rn = fieldFromInstruction(Val, 8, 4);3682 unsigned imm = fieldFromInstruction(Val, 0, 8);3683 if (WriteBack) {3684 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))3685 return MCDisassembler::Fail;3686 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))3687 return MCDisassembler::Fail;3688 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))3689 return MCDisassembler::Fail;3690 3691 return S;3692}3693 3694static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,3695 uint64_t Address,3696 const MCDisassembler *Decoder) {3697 DecodeStatus S = MCDisassembler::Success;3698 3699 unsigned Rt = fieldFromInstruction(Insn, 12, 4);3700 unsigned Rn = fieldFromInstruction(Insn, 16, 4);3701 unsigned addr = fieldFromInstruction(Insn, 0, 8);3702 addr |= fieldFromInstruction(Insn, 9, 1) << 8;3703 addr |= Rn << 9;3704 unsigned load = fieldFromInstruction(Insn, 20, 1);3705 3706 if (Rn == 15) {3707 switch (Inst.getOpcode()) {3708 case ARM::t2LDR_PRE:3709 case ARM::t2LDR_POST:3710 Inst.setOpcode(ARM::t2LDRpci);3711 break;3712 case ARM::t2LDRB_PRE:3713 case ARM::t2LDRB_POST:3714 Inst.setOpcode(ARM::t2LDRBpci);3715 break;3716 case ARM::t2LDRH_PRE:3717 case ARM::t2LDRH_POST:3718 Inst.setOpcode(ARM::t2LDRHpci);3719 break;3720 case ARM::t2LDRSB_PRE:3721 case ARM::t2LDRSB_POST:3722 if (Rt == 15)3723 Inst.setOpcode(ARM::t2PLIpci);3724 else3725 Inst.setOpcode(ARM::t2LDRSBpci);3726 break;3727 case ARM::t2LDRSH_PRE:3728 case ARM::t2LDRSH_POST:3729 Inst.setOpcode(ARM::t2LDRSHpci);3730 break;3731 default:3732 return MCDisassembler::Fail;3733 }3734 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);3735 }3736 3737 if (!load) {3738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))3739 return MCDisassembler::Fail;3740 }3741 3742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))3743 return MCDisassembler::Fail;3744 3745 if (load) {3746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))3747 return MCDisassembler::Fail;3748 }3749 3750 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))3751 return MCDisassembler::Fail;3752 3753 DecodePredicateOperand(Inst, Decoder);3754 return S;3755}3756 3757static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,3758 uint64_t Address,3759 const MCDisassembler *Decoder) {3760 unsigned imm = fieldFromInstruction(Insn, 0, 7);3761 3762 Inst.addOperand(MCOperand::createReg(ARM::SP));3763 Inst.addOperand(MCOperand::createReg(ARM::SP));3764 Inst.addOperand(MCOperand::createImm(imm));3765 3766 DecodePredicateOperand(Inst, Decoder);3767 return MCDisassembler::Success;3768}3769 3770static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,3771 uint64_t Address,3772 const MCDisassembler *Decoder) {3773 DecodeStatus S = MCDisassembler::Success;3774 3775 if (Inst.getOpcode() == ARM::tADDrSP) {3776 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);3777 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;3778 3779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))3780 return MCDisassembler::Fail;3781 Inst.addOperand(MCOperand::createReg(ARM::SP));3782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))3783 return MCDisassembler::Fail;3784 } else if (Inst.getOpcode() == ARM::tADDspr) {3785 unsigned Rm = fieldFromInstruction(Insn, 3, 4);3786 3787 Inst.addOperand(MCOperand::createReg(ARM::SP));3788 Inst.addOperand(MCOperand::createReg(ARM::SP));3789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))3790 return MCDisassembler::Fail;3791 }3792 3793 DecodePredicateOperand(Inst, Decoder);3794 return S;3795}3796 3797static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,3798 uint64_t Address,3799 const MCDisassembler *Decoder) {3800 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;3801 unsigned flags = fieldFromInstruction(Insn, 0, 3);3802 3803 Inst.addOperand(MCOperand::createImm(imod));3804 Inst.addOperand(MCOperand::createImm(flags));3805 3806 return MCDisassembler::Success;3807}3808 3809static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,3810 uint64_t Address,3811 const MCDisassembler *Decoder) {3812 DecodeStatus S = MCDisassembler::Success;3813 unsigned Rm = fieldFromInstruction(Insn, 0, 4);3814 unsigned add = fieldFromInstruction(Insn, 4, 1);3815 3816 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))3817 return MCDisassembler::Fail;3818 Inst.addOperand(MCOperand::createImm(add));3819 3820 return S;3821}3822 3823static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,3824 uint64_t Address,3825 const MCDisassembler *Decoder) {3826 DecodeStatus S = MCDisassembler::Success;3827 unsigned Rn = fieldFromInstruction(Insn, 3, 4);3828 unsigned Qm = fieldFromInstruction(Insn, 0, 3);3829 3830 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))3831 return MCDisassembler::Fail;3832 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))3833 return MCDisassembler::Fail;3834 3835 return S;3836}3837 3838template <int shift>3839static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,3840 uint64_t Address,3841 const MCDisassembler *Decoder) {3842 DecodeStatus S = MCDisassembler::Success;3843 unsigned Qm = fieldFromInstruction(Insn, 8, 3);3844 int imm = fieldFromInstruction(Insn, 0, 7);3845 3846 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))3847 return MCDisassembler::Fail;3848 3849 if(!fieldFromInstruction(Insn, 7, 1)) {3850 if (imm == 0)3851 imm = INT32_MIN; // indicate -03852 else3853 imm *= -1;3854 }3855 if (imm != INT32_MIN)3856 imm *= (1U << shift);3857 Inst.addOperand(MCOperand::createImm(imm));3858 3859 return S;3860}3861 3862static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,3863 uint64_t Address,3864 const MCDisassembler *Decoder) {3865 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'3866 // Note only one trailing zero not two. Also the J1 and J2 values are from3867 // the encoded instruction. So here change to I1 and I2 values via:3868 // I1 = NOT(J1 EOR S);3869 // I2 = NOT(J2 EOR S);3870 // and build the imm32 with two trailing zeros as documented:3871 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);3872 unsigned S = (Val >> 23) & 1;3873 unsigned J1 = (Val >> 22) & 1;3874 unsigned J2 = (Val >> 21) & 1;3875 unsigned I1 = !(J1 ^ S);3876 unsigned I2 = !(J2 ^ S);3877 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);3878 int imm32 = SignExtend32<25>(tmp << 1);3879 3880 if (!tryAddingSymbolicOperand(Address,3881 (Address & ~2u) + imm32 + 4,3882 true, 4, Inst, Decoder))3883 Inst.addOperand(MCOperand::createImm(imm32));3884 return MCDisassembler::Success;3885}3886 3887static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,3888 uint64_t Address,3889 const MCDisassembler *Decoder) {3890 if (Val == 0xA || Val == 0xB)3891 return MCDisassembler::Fail;3892 3893 const FeatureBitset &featureBits =3894 Decoder->getSubtargetInfo().getFeatureBits();3895 3896 if (!isValidCoprocessorNumber(Val, featureBits))3897 return MCDisassembler::Fail;3898 3899 Inst.addOperand(MCOperand::createImm(Val));3900 return MCDisassembler::Success;3901}3902 3903static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,3904 uint64_t Address,3905 const MCDisassembler *Decoder) {3906 const FeatureBitset &FeatureBits =3907 Decoder->getSubtargetInfo().getFeatureBits();3908 DecodeStatus S = MCDisassembler::Success;3909 3910 unsigned Rn = fieldFromInstruction(Insn, 16, 4);3911 unsigned Rm = fieldFromInstruction(Insn, 0, 4);3912 3913 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;3914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))3915 return MCDisassembler::Fail;3916 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))3917 return MCDisassembler::Fail;3918 DecodePredicateOperand(Inst, Decoder);3919 return S;3920}3921 3922static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,3923 uint64_t Address,3924 const MCDisassembler *Decoder) {3925 if (Val & ~0xf)3926 return MCDisassembler::Fail;3927 3928 Inst.addOperand(MCOperand::createImm(Val));3929 return MCDisassembler::Success;3930}3931 3932static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,3933 uint64_t Address,3934 const MCDisassembler *Decoder) {3935 DecodeStatus S = MCDisassembler::Success;3936 3937 unsigned pred = fieldFromInstruction(Insn, 22, 4);3938 if (pred == 0xE || pred == 0xF) {3939 unsigned opc = fieldFromInstruction(Insn, 4, 28);3940 switch (opc) {3941 default:3942 return MCDisassembler::Fail;3943 case 0xf3bf8f4:3944 Inst.setOpcode(ARM::t2DSB);3945 break;3946 case 0xf3bf8f5:3947 Inst.setOpcode(ARM::t2DMB);3948 break;3949 case 0xf3bf8f6:3950 Inst.setOpcode(ARM::t2ISB);3951 break;3952 }3953 3954 unsigned imm = fieldFromInstruction(Insn, 0, 4);3955 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);3956 }3957 3958 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;3959 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;3960 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;3961 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;3962 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;3963 3964 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))3965 return MCDisassembler::Fail;3966 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))3967 return MCDisassembler::Fail;3968 3969 return S;3970}3971 3972// Decode a shifted immediate operand. These basically consist3973// of an 8-bit value, and a 4-bit directive that specifies either3974// a splat operation or a rotation.3975static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,3976 const MCDisassembler *Decoder) {3977 unsigned ctrl = fieldFromInstruction(Val, 10, 2);3978 if (ctrl == 0) {3979 unsigned byte = fieldFromInstruction(Val, 8, 2);3980 unsigned imm = fieldFromInstruction(Val, 0, 8);3981 switch (byte) {3982 case 0:3983 Inst.addOperand(MCOperand::createImm(imm));3984 break;3985 case 1:3986 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));3987 break;3988 case 2:3989 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));3990 break;3991 case 3:3992 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |3993 (imm << 8) | imm));3994 break;3995 }3996 } else {3997 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;3998 unsigned rot = fieldFromInstruction(Val, 7, 5);3999 unsigned imm = llvm::rotr<uint32_t>(unrot, rot);4000 Inst.addOperand(MCOperand::createImm(imm));4001 }4002 4003 return MCDisassembler::Success;4004}4005 4006static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,4007 uint64_t Address,4008 const MCDisassembler *Decoder) {4009 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,4010 true, 2, Inst, Decoder))4011 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));4012 return MCDisassembler::Success;4013}4014 4015static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,4016 uint64_t Address,4017 const MCDisassembler *Decoder) {4018 // Val is passed in as S:J1:J2:imm10:imm114019 // Note no trailing zero after imm11. Also the J1 and J2 values are from4020 // the encoded instruction. So here change to I1 and I2 values via:4021 // I1 = NOT(J1 EOR S);4022 // I2 = NOT(J2 EOR S);4023 // and build the imm32 with one trailing zero as documented:4024 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);4025 unsigned S = (Val >> 23) & 1;4026 unsigned J1 = (Val >> 22) & 1;4027 unsigned J2 = (Val >> 21) & 1;4028 unsigned I1 = !(J1 ^ S);4029 unsigned I2 = !(J2 ^ S);4030 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);4031 int imm32 = SignExtend32<25>(tmp << 1);4032 4033 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,4034 true, 4, Inst, Decoder))4035 Inst.addOperand(MCOperand::createImm(imm32));4036 return MCDisassembler::Success;4037}4038 4039static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,4040 uint64_t Address,4041 const MCDisassembler *Decoder) {4042 if (Val & ~0xf)4043 return MCDisassembler::Fail;4044 4045 Inst.addOperand(MCOperand::createImm(Val));4046 return MCDisassembler::Success;4047}4048 4049static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,4050 const MCDisassembler *Decoder) {4051 DecodeStatus S = MCDisassembler::Success;4052 const FeatureBitset &FeatureBits =4053 Decoder->getSubtargetInfo().getFeatureBits();4054 4055 if (FeatureBits[ARM::FeatureMClass]) {4056 unsigned ValLow = Val & 0xff;4057 4058 // Validate the SYSm value first.4059 switch (ValLow) {4060 case 0: // apsr4061 case 1: // iapsr4062 case 2: // eapsr4063 case 3: // xpsr4064 case 5: // ipsr4065 case 6: // epsr4066 case 7: // iepsr4067 case 8: // msp4068 case 9: // psp4069 case 16: // primask4070 case 20: // control4071 break;4072 case 17: // basepri4073 case 18: // basepri_max4074 case 19: // faultmask4075 if (!(FeatureBits[ARM::HasV7Ops]))4076 // Values basepri, basepri_max and faultmask are only valid for v7m.4077 return MCDisassembler::Fail;4078 break;4079 case 0x8a: // msplim_ns4080 case 0x8b: // psplim_ns4081 case 0x91: // basepri_ns4082 case 0x93: // faultmask_ns4083 if (!(FeatureBits[ARM::HasV8MMainlineOps]))4084 return MCDisassembler::Fail;4085 [[fallthrough]];4086 case 10: // msplim4087 case 11: // psplim4088 case 0x88: // msp_ns4089 case 0x89: // psp_ns4090 case 0x90: // primask_ns4091 case 0x94: // control_ns4092 case 0x98: // sp_ns4093 if (!(FeatureBits[ARM::Feature8MSecExt]))4094 return MCDisassembler::Fail;4095 break;4096 case 0x20: // pac_key_p_04097 case 0x21: // pac_key_p_14098 case 0x22: // pac_key_p_24099 case 0x23: // pac_key_p_34100 case 0x24: // pac_key_u_04101 case 0x25: // pac_key_u_14102 case 0x26: // pac_key_u_24103 case 0x27: // pac_key_u_34104 case 0xa0: // pac_key_p_0_ns4105 case 0xa1: // pac_key_p_1_ns4106 case 0xa2: // pac_key_p_2_ns4107 case 0xa3: // pac_key_p_3_ns4108 case 0xa4: // pac_key_u_0_ns4109 case 0xa5: // pac_key_u_1_ns4110 case 0xa6: // pac_key_u_2_ns4111 case 0xa7: // pac_key_u_3_ns4112 if (!(FeatureBits[ARM::FeaturePACBTI]))4113 return MCDisassembler::Fail;4114 break;4115 default:4116 // Architecturally defined as unpredictable4117 S = MCDisassembler::SoftFail;4118 break;4119 }4120 4121 if (Inst.getOpcode() == ARM::t2MSR_M) {4122 unsigned Mask = fieldFromInstruction(Val, 10, 2);4123 if (!(FeatureBits[ARM::HasV7Ops])) {4124 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are4125 // unpredictable.4126 if (Mask != 2)4127 S = MCDisassembler::SoftFail;4128 }4129 else {4130 // The ARMv7-M architecture stores an additional 2-bit mask value in4131 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and4132 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if4133 // the NZCVQ bits should be moved by the instruction. Bit mask{0}4134 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set4135 // only if the processor includes the DSP extension.4136 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||4137 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))4138 S = MCDisassembler::SoftFail;4139 }4140 }4141 } else {4142 // A/R class4143 if (Val == 0)4144 return MCDisassembler::Fail;4145 }4146 Inst.addOperand(MCOperand::createImm(Val));4147 return S;4148}4149 4150static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,4151 uint64_t Address,4152 const MCDisassembler *Decoder) {4153 unsigned R = fieldFromInstruction(Val, 5, 1);4154 unsigned SysM = fieldFromInstruction(Val, 0, 5);4155 4156 // The table of encodings for these banked registers comes from B9.2.3 of the4157 // ARM ARM. There are patterns, but nothing regular enough to make this logic4158 // neater. So by fiat, these values are UNPREDICTABLE:4159 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))4160 return MCDisassembler::Fail;4161 4162 Inst.addOperand(MCOperand::createImm(Val));4163 return MCDisassembler::Success;4164}4165 4166static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,4167 uint64_t Address,4168 const MCDisassembler *Decoder) {4169 DecodeStatus S = MCDisassembler::Success;4170 4171 unsigned Rt = fieldFromInstruction(Insn, 12, 4);4172 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4173 unsigned pred = fieldFromInstruction(Insn, 28, 4);4174 4175 if (Rn == 0xF)4176 S = MCDisassembler::SoftFail;4177 4178 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))4179 return MCDisassembler::Fail;4180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4181 return MCDisassembler::Fail;4182 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))4183 return MCDisassembler::Fail;4184 4185 return S;4186}4187 4188static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,4189 uint64_t Address,4190 const MCDisassembler *Decoder) {4191 DecodeStatus S = MCDisassembler::Success;4192 4193 unsigned Rd = fieldFromInstruction(Insn, 12, 4);4194 unsigned Rt = fieldFromInstruction(Insn, 0, 4);4195 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4196 unsigned pred = fieldFromInstruction(Insn, 28, 4);4197 4198 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))4199 return MCDisassembler::Fail;4200 4201 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)4202 S = MCDisassembler::SoftFail;4203 4204 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))4205 return MCDisassembler::Fail;4206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4207 return MCDisassembler::Fail;4208 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))4209 return MCDisassembler::Fail;4210 4211 return S;4212}4213 4214static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,4215 uint64_t Address,4216 const MCDisassembler *Decoder) {4217 DecodeStatus S = MCDisassembler::Success;4218 4219 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4220 unsigned Rt = fieldFromInstruction(Insn, 12, 4);4221 unsigned imm = fieldFromInstruction(Insn, 0, 12);4222 imm |= fieldFromInstruction(Insn, 16, 4) << 13;4223 imm |= fieldFromInstruction(Insn, 23, 1) << 12;4224 unsigned pred = fieldFromInstruction(Insn, 28, 4);4225 4226 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;4227 4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))4229 return MCDisassembler::Fail;4230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4231 return MCDisassembler::Fail;4232 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))4233 return MCDisassembler::Fail;4234 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))4235 return MCDisassembler::Fail;4236 4237 return S;4238}4239 4240static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,4241 uint64_t Address,4242 const MCDisassembler *Decoder) {4243 DecodeStatus S = MCDisassembler::Success;4244 4245 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4246 unsigned Rt = fieldFromInstruction(Insn, 12, 4);4247 unsigned imm = fieldFromInstruction(Insn, 0, 12);4248 imm |= fieldFromInstruction(Insn, 16, 4) << 13;4249 imm |= fieldFromInstruction(Insn, 23, 1) << 12;4250 unsigned pred = fieldFromInstruction(Insn, 28, 4);4251 unsigned Rm = fieldFromInstruction(Insn, 0, 4);4252 4253 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;4254 if (Rm == 0xF) S = MCDisassembler::SoftFail;4255 4256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))4257 return MCDisassembler::Fail;4258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4259 return MCDisassembler::Fail;4260 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))4261 return MCDisassembler::Fail;4262 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))4263 return MCDisassembler::Fail;4264 4265 return S;4266}4267 4268static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,4269 uint64_t Address,4270 const MCDisassembler *Decoder) {4271 DecodeStatus S = MCDisassembler::Success;4272 4273 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4274 unsigned Rt = fieldFromInstruction(Insn, 12, 4);4275 unsigned imm = fieldFromInstruction(Insn, 0, 12);4276 imm |= fieldFromInstruction(Insn, 16, 4) << 13;4277 imm |= fieldFromInstruction(Insn, 23, 1) << 12;4278 unsigned pred = fieldFromInstruction(Insn, 28, 4);4279 4280 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;4281 4282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4283 return MCDisassembler::Fail;4284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))4285 return MCDisassembler::Fail;4286 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))4287 return MCDisassembler::Fail;4288 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))4289 return MCDisassembler::Fail;4290 4291 return S;4292}4293 4294static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,4295 uint64_t Address,4296 const MCDisassembler *Decoder) {4297 DecodeStatus S = MCDisassembler::Success;4298 4299 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4300 unsigned Rt = fieldFromInstruction(Insn, 12, 4);4301 unsigned imm = fieldFromInstruction(Insn, 0, 12);4302 imm |= fieldFromInstruction(Insn, 16, 4) << 13;4303 imm |= fieldFromInstruction(Insn, 23, 1) << 12;4304 unsigned pred = fieldFromInstruction(Insn, 28, 4);4305 4306 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;4307 4308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4309 return MCDisassembler::Fail;4310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))4311 return MCDisassembler::Fail;4312 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))4313 return MCDisassembler::Fail;4314 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))4315 return MCDisassembler::Fail;4316 4317 return S;4318}4319 4320static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,4321 const MCDisassembler *Decoder) {4322 DecodeStatus S = MCDisassembler::Success;4323 4324 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4325 unsigned Rm = fieldFromInstruction(Insn, 0, 4);4326 unsigned Rd = fieldFromInstruction(Insn, 12, 4);4327 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;4328 unsigned size = fieldFromInstruction(Insn, 10, 2);4329 4330 unsigned align = 0;4331 unsigned index = 0;4332 switch (size) {4333 default:4334 return MCDisassembler::Fail;4335 case 0:4336 if (fieldFromInstruction(Insn, 4, 1))4337 return MCDisassembler::Fail; // UNDEFINED4338 index = fieldFromInstruction(Insn, 5, 3);4339 break;4340 case 1:4341 if (fieldFromInstruction(Insn, 5, 1))4342 return MCDisassembler::Fail; // UNDEFINED4343 index = fieldFromInstruction(Insn, 6, 2);4344 if (fieldFromInstruction(Insn, 4, 1))4345 align = 2;4346 break;4347 case 2:4348 if (fieldFromInstruction(Insn, 6, 1))4349 return MCDisassembler::Fail; // UNDEFINED4350 index = fieldFromInstruction(Insn, 7, 1);4351 4352 switch (fieldFromInstruction(Insn, 4, 2)) {4353 case 0 :4354 align = 0; break;4355 case 3:4356 align = 4; break;4357 default:4358 return MCDisassembler::Fail;4359 }4360 break;4361 }4362 4363 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4364 return MCDisassembler::Fail;4365 if (Rm != 0xF) { // Writeback4366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4367 return MCDisassembler::Fail;4368 }4369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4370 return MCDisassembler::Fail;4371 Inst.addOperand(MCOperand::createImm(align));4372 if (Rm != 0xF) {4373 if (Rm != 0xD) {4374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))4375 return MCDisassembler::Fail;4376 } else4377 Inst.addOperand(MCOperand::createReg(0));4378 }4379 4380 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4381 return MCDisassembler::Fail;4382 Inst.addOperand(MCOperand::createImm(index));4383 4384 DecodePredicateOperand(Inst, Decoder);4385 return S;4386}4387 4388static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,4389 const MCDisassembler *Decoder) {4390 DecodeStatus S = MCDisassembler::Success;4391 4392 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4393 unsigned Rm = fieldFromInstruction(Insn, 0, 4);4394 unsigned Rd = fieldFromInstruction(Insn, 12, 4);4395 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;4396 unsigned size = fieldFromInstruction(Insn, 10, 2);4397 4398 unsigned align = 0;4399 unsigned index = 0;4400 switch (size) {4401 default:4402 return MCDisassembler::Fail;4403 case 0:4404 if (fieldFromInstruction(Insn, 4, 1))4405 return MCDisassembler::Fail; // UNDEFINED4406 index = fieldFromInstruction(Insn, 5, 3);4407 break;4408 case 1:4409 if (fieldFromInstruction(Insn, 5, 1))4410 return MCDisassembler::Fail; // UNDEFINED4411 index = fieldFromInstruction(Insn, 6, 2);4412 if (fieldFromInstruction(Insn, 4, 1))4413 align = 2;4414 break;4415 case 2:4416 if (fieldFromInstruction(Insn, 6, 1))4417 return MCDisassembler::Fail; // UNDEFINED4418 index = fieldFromInstruction(Insn, 7, 1);4419 4420 switch (fieldFromInstruction(Insn, 4, 2)) {4421 case 0:4422 align = 0; break;4423 case 3:4424 align = 4; break;4425 default:4426 return MCDisassembler::Fail;4427 }4428 break;4429 }4430 4431 if (Rm != 0xF) { // Writeback4432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4433 return MCDisassembler::Fail;4434 }4435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4436 return MCDisassembler::Fail;4437 Inst.addOperand(MCOperand::createImm(align));4438 if (Rm != 0xF) {4439 if (Rm != 0xD) {4440 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))4441 return MCDisassembler::Fail;4442 } else4443 Inst.addOperand(MCOperand::createReg(0));4444 }4445 4446 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4447 return MCDisassembler::Fail;4448 Inst.addOperand(MCOperand::createImm(index));4449 4450 DecodePredicateOperand(Inst, Decoder);4451 return S;4452}4453 4454static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,4455 const MCDisassembler *Decoder) {4456 DecodeStatus S = MCDisassembler::Success;4457 4458 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4459 unsigned Rm = fieldFromInstruction(Insn, 0, 4);4460 unsigned Rd = fieldFromInstruction(Insn, 12, 4);4461 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;4462 unsigned size = fieldFromInstruction(Insn, 10, 2);4463 4464 unsigned align = 0;4465 unsigned index = 0;4466 unsigned inc = 1;4467 switch (size) {4468 default:4469 return MCDisassembler::Fail;4470 case 0:4471 index = fieldFromInstruction(Insn, 5, 3);4472 if (fieldFromInstruction(Insn, 4, 1))4473 align = 2;4474 break;4475 case 1:4476 index = fieldFromInstruction(Insn, 6, 2);4477 if (fieldFromInstruction(Insn, 4, 1))4478 align = 4;4479 if (fieldFromInstruction(Insn, 5, 1))4480 inc = 2;4481 break;4482 case 2:4483 if (fieldFromInstruction(Insn, 5, 1))4484 return MCDisassembler::Fail; // UNDEFINED4485 index = fieldFromInstruction(Insn, 7, 1);4486 if (fieldFromInstruction(Insn, 4, 1) != 0)4487 align = 8;4488 if (fieldFromInstruction(Insn, 6, 1))4489 inc = 2;4490 break;4491 }4492 4493 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4494 return MCDisassembler::Fail;4495 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))4496 return MCDisassembler::Fail;4497 if (Rm != 0xF) { // Writeback4498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4499 return MCDisassembler::Fail;4500 }4501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4502 return MCDisassembler::Fail;4503 Inst.addOperand(MCOperand::createImm(align));4504 if (Rm != 0xF) {4505 if (Rm != 0xD) {4506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))4507 return MCDisassembler::Fail;4508 } else4509 Inst.addOperand(MCOperand::createReg(0));4510 }4511 4512 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4513 return MCDisassembler::Fail;4514 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))4515 return MCDisassembler::Fail;4516 Inst.addOperand(MCOperand::createImm(index));4517 4518 DecodePredicateOperand(Inst, Decoder);4519 return S;4520}4521 4522static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,4523 const MCDisassembler *Decoder) {4524 DecodeStatus S = MCDisassembler::Success;4525 4526 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4527 unsigned Rm = fieldFromInstruction(Insn, 0, 4);4528 unsigned Rd = fieldFromInstruction(Insn, 12, 4);4529 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;4530 unsigned size = fieldFromInstruction(Insn, 10, 2);4531 4532 unsigned align = 0;4533 unsigned index = 0;4534 unsigned inc = 1;4535 switch (size) {4536 default:4537 return MCDisassembler::Fail;4538 case 0:4539 index = fieldFromInstruction(Insn, 5, 3);4540 if (fieldFromInstruction(Insn, 4, 1))4541 align = 2;4542 break;4543 case 1:4544 index = fieldFromInstruction(Insn, 6, 2);4545 if (fieldFromInstruction(Insn, 4, 1))4546 align = 4;4547 if (fieldFromInstruction(Insn, 5, 1))4548 inc = 2;4549 break;4550 case 2:4551 if (fieldFromInstruction(Insn, 5, 1))4552 return MCDisassembler::Fail; // UNDEFINED4553 index = fieldFromInstruction(Insn, 7, 1);4554 if (fieldFromInstruction(Insn, 4, 1) != 0)4555 align = 8;4556 if (fieldFromInstruction(Insn, 6, 1))4557 inc = 2;4558 break;4559 }4560 4561 if (Rm != 0xF) { // Writeback4562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4563 return MCDisassembler::Fail;4564 }4565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4566 return MCDisassembler::Fail;4567 Inst.addOperand(MCOperand::createImm(align));4568 if (Rm != 0xF) {4569 if (Rm != 0xD) {4570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))4571 return MCDisassembler::Fail;4572 } else4573 Inst.addOperand(MCOperand::createReg(0));4574 }4575 4576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4577 return MCDisassembler::Fail;4578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))4579 return MCDisassembler::Fail;4580 Inst.addOperand(MCOperand::createImm(index));4581 4582 DecodePredicateOperand(Inst, Decoder);4583 return S;4584}4585 4586static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,4587 const MCDisassembler *Decoder) {4588 DecodeStatus S = MCDisassembler::Success;4589 4590 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4591 unsigned Rm = fieldFromInstruction(Insn, 0, 4);4592 unsigned Rd = fieldFromInstruction(Insn, 12, 4);4593 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;4594 unsigned size = fieldFromInstruction(Insn, 10, 2);4595 4596 unsigned align = 0;4597 unsigned index = 0;4598 unsigned inc = 1;4599 switch (size) {4600 default:4601 return MCDisassembler::Fail;4602 case 0:4603 if (fieldFromInstruction(Insn, 4, 1))4604 return MCDisassembler::Fail; // UNDEFINED4605 index = fieldFromInstruction(Insn, 5, 3);4606 break;4607 case 1:4608 if (fieldFromInstruction(Insn, 4, 1))4609 return MCDisassembler::Fail; // UNDEFINED4610 index = fieldFromInstruction(Insn, 6, 2);4611 if (fieldFromInstruction(Insn, 5, 1))4612 inc = 2;4613 break;4614 case 2:4615 if (fieldFromInstruction(Insn, 4, 2))4616 return MCDisassembler::Fail; // UNDEFINED4617 index = fieldFromInstruction(Insn, 7, 1);4618 if (fieldFromInstruction(Insn, 6, 1))4619 inc = 2;4620 break;4621 }4622 4623 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4624 return MCDisassembler::Fail;4625 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))4626 return MCDisassembler::Fail;4627 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))4628 return MCDisassembler::Fail;4629 4630 if (Rm != 0xF) { // Writeback4631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4632 return MCDisassembler::Fail;4633 }4634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4635 return MCDisassembler::Fail;4636 Inst.addOperand(MCOperand::createImm(align));4637 if (Rm != 0xF) {4638 if (Rm != 0xD) {4639 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))4640 return MCDisassembler::Fail;4641 } else4642 Inst.addOperand(MCOperand::createReg(0));4643 }4644 4645 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4646 return MCDisassembler::Fail;4647 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))4648 return MCDisassembler::Fail;4649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))4650 return MCDisassembler::Fail;4651 Inst.addOperand(MCOperand::createImm(index));4652 4653 DecodePredicateOperand(Inst, Decoder);4654 return S;4655}4656 4657static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,4658 const MCDisassembler *Decoder) {4659 DecodeStatus S = MCDisassembler::Success;4660 4661 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4662 unsigned Rm = fieldFromInstruction(Insn, 0, 4);4663 unsigned Rd = fieldFromInstruction(Insn, 12, 4);4664 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;4665 unsigned size = fieldFromInstruction(Insn, 10, 2);4666 4667 unsigned align = 0;4668 unsigned index = 0;4669 unsigned inc = 1;4670 switch (size) {4671 default:4672 return MCDisassembler::Fail;4673 case 0:4674 if (fieldFromInstruction(Insn, 4, 1))4675 return MCDisassembler::Fail; // UNDEFINED4676 index = fieldFromInstruction(Insn, 5, 3);4677 break;4678 case 1:4679 if (fieldFromInstruction(Insn, 4, 1))4680 return MCDisassembler::Fail; // UNDEFINED4681 index = fieldFromInstruction(Insn, 6, 2);4682 if (fieldFromInstruction(Insn, 5, 1))4683 inc = 2;4684 break;4685 case 2:4686 if (fieldFromInstruction(Insn, 4, 2))4687 return MCDisassembler::Fail; // UNDEFINED4688 index = fieldFromInstruction(Insn, 7, 1);4689 if (fieldFromInstruction(Insn, 6, 1))4690 inc = 2;4691 break;4692 }4693 4694 if (Rm != 0xF) { // Writeback4695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4696 return MCDisassembler::Fail;4697 }4698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4699 return MCDisassembler::Fail;4700 Inst.addOperand(MCOperand::createImm(align));4701 if (Rm != 0xF) {4702 if (Rm != 0xD) {4703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))4704 return MCDisassembler::Fail;4705 } else4706 Inst.addOperand(MCOperand::createReg(0));4707 }4708 4709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4710 return MCDisassembler::Fail;4711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))4712 return MCDisassembler::Fail;4713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))4714 return MCDisassembler::Fail;4715 Inst.addOperand(MCOperand::createImm(index));4716 4717 DecodePredicateOperand(Inst, Decoder);4718 return S;4719}4720 4721static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,4722 const MCDisassembler *Decoder) {4723 DecodeStatus S = MCDisassembler::Success;4724 4725 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4726 unsigned Rm = fieldFromInstruction(Insn, 0, 4);4727 unsigned Rd = fieldFromInstruction(Insn, 12, 4);4728 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;4729 unsigned size = fieldFromInstruction(Insn, 10, 2);4730 4731 unsigned align = 0;4732 unsigned index = 0;4733 unsigned inc = 1;4734 switch (size) {4735 default:4736 return MCDisassembler::Fail;4737 case 0:4738 if (fieldFromInstruction(Insn, 4, 1))4739 align = 4;4740 index = fieldFromInstruction(Insn, 5, 3);4741 break;4742 case 1:4743 if (fieldFromInstruction(Insn, 4, 1))4744 align = 8;4745 index = fieldFromInstruction(Insn, 6, 2);4746 if (fieldFromInstruction(Insn, 5, 1))4747 inc = 2;4748 break;4749 case 2:4750 switch (fieldFromInstruction(Insn, 4, 2)) {4751 case 0:4752 align = 0; break;4753 case 3:4754 return MCDisassembler::Fail;4755 default:4756 align = 4 << fieldFromInstruction(Insn, 4, 2); break;4757 }4758 4759 index = fieldFromInstruction(Insn, 7, 1);4760 if (fieldFromInstruction(Insn, 6, 1))4761 inc = 2;4762 break;4763 }4764 4765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4766 return MCDisassembler::Fail;4767 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))4768 return MCDisassembler::Fail;4769 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))4770 return MCDisassembler::Fail;4771 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))4772 return MCDisassembler::Fail;4773 4774 if (Rm != 0xF) { // Writeback4775 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4776 return MCDisassembler::Fail;4777 }4778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4779 return MCDisassembler::Fail;4780 Inst.addOperand(MCOperand::createImm(align));4781 if (Rm != 0xF) {4782 if (Rm != 0xD) {4783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))4784 return MCDisassembler::Fail;4785 } else4786 Inst.addOperand(MCOperand::createReg(0));4787 }4788 4789 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4790 return MCDisassembler::Fail;4791 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))4792 return MCDisassembler::Fail;4793 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))4794 return MCDisassembler::Fail;4795 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))4796 return MCDisassembler::Fail;4797 Inst.addOperand(MCOperand::createImm(index));4798 4799 DecodePredicateOperand(Inst, Decoder);4800 return S;4801}4802 4803static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,4804 const MCDisassembler *Decoder) {4805 DecodeStatus S = MCDisassembler::Success;4806 4807 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4808 unsigned Rm = fieldFromInstruction(Insn, 0, 4);4809 unsigned Rd = fieldFromInstruction(Insn, 12, 4);4810 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;4811 unsigned size = fieldFromInstruction(Insn, 10, 2);4812 4813 unsigned align = 0;4814 unsigned index = 0;4815 unsigned inc = 1;4816 switch (size) {4817 default:4818 return MCDisassembler::Fail;4819 case 0:4820 if (fieldFromInstruction(Insn, 4, 1))4821 align = 4;4822 index = fieldFromInstruction(Insn, 5, 3);4823 break;4824 case 1:4825 if (fieldFromInstruction(Insn, 4, 1))4826 align = 8;4827 index = fieldFromInstruction(Insn, 6, 2);4828 if (fieldFromInstruction(Insn, 5, 1))4829 inc = 2;4830 break;4831 case 2:4832 switch (fieldFromInstruction(Insn, 4, 2)) {4833 case 0:4834 align = 0; break;4835 case 3:4836 return MCDisassembler::Fail;4837 default:4838 align = 4 << fieldFromInstruction(Insn, 4, 2); break;4839 }4840 4841 index = fieldFromInstruction(Insn, 7, 1);4842 if (fieldFromInstruction(Insn, 6, 1))4843 inc = 2;4844 break;4845 }4846 4847 if (Rm != 0xF) { // Writeback4848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4849 return MCDisassembler::Fail;4850 }4851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))4852 return MCDisassembler::Fail;4853 Inst.addOperand(MCOperand::createImm(align));4854 if (Rm != 0xF) {4855 if (Rm != 0xD) {4856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))4857 return MCDisassembler::Fail;4858 } else4859 Inst.addOperand(MCOperand::createReg(0));4860 }4861 4862 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))4863 return MCDisassembler::Fail;4864 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))4865 return MCDisassembler::Fail;4866 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))4867 return MCDisassembler::Fail;4868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))4869 return MCDisassembler::Fail;4870 Inst.addOperand(MCOperand::createImm(index));4871 4872 DecodePredicateOperand(Inst, Decoder);4873 return S;4874}4875 4876static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,4877 const MCDisassembler *Decoder) {4878 DecodeStatus S = MCDisassembler::Success;4879 unsigned Rt = fieldFromInstruction(Insn, 12, 4);4880 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);4881 unsigned Rm = fieldFromInstruction(Insn, 5, 1);4882 unsigned pred = fieldFromInstruction(Insn, 28, 4);4883 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;4884 4885 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)4886 S = MCDisassembler::SoftFail;4887 4888 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))4889 return MCDisassembler::Fail;4890 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))4891 return MCDisassembler::Fail;4892 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))4893 return MCDisassembler::Fail;4894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))4895 return MCDisassembler::Fail;4896 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))4897 return MCDisassembler::Fail;4898 4899 return S;4900}4901 4902static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,4903 const MCDisassembler *Decoder) {4904 DecodeStatus S = MCDisassembler::Success;4905 unsigned Rt = fieldFromInstruction(Insn, 12, 4);4906 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);4907 unsigned Rm = fieldFromInstruction(Insn, 5, 1);4908 unsigned pred = fieldFromInstruction(Insn, 28, 4);4909 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;4910 4911 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)4912 S = MCDisassembler::SoftFail;4913 4914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))4915 return MCDisassembler::Fail;4916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))4917 return MCDisassembler::Fail;4918 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))4919 return MCDisassembler::Fail;4920 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))4921 return MCDisassembler::Fail;4922 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))4923 return MCDisassembler::Fail;4924 4925 return S;4926}4927 4928static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address,4929 const MCDisassembler *Decoder) {4930 DecodeStatus S = MCDisassembler::Success;4931 unsigned pred = fieldFromInstruction(Insn, 4, 4);4932 unsigned mask = fieldFromInstruction(Insn, 0, 4);4933 4934 if (pred == 0xF) {4935 pred = 0xE;4936 S = MCDisassembler::SoftFail;4937 }4938 4939 if (mask == 0x0)4940 return MCDisassembler::Fail;4941 4942 // IT masks are encoded as a sequence of replacement low-order bits4943 // for the condition code. So if the low bit of the starting4944 // condition code is 1, then we have to flip all the bits above the4945 // terminating bit (which is the lowest 1 bit).4946 if (pred & 1) {4947 unsigned LowBit = mask & -mask;4948 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);4949 mask ^= BitsAboveLowBit;4950 }4951 4952 Inst.addOperand(MCOperand::createImm(pred));4953 Inst.addOperand(MCOperand::createImm(mask));4954 return S;4955}4956 4957static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,4958 uint64_t Address,4959 const MCDisassembler *Decoder) {4960 DecodeStatus S = MCDisassembler::Success;4961 4962 unsigned Rt = fieldFromInstruction(Insn, 12, 4);4963 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);4964 unsigned Rn = fieldFromInstruction(Insn, 16, 4);4965 unsigned addr = fieldFromInstruction(Insn, 0, 8);4966 unsigned W = fieldFromInstruction(Insn, 21, 1);4967 unsigned U = fieldFromInstruction(Insn, 23, 1);4968 unsigned P = fieldFromInstruction(Insn, 24, 1);4969 bool writeback = (W == 1) | (P == 0);4970 4971 addr |= (U << 8) | (Rn << 9);4972 4973 if (writeback && (Rn == Rt || Rn == Rt2))4974 Check(S, MCDisassembler::SoftFail);4975 if (Rt == Rt2)4976 Check(S, MCDisassembler::SoftFail);4977 4978 // Rt4979 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))4980 return MCDisassembler::Fail;4981 // Rt24982 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))4983 return MCDisassembler::Fail;4984 // Writeback operand4985 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))4986 return MCDisassembler::Fail;4987 // addr4988 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))4989 return MCDisassembler::Fail;4990 4991 DecodePredicateOperand(Inst, Decoder);4992 return S;4993}4994 4995static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,4996 uint64_t Address,4997 const MCDisassembler *Decoder) {4998 DecodeStatus S = MCDisassembler::Success;4999 5000 unsigned Rt = fieldFromInstruction(Insn, 12, 4);5001 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);5002 unsigned Rn = fieldFromInstruction(Insn, 16, 4);5003 unsigned addr = fieldFromInstruction(Insn, 0, 8);5004 unsigned W = fieldFromInstruction(Insn, 21, 1);5005 unsigned U = fieldFromInstruction(Insn, 23, 1);5006 unsigned P = fieldFromInstruction(Insn, 24, 1);5007 bool writeback = (W == 1) | (P == 0);5008 5009 addr |= (U << 8) | (Rn << 9);5010 5011 if (writeback && (Rn == Rt || Rn == Rt2))5012 Check(S, MCDisassembler::SoftFail);5013 5014 // Writeback operand5015 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))5016 return MCDisassembler::Fail;5017 // Rt5018 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))5019 return MCDisassembler::Fail;5020 // Rt25021 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))5022 return MCDisassembler::Fail;5023 // addr5024 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))5025 return MCDisassembler::Fail;5026 5027 DecodePredicateOperand(Inst, Decoder);5028 return S;5029}5030 5031static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address,5032 const MCDisassembler *Decoder) {5033 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);5034 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);5035 if (sign1 != sign2) return MCDisassembler::Fail;5036 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);5037 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");5038 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);5039 5040 unsigned Val = fieldFromInstruction(Insn, 0, 8);5041 Val |= fieldFromInstruction(Insn, 12, 3) << 8;5042 Val |= fieldFromInstruction(Insn, 26, 1) << 11;5043 // If sign, then it is decreasing the address.5044 if (sign1) {5045 // Following ARMv7 Architecture Manual, when the offset5046 // is zero, it is decoded as a subw, not as a adr.w5047 if (!Val) {5048 Inst.setOpcode(ARM::t2SUBri12);5049 Inst.addOperand(MCOperand::createReg(ARM::PC));5050 } else5051 Val = -Val;5052 }5053 Inst.addOperand(MCOperand::createImm(Val));5054 DecodePredicateOperand(Inst, Decoder);5055 return S;5056}5057 5058static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,5059 uint64_t Address,5060 const MCDisassembler *Decoder) {5061 DecodeStatus S = MCDisassembler::Success;5062 5063 // Shift of "asr #32" is not allowed in Thumb2 mode.5064 if (Val == 0x20) S = MCDisassembler::Fail;5065 Inst.addOperand(MCOperand::createImm(Val));5066 return S;5067}5068 5069static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,5070 const MCDisassembler *Decoder) {5071 unsigned Rt = fieldFromInstruction(Insn, 12, 4);5072 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);5073 unsigned Rn = fieldFromInstruction(Insn, 16, 4);5074 unsigned pred = fieldFromInstruction(Insn, 28, 4);5075 5076 if (pred == 0xF)5077 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);5078 5079 DecodeStatus S = MCDisassembler::Success;5080 5081 if (Rt == Rn || Rn == Rt2)5082 S = MCDisassembler::SoftFail;5083 5084 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))5085 return MCDisassembler::Fail;5086 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))5087 return MCDisassembler::Fail;5088 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))5089 return MCDisassembler::Fail;5090 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))5091 return MCDisassembler::Fail;5092 5093 return S;5094}5095 5096static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,5097 const MCDisassembler *Decoder) {5098 const FeatureBitset &featureBits =5099 Decoder->getSubtargetInfo().getFeatureBits();5100 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];5101 5102 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);5103 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);5104 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);5105 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);5106 unsigned imm = fieldFromInstruction(Insn, 16, 6);5107 unsigned cmode = fieldFromInstruction(Insn, 8, 4);5108 unsigned op = fieldFromInstruction(Insn, 5, 1);5109 5110 DecodeStatus S = MCDisassembler::Success;5111 5112 // If the top 3 bits of imm are clear, this is a VMOV (immediate)5113 if (!(imm & 0x38)) {5114 if (cmode == 0xF) {5115 if (op == 1) return MCDisassembler::Fail;5116 Inst.setOpcode(ARM::VMOVv2f32);5117 }5118 if (hasFullFP16) {5119 if (cmode == 0xE) {5120 if (op == 1) {5121 Inst.setOpcode(ARM::VMOVv1i64);5122 } else {5123 Inst.setOpcode(ARM::VMOVv8i8);5124 }5125 }5126 if (cmode == 0xD) {5127 if (op == 1) {5128 Inst.setOpcode(ARM::VMVNv2i32);5129 } else {5130 Inst.setOpcode(ARM::VMOVv2i32);5131 }5132 }5133 if (cmode == 0xC) {5134 if (op == 1) {5135 Inst.setOpcode(ARM::VMVNv2i32);5136 } else {5137 Inst.setOpcode(ARM::VMOVv2i32);5138 }5139 }5140 }5141 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);5142 }5143 5144 if (!(imm & 0x20)) return MCDisassembler::Fail;5145 5146 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))5147 return MCDisassembler::Fail;5148 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))5149 return MCDisassembler::Fail;5150 Inst.addOperand(MCOperand::createImm(64 - imm));5151 5152 DecodePredicateOperand(Inst, Decoder);5153 return S;5154}5155 5156static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,5157 const MCDisassembler *Decoder) {5158 const FeatureBitset &featureBits =5159 Decoder->getSubtargetInfo().getFeatureBits();5160 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];5161 5162 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);5163 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);5164 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);5165 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);5166 unsigned imm = fieldFromInstruction(Insn, 16, 6);5167 unsigned cmode = fieldFromInstruction(Insn, 8, 4);5168 unsigned op = fieldFromInstruction(Insn, 5, 1);5169 5170 DecodeStatus S = MCDisassembler::Success;5171 5172 // If the top 3 bits of imm are clear, this is a VMOV (immediate)5173 if (!(imm & 0x38)) {5174 if (cmode == 0xF) {5175 if (op == 1) return MCDisassembler::Fail;5176 Inst.setOpcode(ARM::VMOVv4f32);5177 }5178 if (hasFullFP16) {5179 if (cmode == 0xE) {5180 if (op == 1) {5181 Inst.setOpcode(ARM::VMOVv2i64);5182 } else {5183 Inst.setOpcode(ARM::VMOVv16i8);5184 }5185 }5186 if (cmode == 0xD) {5187 if (op == 1) {5188 Inst.setOpcode(ARM::VMVNv4i32);5189 } else {5190 Inst.setOpcode(ARM::VMOVv4i32);5191 }5192 }5193 if (cmode == 0xC) {5194 if (op == 1) {5195 Inst.setOpcode(ARM::VMVNv4i32);5196 } else {5197 Inst.setOpcode(ARM::VMOVv4i32);5198 }5199 }5200 }5201 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);5202 }5203 5204 if (!(imm & 0x20)) return MCDisassembler::Fail;5205 5206 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))5207 return MCDisassembler::Fail;5208 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))5209 return MCDisassembler::Fail;5210 Inst.addOperand(MCOperand::createImm(64 - imm));5211 5212 DecodePredicateOperand(Inst, Decoder);5213 return S;5214}5215 5216static DecodeStatus5217DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn,5218 uint64_t Address,5219 const MCDisassembler *Decoder) {5220 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);5221 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);5222 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);5223 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);5224 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);5225 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);5226 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);5227 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);5228 5229 DecodeStatus S = MCDisassembler::Success;5230 5231 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;5232 5233 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))5234 return MCDisassembler::Fail;5235 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))5236 return MCDisassembler::Fail;5237 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))5238 return MCDisassembler::Fail;5239 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))5240 return MCDisassembler::Fail;5241 // The lane index does not have any bits in the encoding, because it can only5242 // be 0.5243 Inst.addOperand(MCOperand::createImm(0));5244 Inst.addOperand(MCOperand::createImm(rotate));5245 5246 return S;5247}5248 5249static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,5250 const MCDisassembler *Decoder) {5251 DecodeStatus S = MCDisassembler::Success;5252 5253 unsigned Rn = fieldFromInstruction(Val, 16, 4);5254 unsigned Rt = fieldFromInstruction(Val, 12, 4);5255 unsigned Rm = fieldFromInstruction(Val, 0, 4);5256 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);5257 unsigned Cond = fieldFromInstruction(Val, 28, 4);5258 5259 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)5260 S = MCDisassembler::SoftFail;5261 5262 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))5263 return MCDisassembler::Fail;5264 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))5265 return MCDisassembler::Fail;5266 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))5267 return MCDisassembler::Fail;5268 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))5269 return MCDisassembler::Fail;5270 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))5271 return MCDisassembler::Fail;5272 5273 return S;5274}5275 5276static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,5277 uint64_t Address,5278 const MCDisassembler *Decoder) {5279 DecodeStatus S = MCDisassembler::Success;5280 5281 unsigned CRm = fieldFromInstruction(Val, 0, 4);5282 unsigned opc1 = fieldFromInstruction(Val, 4, 4);5283 unsigned cop = fieldFromInstruction(Val, 8, 4);5284 unsigned Rt = fieldFromInstruction(Val, 12, 4);5285 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);5286 5287 if ((cop & ~0x1) == 0xa)5288 return MCDisassembler::Fail;5289 5290 if (Rt == Rt2)5291 S = MCDisassembler::SoftFail;5292 5293 // We have to check if the instruction is MRRC25294 // or MCRR2 when constructing the operands for5295 // Inst. Reason is because MRRC2 stores to two5296 // registers so it's tablegen desc has two5297 // outputs whereas MCRR doesn't store to any5298 // registers so all of it's operands are listed5299 // as inputs, therefore the operand order for5300 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]5301 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]5302 5303 if (Inst.getOpcode() == ARM::MRRC2) {5304 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))5305 return MCDisassembler::Fail;5306 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))5307 return MCDisassembler::Fail;5308 }5309 Inst.addOperand(MCOperand::createImm(cop));5310 Inst.addOperand(MCOperand::createImm(opc1));5311 if (Inst.getOpcode() == ARM::MCRR2) {5312 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))5313 return MCDisassembler::Fail;5314 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))5315 return MCDisassembler::Fail;5316 }5317 Inst.addOperand(MCOperand::createImm(CRm));5318 5319 return S;5320}5321 5322static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,5323 uint64_t Address,5324 const MCDisassembler *Decoder) {5325 const FeatureBitset &featureBits =5326 Decoder->getSubtargetInfo().getFeatureBits();5327 DecodeStatus S = MCDisassembler::Success;5328 5329 // Add explicit operand for the destination sysreg, for cases where5330 // we have to model it for code generation purposes.5331 switch (Inst.getOpcode()) {5332 case ARM::VMSR_FPSCR_NZCVQC:5333 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));5334 break;5335 case ARM::VMSR_P0:5336 Inst.addOperand(MCOperand::createReg(ARM::VPR));5337 break;5338 }5339 5340 if (Inst.getOpcode() != ARM::FMSTAT) {5341 unsigned Rt = fieldFromInstruction(Val, 12, 4);5342 5343 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {5344 if (Rt == 13 || Rt == 15)5345 S = MCDisassembler::SoftFail;5346 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));5347 } else5348 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));5349 }5350 5351 // Add explicit operand for the source sysreg, similarly to above.5352 switch (Inst.getOpcode()) {5353 case ARM::VMRS_FPSCR_NZCVQC:5354 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));5355 break;5356 case ARM::VMRS_P0:5357 Inst.addOperand(MCOperand::createReg(ARM::VPR));5358 break;5359 }5360 5361 if (featureBits[ARM::ModeThumb]) {5362 Inst.addOperand(MCOperand::createImm(ARMCC::AL));5363 Inst.addOperand(MCOperand::createReg(0));5364 } else {5365 unsigned pred = fieldFromInstruction(Val, 28, 4);5366 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))5367 return MCDisassembler::Fail;5368 }5369 5370 return S;5371}5372 5373template <bool isSigned, bool isNeg, bool zeroPermitted, int size>5374static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,5375 uint64_t Address,5376 const MCDisassembler *Decoder) {5377 DecodeStatus S = MCDisassembler::Success;5378 if (Val == 0 && !zeroPermitted)5379 S = MCDisassembler::Fail;5380 5381 uint64_t DecVal;5382 if (isSigned)5383 DecVal = SignExtend32<size + 1>(Val << 1);5384 else5385 DecVal = (Val << 1);5386 5387 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,5388 Decoder))5389 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));5390 return S;5391}5392 5393static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,5394 uint64_t Address,5395 const MCDisassembler *Decoder) {5396 5397 uint64_t LocImm = Inst.getOperand(0).getImm();5398 Val = LocImm + (2 << Val);5399 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,5400 Decoder))5401 Inst.addOperand(MCOperand::createImm(Val));5402 return MCDisassembler::Success;5403}5404 5405static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,5406 uint64_t Address,5407 const MCDisassembler *Decoder) {5408 if (Val >= ARMCC::AL) // also exclude the non-condition NV5409 return MCDisassembler::Fail;5410 Inst.addOperand(MCOperand::createImm(Val));5411 return MCDisassembler::Success;5412}5413 5414static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,5415 const MCDisassembler *Decoder) {5416 DecodeStatus S = MCDisassembler::Success;5417 5418 if (Inst.getOpcode() == ARM::MVE_LCTP) {5419 DecodePredicateOperand(Inst, Decoder);5420 return S;5421 }5422 5423 unsigned Imm = fieldFromInstruction(Insn, 11, 1) |5424 fieldFromInstruction(Insn, 1, 10) << 1;5425 switch (Inst.getOpcode()) {5426 case ARM::t2LEUpdate:5427 case ARM::MVE_LETP:5428 Inst.addOperand(MCOperand::createReg(ARM::LR));5429 Inst.addOperand(MCOperand::createReg(ARM::LR));5430 [[fallthrough]];5431 case ARM::t2LE:5432 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>(5433 Inst, Imm, Address, Decoder)))5434 return MCDisassembler::Fail;5435 break;5436 case ARM::t2WLS:5437 case ARM::MVE_WLSTP_8:5438 case ARM::MVE_WLSTP_16:5439 case ARM::MVE_WLSTP_32:5440 case ARM::MVE_WLSTP_64:5441 Inst.addOperand(MCOperand::createReg(ARM::LR));5442 if (!Check(S,5443 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),5444 Address, Decoder)) ||5445 !Check(S, DecodeBFLabelOperand<false, false, true, 11>(5446 Inst, Imm, Address, Decoder)))5447 return MCDisassembler::Fail;5448 break;5449 case ARM::t2DLS:5450 case ARM::MVE_DLSTP_8:5451 case ARM::MVE_DLSTP_16:5452 case ARM::MVE_DLSTP_32:5453 case ARM::MVE_DLSTP_64:5454 unsigned Rn = fieldFromInstruction(Insn, 16, 4);5455 if (Rn == 0xF) {5456 // Enforce all the rest of the instruction bits in LCTP, which5457 // won't have been reliably checked based on LCTP's own tablegen5458 // record, because we came to this decode by a roundabout route.5459 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;5460 if ((Insn & ~SBZMask) != CanonicalLCTP)5461 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail5462 if (Insn != CanonicalLCTP)5463 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail5464 5465 Inst.setOpcode(ARM::MVE_LCTP);5466 DecodePredicateOperand(Inst, Decoder);5467 } else {5468 Inst.addOperand(MCOperand::createReg(ARM::LR));5469 if (!Check(S, DecoderGPRRegisterClass(Inst,5470 fieldFromInstruction(Insn, 16, 4),5471 Address, Decoder)))5472 return MCDisassembler::Fail;5473 }5474 break;5475 }5476 return S;5477}5478 5479static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,5480 uint64_t Address,5481 const MCDisassembler *Decoder) {5482 DecodeStatus S = MCDisassembler::Success;5483 5484 if (Val == 0)5485 Val = 32;5486 5487 Inst.addOperand(MCOperand::createImm(Val));5488 5489 return S;5490}5491 5492static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,5493 uint64_t Address,5494 const MCDisassembler *Decoder) {5495 if ((RegNo) + 1 > 11)5496 return MCDisassembler::Fail;5497 5498 unsigned Register = GPRDecoderTable[(RegNo) + 1];5499 Inst.addOperand(MCOperand::createReg(Register));5500 return MCDisassembler::Success;5501}5502 5503static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,5504 uint64_t Address,5505 const MCDisassembler *Decoder) {5506 if ((RegNo) > 14)5507 return MCDisassembler::Fail;5508 5509 unsigned Register = GPRDecoderTable[(RegNo)];5510 Inst.addOperand(MCOperand::createReg(Register));5511 return MCDisassembler::Success;5512}5513 5514static DecodeStatus5515DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,5516 uint64_t Address,5517 const MCDisassembler *Decoder) {5518 if (RegNo == 15) {5519 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));5520 return MCDisassembler::Success;5521 }5522 5523 unsigned Register = GPRDecoderTable[RegNo];5524 Inst.addOperand(MCOperand::createReg(Register));5525 5526 if (RegNo == 13)5527 return MCDisassembler::SoftFail;5528 5529 return MCDisassembler::Success;5530}5531 5532static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,5533 const MCDisassembler *Decoder) {5534 DecodeStatus S = MCDisassembler::Success;5535 5536 Inst.addOperand(MCOperand::createImm(ARMCC::AL));5537 Inst.addOperand(MCOperand::createReg(0));5538 unsigned regs = fieldFromInstruction(Insn, 0, 8);5539 if (regs == 0) {5540 // Register list contains only VPR5541 } else if (Inst.getOpcode() == ARM::VSCCLRMD) {5542 unsigned reglist = regs | (fieldFromInstruction(Insn, 12, 4) << 8) |5543 (fieldFromInstruction(Insn, 22, 1) << 12);5544 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {5545 return MCDisassembler::Fail;5546 }5547 } else {5548 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 1) |5549 fieldFromInstruction(Insn, 22, 1);5550 // Registers past s31 are permitted and treated as being half of a d5551 // register, though both halves of each d register must be present.5552 unsigned max_reg = Vd + regs;5553 if (max_reg > 64 || (max_reg > 32 && (max_reg & 1)))5554 S = MCDisassembler::SoftFail;5555 unsigned max_sreg = std::min(32u, max_reg);5556 unsigned max_dreg = std::min(32u, max_reg / 2);5557 for (unsigned i = Vd; i < max_sreg; ++i)5558 if (!Check(S, DecodeSPRRegisterClass(Inst, i, Address, Decoder)))5559 return MCDisassembler::Fail;5560 for (unsigned i = 16; i < max_dreg; ++i)5561 if (!Check(S, DecodeDPRRegisterClass(Inst, i, Address, Decoder)))5562 return MCDisassembler::Fail;5563 }5564 Inst.addOperand(MCOperand::createReg(ARM::VPR));5565 5566 return S;5567}5568 5569static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,5570 uint64_t Address,5571 const MCDisassembler *Decoder) {5572 DecodeStatus S = MCDisassembler::Success;5573 5574 // Parse VPT mask and encode it in the MCInst as an immediate with the same5575 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and5576 // 't' as 0 and finish with a 1.5577 unsigned Imm = 0;5578 // We always start with a 't'.5579 unsigned CurBit = 0;5580 for (int i = 3; i >= 0; --i) {5581 // If the bit we are looking at is not the same as last one, invert the5582 // CurBit, if it is the same leave it as is.5583 CurBit ^= (Val >> i) & 1U;5584 5585 // Encode the CurBit at the right place in the immediate.5586 Imm |= (CurBit << i);5587 5588 // If we are done, finish the encoding with a 1.5589 if ((Val & ~(~0U << i)) == 0) {5590 Imm |= 1U << i;5591 break;5592 }5593 }5594 5595 Inst.addOperand(MCOperand::createImm(Imm));5596 5597 return S;5598}5599 5600static DecodeStatus5601DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,5602 const MCDisassembler *Decoder) {5603 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));5604 return MCDisassembler::Success;5605}5606 5607static DecodeStatus5608DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,5609 const MCDisassembler *Decoder) {5610 unsigned Code;5611 switch (Val & 0x3) {5612 case 0:5613 Code = ARMCC::GE;5614 break;5615 case 1:5616 Code = ARMCC::LT;5617 break;5618 case 2:5619 Code = ARMCC::GT;5620 break;5621 case 3:5622 Code = ARMCC::LE;5623 break;5624 }5625 Inst.addOperand(MCOperand::createImm(Code));5626 return MCDisassembler::Success;5627}5628 5629static DecodeStatus5630DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,5631 const MCDisassembler *Decoder) {5632 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));5633 return MCDisassembler::Success;5634}5635 5636static DecodeStatus5637DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,5638 const MCDisassembler *Decoder) {5639 unsigned Code;5640 switch (Val) {5641 default:5642 return MCDisassembler::Fail;5643 case 0:5644 Code = ARMCC::EQ;5645 break;5646 case 1:5647 Code = ARMCC::NE;5648 break;5649 case 4:5650 Code = ARMCC::GE;5651 break;5652 case 5:5653 Code = ARMCC::LT;5654 break;5655 case 6:5656 Code = ARMCC::GT;5657 break;5658 case 7:5659 Code = ARMCC::LE;5660 break;5661 }5662 5663 Inst.addOperand(MCOperand::createImm(Code));5664 return MCDisassembler::Success;5665}5666 5667static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,5668 uint64_t Address,5669 const MCDisassembler *Decoder) {5670 DecodeStatus S = MCDisassembler::Success;5671 5672 unsigned DecodedVal = 64 - Val;5673 5674 switch (Inst.getOpcode()) {5675 case ARM::MVE_VCVTf16s16_fix:5676 case ARM::MVE_VCVTs16f16_fix:5677 case ARM::MVE_VCVTf16u16_fix:5678 case ARM::MVE_VCVTu16f16_fix:5679 if (DecodedVal > 16)5680 return MCDisassembler::Fail;5681 break;5682 case ARM::MVE_VCVTf32s32_fix:5683 case ARM::MVE_VCVTs32f32_fix:5684 case ARM::MVE_VCVTf32u32_fix:5685 case ARM::MVE_VCVTu32f32_fix:5686 if (DecodedVal > 32)5687 return MCDisassembler::Fail;5688 break;5689 }5690 5691 Inst.addOperand(MCOperand::createImm(64 - Val));5692 5693 return S;5694}5695 5696static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {5697 switch (Opcode) {5698 case ARM::VSTR_P0_off:5699 case ARM::VSTR_P0_pre:5700 case ARM::VSTR_P0_post:5701 case ARM::VLDR_P0_off:5702 case ARM::VLDR_P0_pre:5703 case ARM::VLDR_P0_post:5704 return ARM::P0;5705 case ARM::VSTR_FPSCR_NZCVQC_off:5706 case ARM::VSTR_FPSCR_NZCVQC_pre:5707 case ARM::VSTR_FPSCR_NZCVQC_post:5708 case ARM::VLDR_FPSCR_NZCVQC_off:5709 case ARM::VLDR_FPSCR_NZCVQC_pre:5710 case ARM::VLDR_FPSCR_NZCVQC_post:5711 return ARM::FPSCR;5712 default:5713 return 0;5714 }5715}5716 5717template <bool Writeback>5718static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,5719 uint64_t Address,5720 const MCDisassembler *Decoder) {5721 switch (Inst.getOpcode()) {5722 case ARM::VSTR_FPSCR_pre:5723 case ARM::VSTR_FPSCR_NZCVQC_pre:5724 case ARM::VLDR_FPSCR_pre:5725 case ARM::VLDR_FPSCR_NZCVQC_pre:5726 case ARM::VSTR_FPSCR_off:5727 case ARM::VSTR_FPSCR_NZCVQC_off:5728 case ARM::VLDR_FPSCR_off:5729 case ARM::VLDR_FPSCR_NZCVQC_off:5730 case ARM::VSTR_FPSCR_post:5731 case ARM::VSTR_FPSCR_NZCVQC_post:5732 case ARM::VLDR_FPSCR_post:5733 case ARM::VLDR_FPSCR_NZCVQC_post:5734 const FeatureBitset &featureBits =5735 Decoder->getSubtargetInfo().getFeatureBits();5736 5737 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])5738 return MCDisassembler::Fail;5739 }5740 5741 DecodeStatus S = MCDisassembler::Success;5742 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))5743 Inst.addOperand(MCOperand::createReg(Sysreg));5744 unsigned Rn = fieldFromInstruction(Val, 16, 4);5745 unsigned addr = fieldFromInstruction(Val, 0, 7) |5746 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);5747 5748 if (Writeback) {5749 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))5750 return MCDisassembler::Fail;5751 }5752 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))5753 return MCDisassembler::Fail;5754 5755 Inst.addOperand(MCOperand::createImm(ARMCC::AL));5756 Inst.addOperand(MCOperand::createReg(0));5757 5758 return S;5759}5760 5761static inline DecodeStatus5762DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address,5763 const MCDisassembler *Decoder, unsigned Rn,5764 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {5765 DecodeStatus S = MCDisassembler::Success;5766 5767 unsigned Qd = fieldFromInstruction(Val, 13, 3);5768 unsigned addr = fieldFromInstruction(Val, 0, 7) |5769 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);5770 5771 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))5772 return MCDisassembler::Fail;5773 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))5774 return MCDisassembler::Fail;5775 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))5776 return MCDisassembler::Fail;5777 5778 Check(S, DecodeVpredNOperand(Inst, Decoder));5779 return S;5780}5781 5782template <int shift>5783static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,5784 uint64_t Address,5785 const MCDisassembler *Decoder) {5786 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,5787 fieldFromInstruction(Val, 16, 3),5788 DecodetGPRRegisterClass,5789 DecodeTAddrModeImm7<shift>);5790}5791 5792template <int shift>5793static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,5794 uint64_t Address,5795 const MCDisassembler *Decoder) {5796 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,5797 fieldFromInstruction(Val, 16, 4),5798 DecoderGPRRegisterClass,5799 DecodeT2AddrModeImm7<shift,1>);5800}5801 5802template <int shift>5803static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,5804 uint64_t Address,5805 const MCDisassembler *Decoder) {5806 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,5807 fieldFromInstruction(Val, 17, 3),5808 DecodeMQPRRegisterClass,5809 DecodeMveAddrModeQ<shift>);5810}5811 5812template <unsigned MinLog, unsigned MaxLog>5813static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,5814 uint64_t Address,5815 const MCDisassembler *Decoder) {5816 DecodeStatus S = MCDisassembler::Success;5817 5818 if (Val < MinLog || Val > MaxLog)5819 return MCDisassembler::Fail;5820 5821 Inst.addOperand(MCOperand::createImm(1LL << Val));5822 return S;5823}5824 5825template <unsigned start>5826static DecodeStatus5827DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,5828 const MCDisassembler *Decoder) {5829 DecodeStatus S = MCDisassembler::Success;5830 5831 Inst.addOperand(MCOperand::createImm(start + Val));5832 5833 return S;5834}5835 5836static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,5837 uint64_t Address,5838 const MCDisassembler *Decoder) {5839 DecodeStatus S = MCDisassembler::Success;5840 unsigned Rt = fieldFromInstruction(Insn, 0, 4);5841 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);5842 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |5843 fieldFromInstruction(Insn, 13, 3));5844 unsigned index = fieldFromInstruction(Insn, 4, 1);5845 5846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))5847 return MCDisassembler::Fail;5848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))5849 return MCDisassembler::Fail;5850 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))5851 return MCDisassembler::Fail;5852 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))5853 return MCDisassembler::Fail;5854 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))5855 return MCDisassembler::Fail;5856 5857 DecodePredicateOperand(Inst, Decoder);5858 return S;5859}5860 5861static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,5862 uint64_t Address,5863 const MCDisassembler *Decoder) {5864 DecodeStatus S = MCDisassembler::Success;5865 unsigned Rt = fieldFromInstruction(Insn, 0, 4);5866 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);5867 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |5868 fieldFromInstruction(Insn, 13, 3));5869 unsigned index = fieldFromInstruction(Insn, 4, 1);5870 5871 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))5872 return MCDisassembler::Fail;5873 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))5874 return MCDisassembler::Fail;5875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))5876 return MCDisassembler::Fail;5877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))5878 return MCDisassembler::Fail;5879 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))5880 return MCDisassembler::Fail;5881 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))5882 return MCDisassembler::Fail;5883 5884 DecodePredicateOperand(Inst, Decoder);5885 return S;5886}5887 5888static DecodeStatus5889DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,5890 const MCDisassembler *Decoder) {5891 DecodeStatus S = MCDisassembler::Success;5892 5893 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;5894 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;5895 unsigned Rm = fieldFromInstruction(Insn, 12, 4);5896 5897 if (RdaHi == 14) {5898 // This value of RdaHi (really indicating pc, because RdaHi has to5899 // be an odd-numbered register, so the low bit will be set by the5900 // decode function below) indicates that we must decode as SQRSHR5901 // or UQRSHL, which both have a single Rda register field with all5902 // four bits.5903 unsigned Rda = fieldFromInstruction(Insn, 16, 4);5904 5905 switch (Inst.getOpcode()) {5906 case ARM::MVE_ASRLr:5907 case ARM::MVE_SQRSHRL:5908 Inst.setOpcode(ARM::MVE_SQRSHR);5909 break;5910 case ARM::MVE_LSLLr:5911 case ARM::MVE_UQRSHLL:5912 Inst.setOpcode(ARM::MVE_UQRSHL);5913 break;5914 default:5915 llvm_unreachable("Unexpected starting opcode!");5916 }5917 5918 // Rda as output parameter5919 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))5920 return MCDisassembler::Fail;5921 5922 // Rda again as input parameter5923 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))5924 return MCDisassembler::Fail;5925 5926 // Rm, the amount to shift by5927 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))5928 return MCDisassembler::Fail;5929 5930 DecodePredicateOperand(Inst, Decoder);5931 5932 if (fieldFromInstruction (Insn, 6, 3) != 4)5933 return MCDisassembler::SoftFail;5934 5935 if (Rda == Rm)5936 return MCDisassembler::SoftFail;5937 5938 return S;5939 }5940 5941 // Otherwise, we decode as whichever opcode our caller has already5942 // put into Inst. Those all look the same:5943 5944 // RdaLo,RdaHi as output parameters5945 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))5946 return MCDisassembler::Fail;5947 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))5948 return MCDisassembler::Fail;5949 5950 // RdaLo,RdaHi again as input parameters5951 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))5952 return MCDisassembler::Fail;5953 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))5954 return MCDisassembler::Fail;5955 5956 // Rm, the amount to shift by5957 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))5958 return MCDisassembler::Fail;5959 5960 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||5961 Inst.getOpcode() == ARM::MVE_UQRSHLL) {5962 unsigned Saturate = fieldFromInstruction(Insn, 7, 1);5963 // Saturate, the bit position for saturation5964 Inst.addOperand(MCOperand::createImm(Saturate));5965 }5966 5967 DecodePredicateOperand(Inst, Decoder);5968 return S;5969}5970 5971static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,5972 uint64_t Address,5973 const MCDisassembler *Decoder) {5974 DecodeStatus S = MCDisassembler::Success;5975 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |5976 fieldFromInstruction(Insn, 13, 3));5977 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |5978 fieldFromInstruction(Insn, 1, 3));5979 unsigned imm6 = fieldFromInstruction(Insn, 16, 6);5980 5981 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))5982 return MCDisassembler::Fail;5983 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))5984 return MCDisassembler::Fail;5985 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))5986 return MCDisassembler::Fail;5987 Check(S, DecodeVpredROperand(Inst, Decoder));5988 return S;5989}5990 5991template <bool scalar, OperandDecoder predicate_decoder>5992static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,5993 const MCDisassembler *Decoder) {5994 DecodeStatus S = MCDisassembler::Success;5995 Inst.addOperand(MCOperand::createReg(ARM::VPR));5996 unsigned Qn = fieldFromInstruction(Insn, 17, 3);5997 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))5998 return MCDisassembler::Fail;5999 6000 unsigned fc;6001 6002 if (scalar) {6003 fc = fieldFromInstruction(Insn, 12, 1) << 2 |6004 fieldFromInstruction(Insn, 7, 1) |6005 fieldFromInstruction(Insn, 5, 1) << 1;6006 unsigned Rm = fieldFromInstruction(Insn, 0, 4);6007 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))6008 return MCDisassembler::Fail;6009 } else {6010 fc = fieldFromInstruction(Insn, 12, 1) << 2 |6011 fieldFromInstruction(Insn, 7, 1) |6012 fieldFromInstruction(Insn, 0, 1) << 1;6013 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |6014 fieldFromInstruction(Insn, 1, 3);6015 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))6016 return MCDisassembler::Fail;6017 }6018 6019 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))6020 return MCDisassembler::Fail;6021 6022 Check(S, DecodeVpredNOperand(Inst, Decoder));6023 return S;6024}6025 6026static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,6027 const MCDisassembler *Decoder) {6028 DecodeStatus S = MCDisassembler::Success;6029 Inst.addOperand(MCOperand::createReg(ARM::VPR));6030 unsigned Rn = fieldFromInstruction(Insn, 16, 4);6031 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))6032 return MCDisassembler::Fail;6033 Check(S, DecodeVpredNOperand(Inst, Decoder));6034 return S;6035}6036 6037static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,6038 uint64_t Address,6039 const MCDisassembler *Decoder) {6040 DecodeStatus S = MCDisassembler::Success;6041 Inst.addOperand(MCOperand::createReg(ARM::VPR));6042 Inst.addOperand(MCOperand::createReg(ARM::VPR));6043 Check(S, DecodeVpredNOperand(Inst, Decoder));6044 return S;6045}6046 6047static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,6048 uint64_t Address,6049 const MCDisassembler *Decoder) {6050 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);6051 const unsigned Rn = fieldFromInstruction(Insn, 16, 4);6052 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |6053 fieldFromInstruction(Insn, 12, 3) << 8 |6054 fieldFromInstruction(Insn, 0, 8);6055 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);6056 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);6057 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);6058 unsigned S = fieldFromInstruction(Insn, 20, 1);6059 if (sign1 != sign2)6060 return MCDisassembler::Fail;6061 6062 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)6063 DecodeStatus DS = MCDisassembler::Success;6064 if ((!Check(DS,6065 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst6066 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))6067 return MCDisassembler::Fail;6068 if (TypeT3) {6069 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);6070 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm126071 DecodePredicateOperand(Inst, Decoder);6072 } else {6073 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);6074 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm126075 return MCDisassembler::Fail;6076 DecodePredicateOperand(Inst, Decoder);6077 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out6078 return MCDisassembler::Fail;6079 }6080 6081 return DS;6082}6083 6084static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,6085 uint64_t Address,6086 const MCDisassembler *Decoder) {6087 DecodeStatus S = MCDisassembler::Success;6088 6089 const unsigned Rn = fieldFromInstruction(Insn, 16, 4);6090 // Adding Rn, holding memory location to save/load to/from, the only argument6091 // that is being encoded.6092 // '$Rn' in the assembly.6093 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))6094 return MCDisassembler::Fail;6095 // An optional predicate, '$p' in the assembly.6096 DecodePredicateOperand(Inst, Decoder);6097 // An immediate that represents a floating point registers list. '$regs' in6098 // the assembly.6099 Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect.6100 6101 return S;6102}6103 6104#include "ARMGenDisassemblerTables.inc"6105 6106// Post-decoding checks6107static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,6108 uint64_t Address, raw_ostream &CS,6109 uint32_t Insn,6110 DecodeStatus Result) {6111 switch (MI.getOpcode()) {6112 case ARM::HVC: {6113 // HVC is undefined if condition = 0xf otherwise upredictable6114 // if condition != 0xe6115 uint32_t Cond = (Insn >> 28) & 0xF;6116 if (Cond == 0xF)6117 return MCDisassembler::Fail;6118 if (Cond != 0xE)6119 return MCDisassembler::SoftFail;6120 return Result;6121 }6122 case ARM::t2ADDri:6123 case ARM::t2ADDri12:6124 case ARM::t2ADDrr:6125 case ARM::t2ADDrs:6126 case ARM::t2SUBri:6127 case ARM::t2SUBri12:6128 case ARM::t2SUBrr:6129 case ARM::t2SUBrs:6130 if (MI.getOperand(0).getReg() == ARM::SP &&6131 MI.getOperand(1).getReg() != ARM::SP)6132 return MCDisassembler::SoftFail;6133 return Result;6134 default: return Result;6135 }6136}6137 6138uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,6139 uint64_t Address) const {6140 // In Arm state, instructions are always 4 bytes wide, so there's no6141 // point in skipping any smaller number of bytes if an instruction6142 // can't be decoded.6143 if (!STI.hasFeature(ARM::ModeThumb))6144 return 4;6145 6146 // In a Thumb instruction stream, a halfword is a standalone 2-byte6147 // instruction if and only if its value is less than 0xE800.6148 // Otherwise, it's the first halfword of a 4-byte instruction.6149 //6150 // So, if we can see the upcoming halfword, we can judge on that6151 // basis, and maybe skip a whole 4-byte instruction that we don't6152 // know how to decode, without accidentally trying to interpret its6153 // second half as something else.6154 //6155 // If we don't have the instruction data available, we just have to6156 // recommend skipping the minimum sensible distance, which is 26157 // bytes.6158 if (Bytes.size() < 2)6159 return 2;6160 6161 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(6162 Bytes.data(), InstructionEndianness);6163 return Insn16 < 0xE800 ? 2 : 4;6164}6165 6166DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,6167 ArrayRef<uint8_t> Bytes,6168 uint64_t Address,6169 raw_ostream &CS) const {6170 DecodeStatus S;6171 if (STI.hasFeature(ARM::ModeThumb))6172 S = getThumbInstruction(MI, Size, Bytes, Address, CS);6173 else6174 S = getARMInstruction(MI, Size, Bytes, Address, CS);6175 if (S == DecodeStatus::Fail)6176 return S;6177 6178 // Verify that the decoded instruction has the correct number of operands.6179 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());6180 if (!MCID.isVariadic() && MI.getNumOperands() != MCID.getNumOperands()) {6181 reportFatalInternalError(MCII->getName(MI.getOpcode()) + ": expected " +6182 Twine(MCID.getNumOperands()) + " operands, got " +6183 Twine(MI.getNumOperands()) + "\n");6184 }6185 6186 return S;6187}6188 6189DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,6190 ArrayRef<uint8_t> Bytes,6191 uint64_t Address,6192 raw_ostream &CS) const {6193 CommentStream = &CS;6194 6195 assert(!STI.hasFeature(ARM::ModeThumb) &&6196 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "6197 "mode!");6198 6199 // We want to read exactly 4 bytes of data.6200 if (Bytes.size() < 4) {6201 Size = 0;6202 return MCDisassembler::Fail;6203 }6204 6205 // Encoded as a 32-bit word in the stream.6206 uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(),6207 InstructionEndianness);6208 6209 // Calling the auto-generated decoder function.6210 DecodeStatus Result =6211 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);6212 if (Result != MCDisassembler::Fail) {6213 Size = 4;6214 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);6215 }6216 6217 const uint8_t *Tables[] = {6218 DecoderTableVFP32, DecoderTableVFPV832,6219 DecoderTableNEONData32, DecoderTableNEONLoadStore32,6220 DecoderTableNEONDup32, DecoderTablev8NEON32,6221 DecoderTablev8Crypto32,6222 };6223 6224 for (const uint8_t *Table : Tables) {6225 Result = decodeInstruction(Table, MI, Insn, Address, this, STI);6226 if (Result != MCDisassembler::Fail) {6227 Size = 4;6228 return Result;6229 }6230 }6231 6232 Result =6233 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);6234 if (Result != MCDisassembler::Fail) {6235 Size = 4;6236 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);6237 }6238 6239 Size = 4;6240 return MCDisassembler::Fail;6241}6242 6243bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {6244 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());6245 for (unsigned i = 0; i < MCID.NumOperands; ++i) {6246 if (ARM::isVpred(MCID.operands()[i].OperandType))6247 return true;6248 }6249 return false;6250}6251 6252// Most Thumb instructions don't have explicit predicates in the encoding,6253// but rather get their predicates from IT context. Here, we check that the6254// decoded instruction is allowed to have the decoded predicate and advance6255// IT/VPT block states.6256MCDisassembler::DecodeStatus6257ARMDisassembler::checkThumbPredicate(MCInst &MI) const {6258 MCDisassembler::DecodeStatus S = Success;6259 6260 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();6261 6262 switch (MI.getOpcode()) {6263 case ARM::tBcc:6264 case ARM::t2Bcc:6265 case ARM::tCBZ:6266 case ARM::tCBNZ:6267 case ARM::tCPS:6268 case ARM::t2CPS3p:6269 case ARM::t2CPS2p:6270 case ARM::t2CPS1p:6271 case ARM::t2CSEL:6272 case ARM::t2CSINC:6273 case ARM::t2CSINV:6274 case ARM::t2CSNEG:6275 case ARM::tMOVSr:6276 case ARM::tSETEND:6277 // Some instructions (mostly conditional branches) are not6278 // allowed in IT blocks.6279 if (ITBlock.instrInITBlock())6280 S = SoftFail;6281 else6282 return Success;6283 break;6284 case ARM::t2HINT:6285 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)6286 S = SoftFail;6287 break;6288 case ARM::tB:6289 case ARM::t2B:6290 case ARM::t2TBB:6291 case ARM::t2TBH:6292 // Some instructions (mostly unconditional branches) can6293 // only appears at the end of, or outside of, an IT.6294 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())6295 S = SoftFail;6296 break;6297 default:6298 break;6299 }6300 6301 // Warn on non-VPT predicable instruction in a VPT block and a VPT6302 // predicable instruction in an IT block6303 if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) ||6304 (isVectorPredicable(MI) && ITBlock.instrInITBlock()))6305 S = SoftFail;6306 6307 if (ITBlock.instrInITBlock())6308 ITBlock.advanceITState();6309 else if (VPTBlock.instrInVPTBlock())6310 VPTBlock.advanceVPTState();6311 6312 return S;6313}6314 6315// Thumb VFP and some NEON instructions are a special case. Because we share6316// their encodings between ARM and Thumb modes, and they are predicable in ARM6317// mode, the auto-generated decoder will give them an (incorrect)6318// predicate operand. We need to rewrite these operands based on the IT6319// context as a post-pass.6320void ARMDisassembler::UpdateThumbPredicate(DecodeStatus &S, MCInst &MI) const {6321 unsigned CC;6322 CC = ITBlock.getITCC();6323 if (CC == 0xF)6324 CC = ARMCC::AL;6325 if (ITBlock.instrInITBlock())6326 ITBlock.advanceITState();6327 else if (VPTBlock.instrInVPTBlock()) {6328 CC = VPTBlock.getVPTPred();6329 VPTBlock.advanceVPTState();6330 }6331 6332 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());6333 ArrayRef<MCOperandInfo> OpInfo = MCID.operands();6334 MCInst::iterator I = MI.begin();6335 unsigned short NumOps = MCID.NumOperands;6336 for (unsigned i = 0; i < NumOps; ++i, ++I) {6337 if (OpInfo[i].isPredicate() ) {6338 if (CC != ARMCC::AL && !MCID.isPredicable())6339 Check(S, SoftFail);6340 I->setImm(CC);6341 ++I;6342 if (CC == ARMCC::AL)6343 I->setReg(ARM::NoRegister);6344 else6345 I->setReg(ARM::CPSR);6346 return;6347 }6348 }6349}6350 6351DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,6352 ArrayRef<uint8_t> Bytes,6353 uint64_t Address,6354 raw_ostream &CS) const {6355 CommentStream = &CS;6356 6357 assert(STI.hasFeature(ARM::ModeThumb) &&6358 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");6359 6360 // We want to read exactly 2 bytes of data.6361 if (Bytes.size() < 2) {6362 Size = 0;6363 return MCDisassembler::Fail;6364 }6365 6366 uint16_t Insn16 = llvm::support::endian::read<uint16_t>(6367 Bytes.data(), InstructionEndianness);6368 DecodeStatus Result =6369 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);6370 if (Result != MCDisassembler::Fail) {6371 Size = 2;6372 Check(Result, checkThumbPredicate(MI));6373 return Result;6374 }6375 6376 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,6377 STI);6378 if (Result) {6379 Size = 2;6380 Check(Result, checkThumbPredicate(MI));6381 return Result;6382 }6383 6384 Result =6385 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);6386 if (Result != MCDisassembler::Fail) {6387 Size = 2;6388 6389 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add6390 // the Thumb predicate.6391 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())6392 Result = MCDisassembler::SoftFail;6393 6394 Check(Result, checkThumbPredicate(MI));6395 6396 // If we find an IT instruction, we need to parse its condition6397 // code and mask operands so that we can apply them correctly6398 // to the subsequent instructions.6399 if (MI.getOpcode() == ARM::t2IT) {6400 unsigned Firstcond = MI.getOperand(0).getImm();6401 unsigned Mask = MI.getOperand(1).getImm();6402 ITBlock.setITState(Firstcond, Mask);6403 6404 // An IT instruction that would give a 'NV' predicate is unpredictable.6405 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))6406 CS << "unpredictable IT predicate sequence";6407 }6408 6409 return Result;6410 }6411 6412 // We want to read exactly 4 bytes of data.6413 if (Bytes.size() < 4) {6414 Size = 0;6415 return MCDisassembler::Fail;6416 }6417 6418 uint32_t Insn32 =6419 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>(6420 Bytes.data() + 2, InstructionEndianness);6421 6422 Result =6423 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);6424 if (Result != MCDisassembler::Fail) {6425 Size = 4;6426 6427 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add6428 // the VPT predicate.6429 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())6430 Result = MCDisassembler::SoftFail;6431 6432 Check(Result, checkThumbPredicate(MI));6433 6434 if (isVPTOpcode(MI.getOpcode())) {6435 unsigned Mask = MI.getOperand(0).getImm();6436 VPTBlock.setVPTState(Mask);6437 }6438 6439 return Result;6440 }6441 6442 Result =6443 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);6444 if (Result != MCDisassembler::Fail) {6445 Size = 4;6446 Check(Result, checkThumbPredicate(MI));6447 return Result;6448 }6449 6450 Result =6451 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);6452 if (Result != MCDisassembler::Fail) {6453 Size = 4;6454 Check(Result, checkThumbPredicate(MI));6455 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);6456 }6457 6458 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {6459 Result =6460 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);6461 if (Result != MCDisassembler::Fail) {6462 Size = 4;6463 UpdateThumbPredicate(Result, MI);6464 return Result;6465 }6466 }6467 6468 Result =6469 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);6470 if (Result != MCDisassembler::Fail) {6471 Size = 4;6472 return Result;6473 }6474 6475 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {6476 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,6477 STI);6478 if (Result != MCDisassembler::Fail) {6479 Size = 4;6480 UpdateThumbPredicate(Result, MI);6481 return Result;6482 }6483 }6484 6485 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {6486 uint32_t NEONLdStInsn = Insn32;6487 NEONLdStInsn &= 0xF0FFFFFF;6488 NEONLdStInsn |= 0x04000000;6489 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,6490 Address, this, STI);6491 if (Result != MCDisassembler::Fail) {6492 Size = 4;6493 Check(Result, checkThumbPredicate(MI));6494 return Result;6495 }6496 }6497 6498 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {6499 uint32_t NEONDataInsn = Insn32;6500 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-246501 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 246502 NEONDataInsn |= 0x12000000; // Set bits 28 and 256503 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,6504 Address, this, STI);6505 if (Result != MCDisassembler::Fail) {6506 Size = 4;6507 Check(Result, checkThumbPredicate(MI));6508 return Result;6509 }6510 6511 uint32_t NEONCryptoInsn = Insn32;6512 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-246513 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 246514 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 256515 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,6516 Address, this, STI);6517 if (Result != MCDisassembler::Fail) {6518 Size = 4;6519 return Result;6520 }6521 6522 uint32_t NEONv8Insn = Insn32;6523 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-266524 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,6525 this, STI);6526 if (Result != MCDisassembler::Fail) {6527 Size = 4;6528 return Result;6529 }6530 }6531 6532 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);6533 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)6534 ? DecoderTableThumb2CDE326535 : DecoderTableThumb2CoProc32;6536 Result =6537 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);6538 if (Result != MCDisassembler::Fail) {6539 Size = 4;6540 Check(Result, checkThumbPredicate(MI));6541 return Result;6542 }6543 6544 // Advance IT state to prevent next instruction inheriting6545 // the wrong IT state.6546 if (ITBlock.instrInITBlock())6547 ITBlock.advanceITState();6548 Size = 0;6549 return MCDisassembler::Fail;6550}6551 6552static MCDisassembler *createARMDisassembler(const Target &T,6553 const MCSubtargetInfo &STI,6554 MCContext &Ctx) {6555 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo());6556}6557 6558extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void6559LLVMInitializeARMDisassembler() {6560 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),6561 createARMDisassembler);6562 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),6563 createARMDisassembler);6564 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),6565 createARMDisassembler);6566 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),6567 createARMDisassembler);6568}6569