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1//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides ARM specific target descriptions.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H14#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H15 16#include "llvm/Support/DataTypes.h"17#include "llvm/MC/MCInstrDesc.h"18#include <memory>19#include <string>20 21namespace llvm {22class formatted_raw_ostream;23class MCAsmBackend;24class MCCodeEmitter;25class MCContext;26class MCInstrInfo;27class MCInstPrinter;28class MCObjectTargetWriter;29class MCObjectWriter;30class MCRegisterInfo;31class MCSubtargetInfo;32class MCStreamer;33class MCTargetOptions;34class MCRelocationInfo;35class MCTargetStreamer;36class StringRef;37class Target;38class Triple;39 40namespace ARM_MC {41std::string ParseARMTriple(const Triple &TT, StringRef CPU);42void initLLVMToCVRegMapping(MCRegisterInfo *MRI);43 44bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);45bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);46 47template<class Inst>48bool isLDMBaseRegInList(const Inst &MI) {49 auto BaseReg = MI.getOperand(0).getReg();50 for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) {51 const auto &Op = MI.getOperand(I);52 if (Op.isReg() && Op.getReg() == BaseReg)53 return true;54 }55 return false;56}57 58uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr,59 int64_t Imm);60 61/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.62/// do not need to go through TargetRegistry.63MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,64 StringRef FS);65}66 67MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);68MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,69 formatted_raw_ostream &OS,70 MCInstPrinter *InstPrint);71MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,72 const MCSubtargetInfo &STI);73MCTargetStreamer *createARMObjectTargetELFStreamer(MCStreamer &S);74MCTargetStreamer *createARMObjectTargetMachOStreamer(MCStreamer &S);75MCTargetStreamer *createARMObjectTargetWinCOFFStreamer(MCStreamer &S);76 77MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,78 MCContext &Ctx);79 80MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,81 MCContext &Ctx);82 83MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,84 const MCRegisterInfo &MRI,85 const MCTargetOptions &Options);86 87MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,88 const MCRegisterInfo &MRI,89 const MCTargetOptions &Options);90 91// Construct a PE/COFF machine code streamer which will generate a PE/COFF92// object file.93MCStreamer *createARMWinCOFFStreamer(MCContext &Context,94 std::unique_ptr<MCAsmBackend> &&MAB,95 std::unique_ptr<MCObjectWriter> &&OW,96 std::unique_ptr<MCCodeEmitter> &&Emitter);97 98/// Construct an ELF Mach-O object writer.99std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI);100 101/// Construct an ARM Mach-O object writer.102std::unique_ptr<MCObjectTargetWriter>103createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,104 uint32_t CPUSubtype);105 106/// Construct an ARM PE/COFF object writer.107std::unique_ptr<MCObjectTargetWriter>108createARMWinCOFFObjectWriter();109 110/// Construct ARM Mach-O relocation info.111MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);112 113namespace ARM {114enum OperandType {115 OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET,116 OPERAND_VPRED_N,117};118inline bool isVpred(OperandType op) {119 return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N;120}121inline bool isVpred(uint8_t op) {122 return isVpred(static_cast<OperandType>(op));123}124 125bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI);126 127} // end namespace ARM128 129} // End llvm namespace130 131// Defines symbolic names for ARM registers. This defines a mapping from132// register name to register number.133//134#define GET_REGINFO_ENUM135#include "ARMGenRegisterInfo.inc"136 137// Defines symbolic names for the ARM instructions.138//139#define GET_INSTRINFO_ENUM140#define GET_INSTRINFO_MC_HELPER_DECLS141#include "ARMGenInstrInfo.inc"142 143#define GET_SUBTARGETINFO_ENUM144#include "ARMGenSubtargetInfo.inc"145 146#endif147