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1//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the Thumb-2 implementation of the TargetInstrInfo class.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H14#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H15 16#include "ARMBaseInstrInfo.h"17#include "ThumbRegisterInfo.h"18 19namespace llvm {20class ARMSubtarget;21 22class Thumb2InstrInfo : public ARMBaseInstrInfo {23 ThumbRegisterInfo RI;24public:25 explicit Thumb2InstrInfo(const ARMSubtarget &STI);26 27 /// Return the noop instruction to use for a noop.28 MCInst getNop() const override;29 30 // Return the non-pre/post incrementing version of 'Opc'. Return 031 // if there is not such an opcode.32 unsigned getUnindexedOpcode(unsigned Opc) const override;33 34 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,35 MachineBasicBlock *NewDest) const override;36 37 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,38 MachineBasicBlock::iterator MBBI) const override;39 40 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,41 const DebugLoc &DL, Register DestReg, Register SrcReg,42 bool KillSrc, bool RenamableDest = false,43 bool RenamableSrc = false) const override;44 45 void storeRegToStackSlot(46 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,47 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,48 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;49 50 void loadRegFromStackSlot(51 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,52 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,53 Register VReg,54 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;55 56 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As57 /// such, whenever a client has an instance of instruction info, it should58 /// always be able to get register info as well (through this method).59 ///60 const ThumbRegisterInfo &getRegisterInfo() const { return RI; }61 62 MachineInstr *optimizeSelect(MachineInstr &MI,63 SmallPtrSetImpl<MachineInstr *> &SeenMIs,64 bool) const override;65 66 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,67 unsigned OpIdx1,68 unsigned OpIdx2) const override;69 70 bool isSchedulingBoundary(const MachineInstr &MI,71 const MachineBasicBlock *MBB,72 const MachineFunction &MF) const override;73 74private:75 void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;76};77 78/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical79/// to llvm::getInstrPredicate except it returns AL for conditional branch80/// instructions which are "predicated", but are not in IT blocks.81ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);82 83// getVPTInstrPredicate: VPT analogue of that, plus a helper function84// corresponding to MachineInstr::findFirstPredOperandIdx.85int findFirstVPTPredOperandIdx(const MachineInstr &MI);86ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI,87 Register &PredReg);88inline ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI) {89 Register PredReg;90 return getVPTInstrPredicate(MI, PredReg);91}92// Identify the input operand in an MVE predicated instruction which93// contributes the values of any inactive vector lanes.94int findVPTInactiveOperandIdx(const MachineInstr &MI);95 96// Recomputes the Block Mask of Instr, a VPT or VPST instruction.97// This rebuilds the block mask of the instruction depending on the predicates98// of the instructions following it. This should only be used after the99// MVEVPTBlockInsertion pass has run, and should be used whenever a predicated100// instruction is added to/removed from the block.101void recomputeVPTBlockMask(MachineInstr &Instr);102} // namespace llvm103 104#endif105