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1//===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the AVR implementation of the TargetInstrInfo class.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_AVR_INSTR_INFO_H14#define LLVM_AVR_INSTR_INFO_H15 16#include "llvm/CodeGen/TargetInstrInfo.h"17 18#include "AVRRegisterInfo.h"19 20#define GET_INSTRINFO_HEADER21#include "AVRGenInstrInfo.inc"22#undef GET_INSTRINFO_HEADER23 24namespace llvm {25 26class AVRSubtarget;27 28namespace AVRCC {29 30/// AVR specific condition codes.31/// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.32/// They must be kept in synch.33enum CondCodes {34 COND_EQ, //!< Equal35 COND_NE, //!< Not equal36 COND_GE, //!< Greater than or equal37 COND_LT, //!< Less than38 COND_SH, //!< Unsigned same or higher39 COND_LO, //!< Unsigned lower40 COND_MI, //!< Minus41 COND_PL, //!< Plus42 COND_INVALID43};44 45} // end of namespace AVRCC46 47namespace AVRII {48 49/// Specifies a target operand flag.50enum TOF {51 MO_NO_FLAG,52 53 /// On a symbol operand, this represents the lo part.54 MO_LO = (1 << 1),55 56 /// On a symbol operand, this represents the hi part.57 MO_HI = (1 << 2),58 59 /// On a symbol operand, this represents it has to be negated.60 MO_NEG = (1 << 3)61};62 63} // end of namespace AVRII64 65/// Utilities related to the AVR instruction set.66class AVRInstrInfo : public AVRGenInstrInfo {67public:68 explicit AVRInstrInfo(const AVRSubtarget &STI);69 70 const AVRRegisterInfo &getRegisterInfo() const { return RI; }71 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;72 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;73 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;74 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;75 76 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,77 const DebugLoc &DL, Register DestReg, Register SrcReg,78 bool KillSrc, bool RenamableDest = false,79 bool RenamableSrc = false) const override;80 void storeRegToStackSlot(81 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,82 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,83 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;84 void loadRegFromStackSlot(85 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,86 int FrameIndex, const TargetRegisterClass *RC, Register VReg,87 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;88 Register isLoadFromStackSlot(const MachineInstr &MI,89 int &FrameIndex) const override;90 Register isStoreToStackSlot(const MachineInstr &MI,91 int &FrameIndex) const override;92 93 // Branch analysis.94 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,95 MachineBasicBlock *&FBB,96 SmallVectorImpl<MachineOperand> &Cond,97 bool AllowModify = false) const override;98 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,99 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,100 const DebugLoc &DL,101 int *BytesAdded = nullptr) const override;102 unsigned removeBranch(MachineBasicBlock &MBB,103 int *BytesRemoved = nullptr) const override;104 bool105 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;106 107 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;108 109 bool isBranchOffsetInRange(unsigned BranchOpc,110 int64_t BrOffset) const override;111 112 void insertIndirectBranch(MachineBasicBlock &MBB,113 MachineBasicBlock &NewDestBB,114 MachineBasicBlock &RestoreBB, const DebugLoc &DL,115 int64_t BrOffset, RegScavenger *RS) const override;116 117private:118 const AVRRegisterInfo RI;119 120protected:121 const AVRSubtarget &STI;122};123 124} // end namespace llvm125 126#endif // LLVM_AVR_INSTR_INFO_H127