1713 lines · plain
1//===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the AVR instructions in TableGen format.10//11//===----------------------------------------------------------------------===//12 13include "AVRInstrFormats.td"14 15//===----------------------------------------------------------------------===//16// AVR Type Profiles17//===----------------------------------------------------------------------===//18 19def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;20def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;21def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;22def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;23def SDT_AVRBrcond24 : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;25def SDT_AVRCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;26def SDT_AVRTst : SDTypeProfile<0, 1, [SDTCisInt<0>]>;27def SDT_AVRSelectCC28 : SDTypeProfile<1, 3,29 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;30 31//===----------------------------------------------------------------------===//32// AVR Specific Node Definitions33//===----------------------------------------------------------------------===//34 35// Return from subroutine.36def AVRretglue : SDNode<"AVRISD::RET_GLUE", SDTNone,37 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;38 39// Return from ISR.40def AVRretiglue : SDNode<"AVRISD::RETI_GLUE", SDTNone,41 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;42 43 44def AVRcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AVRCallSeqStart,45 [SDNPHasChain, SDNPOutGlue]>;46def AVRcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AVRCallSeqEnd,47 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;48 49// Represents an abstract call instruction,50// which includes a bunch of information.51def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall,52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;53 54// A wrapper node for TargetConstantPool,55// TargetExternalSymbol, and TargetGlobalAddress.56def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>;57 58// AVR conditional branches. Operand 0 is the chain operand, operand 159// is the block to branch if condition is true, operand 2 is the60// condition code, and operand 3 is the flag operand produced by a CMP61// or TEST instruction.62def AVRbrcond63 : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond, [SDNPHasChain, SDNPInGlue]>;64 65// Compare instruction.66def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>;67 68// Compare with carry instruction.69def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>;70 71// Test for zero or minus instruction.72def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>;73 74// Operand 0 and operand 1 are selection variable, operand 275// is condition code and operand 3 is flag operand.76def AVRselectcc : SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>;77 78// Shift nodes.79def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>; // Logical shift left.80def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>; // Logical shift right.81def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>; // Bit rotate left.82def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>; // Bit rotate right.83def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>; // Arithmetic shift right.84def AVRlslhi : SDNode<"AVRISD::LSLHI", SDTIntUnaryOp>; // Higher 8-bit of word logical shift left.85def AVRlsrlo : SDNode<"AVRISD::LSRLO", SDTIntUnaryOp>; // Lower 8-bit of word logical shift right.86def AVRasrlo : SDNode<"AVRISD::ASRLO", SDTIntUnaryOp>; // Lower 8-bit of word arithmetic shift right.87def AVRlslbn : SDNode<"AVRISD::LSLBN", SDTIntBinOp>; // Byte logical shift left N bits.88def AVRlsrbn : SDNode<"AVRISD::LSRBN", SDTIntBinOp>; // Byte logical shift right N bits.89def AVRasrbn : SDNode<"AVRISD::ASRBN", SDTIntBinOp>; // Byte arithmetic shift right N bits.90def AVRlslwn : SDNode<"AVRISD::LSLWN", SDTIntBinOp>; // Higher 8-bit of word logical shift left.91def AVRlsrwn : SDNode<"AVRISD::LSRWN", SDTIntBinOp>; // Word logical shift right N bits.92def AVRasrwn : SDNode<"AVRISD::ASRWN", SDTIntBinOp>; // Word arithmetic shift right N bits.93def AVRlslw : SDNode<"AVRISD::LSLW", SDTIntShiftPairOp>; // Wide logical shift left.94def AVRlsrw : SDNode<"AVRISD::LSRW", SDTIntShiftPairOp>; // Wide logical shift right.95def AVRasrw : SDNode<"AVRISD::ASRW", SDTIntShiftPairOp>; // Wide arithmetic shift right.96 97// Pseudo shift nodes for non-constant shift amounts.98def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;99def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>;100def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>;101def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>;102def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>;103 104// SWAP node.105def AVRSwap : SDNode<"AVRISD::SWAP", SDTIntUnaryOp>;106 107//===----------------------------------------------------------------------===//108// AVR Operands, Complex Patterns and Transformations Definitions.109//===----------------------------------------------------------------------===//110 111def imm8_neg_XFORM : SDNodeXForm<imm, [{112 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i8);113}]>;114 115def imm16_neg_XFORM : SDNodeXForm<imm, [{116 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16);117}]>;118 119def imm0_63_neg : PatLeaf<(imm), [{120 int64_t val = -N->getSExtValue();121 return val >= 0 && val < 64;122}], imm16_neg_XFORM>;123 124def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>;125 126// imm_com8_XFORM - Return the complement of a imm_com8 value127def imm_com8_XFORM : SDNodeXForm<imm, [{128 return CurDAG->getTargetConstant(129 ~((uint8_t) N->getZExtValue()), SDLoc(N), MVT::i8);130}]>;131 132// imm_com8 - Match an immediate that is a complement133// of a 8-bit immediate.134// Note: this pattern doesn't require an encoder method and such, as it's135// only used on aliases (Pat<> and InstAlias<>). The actual encoding136// is handled by the destination instructions, which use imm_com8.137def imm_com8_asmoperand : AsmOperandClass { let Name = "ImmCom8"; }138def imm_com8 : Operand<i8> { let ParserMatchClass = imm_com8_asmoperand; }139 140def ioaddr_XFORM : SDNodeXForm<imm, [{141 uint8_t offset = Subtarget->getIORegisterOffset();142 return CurDAG->getTargetConstant(143 uint8_t(N->getZExtValue()) - offset, SDLoc(N), MVT::i8);144}]>;145 146def iobitpos8_XFORM : SDNodeXForm<imm, [{147 return CurDAG->getTargetConstant(148 Log2_32(uint8_t(N->getZExtValue())), SDLoc(N), MVT::i8);149}]>;150 151def iobitposn8_XFORM : SDNodeXForm<imm, [{152 return CurDAG->getTargetConstant(153 Log2_32(uint8_t(~N->getZExtValue())), SDLoc(N), MVT::i8);154}]>;155 156def ioaddr8 : PatLeaf<(imm), [{157 uint8_t offset = Subtarget->getIORegisterOffset();158 uint64_t val = N->getZExtValue() - offset;159 return val < 0x40;160}], ioaddr_XFORM>;161 162def lowioaddr8 : PatLeaf<(imm), [{163 uint8_t offset = Subtarget->getIORegisterOffset();164 uint64_t val = N->getZExtValue() - offset;165 return val < 0x20;166}], ioaddr_XFORM>;167 168def ioaddr16 : PatLeaf<(imm), [{169 uint8_t offset = Subtarget->getIORegisterOffset();170 uint64_t val = N->getZExtValue() - offset;171 return val < 0x3f;172}], ioaddr_XFORM>;173 174def iobitpos8 : PatLeaf<(imm), [{175 return isPowerOf2_32(uint8_t(N->getZExtValue()));176}], iobitpos8_XFORM>;177 178def iobitposn8 : PatLeaf<(imm), [{179 return isPowerOf2_32(uint8_t(~N->getZExtValue()));180}], iobitposn8_XFORM>;181 182def MemriAsmOperand : AsmOperandClass {183 let Name = "Memri";184 let ParserMethod = "parseMemriOperand";185}186 187/// Address operand for `reg+imm` used by STD and LDD.188def memri : Operand<iPTR> {189 let MIOperandInfo = (ops PTRDISPREGS, i16imm);190 191 let PrintMethod = "printMemri";192 let EncoderMethod = "encodeMemri";193 let DecoderMethod = "decodeMemri";194 195 let ParserMatchClass = MemriAsmOperand;196}197 198// Address operand for `SP+imm` used by STD{W}SPQRr199def memspi : Operand<iPTR> {200 let MIOperandInfo = (ops GPRSP, i16imm);201 let PrintMethod = "printMemspi";202}203 204def relbrtarget_7 : Operand<OtherVT> {205 let PrintMethod = "printPCRelImm";206 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>";207 let DecoderMethod = "decodeRelCondBrTarget7";208}209 210def brtarget_13 : Operand<OtherVT> {211 let PrintMethod = "printPCRelImm";212 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";213 let DecoderMethod = "decodeRelCondBrTarget13";214}215 216def rcalltarget_13 : Operand<i16> {217 let PrintMethod = "printPCRelImm";218 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";219 let DecoderMethod = "decodeRelCondBrTarget13";220}221 222// The target of a 22 or 16-bit call/jmp instruction.223def call_target : Operand<iPTR> {224 let EncoderMethod = "encodeCallTarget";225 let DecoderMethod = "decodeCallTarget";226}227 228// A 16-bit address (which can lead to an R_AVR_16 relocation).229def imm16 : Operand<i16> { let EncoderMethod = "encodeImm<AVR::fixup_16, 2>"; }230 231// A 7-bit address (which can lead to an R_AVR_LDS_STS_16 relocation).232def imm7tiny : Operand<i16> {233 let EncoderMethod = "encodeImm<AVR::fixup_lds_sts_16, 0>";234}235 236/// A 6-bit immediate used in the ADIW/SBIW instructions.237def imm_arith6 : Operand<i16> {238 let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>";239}240 241/// An 8-bit immediate inside an instruction with the same format242/// as the `LDI` instruction (the `FRdK` format).243def imm_ldi8 : Operand<i8> {244 let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>";245}246 247/// A 5-bit port number used in SBIC and friends (the `FIOBIT` format).248def imm_port5 : Operand<i8> {249 let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>";250}251 252/// A 6-bit port number used in the `IN` instruction and friends (the253/// `FIORdA` format.254def imm_port6 : Operand<i8> {255 let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>";256}257 258// Addressing mode pattern reg+imm6259let WantsRoot = true in260def addr : ComplexPattern<iPTR, 2, "SelectAddr">;261 262//===----------------------------------------------------------------------===//263// AVR predicates for subtarget features264//===----------------------------------------------------------------------===//265 266def HasSRAM : Predicate<"Subtarget->hasSRAM()">,267 AssemblerPredicate<(all_of FeatureSRAM)>;268 269def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">,270 AssemblerPredicate<(all_of FeatureJMPCALL)>;271 272def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">,273 AssemblerPredicate<(all_of FeatureIJMPCALL)>;274 275def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">,276 AssemblerPredicate<(all_of FeatureEIJMPCALL)>;277 278def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">,279 AssemblerPredicate<(all_of FeatureADDSUBIW)>;280 281def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">,282 AssemblerPredicate<(all_of FeatureSmallStack)>;283 284def HasMOVW : Predicate<"Subtarget->hasMOVW()">,285 AssemblerPredicate<(all_of FeatureMOVW)>;286 287def HasLPM : Predicate<"Subtarget->hasLPM()">,288 AssemblerPredicate<(all_of FeatureLPM)>;289 290def HasLPMX : Predicate<"Subtarget->hasLPMX()">,291 AssemblerPredicate<(all_of FeatureLPMX)>;292 293def HasELPM : Predicate<"Subtarget->hasELPM()">,294 AssemblerPredicate<(all_of FeatureELPM)>;295 296def HasELPMX : Predicate<"Subtarget->hasELPMX()">,297 AssemblerPredicate<(all_of FeatureELPMX)>;298 299def HasSPM : Predicate<"Subtarget->hasSPM()">,300 AssemblerPredicate<(all_of FeatureSPM)>;301 302def HasSPMX : Predicate<"Subtarget->hasSPMX()">,303 AssemblerPredicate<(all_of FeatureSPMX)>;304 305def HasDES : Predicate<"Subtarget->hasDES()">,306 AssemblerPredicate<(all_of FeatureDES)>;307 308def SupportsRMW : Predicate<"Subtarget->supportsRMW()">,309 AssemblerPredicate<(all_of FeatureRMW)>;310 311def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">,312 AssemblerPredicate<(all_of FeatureMultiplication)>;313 314def HasBREAK : Predicate<"Subtarget->hasBREAK()">,315 AssemblerPredicate<(all_of FeatureBREAK)>;316 317def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">,318 AssemblerPredicate<(all_of FeatureTinyEncoding)>;319 320def HasNonTinyEncoding : Predicate<"!Subtarget->hasTinyEncoding()">,321 AssemblerPredicate<(any_of (not FeatureTinyEncoding))>;322 323// AVR specific condition code. These correspond to AVR_*_COND in324// AVRInstrInfo.td. They must be kept in synch.325def AVR_COND_EQ : PatLeaf<(i8 0)>;326def AVR_COND_NE : PatLeaf<(i8 1)>;327def AVR_COND_GE : PatLeaf<(i8 2)>;328def AVR_COND_LT : PatLeaf<(i8 3)>;329def AVR_COND_SH : PatLeaf<(i8 4)>;330def AVR_COND_LO : PatLeaf<(i8 5)>;331def AVR_COND_MI : PatLeaf<(i8 6)>;332def AVR_COND_PL : PatLeaf<(i8 7)>;333 334//===----------------------------------------------------------------------===//335//===----------------------------------------------------------------------===//336// AVR Instruction list337//===----------------------------------------------------------------------===//338//===----------------------------------------------------------------------===//339 340// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into341// a stack adjustment and the codegen must know that they may modify the stack342// pointer before prolog-epilog rewriting occurs.343// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become344// sub / add which can clobber SREG.345let Defs = [SP, SREG], Uses = [SP] in {346 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt, i16imm:$amt2),347 "#ADJCALLSTACKDOWN",348 [(AVRcallseq_start timm:$amt, timm:$amt2)]>;349 350 // R31R30 is used to update SP. It is normally free because it is a351 // call-clobbered register but it is necessary to set it as a def as the352 // register allocator might use it in rare cases (for rematerialization, it353 // seems). hasSideEffects needs to be set to true so this instruction isn't354 // considered dead.355 let Defs = [R31R30], hasSideEffects = 1 in def ADJCALLSTACKUP356 : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),357 "#ADJCALLSTACKUP", [(AVRcallseq_end timm:$amt1, timm:$amt2)]>;358}359 360//===----------------------------------------------------------------------===//361// Addition362//===----------------------------------------------------------------------===//363let isCommutable = 1, Constraints = "$src = $rd", Defs = [SREG] in {364 // ADD Rd, Rr365 // Adds two 8-bit registers.366 def ADDRdRr : FRdRr<0b0000, 0b11, (outs GPR8:$rd),(ins GPR8:$src, GPR8:$rr),367 "add\t$rd, $rr",368 [(set i8:$rd, (add i8:$src, i8:$rr))]>;369 370 // ADDW Rd+1:Rd, Rr+1:Rr371 // Pseudo instruction to add four 8-bit registers as two 16-bit values.372 //373 // Expands to:374 // add Rd, Rr375 // adc Rd+1, Rr+1376 def ADDWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),377 "addw\t$rd, $rr",378 [(set i16:$rd, (add i16:$src, i16:$rr))]>;379 380 // ADC Rd, Rr381 // Adds two 8-bit registers with carry.382 let Uses = [SREG] in383 def ADCRdRr : FRdRr<0b0001, 0b11, (outs GPR8:$rd), (ins GPR8:$src, GPR8:$rr),384 "adc\t$rd, $rr",385 [(set i8:$rd, (adde i8:$src, i8:$rr))]>;386 387 // ADCW Rd+1:Rd, Rr+1:Rr388 // Pseudo instruction to add four 8-bit registers as two 16-bit values with389 // carry.390 //391 // Expands to:392 // adc Rd, Rr393 // adc Rd+1, Rr+1394 let Uses = [SREG] in395 def ADCWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),396 "adcw\t$rd, $rr",397 [(set i16:$rd, (adde i16:$src, i16:$rr))]>;398 399 // AIDW Rd, k400 // Adds an immediate 6-bit value K to Rd, placing the result in Rd.401 def ADIWRdK : FWRdK<0b0, (outs IWREGS:$rd), (ins IWREGS :$src, imm_arith6:$k),402 "adiw\t$rd, $k",403 [(set i16:$rd, (add i16:$src, uimm6:$k))]>,404 Requires<[HasADDSUBIW]>;405}406 407//===----------------------------------------------------------------------===//408// Subtraction409//===----------------------------------------------------------------------===//410let Constraints = "$rs = $rd", Defs = [SREG] in {411 // SUB Rd, Rr412 // Subtracts the 8-bit value of Rr from Rd and places the value in Rd.413 def SUBRdRr : FRdRr<0b0001, 0b10, (outs GPR8:$rd), (ins GPR8:$rs, GPR8:$rr),414 "sub\t$rd, $rr",415 [(set i8:$rd, (sub i8:$rs, i8:$rr))]>;416 417 // SUBW Rd+1:Rd, Rr+1:Rr418 // Subtracts two 16-bit values and places the result into Rd.419 //420 // Expands to:421 // sub Rd, Rr422 // sbc Rd+1, Rr+1423 def SUBWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$rs, DREGS:$rr),424 "subw\t$rd, $rr",425 [(set i16:$rd, (sub i16:$rs, i16:$rr))]>;426 427 def SUBIRdK : FRdK<0b0101, (outs LD8:$rd), (ins LD8:$rs, imm_ldi8:$k),428 "subi\t$rd, $k",429 [(set i8:$rd, (sub i8:$rs, imm:$k))]>;430 431 // SUBIW Rd+1:Rd, K+1:K432 //433 // Expands to:434 // subi Rd, K435 // sbci Rd+1, K+1436 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$rs, i16imm:$rr),437 "subiw\t$rd, $rr",438 [(set i16:$rd, (sub i16:$rs, imm:$rr))]>;439 440 def SBIWRdK : FWRdK<0b1, (outs IWREGS:$rd), (ins IWREGS:$rs, imm_arith6:$k),441 "sbiw\t$rd, $k",442 [(set i16:$rd, (sub i16:$rs, uimm6:$k))]>,443 Requires<[HasADDSUBIW]>;444 445 // Subtract with carry operations which must read the carry flag in SREG.446 let Uses = [SREG] in {447 def SBCRdRr : FRdRr<0b0000, 0b10, (outs GPR8:$rd), (ins GPR8:$rs, GPR8:$rr),448 "sbc\t$rd, $rr",449 [(set i8:$rd, (sube i8:$rs, i8:$rr))]>;450 451 // SBCW Rd+1:Rd, Rr+1:Rr452 //453 // Expands to:454 // sbc Rd, Rr455 // sbc Rd+1, Rr+1456 def SBCWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$rs, DREGS:$rr),457 "sbcw\t$rd, $rr",458 [(set i16:$rd, (sube i16:$rs, i16:$rr))]>;459 460 def SBCIRdK : FRdK<0b0100, (outs LD8:$rd), (ins LD8:$rs, imm_ldi8:$k),461 "sbci\t$rd, $k",462 [(set i8:$rd, (sube i8:$rs, imm:$k))]>;463 464 // SBCIW Rd+1:Rd, K+1:K465 // sbci Rd, K466 // sbci Rd+1, K+1467 def SBCIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$rs, i16imm:$rr),468 "sbciw\t$rd, $rr",469 [(set i16:$rd, (sube i16:$rs, imm:$rr))]>;470 }471}472 473//===----------------------------------------------------------------------===//474// Increment and Decrement475//===----------------------------------------------------------------------===//476let Constraints = "$src = $rd", Defs = [SREG] in {477 def INCRd : FRd<0b1001, 0b0100011, (outs GPR8:$rd), (ins GPR8:$src),478 "inc\t$rd",479 [(set i8:$rd, (add i8:$src, 1))]>;480 481 def DECRd : FRd<0b1001, 0b0101010, (outs GPR8:$rd), (ins GPR8:$src),482 "dec\t$rd",483 [(set i8:$rd, (add i8:$src, -1))]>;484}485 486//===----------------------------------------------------------------------===//487// Multiplication488//===----------------------------------------------------------------------===//489 490let isCommutable = 1, Defs = [R1, R0, SREG] in {491 // MUL Rd, Rr492 // Multiplies Rd by Rr and places the result into R1:R0.493 let usesCustomInserter = 1 in {494 def MULRdRr : FRdRr<0b1001, 0b11, (outs), (ins GPR8:$rd, GPR8:$rr),495 "mul\t$rd, $rr", []>,496 Requires<[SupportsMultiplication]>;497 498 def MULSRdRr : FMULSRdRr<(outs), (ins LD8:$rd, LD8:$rr),499 "muls\t$rd, $rr", []>,500 Requires<[SupportsMultiplication]>;501 }502 503 def MULSURdRr : FMULSURdRr<(outs), (ins LD8lo:$rd, LD8lo:$rr),504 "mulsu\t$rd, $rr", []>,505 Requires<[SupportsMultiplication]>;506 507 def FMUL : FFMULRdRr<0b01, (outs), (ins LD8lo:$rd, LD8lo:$rr),508 "fmul\t$rd, $rr", []>,509 Requires<[SupportsMultiplication]>;510 511 def FMULS : FFMULRdRr<0b10, (outs), (ins LD8lo:$rd, LD8lo:$rr),512 "fmuls\t$rd, $rr", []>,513 Requires<[SupportsMultiplication]>;514 515 def FMULSU : FFMULRdRr<0b11, (outs), (ins LD8lo:$rd, LD8lo:$rr),516 "fmulsu\t$rd, $rr", []>,517 Requires<[SupportsMultiplication]>;518}519 520let Defs =521 [R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R1, R0] in522def DESK : FDES<(outs), (ins i8imm:$k), "des\t$k", []>, Requires<[HasDES]>;523 524//===----------------------------------------------------------------------===//525// Logic526//===----------------------------------------------------------------------===//527let Constraints = "$src = $rd", Defs = [SREG] in {528 // Register-Register logic instructions (which have the529 // property of commutativity).530 let isCommutable = 1 in {531 def ANDRdRr : FRdRr<0b0010, 0b00, (outs GPR8:$rd),532 (ins GPR8:$src, GPR8:$rr), "and\t$rd, $rr",533 [(set i8:$rd, (and i8:$src, i8:$rr))]>;534 535 // ANDW Rd+1:Rd, Rr+1:Rr536 //537 // Expands to:538 // and Rd, Rr539 // and Rd+1, Rr+1540 def ANDWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),541 "andw\t$rd, $rr",542 [(set i16:$rd, (and i16:$src, i16:$rr))]>;543 544 def ORRdRr : FRdRr<0b0010, 0b10, (outs GPR8:$rd), (ins GPR8:$src, GPR8:$rr),545 "or\t$rd, $rr",546 [(set i8:$rd, (or i8:$src, i8:$rr))]>;547 548 // ORW Rd+1:Rd, Rr+1:Rr549 //550 // Expands to:551 // or Rd, Rr552 // or Rd+1, Rr+1553 def ORWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),554 "orw\t$rd, $rr",555 [(set i16:$rd, (or i16:$src, i16:$rr))]>;556 557 def EORRdRr : FRdRr<0b0010, 0b01, (outs GPR8:$rd),558 (ins GPR8:$src, GPR8:$rr), "eor\t$rd, $rr",559 [(set i8:$rd, (xor i8:$src, i8:$rr))]>;560 561 // EORW Rd+1:Rd, Rr+1:Rr562 //563 // Expands to:564 // eor Rd, Rr565 // eor Rd+1, Rr+1566 def EORWRdRr : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, DREGS:$rr),567 "eorw\t$rd, $rr",568 [(set i16:$rd, (xor i16:$src, i16:$rr))]>;569 }570 571 def ANDIRdK : FRdK<0b0111, (outs LD8:$rd), (ins LD8:$src, imm_ldi8:$k),572 "andi\t$rd, $k",573 [(set i8:$rd, (and i8:$src, imm:$k))]>;574 575 // ANDI Rd+1:Rd, K+1:K576 //577 // Expands to:578 // andi Rd, K579 // andi Rd+1, K+1580 def ANDIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$src, i16imm:$k),581 "andiw\t$rd, $k",582 [(set i16:$rd, (and i16:$src, imm:$k))]>;583 584 def ORIRdK : FRdK<0b0110, (outs LD8:$rd), (ins LD8:$src, imm_ldi8:$k),585 "ori\t$rd, $k",586 [(set i8:$rd, (or i8:$src, imm:$k))]>;587 588 // ORIW Rd+1:Rd, K+1,K589 //590 // Expands to:591 // ori Rd, K592 // ori Rd+1, K+1593 def ORIWRdK : Pseudo<(outs DLDREGS:$rd), (ins DLDREGS:$src, i16imm:$rr),594 "oriw\t$rd, $rr",595 [(set i16:$rd, (or i16:$src, imm:$rr))]>;596}597 598//===----------------------------------------------------------------------===//599// One's/Two's Complement600//===----------------------------------------------------------------------===//601let Constraints = "$src = $rd", Defs = [SREG] in {602 def COMRd : FRd<0b1001, 0b0100000, (outs GPR8:$rd), (ins GPR8:$src),603 "com\t$rd", [(set i8:$rd, (not i8:$src))]>;604 605 // COMW Rd+1:Rd606 //607 // Expands to:608 // com Rd609 // com Rd+1610 def COMWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "comw\t$rd",611 [(set i16:$rd, (not i16:$src))]>;612 613 def NEGRd : FRd<0b1001, 0b0100001, (outs GPR8:$rd), (ins GPR8:$src),614 "neg\t$rd", [(set i8:$rd, (ineg i8:$src))]>;615 616 // NEGW Rd+1:Rd617 //618 // Expands to:619 // neg Rd+1620 // neg Rd621 // sbc Rd+1, r1622 let hasSideEffects=0 in623 def NEGWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, GPR8:$zero),624 "negw\t$rd", []>;625}626 627// TST Rd628// Test for zero of minus.629// This operation is identical to a `Rd AND Rd`.630def : InstAlias<"tst\t$rd", (ANDRdRr GPR8:$rd, GPR8:$rd)>;631 632// SBR Rd, K633//634// Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands,635// same everything.636def : InstAlias<"sbr\t$rd, $k", (ORIRdK LD8:$rd, imm_ldi8:$k),637 /* Disable display, so we don't override ORI */ 0>;638 639//===----------------------------------------------------------------------===//640// Jump instructions641//===----------------------------------------------------------------------===//642let isBarrier = 1, isBranch = 1, isTerminator = 1 in {643 def RJMPk : FBRk<0, (outs), (ins brtarget_13:$k), "rjmp\t$k", [(br bb:$k)]>;644 645 let isIndirectBranch = 1, Uses = [R31R30] in646 def IJMP : F16<0b1001010000001001, (outs), (ins), "ijmp", []>,647 Requires<[HasIJMPCALL]>;648 649 let isIndirectBranch = 1, Uses = [R31R30] in650 def EIJMP : F16<0b1001010000011001, (outs), (ins), "eijmp", []>,651 Requires<[HasEIJMPCALL]>;652 653 def JMPk : F32BRk<0b110, (outs), (ins call_target:$k), "jmp\t$k", []>,654 Requires<[HasJMPCALL]>;655}656 657//===----------------------------------------------------------------------===//658// Call instructions659//===----------------------------------------------------------------------===//660let isCall = 1 in {661 // SP is marked as a use to prevent stack-pointer assignments that appear662 // immediately before calls from potentially appearing dead.663 let Uses = [SP] in664 def RCALLk : FBRk<1, (outs), (ins rcalltarget_13:$k), "rcall\t$k",665 [(AVRcall imm:$k)]>;666 667 // SP is marked as a use to prevent stack-pointer assignments that appear668 // immediately before calls from potentially appearing dead.669 let Uses = [SP, R31R30] in670 def ICALL : F16<0b1001010100001001, (outs), (ins variable_ops), "icall", []>,671 Requires<[HasIJMPCALL]>;672 673 // SP is marked as a use to prevent stack-pointer assignments that appear674 // immediately before calls from potentially appearing dead.675 let Uses = [SP, R31R30] in676 def EICALL : F16<0b1001010100011001, (outs), (ins variable_ops), "eicall",677 []>,678 Requires<[HasEIJMPCALL]>;679 680 // SP is marked as a use to prevent stack-pointer assignments that appear681 // immediately before calls from potentially appearing dead.682 //683 // TODO: the imm field can be either 16 or 22 bits in devices with more684 // than 64k of ROM, fix it once we support the largest devices.685 let Uses = [SP] in686 def CALLk : F32BRk<0b111, (outs), (ins call_target:$k), "call\t$k",687 [(AVRcall imm:$k)]>,688 Requires<[HasJMPCALL]>;689}690 691//===----------------------------------------------------------------------===//692// Return instructions.693//===----------------------------------------------------------------------===//694let isTerminator = 1, isReturn = 1, isBarrier = 1 in {695 def RET : F16<0b1001010100001000, (outs), (ins), "ret", [(AVRretglue)]>;696 697 def RETI : F16<0b1001010100011000, (outs), (ins), "reti", [(AVRretiglue)]>;698}699 700//===----------------------------------------------------------------------===//701// Compare operations.702//===----------------------------------------------------------------------===//703let Defs = [SREG] in {704 // CPSE Rd, Rr705 // Compare Rd and Rr, skipping the next instruction if they are equal.706 let isBarrier = 1, isBranch = 1, isTerminator = 1 in707 def CPSE : FRdRr<0b0001, 0b00, (outs), (ins GPR8:$rd, GPR8:$rr),708 "cpse\t$rd, $rr", []>;709 710 def CPRdRr : FRdRr<0b0001, 0b01, (outs), (ins GPR8:$rd, GPR8:$rr),711 "cp\t$rd, $rr",712 [(AVRcmp i8:$rd, i8:$rr)]>;713 714 // CPW Rd+1:Rd, Rr+1:Rr715 //716 // Expands to:717 // cp Rd, Rr718 // cpc Rd+1, Rr+1719 def CPWRdRr : Pseudo<(outs), (ins DREGS:$src, DREGS:$src2),720 "cpw\t$src, $src2",721 [(AVRcmp i16:$src, i16:$src2)]>;722 723 let Uses = [SREG] in724 def CPCRdRr : FRdRr<0b0000, 0b01, (outs), (ins GPR8:$rd, GPR8:$rr),725 "cpc\t$rd, $rr",726 [(AVRcmpc i8:$rd, i8:$rr)]>;727 728 // CPCW Rd+1:Rd. Rr+1:Rr729 //730 // Expands to:731 // cpc Rd, Rr732 // cpc Rd+1, Rr+1733 let Uses = [SREG] in734 def CPCWRdRr : Pseudo<(outs), (ins DREGS:$src, DREGS:$src2),735 "cpcw\t$src, $src2",736 [(AVRcmpc i16:$src, i16:$src2)]>;737 738 // CPI Rd, K739 // Compares a register with an 8 bit immediate.740 def CPIRdK : FRdK<0b0011, (outs), (ins LD8:$rd, imm_ldi8:$k), "cpi\t$rd, $k",741 [(AVRcmp i8:$rd, imm:$k)]>;742}743 744//===----------------------------------------------------------------------===//745// Register conditional skipping/branching operations.746//===----------------------------------------------------------------------===//747let isBranch = 1, isTerminator = 1 in {748 // Conditional skipping on GPR register bits, and749 // conditional skipping on IO register bits.750 let isBarrier = 1 in {751 def SBRCRrB : FRdB<0b10, (outs), (ins GPR8:$rd, i8imm:$b), "sbrc\t$rd, $b",752 []>;753 754 def SBRSRrB : FRdB<0b11, (outs), (ins GPR8:$rd, i8imm:$b), "sbrs\t$rd, $b",755 []>;756 757 def SBICAb : FIOBIT<0b01, (outs), (ins imm_port5:$addr, i8imm:$b),758 "sbic\t$addr, $b", []>;759 760 def SBISAb : FIOBIT<0b11, (outs), (ins imm_port5:$addr, i8imm:$b),761 "sbis\t$addr, $b", []>;762 }763 764 // Relative branches on status flag bits.765 let Uses = [SREG] in {766 // BRBS s, k767 // Branch if `s` flag in status register is set.768 def BRBSsk : FSK<0, (outs), (ins i8imm:$s, relbrtarget_7:$k),769 "brbs\t$s, $k", []>;770 771 // BRBC s, k772 // Branch if `s` flag in status register is clear.773 def BRBCsk : FSK<1, (outs), (ins i8imm:$s, relbrtarget_7:$k),774 "brbc\t$s, $k", []>;775 }776}777 778// BRCS k779// Branch if carry flag is set780def : InstAlias<"brcs\t$k", (BRBSsk 0, relbrtarget_7 : $k)>;781 782// BRCC k783// Branch if carry flag is clear784def : InstAlias<"brcc\t$k", (BRBCsk 0, relbrtarget_7 : $k)>;785 786// BRHS k787// Branch if half carry flag is set788def : InstAlias<"brhs\t$k", (BRBSsk 5, relbrtarget_7 : $k)>;789 790// BRHC k791// Branch if half carry flag is clear792def : InstAlias<"brhc\t$k", (BRBCsk 5, relbrtarget_7 : $k)>;793 794// BRTS k795// Branch if the T flag is set796def : InstAlias<"brts\t$k", (BRBSsk 6, relbrtarget_7 : $k)>;797 798// BRTC k799// Branch if the T flag is clear800def : InstAlias<"brtc\t$k", (BRBCsk 6, relbrtarget_7 : $k)>;801 802// BRVS k803// Branch if the overflow flag is set804def : InstAlias<"brvs\t$k", (BRBSsk 3, relbrtarget_7 : $k)>;805 806// BRVC k807// Branch if the overflow flag is clear808def : InstAlias<"brvc\t$k", (BRBCsk 3, relbrtarget_7 : $k)>;809 810// BRIE k811// Branch if the global interrupt flag is enabled812def : InstAlias<"brie\t$k", (BRBSsk 7, relbrtarget_7 : $k)>;813 814// BRID k815// Branch if the global interrupt flag is disabled816def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7 : $k)>;817 818//===----------------------------------------------------------------------===//819// PC-relative conditional branches820//===----------------------------------------------------------------------===//821// Based on status register. We cannot simplify these into instruction aliases822// because we also need to be able to specify a pattern to match for ISel.823let isBranch = 1, isTerminator = 1, Uses = [SREG] in {824 def BREQk : FBRsk<0, 0b001, (outs), (ins relbrtarget_7:$k), "breq\t$k",825 [(AVRbrcond bb:$k, AVR_COND_EQ)]>;826 827 def BRNEk : FBRsk<1, 0b001, (outs), (ins relbrtarget_7:$k), "brne\t$k",828 [(AVRbrcond bb:$k, AVR_COND_NE)]>;829 830 def BRSHk : FBRsk<1, 0b000, (outs), (ins relbrtarget_7:$k), "brsh\t$k",831 [(AVRbrcond bb:$k, AVR_COND_SH)]>;832 833 def BRLOk : FBRsk<0, 0b000, (outs), (ins relbrtarget_7:$k), "brlo\t$k",834 [(AVRbrcond bb:$k, AVR_COND_LO)]>;835 836 def BRMIk : FBRsk<0, 0b010, (outs), (ins relbrtarget_7:$k), "brmi\t$k",837 [(AVRbrcond bb:$k, AVR_COND_MI)]>;838 839 def BRPLk : FBRsk<1, 0b010, (outs), (ins relbrtarget_7:$k), "brpl\t$k",840 [(AVRbrcond bb:$k, AVR_COND_PL)]>;841 842 def BRGEk : FBRsk<1, 0b100, (outs), (ins relbrtarget_7:$k), "brge\t$k",843 [(AVRbrcond bb:$k, AVR_COND_GE)]>;844 845 def BRLTk : FBRsk<0, 0b100, (outs), (ins relbrtarget_7:$k), "brlt\t$k",846 [(AVRbrcond bb:$k, AVR_COND_LT)]>;847}848 849//===----------------------------------------------------------------------===//850// Data transfer instructions851//===----------------------------------------------------------------------===//852// 8 and 16-bit register move instructions.853let hasSideEffects = 0 in {854 def MOVRdRr : FRdRr<0b0010, 0b11, (outs GPR8:$rd), (ins GPR8:$rr),855 "mov\t$rd, $rr", []>;856 857 def MOVWRdRr : FMOVWRdRr<(outs DREGS:$rd), (ins DREGS:$rr), "movw\t$rd, $rr",858 []>,859 Requires<[HasMOVW]>;860}861 862// Load immediate values into registers.863let isReMaterializable = 1 in {864 def LDIRdK : FRdK<0b1110, (outs LD8:$rd), (ins imm_ldi8:$k), "ldi\t$rd, $k",865 [(set i8:$rd, imm:$k)]>;866 867 // LDIW Rd+1:Rd, K+1:K868 //869 // Expands to:870 // ldi Rd, K871 // ldi Rd+1, K+1872 def LDIWRdK : Pseudo<(outs DLDREGS:$dst), (ins i16imm:$src),873 "ldiw\t$dst, $src", [(set i16:$dst, imm:$src)]>;874}875 876// Load from data space into register.877let canFoldAsLoad = 1, isReMaterializable = 1 in {878 def LDSRdK : F32DM<0b0, (outs GPR8:$rd), (ins imm16:$k), "lds\t$rd, $k",879 [(set i8:$rd, (load imm:$k))]>,880 Requires<[HasSRAM, HasNonTinyEncoding]>;881 882 // Load from data space into register, which is only available on AVRTiny.883 def LDSRdKTiny : FLDSSTSTINY<0b0, (outs LD8:$rd), (ins imm7tiny:$k),884 "lds\t$rd, $k", [(set i8:$rd, (load imm:$k))]>,885 Requires<[HasSRAM, HasTinyEncoding]>;886 887 // LDSW Rd+1:Rd, K+1:K888 //889 // Expands to:890 // lds Rd, (K+1:K)891 // lds Rd+1 (K+1:K) + 1892 def LDSWRdK : Pseudo<(outs DREGS:$dst), (ins i16imm:$src), "ldsw\t$dst, $src",893 [(set i16:$dst, (load imm:$src))]>,894 Requires<[HasSRAM, HasNonTinyEncoding]>;895}896 897// Indirect loads.898let canFoldAsLoad = 1, isReMaterializable = 1 in {899 def LDRdPtr : FSTLD<0, 0b00, (outs GPR8:$reg), (ins PTRREGS:$ptrreg),900 "ld\t$reg, $ptrreg",901 [(set GPR8:$reg, (load i16:$ptrreg))]>,902 Requires<[HasSRAM]>;903 904 // LDW Rd+1:Rd, P905 //906 // Expands to:907 // ld Rd, P908 // ldd Rd+1, P+1909 // On reduced tiny cores, this instruction expands to:910 // ld Rd, P+911 // ld Rd+1, P+912 // subiw P, 2913 let Constraints = "@earlyclobber $reg" in def LDWRdPtr914 : Pseudo<(outs DREGS:$reg), (ins PTRDISPREGS:$ptrreg),915 "ldw\t$reg, $ptrreg", [(set i16:$reg, (load i16:$ptrreg))]>,916 Requires<[HasSRAM]>;917}918 919// Indirect loads (with postincrement or predecrement).920let mayLoad = 1, hasSideEffects = 0,921 Constraints = "$ptrreg = $base_wb,@earlyclobber $reg" in {922 def LDRdPtrPi : FSTLD<0, 0b01, (outs GPR8:$reg, PTRREGS:$base_wb),923 (ins PTRREGS:$ptrreg), "ld\t$reg, $ptrreg+", []>,924 Requires<[HasSRAM]>;925 926 // LDW Rd+1:Rd, P+927 // Expands to:928 // ld Rd, P+929 // ld Rd+1, P+930 def LDWRdPtrPi : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb),931 (ins PTRREGS:$ptrreg), "ldw\t$reg, $ptrreg+", []>,932 Requires<[HasSRAM]>;933 934 def LDRdPtrPd : FSTLD<0, 0b10, (outs GPR8:$reg, PTRREGS:$base_wb),935 (ins PTRREGS:$ptrreg), "ld\t$reg, -$ptrreg", []>,936 Requires<[HasSRAM]>;937 938 // LDW Rd+1:Rd, -P939 //940 // Expands to:941 // ld Rd+1, -P942 // ld Rd, -P943 def LDWRdPtrPd : Pseudo<(outs DREGS:$reg, PTRREGS:$base_wb),944 (ins PTRREGS:$ptrreg), "ldw\t$reg, -$ptrreg", []>,945 Requires<[HasSRAM]>;946}947 948// Load indirect with displacement operations.949let canFoldAsLoad = 1, isReMaterializable = 1 in {950 def LDDRdPtrQ : FSTDLDD<0, (outs GPR8:$reg), (ins memri:$memri),951 "ldd\t$reg, $memri",952 [(set i8:$reg, (load addr:$memri))]>,953 Requires<[HasSRAM, HasNonTinyEncoding]>;954 955 // LDDW Rd+1:Rd, P+q956 //957 // Expands to:958 // ldd Rd, P+q959 // ldd Rd+1, P+q+1960 // On reduced tiny cores, this instruction expands to:961 // subiw P, -q962 // ld Rd, P+963 // ld Rd+1, P+964 // subiw P, q+2965 let Constraints = "@earlyclobber $dst" in966 def LDDWRdPtrQ : Pseudo<(outs DREGS:$dst), (ins memri:$memri),967 "lddw\t$dst, $memri",968 [(set i16:$dst, (load addr:$memri))]>,969 Requires<[HasSRAM]>;970 971 // An identical pseudo instruction to LDDWRdPtrQ, expect restricted to the Y972 // register and without the @earlyclobber flag.973 //974 // Used to work around a bug caused by the register allocator not975 // being able to handle the expansion of a COPY into an machine instruction976 // that has an earlyclobber flag. This is because the register allocator will977 // try expand a copy from a register slot into an earlyclobber instruction.978 // Instructions that are earlyclobber need to be in a dedicated earlyclobber979 // slot.980 //981 // This pseudo instruction can be used pre-AVR pseudo expansion in order to982 // get a frame index load without directly using earlyclobber instructions.983 //984 // The pseudo expansion pass trivially expands this into LDDWRdPtrQ.985 //986 // This instruction may be removed once PR13375 is fixed.987 let mayLoad = 1, hasSideEffects = 0 in988 def LDDWRdYQ : Pseudo<(outs DREGS:$dst), (ins memri:$memri),989 "lddw\t$dst, $memri", []>,990 Requires<[HasSRAM]>;991}992 993class AtomicLoad<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>994 : Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",995 [(set DRC:$rd, (Op i16:$rr))]>;996 997class AtomicStore<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>998 : Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",999 [(Op DRC:$rr, i16:$rd)]>;1000 1001class AtomicLoadOp<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>1002 : Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand), "atomic_op",1003 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;1004 1005// Atomic instructions1006// ===================1007//1008// 8-bit operations can use any pointer register because1009// they are expanded directly into an LD/ST instruction.1010//1011// 16-bit operations use 16-bit load/store postincrement instructions,1012// which require PTRDISPREGS.1013 1014def AtomicLoad8 : AtomicLoad<atomic_load_nonext_8, GPR8, PTRREGS>;1015def AtomicLoad16 : AtomicLoad<atomic_load_nonext_16, DREGS, PTRDISPREGS>;1016 1017def AtomicStore8 : AtomicStore<atomic_store_8, GPR8, PTRREGS>;1018def AtomicStore16 : AtomicStore<atomic_store_16, DREGS, PTRDISPREGS>;1019 1020class AtomicLoadOp8<PatFrag Op> : AtomicLoadOp<Op, GPR8, PTRREGS>;1021class AtomicLoadOp16<PatFrag Op> : AtomicLoadOp<Op, DREGS, PTRDISPREGS>;1022 1023let usesCustomInserter=1 in {1024 def AtomicLoadAdd8 : AtomicLoadOp8<atomic_load_add_i8>;1025 def AtomicLoadAdd16 : AtomicLoadOp16<atomic_load_add_i16>;1026 def AtomicLoadSub8 : AtomicLoadOp8<atomic_load_sub_i8>;1027 def AtomicLoadSub16 : AtomicLoadOp16<atomic_load_sub_i16>;1028 def AtomicLoadAnd8 : AtomicLoadOp8<atomic_load_and_i8>;1029 def AtomicLoadAnd16 : AtomicLoadOp16<atomic_load_and_i16>;1030 def AtomicLoadOr8 : AtomicLoadOp8<atomic_load_or_i8>;1031 def AtomicLoadOr16 : AtomicLoadOp16<atomic_load_or_i16>;1032 def AtomicLoadXor8 : AtomicLoadOp8<atomic_load_xor_i8>;1033 def AtomicLoadXor16 : AtomicLoadOp16<atomic_load_xor_i16>;1034}1035 1036def AtomicFence1037 : Pseudo<(outs), (ins), "atomic_fence", [(atomic_fence timm, timm)]>;1038 1039// Indirect store from register to data space.1040def STSKRr : F32DM<0b1, (outs), (ins imm16:$k, GPR8:$rd), "sts\t$k, $rd",1041 [(store i8:$rd, imm:$k)]>,1042 Requires<[HasSRAM, HasNonTinyEncoding]>;1043 1044// Store from register to data space, which is only available on AVRTiny.1045def STSKRrTiny : FLDSSTSTINY<0b1, (outs), (ins imm7tiny:$k, LD8:$rd),1046 "sts\t$k, $rd", [(store i8:$rd, imm:$k)]>,1047 Requires<[HasSRAM, HasTinyEncoding]>;1048 1049// STSW K+1:K, Rr+1:Rr1050//1051// Expands to:1052// sts Rr+1, (K+1:K) + 11053// sts Rr, (K+1:K)1054def STSWKRr : Pseudo<(outs), (ins i16imm:$dst, DREGS:$src),1055 "stsw\t$dst, $src", [(store i16:$src, imm:$dst)]>,1056 Requires<[HasSRAM, HasNonTinyEncoding]>;1057 1058// Indirect stores.1059// ST P, Rr1060// Stores the value of Rr into the location addressed by pointer P.1061def STPtrRr : FSTLD<1, 0b00, (outs), (ins PTRREGS:$ptrreg, GPR8:$reg),1062 "st\t$ptrreg, $reg", [(store GPR8:$reg, i16:$ptrreg)]>,1063 Requires<[HasSRAM]>;1064 1065// STW P, Rr+1:Rr1066// Stores the value of Rr into the location addressed by pointer P.1067//1068// Expands to:1069// st P, Rr1070// std P+1, Rr+11071// On reduced tiny cores, this instruction expands to:1072// st P+, Rr1073// st P+, Rr+11074// subiw P, q+21075def STWPtrRr : Pseudo<(outs), (ins PTRDISPREGS:$ptrreg, DREGS:$reg),1076 "stw\t$ptrreg, $reg", [(store i16:$reg, i16:$ptrreg)]>,1077 Requires<[HasSRAM]>;1078 1079// Indirect stores (with postincrement or predecrement).1080let Constraints = "$ptrreg = $base_wb,@earlyclobber $base_wb" in {1081 1082 // ST P+, Rr1083 // Stores the value of Rr into the location addressed by pointer P.1084 // Post increments P.1085 def STPtrPiRr : FSTLD<1, 0b01, (outs PTRREGS:$base_wb),1086 (ins PTRREGS:$ptrreg, GPR8:$reg, i8imm:$offs),1087 "st\t$ptrreg+, $reg",1088 [(set i16:$base_wb, (post_store GPR8:$reg, i16:$ptrreg,1089 imm:$offs))]>,1090 Requires<[HasSRAM]>;1091 1092 // STW P+, Rr+1:Rr1093 // Stores the value of Rr into the location addressed by pointer P.1094 // Post increments P.1095 //1096 // Expands to:1097 // st P+, Rr1098 // st P+, Rr+11099 def STWPtrPiRr : Pseudo<(outs PTRREGS:$base_wb),1100 (ins PTRREGS:$ptrreg, DREGS:$trh, i8imm:$offs),1101 "stw\t$ptrreg+, $trh",1102 [(set PTRREGS:$base_wb,1103 (post_store DREGS:$trh, PTRREGS:$ptrreg,1104 imm:$offs))]>,1105 Requires<[HasSRAM]>;1106 1107 // ST -P, Rr1108 // Stores the value of Rr into the location addressed by pointer P.1109 // Pre decrements P.1110 def STPtrPdRr : FSTLD<1, 0b10, (outs PTRREGS:$base_wb),1111 (ins PTRREGS:$ptrreg, GPR8:$reg, i8imm:$offs),1112 "st\t-$ptrreg, $reg",1113 [(set i16: $base_wb,1114 (pre_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>,1115 Requires<[HasSRAM]>;1116 1117 // STW -P, Rr+1:Rr1118 // Stores the value of Rr into the location addressed by pointer P.1119 // Pre decrements P.1120 //1121 // Expands to:1122 // st -P, Rr+11123 // st -P, Rr1124 def STWPtrPdRr : Pseudo<(outs PTRREGS:$base_wb),1125 (ins PTRREGS:$ptrreg, DREGS:$reg, i8imm:$offs),1126 "stw\t-$ptrreg, $reg",1127 [(set PTRREGS:$base_wb,1128 (pre_store i16:$reg, i16:$ptrreg, imm:$offs))]>,1129 Requires<[HasSRAM]>;1130}1131 1132// Store indirect with displacement operations.1133// STD P+q, Rr1134// Stores the value of Rr into the location addressed by pointer P with a1135// displacement of q. Does not modify P.1136def STDPtrQRr : FSTDLDD<1, (outs), (ins memri:$memri, GPR8:$reg),1137 "std\t$memri, $reg", [(store i8:$reg, addr:$memri)]>,1138 Requires<[HasSRAM, HasNonTinyEncoding]>;1139 1140// STDW P+q, Rr+1:Rr1141// Stores the value of Rr into the location addressed by pointer P with a1142// displacement of q. Does not modify P.1143//1144// Expands to:1145// std P+q, Rr1146// std P+q+1, Rr+11147// On reduced tiny cores, this instruction expands to:1148// subiw P, -q1149// st P+, Rr1150// st P+, Rr+11151// subiw P, q+21152def STDWPtrQRr : Pseudo<(outs), (ins memri:$memri, DREGS:$src),1153 "stdw\t$memri, $src", [(store i16:$src, addr:$memri)]>,1154 Requires<[HasSRAM]>;1155 1156// Load program memory operations.1157let canFoldAsLoad = 1, isReMaterializable = 1, mayLoad = 1,1158 hasSideEffects = 0 in {1159 let Defs = [R0],1160 Uses = [R31R30] in def LPM1161 : F16<0b1001010111001000, (outs), (ins), "lpm", []>,1162 Requires<[HasLPM]>;1163 1164 // These pseudo instructions are combination of the OUT and LPM instructions.1165 let Defs = [R0] in {1166 def LPMBRdZ : Pseudo<(outs GPR8:$dst), (ins ZREG:$z), "lpmb\t$dst, $z", []>,1167 Requires<[HasLPM]>;1168 1169 let Constraints = "@earlyclobber $dst" in1170 def LPMWRdZ : Pseudo<(outs DREGS:$dst), (ins ZREG:$z), "lpmw\t$dst, $z", []>,1171 Requires<[HasLPM]>;1172 }1173 1174 def LPMRdZ : FLPMX<0, 0, (outs GPR8:$rd), (ins ZREG:$z), "lpm\t$rd, $z", []>,1175 Requires<[HasLPMX]>;1176 1177 // Load program memory, while postincrementing the Z register.1178 let Defs = [R31R30] in {1179 def LPMRdZPi : FLPMX<0, 1, (outs GPR8:$rd), (ins ZREG:$z),1180 "lpm\t$rd, $z+", []>,1181 Requires<[HasLPMX]>;1182 1183 def LPMWRdZPi : Pseudo<(outs DREGS:$dst), (ins ZREG:$z),1184 "lpmw\t$dst, $z+", []>,1185 Requires<[HasLPMX]>;1186 }1187}1188 1189// Extended load program memory operations.1190let mayLoad = 1, hasSideEffects = 0 in {1191 let Defs = [R0], Uses = [R31R30] in1192 def ELPM : F16<0b1001010111011000, (outs), (ins), "elpm", []>,1193 Requires<[HasELPM]>;1194 1195 def ELPMRdZ : FLPMX<1, 0, (outs GPR8:$rd), (ins ZREG:$z), "elpm\t$rd, $z",1196 []>,1197 Requires<[HasELPMX]>;1198 1199 let Defs = [R31R30] in1200 def ELPMRdZPi : FLPMX<1, 1, (outs GPR8:$rd), (ins ZREG:$z), "elpm\t$rd, $z+",1201 []>,1202 Requires<[HasELPMX]>;1203 1204 // These pseudo instructions are combination of the OUT and ELPM instructions.1205 let Defs = [R0] in {1206 def ELPMBRdZ : Pseudo<(outs GPR8:$dst), (ins ZREG:$z, LD8:$p),1207 "elpmb\t$dst, $z, $p", []>,1208 Requires<[HasELPM]>;1209 1210 let Constraints = "@earlyclobber $dst" in1211 def ELPMWRdZ : Pseudo<(outs DREGS:$dst), (ins ZREG:$z, LD8:$p),1212 "elpmw\t$dst, $z, $p", []>,1213 Requires<[HasELPM]>;1214 }1215 1216 // These pseudos are combination of the OUT and ELPM instructions.1217 let Defs = [R31R30], hasSideEffects = 1 in {1218 def ELPMBRdZPi : Pseudo<(outs GPR8:$dst), (ins ZREG:$z, LD8:$p),1219 "elpmb\t$dst, $z+, $p", []>,1220 Requires<[HasELPMX]>;1221 1222 def ELPMWRdZPi : Pseudo<(outs DREGS:$dst), (ins ZREG:$z, LD8:$p),1223 "elpmw\t$dst, $z+, $p", []>,1224 Requires<[HasELPMX]>;1225 }1226}1227 1228// Store program memory operations.1229let Uses = [R1, R0] in {1230 let Uses = [R31R30, R1, R0] in1231 def SPM : F16<0b1001010111101000, (outs), (ins), "spm", []>,1232 Requires<[HasSPM]>;1233 1234 let Defs = [R31R30] in 1235 def SPMZPi : F16<0b1001010111111000, (outs), (ins ZREG:$z), "spm $z+", []>,1236 Requires<[HasSPMX]> {1237 bits<0> z;1238 }1239}1240 1241// Read data from IO location operations.1242let canFoldAsLoad = 1, isReMaterializable = 1 in {1243 def INRdA : FIORdA<(outs GPR8:$rd), (ins imm_port6:$A), "in\t$rd, $A",1244 [(set i8:$rd, (load ioaddr8:$A))]>;1245 1246 def INWRdA : Pseudo<(outs DREGS:$d), (ins imm_port6:$s), "inw\t$d, $s",1247 [(set i16:$d, (load ioaddr16:$s))]>;1248}1249 1250// Write data to IO location operations.1251def OUTARr : FIOARr<(outs), (ins imm_port6:$A, GPR8:$rr), "out\t$A, $rr",1252 [(store i8:$rr, ioaddr8:$A)]>;1253 1254def OUTWARr : Pseudo<(outs), (ins imm_port6:$dst, DREGS:$src),1255 "outw\t$dst, $src", [(store i16:$src, ioaddr16:$dst)]>;1256 1257// Stack push/pop operations.1258let Defs = [SP], Uses = [SP], hasSideEffects = 0 in {1259 // Stack push operations.1260 let mayStore = 1 in {1261 def PUSHRr : FRd<0b1001, 0b0011111, (outs), (ins GPR8:$rd), "push\t$rd",1262 []>,1263 Requires<[HasSRAM]>;1264 1265 def PUSHWRr : Pseudo<(outs), (ins DREGS:$reg), "pushw\t$reg", []>,1266 Requires<[HasSRAM]>;1267 }1268 1269 // Stack pop operations.1270 let mayLoad = 1 in {1271 def POPRd : FRd<0b1001, 0b0001111, (outs GPR8:$rd), (ins), "pop\t$rd", []>,1272 Requires<[HasSRAM]>;1273 1274 def POPWRd : Pseudo<(outs DREGS:$reg), (ins), "popw\t$reg", []>,1275 Requires<[HasSRAM]>;1276 }1277}1278 1279// Read-Write-Modify (RMW) instructions.1280def XCHZRd : FZRd<0b100, (outs GPR8:$rd), (ins ZREG:$z), "xch\t$z, $rd", []>,1281 Requires<[SupportsRMW]>;1282 1283def LASZRd : FZRd<0b101, (outs GPR8:$rd), (ins ZREG:$z), "las\t$z, $rd", []>,1284 Requires<[SupportsRMW]>;1285 1286def LACZRd : FZRd<0b110, (outs GPR8:$rd), (ins ZREG:$z), "lac\t$z, $rd", []>,1287 Requires<[SupportsRMW]>;1288 1289def LATZRd : FZRd<0b111, (outs GPR8:$rd), (ins ZREG:$z), "lat\t$z, $rd", []>,1290 Requires<[SupportsRMW]>;1291 1292//===----------------------------------------------------------------------===//1293// Bit and bit-test instructions1294//===----------------------------------------------------------------------===//1295 1296// Bit shift/rotate operations.1297let Constraints = "$src = $rd", Defs = [SREG] in {1298 // 8-bit LSL is an alias of ADD Rd, Rd1299 1300 def LSLWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "lslw\t$rd",1301 [(set i16:$rd, (AVRlsl i16:$src))]>;1302 1303 def LSLWHiRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "lslwhi\t$rd",1304 [(set i16:$rd, (AVRlslhi i16:$src))]>;1305 1306 def LSLWNRd : Pseudo<(outs DLDREGS:$rd), (ins DREGS:$src, imm16:$bits),1307 "lslwn\t$rd, $bits",1308 [(set i16:$rd, (AVRlslwn i16:$src, imm:$bits))]>;1309 1310 def LSLBNRd : Pseudo<(outs LD8:$rd), (ins GPR8:$src, imm_ldi8:$bits),1311 "lslbn\t$rd, $bits",1312 [(set i8:$rd, (AVRlslbn i8:$src, imm:$bits))]>;1313 1314 def LSRRd : FRd<0b1001, 0b0100110, (outs GPR8:$rd), (ins GPR8:$src), "lsr\t$rd",1315 [(set i8:$rd, (AVRlsr i8:$src))]>;1316 1317 def LSRWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "lsrw\t$rd",1318 [(set i16:$rd, (AVRlsr i16:$src))]>;1319 1320 def LSRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "lsrwlo\t$rd",1321 [(set i16:$rd, (AVRlsrlo i16:$src))]>;1322 1323 def LSRWNRd : Pseudo<(outs DLDREGS:$rd), (ins DREGS:$src, imm16:$bits),1324 "lsrwn\t$rd, $bits",1325 [(set i16:$rd, (AVRlsrwn i16:$src, imm:$bits))]>;1326 1327 def LSRBNRd : Pseudo<(outs LD8:$rd), (ins GPR8:$src, imm_ldi8:$bits),1328 "lsrbn\t$rd, $bits",1329 [(set i8:$rd, (AVRlsrbn i8:$src, imm:$bits))]>;1330 1331 def ASRRd : FRd<0b1001, 0b0100101, (outs GPR8:$rd), (ins GPR8:$src), "asr\t$rd",1332 [(set i8:$rd, (AVRasr i8:$src))]>;1333 1334 def ASRWNRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src, imm16:$bits),1335 "asrwn\t$rd, $bits",1336 [(set i16:$rd, (AVRasrwn i16:$src, imm:$bits))]>;1337 1338 def ASRBNRd : Pseudo<(outs LD8:$rd), (ins GPR8:$src, imm_ldi8:$bits),1339 "asrbn\t$rd, $bits",1340 [(set i8:$rd, (AVRasrbn i8:$src, imm:$bits))]>;1341 1342 def ASRWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "asrw\t$rd",1343 [(set i16:$rd, (AVRasr i16:$src))]>;1344 1345 def ASRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "asrwlo\t$rd",1346 [(set i16:$rd, (AVRasrlo i16:$src))]>;1347 1348 let Uses = [R1] in1349 def ROLBRdR1 : Pseudo<(outs GPR8:$rd), (ins GPR8:$src), "rolb\t$rd",1350 [(set i8:$rd, (AVRrol i8:$src))]>,1351 Requires<[HasNonTinyEncoding]>;1352 1353 let Uses = [R17] in1354 def ROLBRdR17 : Pseudo<(outs GPR8:$rd), (ins GPR8:$src), "rolb\t$rd",1355 [(set i8:$rd, (AVRrol i8:$src))]>,1356 Requires<[HasTinyEncoding]>;1357 1358 def RORBRd : Pseudo<(outs GPR8:$rd), (ins GPR8:$src), "rorb\t$rd",1359 [(set i8:$rd, (AVRror i8:$src))]>;1360 1361 // Bit rotate operations.1362 let Uses = [SREG] in {1363 def ROLWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "rolw\t$rd",1364 [(set i16:$rd, (AVRrol i16:$src))]>;1365 1366 def RORRd : FRd<0b1001, 0b0100111, (outs GPR8:$rd), (ins GPR8:$src),1367 "ror\t$rd", []>;1368 1369 def RORWRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "rorw\t$rd",1370 [(set i16:$rd, (AVRror i16:$src))]>;1371 }1372}1373 1374// SWAP Rd1375// Swaps the high and low nibbles in a register.1376let Constraints = "$src = $rd" in1377def SWAPRd : FRd<0b1001, 0b0100010, (outs GPR8:$rd), (ins GPR8:$src),1378 "swap\t$rd", [(set i8:$rd, (AVRSwap i8:$src))]>;1379 1380// IO register bit set/clear operations.1381//: TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi1382// instead of in+ori+out which requires one more instr.1383def SBIAb : FIOBIT<0b10, (outs), (ins imm_port5:$addr, i8imm:$b),1384 "sbi\t$addr, $b",1385 [(store(or(i8(load lowioaddr8:$addr)), iobitpos8:$b),1386 lowioaddr8:$addr)]>;1387 1388def CBIAb : FIOBIT<0b00, (outs), (ins imm_port5:$addr, i8imm :$b),1389 "cbi\t$addr, $b",1390 [(store(and(i8(load lowioaddr8:$addr)), iobitposn8:$b),1391 lowioaddr8:$addr)]>;1392 1393// Status register bit load/store operations.1394let Defs = [SREG] in1395def BST : FRdB<0b01, (outs), (ins GPR8:$rd, i8imm:$b), "bst\t$rd, $b", []>;1396 1397let Constraints = "$src = $rd", Uses = [SREG] in1398def BLD : FRdB<0b00, (outs GPR8:$rd), (ins GPR8:$src, i8imm:$b), "bld\t$rd, $b",1399 []>;1400 1401def CBR : InstAlias<"cbr\t$rd, $k", (ANDIRdK LD8 : $rd, imm_com8 : $k), 0>;1402 1403// CLR Rd1404// Alias for EOR Rd, Rd1405// -------------1406// Clears all bits in a register.1407def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8 : $rd, GPR8 : $rd)>;1408 1409// LSL Rd1410// Alias for ADD Rd, Rd1411// --------------1412// Logical shift left one bit.1413def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8 : $rd, GPR8 : $rd)>;1414 1415def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8 : $rd, GPR8 : $rd)>;1416 1417// SER Rd1418// Alias for LDI Rd, 0xff1419// ---------1420// Sets all bits in a register.1421def : InstAlias<"ser\t$rd", (LDIRdK LD8 : $rd, 0xff), 0>;1422 1423let hasSideEffects=1 in {1424 let Defs = [SREG] in def BSETs : FS<0, (outs), (ins i8imm:$s), "bset\t$s", []>;1425 let Defs = [SREG] in def BCLRs : FS<1, (outs), (ins i8imm:$s), "bclr\t$s", []>;1426}1427 1428// Set/clear aliases for the carry (C) status flag (bit 0).1429def : InstAlias<"sec", (BSETs 0)>;1430def : InstAlias<"clc", (BCLRs 0)>;1431 1432// Set/clear aliases for the zero (Z) status flag (bit 1).1433def : InstAlias<"sez", (BSETs 1)>;1434def : InstAlias<"clz", (BCLRs 1)>;1435 1436// Set/clear aliases for the negative (N) status flag (bit 2).1437def : InstAlias<"sen", (BSETs 2)>;1438def : InstAlias<"cln", (BCLRs 2)>;1439 1440// Set/clear aliases for the overflow (V) status flag (bit 3).1441def : InstAlias<"sev", (BSETs 3)>;1442def : InstAlias<"clv", (BCLRs 3)>;1443 1444// Set/clear aliases for the signed (S) status flag (bit 4).1445def : InstAlias<"ses", (BSETs 4)>;1446def : InstAlias<"cls", (BCLRs 4)>;1447 1448// Set/clear aliases for the half-carry (H) status flag (bit 5).1449def : InstAlias<"seh", (BSETs 5)>;1450def : InstAlias<"clh", (BCLRs 5)>;1451 1452// Set/clear aliases for the T status flag (bit 6).1453def : InstAlias<"set", (BSETs 6)>;1454def : InstAlias<"clt", (BCLRs 6)>;1455 1456// Set/clear aliases for the interrupt (I) status flag (bit 7).1457def : InstAlias<"sei", (BSETs 7)>;1458def : InstAlias<"cli", (BCLRs 7)>;1459 1460//===----------------------------------------------------------------------===//1461// Special/Control instructions1462//===----------------------------------------------------------------------===//1463 1464// BREAK1465// Breakpoint instruction1466// ---------1467// <|1001|0101|1001|1000>1468def BREAK : F16<0b1001010110011000, (outs), (ins), "break", []>,1469 Requires<[HasBREAK]>;1470 1471// NOP1472// No-operation instruction1473// ---------1474// <|0000|0000|0000|0000>1475def NOP : F16<0b0000000000000000, (outs), (ins), "nop", []>;1476 1477// SLEEP1478// Sleep instruction1479// ---------1480// <|1001|0101|1000|1000>1481def SLEEP : F16<0b1001010110001000, (outs), (ins), "sleep", []>;1482 1483// WDR1484// Watchdog reset1485// ---------1486// <|1001|0101|1010|1000>1487def WDR : F16<0b1001010110101000, (outs), (ins), "wdr", []>;1488 1489//===----------------------------------------------------------------------===//1490// Pseudo instructions for later expansion1491//===----------------------------------------------------------------------===//1492 1493//: TODO: Optimize this for wider types AND optimize the following code1494// compile int foo(char a, char b, char c, char d) {return d+b;}1495// looks like a missed sext_inreg opportunity.1496def SEXT : ExtensionPseudo<(outs DREGS:$dt), (ins GPR8:$src), "sext\t$dt, $src",1497 [(set i16:$dt, (sext i8:$src))]>;1498 1499def ZEXT : ExtensionPseudo<(outs DREGS:$dt), (ins GPR8:$src), "zext\t$dt, $src",1500 [(set i16:$dt, (zext i8:$src))]>;1501 1502// This pseudo gets expanded into a movw+adiw thus it clobbers SREG.1503let Defs = [SREG], hasSideEffects = 0 in1504def FRMIDX : Pseudo<(outs DLDREGS:$dst), (ins DLDREGS:$src, i16imm:$src2),1505 "frmidx\t$dst, $src, $src2", []>;1506 1507// The instructions STDSPQRr and STDWSPQRr are used to store to the stack1508// frame. The most accurate implementation would be to load the SP into1509// a temporary pointer variable and then STDPtrQRr. However for efficiency,1510// we assume that R29R28 contains the current call frame pointer.1511// However in the PEI pass we sometimes rewrite a ADJCALLSTACKDOWN pseudo,1512// plus one or more STDSPQRr/STDWSPQRr pseudo instructions to use Z for a1513// stack adjustment then as a base pointer. To avoid corruption, we thus1514// specify special classes of registers, like GPR8 and DREGS, but with1515// the Z register removed, as the source/input to these instructions.1516// This pseudo is either converted to a regular store or a push which clobbers1517// SP.1518let Defs = [SP], Uses = [SP], hasSideEffects = 0 in1519def STDSPQRr : StorePseudo<(outs), (ins memspi:$dst, GPR8NOZ:$src),1520 "stdstk\t$dst, $src", [(store i8:$src, addr:$dst)]>;1521 1522// See the comment on STDSPQRr.1523// This pseudo is either converted to a regular store or a push which clobbers1524// SP.1525let Defs = [SP], Uses = [SP], hasSideEffects = 0 in1526def STDWSPQRr : StorePseudo<(outs), (ins memspi:$dt, DREGSNOZ:$src),1527 "stdwstk\t$dt, $src", [(store i16:$src, addr:$dt)]>;1528 1529// SP read/write pseudos.1530let hasSideEffects = 0 in {1531 let Uses = [SP] in1532 def SPREAD : Pseudo<(outs DREGS:$dst), (ins GPRSP:$src), "spread\t$dst, $src",1533 []>;1534 let Defs = [SP] in1535 def SPWRITE : Pseudo<(outs GPRSP:$dst), (ins DREGS:$src),1536 "spwrite\t$dst, $src", []>;1537}1538 1539def Select8 : SelectPseudo<(outs GPR8:$dst),1540 (ins GPR8:$src, GPR8:$src2, i8imm:$cc),1541 "# Select8 PSEUDO",1542 [(set i8:$dst,1543 (AVRselectcc i8:$src, i8:$src2, imm:$cc))]>;1544 1545def Select16 : SelectPseudo<(outs DREGS:$dst),1546 (ins DREGS:$src, DREGS:$src2, i8imm:$cc),1547 "# Select16 PSEUDO",1548 [(set i16:$dst,1549 (AVRselectcc i16:$src, i16:$src2, imm:$cc))]>;1550 1551def Lsl8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),1552 "# Lsl8 PSEUDO",1553 [(set i8:$dst, (AVRlslLoop i8:$src, i8:$cnt))]>;1554 1555def Lsl16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),1556 "# Lsl16 PSEUDO",1557 [(set i16:$dst, (AVRlslLoop i16:$src, i8:$cnt))]>;1558 1559def Lsl32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),1560 (ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),1561 "# Lsl32 PSEUDO",1562 [(set i16:$dstlo, i16:$dsthi,1563 (AVRlslw i16:$srclo, i16:$srchi, i8:$cnt))]>;1564 1565def Lsr8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),1566 "# Lsr8 PSEUDO",1567 [(set i8:$dst, (AVRlsrLoop i8:$src, i8:$cnt))]>;1568 1569def Lsr16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),1570 "# Lsr16 PSEUDO",1571 [(set i16:$dst, (AVRlsrLoop i16:$src, i8:$cnt))]>;1572 1573def Lsr32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),1574 (ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),1575 "# Lsr32 PSEUDO",1576 [(set i16:$dstlo, i16:$dsthi,1577 (AVRlsrw i16:$srclo, i16:$srchi, i8:$cnt))]>;1578 1579def Rol8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),1580 "# Rol8 PSEUDO",1581 [(set i8:$dst, (AVRrolLoop i8:$src, i8:$cnt))]>;1582 1583def Rol16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),1584 "# Rol16 PSEUDO",1585 [(set i16:$dst, (AVRrolLoop i16:$src, i8:$cnt))]>;1586 1587def Ror8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),1588 "# Ror8 PSEUDO",1589 [(set i8:$dst, (AVRrorLoop i8:$src, i8:$cnt))]>;1590 1591def Ror16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),1592 "# Ror16 PSEUDO",1593 [(set i16:$dst, (AVRrorLoop i16:$src, i8:$cnt))]>;1594 1595def Asr8 : ShiftPseudo<(outs GPR8:$dst), (ins GPR8:$src, GPR8:$cnt),1596 "# Asr8 PSEUDO",1597 [(set i8:$dst, (AVRasrLoop i8:$src, i8:$cnt))]>;1598 1599def Asr16 : ShiftPseudo<(outs DREGS:$dst), (ins DREGS:$src, GPR8:$cnt),1600 "# Asr16 PSEUDO",1601 [(set i16:$dst, (AVRasrLoop i16:$src, i8:$cnt))]>;1602 1603def Asr32 : ShiftPseudo<(outs DREGS:$dstlo, DREGS:$dsthi),1604 (ins DREGS:$srclo, DREGS:$srchi, i8imm:$cnt),1605 "# Asr32 PSEUDO",1606 [(set i16:$dstlo, i16:$dsthi,1607 (AVRasrw i16:$srclo, i16:$srchi, i8:$cnt))]>;1608 1609// lowered to a copy from the zero register.1610let usesCustomInserter=1 in1611def CopyZero : Pseudo<(outs GPR8:$rd), (ins), "clrz\t$rd", [(set i8:$rd, 0)]>;1612 1613//===----------------------------------------------------------------------===//1614// Non-Instruction Patterns1615//===----------------------------------------------------------------------===//1616 1617//: TODO: look in x86InstrCompiler.td for odd encoding trick related to1618// add x, 128 -> sub x, -128. Clang is emitting an eor for this (ldi+eor)1619 1620// the add instruction always writes the carry flag1621def : Pat<(addc i8 : $src, i8 : $src2), (ADDRdRr i8 : $src, i8 : $src2)>;1622def : Pat<(addc DREGS:$src, DREGS:$src2), (ADDWRdRr DREGS:$src, DREGS:$src2)>;1623 1624// all sub instruction variants always writes the carry flag1625def : Pat<(subc i8 : $src, i8 : $src2), (SUBRdRr i8 : $src, i8 : $src2)>;1626def : Pat<(subc i16 : $src, i16 : $src2), (SUBWRdRr i16 : $src, i16 : $src2)>;1627def : Pat<(subc i8 : $src, imm : $src2), (SUBIRdK i8 : $src, imm : $src2)>;1628def : Pat<(subc i16 : $src, imm : $src2), (SUBIWRdK i16 : $src, imm : $src2)>;1629 1630// These patterns convert add (x, -imm) to sub (x, imm) since we dont have1631// any add with imm instructions. Also take care of the adiw/sbiw instructions.1632def : Pat<(add i16:$s1, imm0_63_neg:$s2), (SBIWRdK i16:$s1, (imm0_63_neg:$s2))>,1633 Requires<[HasADDSUBIW]>;1634 1635def : Pat<(add i16:$src1, imm:$src2),1636 (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;1637 1638def : Pat<(addc i16:$src1, imm:$src2),1639 (SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;1640 1641def : Pat<(add i8:$src1, imm:$src2),1642 (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;1643 1644def : Pat<(addc i8:$src1, imm:$src2),1645 (SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;1646 1647def : Pat<(adde i8:$src1, imm:$src2),1648 (SBCIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;1649 1650// Emit NEGWRd with an extra zero register operand.1651def : Pat<(ineg i16:$src), (NEGWRd i16:$src, (CopyZero))>;1652 1653// Calls.1654let Predicates = [HasJMPCALL] in {1655 def : Pat<(AVRcall(i16 tglobaladdr:$dst)), (CALLk tglobaladdr:$dst)>;1656 def : Pat<(AVRcall(i16 texternalsym:$dst)), (CALLk texternalsym:$dst)>;1657}1658def : Pat<(AVRcall(i16 tglobaladdr:$dst)), (RCALLk tglobaladdr:$dst)>;1659def : Pat<(AVRcall(i16 texternalsym:$dst)), (RCALLk texternalsym:$dst)>;1660 1661// `anyext`1662// FIMXE: Using INSERT_SUBREG is more efficient, but leads to issue #132203.1663def : Pat<(i16(anyext i8:$src)),1664// (INSERT_SUBREG(i16(IMPLICIT_DEF)), i8:$src, sub_lo)>;1665 (ZEXT i8:$src)>;1666 1667// `trunc`1668def : Pat<(i8(trunc i16 : $src)), (EXTRACT_SUBREG i16 : $src, sub_lo)>;1669 1670// sext_inreg1671def : Pat<(sext_inreg i16:$s, i8), (SEXT(i8(EXTRACT_SUBREG i16:$s, sub_lo)))>;1672 1673// GlobalAddress1674def : Pat<(i16(AVRWrapper tglobaladdr : $dst)), (LDIWRdK tglobaladdr : $dst)>;1675def : Pat<(add i16:$src, (AVRWrapper tglobaladdr:$src2)),1676 (SUBIWRdK i16:$src, tglobaladdr:$src2)>;1677def : Pat<(i8(load(AVRWrapper tglobaladdr:$dst))),1678 (LDSRdK tglobaladdr:$dst)>,1679 Requires<[HasSRAM, HasNonTinyEncoding]>;1680def : Pat<(i8(load(AVRWrapper tglobaladdr:$dst))),1681 (LDSRdKTiny tglobaladdr:$dst)>,1682 Requires<[HasSRAM, HasTinyEncoding]>;1683def : Pat<(i16(load(AVRWrapper tglobaladdr:$dst))),1684 (LDSWRdK tglobaladdr:$dst)>,1685 Requires<[HasSRAM, HasNonTinyEncoding]>;1686def : Pat<(store i8:$src, (i16(AVRWrapper tglobaladdr:$dst))),1687 (STSKRr tglobaladdr:$dst, i8:$src)>,1688 Requires<[HasSRAM, HasNonTinyEncoding]>;1689def : Pat<(store i8:$src, (i16(AVRWrapper tglobaladdr:$dst))),1690 (STSKRrTiny tglobaladdr:$dst, i8:$src)>,1691 Requires<[HasSRAM, HasTinyEncoding]>;1692def : Pat<(store i16:$src, (i16(AVRWrapper tglobaladdr:$dst))),1693 (STSWKRr tglobaladdr:$dst, i16:$src)>,1694 Requires<[HasSRAM, HasNonTinyEncoding]>;1695 1696// BlockAddress1697def : Pat<(i16(AVRWrapper tblockaddress :$dst)), (LDIWRdK tblockaddress:$dst)>;1698 1699def : Pat<(i8(trunc(AVRlsrwn DLDREGS:$src, (i16 8)))),1700 (EXTRACT_SUBREG DREGS:$src, sub_hi)>;1701 1702// :FIXME: DAGCombiner produces an shl node after legalization from these seq:1703// BR_JT -> (mul x, 2) -> (shl x, 1)1704def : Pat<(shl i16 : $src1, (i8 1)), (LSLWRd i16 : $src1)>;1705 1706// Lowering of 'tst' node to 'TST' instruction.1707// TST is an alias of AND Rd, Rd.1708def : Pat<(AVRtst i8 : $rd), (ANDRdRr GPR8 : $rd, GPR8 : $rd)>;1709 1710// Lowering of 'lsl' node to 'LSL' instruction.1711// LSL is an alias of 'ADD Rd, Rd'1712def : Pat<(AVRlsl i8 : $rd), (ADDRdRr GPR8 : $rd, GPR8 : $rd)>;1713