1588 lines · plain
1//===-- CSKYInstrInfo.td - Target Description for CSKY -----*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the CSKY instructions in TableGen format.10//11//===----------------------------------------------------------------------===//12 13 14//===----------------------------------------------------------------------===//15// CSKY specific DAG Nodes.16//===----------------------------------------------------------------------===//17 18// Target-independent type requirements, but with target-specific formats.19def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,20 SDTCisVT<1, i32>]>;21 22def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,23 SDTCisVT<1, i32>]>;24 25def SDT_CSKYCall : SDTypeProfile<0, 2, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;26 27def SDT_CSKYCallReg : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;28 29def SDT_CSKY_LOADADDR : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,30 SDTCisVT<1, iPTR>, SDTCisVT<2, iPTR>]>;31 32def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,33 [SDNPHasChain, SDNPOutGlue]>;34def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,35 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;36 37def CSKY_RET : SDNode<"CSKYISD::RET", SDTNone,38 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;39 40def CSKY_CALL : SDNode<"CSKYISD::CALL", SDT_CSKYCall,41 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;42 43def CSKY_CALLReg : SDNode<"CSKYISD::CALLReg", SDT_CSKYCallReg,44 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;45 46def CSKY_TAIL : SDNode<"CSKYISD::TAIL", SDT_CSKYCall,47 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;48 49def CSKY_TAILReg : SDNode<"CSKYISD::TAILReg", SDT_CSKYCallReg,50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;51 52def CSKY_LOAD_ADDR : SDNode<"CSKYISD::LOAD_ADDR", SDT_CSKY_LOADADDR>;53 54//===----------------------------------------------------------------------===//55// Operand and SDNode transformation definitions.56//===----------------------------------------------------------------------===//57class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass {58 let Name = prefix # "Imm" # width # suffix;59 let RenderMethod = "addImmOperands";60 let DiagnosticType = !strconcat("Invalid", Name);61}62 63class SImmAsmOperand<int width, string suffix = "">64 : ImmAsmOperand<"S", width, suffix> {65}66 67class UImmAsmOperand<int width, string suffix = "">68 : ImmAsmOperand<"U", width, suffix> {69}70 71class OImmAsmOperand<int width, string suffix = "">72 : ImmAsmOperand<"O", width, suffix> {73}74 75def to_tframeindex : SDNodeXForm<frameindex, [{76 auto FI = cast<FrameIndexSDNode>(N);77 return CurDAG->getTargetFrameIndex(FI->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));78}]>;79 80def to_tconstpool : SDNodeXForm<constpool, [{81 auto CP = cast<ConstantPoolSDNode>(N);82 return CurDAG->getTargetConstantPool(CP->getConstVal(), TLI->getPointerTy(CurDAG->getDataLayout()),83 CP->getAlign(), CP->getOffset(), CSKYII::MO_None);84}]>;85 86def to_tconstpool_hi16 : SDNodeXForm<constpool, [{87 auto CP = cast<ConstantPoolSDNode>(N);88 return CurDAG->getTargetConstantPool(CP->getConstVal(), TLI->getPointerTy(CurDAG->getDataLayout()),89 CP->getAlign(), CP->getOffset(), CSKYII::MO_ADDR_HI16);90}]>;91 92def to_tconstpool_lo16 : SDNodeXForm<constpool, [{93 auto CP = cast<ConstantPoolSDNode>(N);94 return CurDAG->getTargetConstantPool(CP->getConstVal(), TLI->getPointerTy(CurDAG->getDataLayout()),95 CP->getAlign(), CP->getOffset(), CSKYII::MO_ADDR_LO16);96}]>;97 98class oimm<int num> : Operand<i32>,99 ImmLeaf<i32, "return isUInt<"#num#">(Imm - 1);"> {100 let EncoderMethod = "getOImmOpValue";101 let ParserMatchClass = OImmAsmOperand<num>;102 let DecoderMethod = "decodeOImmOperand<"#num#">";103}104 105def imm_neg_XFORM : SDNodeXForm<imm, [{106 return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);107}]>;108 109class oimm_neg<int num> : Operand<i32>,110 ImmLeaf<i32, "return isUInt<"#num#">(-Imm - 1);"> {111}112 113class uimm<int num, int shift = 0> : Operand<i32>,114 ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(Imm);"> {115 let EncoderMethod = "getImmOpValue<"#shift#">";116 let ParserMatchClass =117 !if(!ne(shift, 0),118 UImmAsmOperand<num, "Shift"#shift>,119 UImmAsmOperand<num>);120 let DecoderMethod = "decodeUImmOperand<"#num#", "#shift#">";121}122 123class uimm_neg<int num, int shift = 0> : Operand<i32>,124 ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(-Imm);"> {125}126 127class simm<int num, int shift = 0> : Operand<i32>,128 ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {129 let EncoderMethod = "getImmOpValue<"#shift#">";130 let ParserMatchClass = SImmAsmOperand<num>;131 let DecoderMethod = "decodeSImmOperand<"#num#", "#shift#">";132}133 134def nimm_XFORM : SDNodeXForm<imm, [{135 return CurDAG->getTargetConstant(~N->getSExtValue(), SDLoc(N), MVT::i32);136}]>;137class nimm<int num> : Operand<i32>,138 ImmLeaf<i32, "return isUInt<"#num#">(~Imm);", nimm_XFORM> {139 let ParserMatchClass = UImmAsmOperand<num>;140}141 142def uimm32_hi16 : SDNodeXForm<imm, [{143 return CurDAG->getTargetConstant((N->getZExtValue() >> 16) & 0xFFFF,144 SDLoc(N), MVT::i32);145}]>;146def uimm32_lo16 : SDNodeXForm<imm, [{147 return CurDAG->getTargetConstant(N->getZExtValue()& 0xFFFF, SDLoc(N), MVT::i32);148}]>;149def uimm16_16_xform : Operand<i32>,150 ImmLeaf<i32, "return isShiftedUInt<16, 16>(Imm);", uimm32_hi16> {151 let ParserMatchClass = UImmAsmOperand<16>;152 let EncoderMethod = "getImmOpValue";153}154 155def uimm_shift : Operand<i32>, ImmLeaf<i32, "return isUInt<2>(Imm);"> {156 let EncoderMethod = "getImmShiftOpValue";157 let ParserMatchClass = UImmAsmOperand<2>;158 let DecoderMethod = "decodeImmShiftOpValue";159}160 161// Optimize (or x, imm) to (BSETI x, log2(imm)). We should exclude the162// case can be opimized to (ORI32/ORI16 x, imm).163def imm32_1_pop_bit_XFORM : SDNodeXForm<imm, [{164 uint32_t I = N->getZExtValue();165 return CurDAG->getTargetConstant(llvm::Log2_32(I), SDLoc(N),166 N->getValueType(0));167}]>;168def imm32_1_pop_bit : PatLeaf<(imm), [{169 uint32_t I = N->getZExtValue();170 return llvm::popcount(I) == 1 && I > 0xfff;171}]>;172 173// Optimize (and x, imm) to (BCLRI x, log2(~imm)). We should exclude the174// case can be opimized to (ANDNI x, ~imm).175def imm32_1_zero_bit_XFORM : SDNodeXForm<imm, [{176 uint32_t I = ~N->getZExtValue();177 return CurDAG->getTargetConstant(llvm::Log2_32(I), SDLoc(N),178 N->getValueType(0));179}]>;180def imm32_1_zero_bit : PatLeaf<(imm), [{181 uint32_t I = ~N->getZExtValue();182 return llvm::popcount(I) == 1 && I > 0xfff;183}]>;184 185def CSKYSymbol : AsmOperandClass {186 let Name = "CSKYSymbol";187 let RenderMethod = "addImmOperands";188 let DiagnosticType = "InvalidCSKYSymbol";189 let ParserMethod = "parseCSKYSymbol";190}191 192def br_symbol : Operand<OtherVT> {193 let EncoderMethod =194 "getBranchSymbolOpValue<CSKY::fixup_csky_pcrel_imm16_scale2>";195 let ParserMatchClass = CSKYSymbol;196 let DecoderMethod = "decodeSImmOperand<16, 1>";197 let PrintMethod = "printCSKYSymbolOperand";198 let OperandType = "OPERAND_PCREL";199}200 201def call_symbol : Operand<iPTR> {202 let ParserMatchClass = CSKYSymbol;203 let EncoderMethod = "getCallSymbolOpValue";204 let DecoderMethod = "decodeSImmOperand<26, 1>";205 let PrintMethod = "printCSKYSymbolOperand";206 let OperandType = "OPERAND_PCREL";207}208 209def Constpool : AsmOperandClass {210 let Name = "Constpool";211 let RenderMethod = "addConstpoolOperands";212 let DiagnosticType = "InvalidConstpool";213 let ParserMethod = "parseConstpoolSymbol";214}215 216def constpool_symbol : Operand<iPTR> {217 let ParserMatchClass = Constpool;218 let EncoderMethod =219 "getConstpoolSymbolOpValue<CSKY::fixup_csky_pcrel_uimm16_scale4>";220 let DecoderMethod = "decodeUImmOperand<16, 2>";221 let PrintMethod = "printConstpool";222 let OperandType = "OPERAND_PCREL";223}224 225def DataAsmClass : AsmOperandClass {226 let Name = "DataSymbol";227 let RenderMethod = "addConstpoolOperands";228 let DiagnosticType = "InvalidConstpool";229 let ParserMethod = "parseDataSymbol";230}231 232class data_symbol<string reloc, int shift> : Operand<iPTR> {233 let ParserMatchClass = Constpool;234 let EncoderMethod =235 "getDataSymbolOpValue<"#reloc#">";236 let DecoderMethod = "decodeUImmOperand<18, "#shift#">";237 let PrintMethod = "printDataSymbol";238}239 240def bare_symbol : Operand<iPTR> {241 let ParserMatchClass = CSKYSymbol;242 let EncoderMethod = "getBareSymbolOpValue";243 let PrintMethod = "printCSKYSymbolOperand";244 let DecoderMethod = "decodeSImmOperand<18, 1>";245 let OperandType = "OPERAND_PCREL";246}247 248def oimm3 : oimm<3> {249 let MCOperandPredicate = [{250 int64_t Imm;251 if (MCOp.evaluateAsConstantImm(Imm))252 return isUInt<3>(Imm - 1);253 return MCOp.isBareSymbolRef();254 }];255}256def oimm4 : oimm<4>;257def oimm5 : oimm<5> {258 let MCOperandPredicate = [{259 int64_t Imm;260 if (MCOp.evaluateAsConstantImm(Imm))261 return isUInt<5>(Imm - 1);262 return MCOp.isBareSymbolRef();263 }];264}265def oimm6 : oimm<6>;266 267def imm5_idly : Operand<i32>, ImmLeaf<i32,268 "return Imm <= 32 && Imm >= 0;"> {269 let EncoderMethod = "getImmOpValueIDLY";270 let DecoderMethod = "decodeOImmOperand<5>";271}272 273def oimm8 : oimm<8> {274 let MCOperandPredicate = [{275 int64_t Imm;276 if (MCOp.evaluateAsConstantImm(Imm))277 return isUInt<8>(Imm - 1);278 return MCOp.isBareSymbolRef();279 }];280}281def oimm12 : oimm<12> {282 let MCOperandPredicate = [{283 int64_t Imm;284 if (MCOp.evaluateAsConstantImm(Imm))285 return isUInt<12>(Imm - 1);286 return MCOp.isBareSymbolRef();287 }];288}289def oimm16 : oimm<16> {290 let MCOperandPredicate = [{291 int64_t Imm;292 if (MCOp.evaluateAsConstantImm(Imm))293 return isUInt<16>(Imm - 1);294 return MCOp.isBareSymbolRef();295 }];296}297 298def oimm8_neg : oimm_neg<8> {299 let MCOperandPredicate = [{300 int64_t Imm;301 if (MCOp.evaluateAsConstantImm(Imm))302 return isUInt<8>(-Imm - 1);303 return MCOp.isBareSymbolRef();304 }];305}306def oimm12_neg : oimm_neg<12> {307 let MCOperandPredicate = [{308 int64_t Imm;309 if (MCOp.evaluateAsConstantImm(Imm))310 return isUInt<12>(-Imm - 1);311 return MCOp.isBareSymbolRef();312 }];313}314 315def nimm12 : nimm<12>;316 317def uimm1 : uimm<1>;318def uimm2 : uimm<2>;319 320 321def uimm2_jmpix : Operand<i32>,322 ImmLeaf<i32, "return Imm == 16 || Imm == 24 || Imm == 32 || Imm == 40;"> {323 let EncoderMethod = "getImmJMPIX";324 let DecoderMethod = "decodeJMPIXImmOperand";325}326 327def uimm3 : uimm<3>;328def uimm4 : uimm<4>;329def uimm5 : uimm<5> {330 let MCOperandPredicate = [{331 int64_t Imm;332 if (MCOp.evaluateAsConstantImm(Imm))333 return isShiftedUInt<5, 0>(Imm);334 return MCOp.isBareSymbolRef();335 }];336}337def uimm5_msb_size : uimm<5> {338 let EncoderMethod = "getImmOpValueMSBSize";339}340 341def uimm5_1 : uimm<5, 1> {342 let MCOperandPredicate = [{343 int64_t Imm;344 if (MCOp.evaluateAsConstantImm(Imm))345 return isShiftedUInt<5, 1>(Imm);346 return MCOp.isBareSymbolRef();347 }];348}349def uimm5_2 : uimm<5, 2> {350 let MCOperandPredicate = [{351 int64_t Imm;352 if (MCOp.evaluateAsConstantImm(Imm))353 return isShiftedUInt<5, 2>(Imm);354 return MCOp.isBareSymbolRef();355 }];356}357def uimm6 : uimm<6>;358def uimm7 : uimm<7>;359def uimm7_1 : uimm<7, 1>;360def uimm7_2 : uimm<7, 2>{361 let MCOperandPredicate = [{362 int64_t Imm;363 if (MCOp.evaluateAsConstantImm(Imm))364 return isShiftedUInt<7, 2>(Imm);365 return MCOp.isBareSymbolRef();366 }];367}368def uimm7_3 : uimm<7, 3>;369def uimm8 : uimm<8> {370 let MCOperandPredicate = [{371 int64_t Imm;372 if (MCOp.evaluateAsConstantImm(Imm))373 return isShiftedUInt<8, 0>(Imm);374 return MCOp.isBareSymbolRef();375 }];376}377def uimm8_2 : uimm<8, 2> {378 let MCOperandPredicate = [{379 int64_t Imm;380 if (MCOp.evaluateAsConstantImm(Imm))381 return isShiftedUInt<8, 2>(Imm);382 return MCOp.isBareSymbolRef();383 }];384}385def uimm8_3 : uimm<8, 3>;386def uimm8_8 : uimm<8, 8>;387def uimm8_16 : uimm<8, 16>;388def uimm8_24 : uimm<8, 24>;389def uimm12 : uimm<12> {390 let MCOperandPredicate = [{391 int64_t Imm;392 if (MCOp.evaluateAsConstantImm(Imm))393 return isShiftedUInt<12, 0>(Imm);394 return MCOp.isBareSymbolRef();395 }];396}397def uimm12_1 : uimm<12, 1> {398 let MCOperandPredicate = [{399 int64_t Imm;400 if (MCOp.evaluateAsConstantImm(Imm))401 return isShiftedUInt<12, 1>(Imm);402 return MCOp.isBareSymbolRef();403 }];404}405def uimm12_2 : uimm<12, 2> {406 let MCOperandPredicate = [{407 int64_t Imm;408 if (MCOp.evaluateAsConstantImm(Imm))409 return isShiftedUInt<12, 2>(Imm);410 return MCOp.isBareSymbolRef();411 }];412}413def uimm16 : uimm<16> {414 let MCOperandPredicate = [{415 int64_t Imm;416 if (MCOp.evaluateAsConstantImm(Imm))417 return isShiftedUInt<16, 0>(Imm);418 return MCOp.isBareSymbolRef();419 }];420}421def uimm16_8 : uimm<16, 8>;422def uimm16_16 : uimm<16, 16>;423def uimm20 : uimm<20>;424def uimm24 : uimm<24>;425def uimm24_8 : uimm<24, 8>;426 427def uimm5_neg : uimm_neg<5>;428 429def simm8_2 : simm<8, 2>;430 431class RegSeqAsmOperand<string Suffix = ""> : AsmOperandClass {432 let Name = "RegSeq"#Suffix;433 let RenderMethod = "addRegSeqOperands";434 let DiagnosticType = "InvalidRegSeq";435 let ParserMethod = "parseRegSeq";436}437 438def regseq : Operand<iPTR> {439 let EncoderMethod = "getRegisterSeqOpValue";440 let ParserMatchClass = RegSeqAsmOperand<"">;441 let PrintMethod = "printRegisterSeq";442 let DecoderMethod = "DecodeRegSeqOperand";443 let MIOperandInfo = (ops GPR, uimm5);444}445 446def RegListAsmOperand : AsmOperandClass {447 let Name = "RegList";448 let RenderMethod = "addRegListOperands";449 let DiagnosticType = "InvalidRegList";450 let ParserMethod = "parseRegList";451}452 453def reglist : Operand<iPTR> {454 let ParserMatchClass = RegListAsmOperand;455 let PrintMethod = "printRegisterList";456}457 458def PSRFlag : AsmOperandClass {459 let Name = "PSRFlag";460 let RenderMethod = "addImmOperands";461 let DiagnosticType = "InvalidPSRFlag";462 let ParserMethod = "parsePSRFlag";463}464 465def psrflag : Operand<i32>, ImmLeaf<i32, "return isShiftedUInt<5, 0>(Imm);"> {466 let EncoderMethod = "getImmOpValue";467 let ParserMatchClass = PSRFlag;468 let PrintMethod = "printPSRFlag";469}470 471multiclass uimm8SRLXForm<SDNode opc> {472 def _0: SDNodeXForm<opc,473 [{return CurDAG->getTargetConstant((N->getZExtValue() >> 0) & 0xFF, SDLoc(N), MVT::i32);}]>;474 def _8: SDNodeXForm<opc,475 [{return CurDAG->getTargetConstant((N->getZExtValue() >> 8) & 0xFF, SDLoc(N), MVT::i32);}]>;476 def _16: SDNodeXForm<opc,477 [{return CurDAG->getTargetConstant((N->getZExtValue() >> 16) & 0xFF, SDLoc(N), MVT::i32);}]>;478 def _24: SDNodeXForm<opc,479 [{return CurDAG->getTargetConstant((N->getZExtValue() >> 24) & 0xFF, SDLoc(N), MVT::i32);}]>;480}481 482defm uimm8SRL : uimm8SRLXForm<imm>;483 484//===----------------------------------------------------------------------===//485// Instruction Formats486//===----------------------------------------------------------------------===//487 488include "CSKYInstrFormats.td"489 490//===----------------------------------------------------------------------===//491// Instruction definitions.492//===----------------------------------------------------------------------===//493 494class TriOpFrag<dag res> : PatFrag<(ops node: $LHS, node:$MHS, node:$RHS), res>;495class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;496class UnOpFrag<dag res> : PatFrag<(ops node:$Src), res>;497 498def eqToAdd : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs), [{499 return isOrEquivalentToAdd(N);500}]>;501 502def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;503 504 505//===----------------------------------------------------------------------===//506// CSKYPseudo507//===----------------------------------------------------------------------===//508 509// Pessimistically assume the stack pointer will be clobbered510let Defs = [R14], Uses = [R14] in {511def ADJCALLSTACKDOWN : CSKYPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),512 "!ADJCALLSTACKDOWN $amt1, $amt2", [(callseq_start timm:$amt1, timm:$amt2)]>;513def ADJCALLSTACKUP : CSKYPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),514 "!ADJCALLSTACKUP $amt1, $amt2", [(callseq_end timm:$amt1, timm:$amt2)]>;515} // Defs = [R14], Uses = [R14]516 517 518//===----------------------------------------------------------------------===//519// Basic ALU instructions.520//===----------------------------------------------------------------------===//521 522let Predicates = [iHasE2] in {523 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {524 let isAdd = 1 in525 def ADDI32 : I_12<0x0, "addi32", add, oimm12>;526 def SUBI32 : I_12<0x1, "subi32", sub, oimm12>;527 def ORI32 : I_16_ZX<"ori32", uimm16,528 [(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;529 def XORI32 : I_12<0x4, "xori32", xor, uimm12>;530 def ANDI32 : I_12<0x2, "andi32", and, uimm12>;531 def ANDNI32 : I_12<0x3, "andni32", and, nimm12>;532 def LSLI32 : I_5_XZ<0x12, 0x1, "lsli32",533 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),534 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;535 def LSRI32 : I_5_XZ<0x12, 0x2, "lsri32",536 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),537 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;538 def ASRI32 : I_5_XZ<0x12, 0x4, "asri32",539 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),540 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;541 def ROTLI32 : I_5_XZ<0x12, 0x8, "rotli32",542 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),543 [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;544 545 def ROTRI32 : CSKYPseudo<(outs GPR:$rz), (ins GPR:$rx, oimm5:$imm5),546 "rotri32 $rz, $rx, $imm5", []>;547 }548 let isAdd = 1 in549 def ADDU32 : R_YXZ_SP_F1<0x0, 0x1,550 BinOpFrag<(add node:$LHS, node:$RHS)>, "addu32", 1>;551 def SUBU32 : R_YXZ_SP_F1<0x0, 0x4,552 BinOpFrag<(sub node:$LHS, node:$RHS)>, "subu32">;553 554 def MULT32 : R_YXZ_SP_F1<0x21, 0x1,555 BinOpFrag<(mul node:$LHS, node:$RHS)>, "mult32", 1>;556 def AND32 : R_YXZ_SP_F1<0x8, 0x1,557 BinOpFrag<(and node:$LHS, node:$RHS)>, "and32", 1>;558 def ANDN32 : R_YXZ_SP_F1<0x8, 0x2,559 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "andn32">;560 def OR32: R_YXZ_SP_F1<0x9, 0x1,561 BinOpFrag<(or node:$LHS, node:$RHS)>, "or32", 1>;562 def XOR32 : R_YXZ_SP_F1<0x9, 0x2,563 BinOpFrag<(xor node:$LHS, node:$RHS)>, "xor32", 1>;564 def NOR32 : R_YXZ_SP_F1<0x9, 0x4,565 BinOpFrag<(not (or node:$LHS, node:$RHS))>, "nor32", 1>;566 let isCodeGenOnly = 1 in567 def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),568 "not32", [(set GPR:$rz, (not GPR:$rx))]>;569 570 let Size = 8 in571 def NEG32 : CSKYPseudo<(outs GPR:$rd), (ins GPR:$rx), "neg32 $rd, $rx", []>;572 573 let Size = 8 in574 def RSUBI32 : CSKYPseudo<(outs GPR:$rd), (ins GPR:$rx, uimm12:$imm12), "rsubi32 $rd, $rx, $imm12", []>;575 576 def : Pat<(add GPR:$rs1, (oimm12_neg:$im)),577 (SUBI32 GPR:$rs1, (imm_neg_XFORM oimm12_neg:$im))>;578 579 def LSL32 : R_YXZ_SP_F1<0x10, 0x1,580 BinOpFrag<(shl node:$LHS, node:$RHS)>, "lsl32">;581 def LSR32 : R_YXZ_SP_F1<0x10, 0x2,582 BinOpFrag<(srl node:$LHS, node:$RHS)>, "lsr32">;583 def ASR32 : R_YXZ_SP_F1<0x10, 0x4,584 BinOpFrag<(sra node:$LHS, node:$RHS)>, "asr32">;585 def ROTL32 : R_YXZ_SP_F1<0x10, 0x8,586 BinOpFrag<(rotl node:$LHS, (and node:$RHS, 0x1f))>, "rotl32">;587 588 def BMASKI32 : I_5_Z<0b010100, 0x1, "bmaski32", oimm5, []>;589 def LSLC32 : I_5_XZ<0x13, 0x1, "lslc32", (outs GPR:$rz, CARRY:$cout),590 (ins GPR:$rx, oimm5:$imm5), []> {591 bits<0> cout;592 }593 def LSRC32 : I_5_XZ<0x13, 0x2, "lsrc32", (outs GPR:$rz, CARRY:$cout),594 (ins GPR:$rx, oimm5:$imm5), []> {595 bits<0> cout;596 }597 def ASRC32 : I_5_XZ<0x13, 0x4, "asrc32", (outs GPR:$rz, CARRY:$cout),598 (ins GPR:$rx, oimm5:$imm5), []> {599 bits<0> cout;600 }601 def XSR32 : I_5_XZ<0x13, 0x8, "xsr32", (outs GPR:$rz, CARRY:$cout),602 (ins GPR:$rx, oimm5:$imm5, CARRY:$cin), []> {603 bits<0> cout;604 bits<0> cin;605 }606 607 def IXH32 : R_YXZ_SP_F1<0x2, 0x1,608 BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 1)))>, "ixh32">;609 def IXW32 : R_YXZ_SP_F1<0x2, 0x2,610 BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 2)))>, "ixw32">;611 let Predicates = [iHas2E3] in612 def IXD32 : R_YXZ_SP_F1<0x2, 0x4,613 BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 3)))>, "ixd32">;614 615 let isCommutable = 1, isAdd = 1 in616 def ADDC32 : R_YXZ<0x31, 0x0, 0x2, (outs GPR:$rz, CARRY:$cout),617 (ins GPR:$rx, GPR:$ry, CARRY:$cin), "addc32", []> {618 bits<0> cout;619 bits<0> cin;620 }621 def SUBC32 : R_YXZ<0x31, 0x0, 0x8, (outs GPR:$rz, CARRY:$cout),622 (ins GPR:$rx, GPR:$ry, CARRY:$cin), "subc32", []> {623 bits<0> cout;624 bits<0> cin;625 }626 627 def INCF32 : I_5_ZX<0x3, 0x1, "incf32", uimm5, []>;628 def INCT32 : I_5_ZX<0x3, 0x2, "inct32", uimm5, []>;629 def DECF32 : I_5_ZX<0x3, 0x4, "decf32", uimm5, []>;630 def DECT32 : I_5_ZX<0x3, 0x8, "dect32", uimm5, []>;631}632 633let Predicates = [iHas2E3] in {634 def DIVS32 : R_YXZ_SP_F1<0x20, 0x2,635 BinOpFrag<(sdiv node:$LHS, node:$RHS)>, "divs32">;636 def DIVU32 : R_YXZ_SP_F1<0x20, 0x1,637 BinOpFrag<(udiv node:$LHS, node:$RHS)>, "divu32">;638 639 def DECGT32 : I_5_XZ<0x4, 0x1, "decgt32", (outs GPR:$rz, CARRY:$cout),640 (ins GPR:$rx, uimm5:$imm5), []> {641 bits<0> cout;642 }643 def DECLT32 : I_5_XZ<0x4, 0x2, "declt32", (outs GPR:$rz, CARRY:$cout),644 (ins GPR:$rx, uimm5:$imm5), []> {645 bits<0> cout;646 }647 def DECNE32 : I_5_XZ<0x4, 0x4, "decne32", (outs GPR:$rz, CARRY:$cout),648 (ins GPR:$rx, uimm5:$imm5), []> {649 bits<0> cout;650 }651 652 def SEXT32 : I_5_XZ_U<0x16, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "sext32", []>;653 let isCodeGenOnly = 1 in {654 def SEXTB32 : I_5_XZ_US<0x16, 0, 7, "sextb32", sext_inreg, i8>;655 def SEXTH32 : I_5_XZ_US<0x16, 0, 15, "sexth32", sext_inreg, i16>;656 def ZEXTB32 : I_5_XZ_UZ<0x15, 0, 7, "zextb32", 255>;657 def ZEXTH32 : I_5_XZ_UZ<0x15, 0, 15, "zexth32", 65535>;658 }659 def ZEXT32 : I_5_XZ_U<0x15, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "zext32",[]>;660 661 let Constraints = "$rZ = $rz" in662 def INS32 : I_5_XZ_INS<0b010111, (outs GPR:$rz), (ins GPR:$rZ, GPR:$rx, uimm5_msb_size:$msb, uimm5:$lsb), "ins32", []>;663}664 665let Predicates = [iHas3E3r1] in {666def MULTS32 : R_YXZ<0x3e, 0x20, 0x10, (outs GPRPair:$rz),667 (ins GPR:$rx, GPR:$ry), "mul.s32", []>;668def MULTU32 : R_YXZ<0x3e, 0x20, 0x00, (outs GPRPair:$rz),669 (ins GPR:$rx, GPR:$ry), "mul.u32", []>;670 671let Constraints = "$rZ = $rz" in {672def MULATS32 : R_YXZ<0x3e, 0x20, 0x14, (outs GPRPair:$rZ),673 (ins GPRPair:$rz, GPR:$rx, GPR:$ry), "mula.s32", []>;674def MULATU32 : R_YXZ<0x3e, 0x20, 0x04, (outs GPRPair:$rZ),675 (ins GPRPair:$rz, GPR:$rx, GPR:$ry), "mula.u32", []>;676}677}678 679def MULSH32 : R_YXZ<0x31, 0b100100, 0b00001, (outs GPR:$rz),680 (ins GPR:$rx, GPR:$ry), "mulsh32", []>;681 682//===----------------------------------------------------------------------===//683// Load & Store instructions.684//===----------------------------------------------------------------------===//685 686def LD32B : I_LD<AddrMode32B, 0x0, "ld32.b", uimm12>;687def LD32H : I_LD<AddrMode32H, 0x1, "ld32.h", uimm12_1>;688def LD32W : I_LD<AddrMode32WD, 0x2, "ld32.w", uimm12_2>;689 690let OutOperandList = (outs GPRPair:$rz) in691def LD32D : I_LD<AddrMode32WD, 0x3, "ld32.d", uimm12_2>;692 693let Predicates = [iHasE2] in {694 def LD32BS : I_LD<AddrMode32B, 0x4, "ld32.bs", uimm12>;695 def LD32HS : I_LD<AddrMode32H, 0x5, "ld32.hs", uimm12_1>;696 697 def LDM32 : I_5_YX<0b110100, 0b000111,698 (outs), (ins GPR:$rx, regseq:$regs, variable_ops), "ldm32\t$regs, (${rx})", []>;699 def STM32 : I_5_YX<0b110101, 0b000111,700 (outs), (ins GPR:$rx, regseq:$regs, variable_ops), "stm32\t$regs, (${rx})", []>;701 702 let Size = 4, isCodeGenOnly = 0 in {703 def LDQ32 : CSKYPseudo<(outs), (ins GPR:$rx, regseq:$regs, variable_ops),704 "ldq32\t$regs, (${rx})", []>;705 def STQ32 : CSKYPseudo<(outs), (ins GPR:$rx, regseq:$regs, variable_ops),706 "stq32\t$regs, (${rx})", []>;707 }708 709}710 711def ST32B : I_ST<AddrMode32B, 0x0, "st32.b", uimm12>;712def ST32H : I_ST<AddrMode32H, 0x1, "st32.h", uimm12_1>;713def ST32W : I_ST<AddrMode32WD, 0x2, "st32.w", uimm12_2>;714 715let InOperandList = (ins GPRPair:$rz, GPR:$rx, uimm12_2:$imm12 ) in716def ST32D : I_ST<AddrMode32WD, 0x3, "st32.d", uimm12_2>;717 718let Predicates = [iHas2E3] in {719 def LDR32B : I_LDR<0x0, "ldr32.b">;720 def LDR32BS : I_LDR<0x4, "ldr32.bs">;721 def LDR32H : I_LDR<0x1, "ldr32.h">;722 def LDR32HS : I_LDR<0x5, "ldr32.hs">;723 def LDR32W : I_LDR<0x2, "ldr32.w">;724 def STR32B : I_STR<0x0, "str32.b">;725 def STR32H : I_STR<0x1, "str32.h">;726 def STR32W : I_STR<0x2, "str32.w">;727}728 729// Indicate that we're dumping the CR register, so we'll need to730// scavenge a register for it.731let mayStore = 1 in {732def SPILL_CARRY : CSKYPseudo<(outs), (ins CARRY:$cond, GPR:$rx, uimm12_2:$imm),733 "!SPILL_CARRY $cond, $rx, $imm", []>;734}735 736// Indicate that we're restoring the CR register (previously737// spilled), so we'll need to scavenge a register for it.738let mayLoad = 1 in {739def RESTORE_CARRY : CSKYPseudo<(outs CARRY:$cond), (ins GPR:$rx, uimm12_2:$imm),740 "!RESTORE_CARRY $cond, $rx, $imm", []>;741}742 743let mayLoad = 1 in {744def STORE_PAIR : CSKYPseudo<(outs), (ins GPRPair:$rz, GPR:$rx, uimm12_2:$imm),745 "!STORE_PAIR $rz, $rx, $imm", []>;746}747 748let mayLoad = 1 in {749def LOAD_PAIR : CSKYPseudo<(outs GPRPair:$rz), (ins GPR:$rx, uimm12_2:$imm),750 "!LOAD_PAIR $rz, $rx, $imm", []>;751}752 753//===----------------------------------------------------------------------===//754// Compare instructions.755//===----------------------------------------------------------------------===//756let Predicates = [iHasE2] in {757 def CMPNEI32 : I_16_X<0x1A, "cmpnei32", uimm16>;758 def CMPHSI32 : I_16_X<0x18, "cmphsi32", oimm16>;759 def CMPLTI32 : I_16_X<0x19, "cmplti32", oimm16>;760 def CMPLEI32 : CSKYPseudo<(outs CARRY:$ca), (ins GPR:$rx, uimm16:$imm16),761 "cmplei32\t$rx, $imm16", []>;762}763let Predicates = [iHas2E3] in {764 def CMPNE32 : R_YX<0x1, 0x4, "cmpne32">;765 def CMPHS32 : R_YX<0x1, 0x1, "cmphs32">;766 def CMPLT32 : R_YX<0x1, 0x2, "cmplt32">;767 768 def SETC32 : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca), (ins), "setc32",769 []> {770 bits<0> ca;771 let Inst{25 - 21} = 0; //rx772 let Inst{20 - 16} = 0; //ry773 let Inst{15 - 10} = 0x1;774 let Inst{9 - 5} = 0x1;775 let Inst{4 - 0} = 0;776 let isCompare = 1;777 }778 def CLRC32 : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca), (ins), "clrc32",779 []> {780 bits<0> ca;781 let Inst{25 - 21} = 0; //rx782 let Inst{20 - 16} = 0; //ry783 let Inst{15 - 10} = 0x1;784 let Inst{9 - 5} = 0x4;785 let Inst{4 - 0} = 0;786 let isCompare = 1;787 }788 789 def TST32 : R_YX<0x8, 0x4, "tst32">;790 def TSTNBZ32 : R_X<0x8, 0x8, (outs CARRY:$ca), (ins GPR:$rx), "tstnbz32",791 []> {792 bits<0> ca;793 }794}795 796//===----------------------------------------------------------------------===//797// Data move instructions.798//===----------------------------------------------------------------------===//799 800let Predicates= [iHasE2] in {801 let isCodeGenOnly = 1 in {802 def MOVT32 : R_ZX<0x3, 0x2, "movt32", []>;803 def MOVF32 : R_ZX<0x3, 0x1, "movf32", []>;804 }805 def MOVI32 : I_16_MOV<0x10, "movi32", uimm16>;806 let Size = 4, isCodeGenOnly = 0 in807 def BGENI : CSKYPseudo<(outs GPR:$dst), (ins uimm5:$imm), "bgeni\t$dst, $imm", []>;808 def MOVIH32 : I_16_MOV<0x11, "movih32", uimm16_16_xform>;809 def MVC32 : R_Z_1<0x1, 0x8, "mvc32">;810 let isCodeGenOnly = 1 in811 def MOV32 : R_XZ<0x12, 0x1, "mov32">;812 813 let usesCustomInserter = 1 in814 def ISEL32 : CSKYPseudo<(outs GPR:$dst), (ins CARRY:$cond, GPR:$src1, GPR:$src2),815 "!isel32\t$dst, $src1, src2", [(set GPR:$dst, (select CARRY:$cond, GPR:$src1, GPR:$src2))]>;816}817 818let Predicates = [iHas2E3] in {819 def MVCV32 : R_Z_1<0x1, 0x10, "mvcv32">;820 def CLRF32 : R_Z_2<0xB, 0x1, "clrf32">;821 def CLRT32 : R_Z_2<0xB, 0x2, "clrt32">;822}823 824//===----------------------------------------------------------------------===//825// Branch and call instructions.826//===----------------------------------------------------------------------===//827 828let isBranch = 1, isTerminator = 1 in {829 let isBarrier = 1, isPredicable = 1 in830 def BR32 : I_16_L<0x0, (outs), (ins br_symbol:$imm16), "br32\t$imm16",831 [(br bb:$imm16)]>;832 833 def BT32 : I_16_L<0x3, (outs), (ins CARRY:$ca, br_symbol:$imm16),834 "bt32\t$imm16", [(brcond CARRY:$ca, bb:$imm16)]>,835 Requires<[iHasE2]> {836 bits<0> ca;837 }838 def BF32 : I_16_L<0x2, (outs), (ins CARRY:$ca, br_symbol:$imm16),839 "bf32\t$imm16", []>, Requires<[iHasE2]> {840 bits<0> ca;841 }842}843 844let Predicates = [iHas2E3] in {845 def BEZ32 : I_16_X_L<0x8, "bez32", br_symbol>;846 def BNEZ32 : I_16_X_L<0x9, "bnez32", br_symbol>;847 def BHZ32 : I_16_X_L<0xA, "bhz32", br_symbol>;848 def BLSZ32 : I_16_X_L<0xB, "blsz32", br_symbol>;849 def BLZ32 : I_16_X_L<0xC, "blz32", br_symbol>;850 def BHSZ32 : I_16_X_L<0xD, "bhsz32", br_symbol>;851 852 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {853 def JMP32 : I_16_JX<0x6, "jmp32", [(brind GPR:$rx)]>; // jmp to register854 def JMPI32 : I_16_L<0x16, (outs), (ins constpool_symbol:$imm16),855 "jmpi32\t$imm16", []>;856 }857 858 let isCall = 1, Defs = [ R15 ] in859 def JSR32 : I_16_JX<0x7, "jsr32", []>;860 861 let isCall = 1, Defs = [ R15 ] , mayLoad = 1 in862 def JSRI32: I_16_L<0x17, (outs),863 (ins constpool_symbol:$imm16), "jsri32\t$imm16", []>;864}865 866def BNEZAD32 : CSKY32Inst<AddrModeNone, 0x3a,867 (outs GPR:$rx_u), (ins GPR:$rx, br_symbol:$imm16), "bnezad32\t$rx, $imm16", []> {868 bits<5> rx;869 bits<16> imm16;870 let Inst{25 - 21} = 0x1;871 let Inst{20 - 16} = rx;872 let Inst{15 - 0} = imm16;873 let isBranch = 1;874 let isTerminator = 1;875 let Constraints = "$rx_u = $rx";876 let Predicates = [iHas2E3, iHas10E60];877}878 879def BSR32 : J<0x38, (outs), (ins call_symbol:$offset), "bsr32", []>;880 881def BSR32_BR : J<0x38, (outs), (ins call_symbol:$offset), "bsr32", []>{882 let isCodeGenOnly = 1;883 let isBranch = 1;884 let isTerminator = 1;885 let isBarrier = 1;886 let isPredicable = 1;887 let Defs = [ R15 ];888}889 890//===----------------------------------------------------------------------===//891// Symbol address instructions.892//===----------------------------------------------------------------------===//893 894def data_symbol_b : data_symbol<"CSKY::fixup_csky_doffset_imm18", 0>;895def data_symbol_h : data_symbol<"CSKY::fixup_csky_doffset_imm18_scale2", 1>;896def data_symbol_w : data_symbol<"CSKY::fixup_csky_doffset_imm18_scale4", 2> {897 let ParserMatchClass = DataAsmClass;898}899 900let Predicates = [iHas2E3] in {901 902def GRS32 : I_18_Z_L<0x3, "grs32\t$rz, $offset",903 (outs GPR:$rz), (ins bare_symbol:$offset), []>;904 905let Uses = [R28] in {906def LRS32B : I_18_Z_L<0x0, "lrs32.b\t$rz, $offset",907 (outs GPR:$rz), (ins data_symbol_b:$offset), []>;908def LRS32H : I_18_Z_L<0x1, "lrs32.h\t$rz, $offset",909 (outs GPR:$rz), (ins data_symbol_h:$offset), []>;910def LRS32W : I_18_Z_L<0x2, "lrs32.w\t$rz, $offset",911 (outs GPR:$rz), (ins data_symbol_w:$offset), []>;912def SRS32B : I_18_Z_L<0x4, "srs32.b\t$rz, $offset",913 (outs), (ins GPR:$rz, data_symbol_b:$offset), []>;914def SRS32H : I_18_Z_L<0x5, "srs32.h\t$rz, $offset",915 (outs), (ins GPR:$rz, data_symbol_h:$offset), []>;916def SRS32W : I_18_Z_L<0x6, "srs32.w\t$rz, $offset",917 (outs), (ins GPR:$rz, data_symbol_w:$offset), []>;918}919 920def PUSH32 : I_12_PP<0b11111, 0b00000, (outs), (ins reglist:$regs, variable_ops), "push32 $regs">;921 922let Uses = [R14, R15], isReturn = 1, isTerminator = 1, isBarrier = 1 in923def POP32 : I_12_PP<0b11110, 0b00000, (outs), (ins reglist:$regs, variable_ops), "pop32 $regs">;924 925}926 927let mayLoad = 1, mayStore = 0 in {928def LRW32 : I_16_Z_L<0x14, "lrw32", (ins constpool_symbol:$imm16), []>;929let isCodeGenOnly = 1 in930def LRW32_Gen : I_16_Z_L<0x14, "lrw32", (ins bare_symbol:$src1, constpool_symbol:$imm16), []>;931}932 933//===----------------------------------------------------------------------===//934// Atomic and fence instructions.935//===----------------------------------------------------------------------===//936 937let Predicates = [iHasMP1E2] in {938 def BRWARW : BAR<0b01111, "bar.brwarw", 0>;939 def BRWARWS : BAR<0b01111, "bar.brwarws", 1>;940 def BRARW : BAR<0b00111, "bar.brarw", 0>;941 def BRARWS : BAR<0b00111, "bar.brarws", 1>;942 def BRWAW : BAR<0b01110, "bar.brwaw", 0>;943 def BRWAWS : BAR<0b01110, "bar.brwaws", 1>;944 def BRAR : BAR<0b00101, "bar.brar", 0>;945 def BRARS : BAR<0b00101, "bar.brars", 1>;946 def BWAW : BAR<0b01010, "bar.bwaw", 0>;947 def BWAWS : BAR<0b01010, "bar.bwaws", 1>;948 949 def LDEX32W : I_LD<AddrMode32WD, 0x7, "ldex32.w", uimm12_2>;950 let Constraints = "$rd = $rz" in951 def STEX32W : I_LDST<AddrMode32WD, 0x37, 7,952 (outs GPR:$rd), (ins GPR:$rz, GPR:$rx, uimm12_2:$imm12), "stex32.w", []>;953}954 955//===----------------------------------------------------------------------===//956// Other operation instructions.957//===----------------------------------------------------------------------===//958 959let Predicates = [iHas2E3] in {960 def BREV32 : R_XZ<0x18, 0x10, "brev32">;961 def ABS32 : R_XZ<0x0, 0x10, "abs32">;962 def BGENR32 : R_XZ<0x14, 0x2, "bgenr32">;963 def REVB32 : R_XZ<0x18, 0x4, "revb32">;964 def REVH32 : R_XZ<0x18, 0x8, "revh32">;965}966 967let Predicates = [iHasE2] in {968 def FF0 : R_XZ<0x1F, 0x1, "ff0.32">;969 def FF1 : R_XZ<0x1F, 0x2, "ff1.32">;970 def XTRB0 : R_XZ<0x1C, 0x1, "xtrb0.32">;971 def XTRB1 : R_XZ<0x1C, 0x2, "xtrb1.32">;972 def XTRB2 : R_XZ<0x1C, 0x4, "xtrb2.32">;973 def XTRB3 : R_XZ<0x1C, 0x8, "xtrb3.32">;974 def BTSTI32 : I_5_X<0x0A, 0x4, "btsti32", uimm5, []>;975 def BCLRI32 : I_5_XZ<0xA, 0x1, "bclri32",976 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5), []>;977 def BSETI32 : I_5_XZ<0xA, 0x2, "bseti32",978 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5), []>;979}980 981//===----------------------------------------------------------------------===//982// Special instructions.983//===----------------------------------------------------------------------===//984 985def MFFCR : CSKY32Inst<AddrModeNone, 0x30,986 (outs GPR:$rx), (ins), "mfcr\t$rx, fcr", []> {987 bits<5> rx;988 989 let Inst{25 - 21} = 0b00010;990 let Inst{20 - 16} = 0b00001;991 let Inst{15 - 10} = 0b011000;992 let Inst{9 - 5} = 0b00001;993 let Inst{4 - 0} = rx;994 let hasSideEffects = 1;995 let isCodeGenOnly = 1;996}997 998def MTFCR : CSKY32Inst<AddrModeNone, 0x30,999 (outs), (ins GPR:$rx), "mtcr\t$rx, fcr", []> {1000 bits<5> rx;1001 1002 let Inst{25 - 21} = 0b00010;1003 let Inst{20 - 16} = rx;1004 let Inst{15 - 10} = 0b011001;1005 let Inst{9 - 5} = 0b00001;1006 let Inst{4 - 0} = 0b00001;1007 let hasSideEffects = 1;1008 let isCodeGenOnly = 1;1009}1010 1011def SYNC32 : I_5_IMM5<0x30, 0b000001, 0b00001, "sync32", uimm5, []>;1012 1013def SYNC0_32 : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins),1014 "sync32", []> {1015 let Inst{25 - 21} = 0;1016 let Inst{20 - 16} = 0;1017 let Inst{15 - 10} = 0b000001;1018 let Inst{9 - 5} = 0b00001;1019 let Inst{4 - 0} = 0;1020}1021 1022def SYNC_32_I : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins),1023 "sync32.i", []> {1024 let Inst{25 - 21} = 1;1025 let Inst{20 - 16} = 0;1026 let Inst{15 - 10} = 0b000001;1027 let Inst{9 - 5} = 0b00001;1028 let Inst{4 - 0} = 0;1029}1030 1031def SYNC_32_S : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins),1032 "sync32.s", []> {1033 let Inst{25 - 21} = 0b10000;1034 let Inst{20 - 16} = 0;1035 let Inst{15 - 10} = 0b000001;1036 let Inst{9 - 5} = 0b00001;1037 let Inst{4 - 0} = 0;1038}1039 1040def SYNC_32_IS : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins),1041 "sync32.is", []> {1042 let Inst{25 - 21} = 0b10001;1043 let Inst{20 - 16} = 0;1044 let Inst{15 - 10} = 0b000001;1045 let Inst{9 - 5} = 0b00001;1046 let Inst{4 - 0} = 0;1047}1048 1049let Predicates = [iHas2E3] in {1050 def RFI32 : I_5_XZ_PRIVI<0x11, 0x1, "rfi32">;1051 def SCE32 : I_5_IMM5<0x30, 0b000110, 0b00001, "sce32", uimm4, []>;1052}1053let Predicates = [HasExtendLrw] in1054def IDLY32 : I_5_IMM5<0x30, 0b000111, 0b00001, "idly32", imm5_idly, []>;1055def STOP32 : I_5_XZ_PRIVI<0x12, 0x1, "stop32">;1056def WAIT32 : I_5_XZ_PRIVI<0x13, 0x1, "wait32">;1057def DOZE32 : I_5_XZ_PRIVI<0x14, 0x1, "doze32">;1058def WE32 : I_5_XZ_PRIVI<0b010101, 0x1, "we32">;1059def SE32 : I_5_XZ_PRIVI<0b010110, 0x1, "se32">;1060def WSC32 : I_5_XZ_PRIVI<0b001111, 0x1, "wsc32">;1061 1062def CPOP32 : I_CPOP<(outs), (ins uimm5:$cpid, uimm20:$usdef), "cpop32 <$cpid, ${usdef}>">;1063def CPRC32 : I_CP<0b0100, (outs CARRY:$ca), (ins uimm5:$cpid, uimm12:$usdef),1064 "cprc32 <$cpid, ${usdef}>"> {1065 bits<0> ca;1066}1067def CPRCR32 : I_CP_Z<0b0010, (outs GPR:$rz), (ins uimm5:$cpid, uimm12:$usdef), "cprcr32 $rz, <$cpid, ${usdef}>">;1068def CPRGR32 : I_CP_Z<0b0000, (outs GPR:$rz), (ins uimm5:$cpid, uimm12:$usdef), "cprgr32 $rz, <$cpid, ${usdef}>">;1069def CPWCR32 : I_CP_Z<0b0011, (outs), (ins GPR:$rz, uimm5:$cpid, uimm12:$usdef), "cpwcr32 $rz, <$cpid, ${usdef}>">;1070def CPWGR32 : I_CP_Z<0b0001, (outs), (ins GPR:$rz, uimm5:$cpid, uimm12:$usdef), "cpwgr32 $rz, <$cpid, ${usdef}>">;1071 1072let Predicates = [iHas3r2E3r3] in {1073def DCACHE_IALL32 : I_5_CACHE<0b100101, 0b01000, "dcache32.iall">;1074def DCACHE_CALL32 : I_5_CACHE<0b100101, 0b00100, "dcache32.call">;1075def DCACHE_CIALL32 : I_5_CACHE<0b100101, 0b01100, "dcache32.ciall">;1076def DCACHE_IVA32 : I_5_X_CACHE<0b100101, 0b01011, "dcache32.iva">;1077def DCACHE_ISW32: I_5_X_CACHE<0b100101, 0b01010, "dcache32.isw">;1078def DCACHE_CVA32 : I_5_X_CACHE<0b100101, 0b00111, "dcache32.cva">;1079def DCACHE_CVAL32 : I_5_X_CACHE<0b100101, 0b10111, "dcache32.cval1">;1080def DCACHE_CSW32 : I_5_X_CACHE<0b100101, 0b00110, "dcache32.csw">;1081def DCACHE_CIVA32 : I_5_X_CACHE<0b100101, 0b01111, "dcache32.civa">;1082def DCACHE_CISW32 : I_5_X_CACHE<0b100101, 0b01110, "dcache32.cisw">;1083 1084def ICACHE_IALL32 : I_5_CACHE<0b100100, 0b01000, "icache32.iall">;1085def ICACHE_IALLS32 : I_5_CACHE<0b100100, 0b11000, "icache32.ialls">;1086def ICACHE_IVA32 : I_5_X_CACHE<0b100100, 0b01011, "icache32.iva">;1087 1088def TLBI_VAA32 : I_5_X_CACHE<0b100010, 0b00010, "tlbi32.vaa">;1089def TLBI_VAAS32 : I_5_X_CACHE<0b100010, 0b10010, "tlbi32.vaas">;1090def TLBI_ASID32 : I_5_X_CACHE<0b100010, 0b00001, "tlbi32.asid">;1091def TLBI_ASIDS32 : I_5_X_CACHE<0b100010, 0b10001, "tlbi32.asids">;1092def TLBI_VA32 : I_5_X_CACHE<0b100010, 0b00011, "tlbi32.va">;1093def TLBI_VAS32 : I_5_X_CACHE<0b100010, 0b10011, "tlbi32.vas">;1094def TLBI_ALL32 : I_5_CACHE<0b100010, 0b00000, "tlbi32.all">;1095def TLBI_ALLS32 : I_5_CACHE<0b100010, 0b10000, "tlbi32.alls">;1096 1097def L2CACHE_IALL : I_5_CACHE<0b100110, 0b01000, "l2cache.iall">;1098def L2CACHE_CALL : I_5_CACHE<0b100110, 0b00100, "l2cache.call">;1099def L2CACHE_CIALL : I_5_CACHE<0b100110, 0b01100, "l2cache.ciall">;1100}1101 1102def PLDR32 :I_PLDR<AddrMode32WD, 0x36, 0b0110, (outs), (ins GPR:$rx, uimm12_2:$imm12), "pldr32", []>;1103def PLDW32 :I_PLDR<AddrMode32WD, 0x37, 0b0110, (outs), (ins GPR:$rx, uimm12_2:$imm12), "pldw32", []>;1104 1105def TRAP32 : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins uimm2:$imm2), "trap32 ${imm2}", []> {1106 bits<2> imm2;1107 1108 let Inst{25 - 21} = 0;1109 let Inst{20 - 16} = 0;1110 let Inst{15 - 12} = 0b0010;1111 let Inst{11 - 10} = imm2;1112 let Inst{9 - 5} = 0b00001;1113 let Inst{4 - 0} = 0;1114 1115}1116 1117//===----------------------------------------------------------------------===//1118// Instruction Patterns.1119//===----------------------------------------------------------------------===//1120 1121// Load & Store Patterns1122multiclass LdPat<PatFrag LoadOp, ImmLeaf imm_type, Instruction Inst, ValueType Type> {1123 def : Pat<(Type (LoadOp GPR:$rs1)), (Inst GPR:$rs1, 0)>;1124 def : Pat<(Type (LoadOp (i32 frameindex:$rs1))), (Inst (i32 (to_tframeindex tframeindex:$rs1)), 0)>;1125 def : Pat<(Type (LoadOp (add GPR:$rs1, imm_type:$uimm))),1126 (Inst GPR:$rs1, imm_type:$uimm)>;1127 def : Pat<(Type (LoadOp (add frameindex:$rs1, imm_type:$uimm))),1128 (Inst (i32 (to_tframeindex tframeindex:$rs1)), imm_type:$uimm)>;1129 def : Pat<(Type (LoadOp (eqToAdd frameindex:$rs1, imm_type:$uimm))),1130 (Inst (i32 (to_tframeindex tframeindex:$rs1)), imm_type:$uimm)>;1131 def : Pat<(Type (LoadOp (add GPR:$rs1, tglobaladdr:$gd))),1132 (Inst GPR:$rs1, tglobaladdr:$gd)>;1133}1134 1135defm : LdPat<extloadi8, uimm12, LD32B, i32>;1136defm : LdPat<zextloadi8, uimm12, LD32B, i32>;1137let Predicates = [iHasE2] in {1138 defm : LdPat<sextloadi8, uimm12, LD32BS, i32>;1139}1140defm : LdPat<extloadi16, uimm12_1, LD32H, i32>;1141defm : LdPat<zextloadi16, uimm12_1, LD32H, i32>;1142let Predicates = [iHasE2] in {1143defm : LdPat<sextloadi16, uimm12_1, LD32HS, i32>;1144}1145defm : LdPat<load, uimm12_2, LD32W, i32>;1146 1147multiclass LdrPat<PatFrag LoadOp, Instruction Inst, ValueType Type> {1148 def : Pat<(Type (LoadOp (add GPR:$rs1, GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2, 0)>;1149 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 1))))), (Inst GPR:$rs1, GPR:$rs2, 1)>;1150 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 2))))), (Inst GPR:$rs1, GPR:$rs2, 2)>;1151 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 3))))), (Inst GPR:$rs1, GPR:$rs2, 3)>;1152}1153 1154let Predicates = [iHas2E3] in {1155 defm : LdrPat<zextloadi8, LDR32B, i32>;1156 defm : LdrPat<sextloadi8, LDR32BS, i32>;1157 defm : LdrPat<extloadi8, LDR32BS, i32>;1158 defm : LdrPat<zextloadi16, LDR32H, i32>;1159 defm : LdrPat<sextloadi16, LDR32HS, i32>;1160 defm : LdrPat<extloadi16, LDR32HS, i32>;1161 defm : LdrPat<load, LDR32W, i32>;1162}1163 1164multiclass StPat<PatFrag StoreOp, ValueType Type, ImmLeaf imm_type, Instruction Inst> {1165 def : Pat<(StoreOp Type:$rs2, GPR:$rs1), (Inst Type:$rs2, GPR:$rs1, 0)>;1166 def : Pat<(StoreOp Type:$rs2, frameindex:$rs1), (Inst Type:$rs2, (i32 (to_tframeindex tframeindex:$rs1)), 0)>;1167 def : Pat<(StoreOp Type:$rs2, (add GPR:$rs1, imm_type:$uimm12)),1168 (Inst Type:$rs2, GPR:$rs1, imm_type:$uimm12)>;1169 def : Pat<(StoreOp Type:$rs2, (add frameindex:$rs1, imm_type:$uimm12)),1170 (Inst Type:$rs2, (i32 (to_tframeindex tframeindex:$rs1)), imm_type:$uimm12)>;1171 def : Pat<(StoreOp Type:$rs2, (eqToAdd frameindex:$rs1, imm_type:$uimm12)),1172 (Inst Type:$rs2, (i32 (to_tframeindex tframeindex:$rs1)), imm_type:$uimm12)>;1173}1174 1175defm : StPat<truncstorei8, i32, uimm12, ST32B>;1176defm : StPat<truncstorei16, i32, uimm12_1, ST32H>;1177defm : StPat<store, i32, uimm12_2, ST32W>;1178 1179multiclass StrPat<PatFrag StoreOp, ValueType Type, Instruction Inst> {1180 def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, GPR:$rs2)), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 0)>;1181 def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, (shl GPR:$rs2, (i32 1)))), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 1)>;1182 def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, (shl GPR:$rs2, (i32 2)))), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 2)>;1183 def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, (shl GPR:$rs2, (i32 3)))), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 3)>;1184}1185 1186let Predicates = [iHas2E3] in {1187 defm : StrPat<truncstorei8, i32, STR32B>;1188 defm : StrPat<truncstorei16, i32, STR32H>;1189 defm : StrPat<store, i32, STR32W>;1190 1191 // Sext & Zext Patterns1192 def : Pat<(sext_inreg GPR:$src, i1), (SEXT32 GPR:$src, 0, 0)>;1193 def : Pat<(and GPR:$src, 255), (ZEXT32 GPR:$src, 7, 0)>;1194 def : Pat<(and GPR:$src, 65535), (ZEXT32 GPR:$src, 15, 0)>;1195 1196 // Call Patterns1197 def : Pat<(CSKY_CALL tglobaladdr, tconstpool:$src2), (JSRI32 tconstpool:$src2)>;1198 def : Pat<(CSKY_CALL texternalsym, tconstpool:$src2), (JSRI32 tconstpool:$src2)>;1199 def : Pat<(CSKY_TAIL tglobaladdr, tconstpool:$src2), (JMPI32 tconstpool:$src2)>;1200 def : Pat<(CSKY_TAIL texternalsym, tconstpool:$src2), (JMPI32 tconstpool:$src2)>;1201 1202 def : Pat<(CSKY_CALLReg GPR:$src), (JSR32 GPR:$src)>;1203 def : Pat<(CSKY_TAILReg GPR:$src), (JMP32 GPR:$src)>;1204}1205 1206// Symbol address Patterns1207def : Pat<(CSKY_LOAD_ADDR tglobaladdr, tconstpool:$src2), (LRW32 tconstpool:$src2)>;1208def : Pat<(CSKY_LOAD_ADDR tblockaddress, tconstpool:$src2), (LRW32 tconstpool:$src2)>;1209def : Pat<(CSKY_LOAD_ADDR tjumptable:$src1, tconstpool:$src2), (LRW32_Gen tjumptable:$src1, tconstpool:$src2)>;1210def : Pat<(CSKY_LOAD_ADDR texternalsym, tconstpool:$src2), (LRW32 tconstpool:$src2)>;1211def : Pat<(CSKY_LOAD_ADDR tconstpool:$src1, tconstpool:$src2), (LRW32_Gen tconstpool:$src1, tconstpool:$src2)>;1212 1213let Predicates = [iHas2E3] in1214 def : Pat<(i32 constpool:$src), (GRS32 (to_tconstpool tconstpool:$src))>;1215 1216let Predicates = [iHasE2] in1217 def : Pat<(i32 constpool:$src),1218 (ORI32 (MOVIH32 (to_tconstpool_hi16 tconstpool:$src)),1219 (to_tconstpool_lo16 tconstpool:$src))>;1220 1221def : Pat<(i32 (load constpool:$src)), (LRW32 (to_tconstpool tconstpool:$src))>;1222 1223// Branch Patterns.1224let Predicates = [iHasE2] in {1225def : Pat<(brcond CARRY:$ca, bb:$imm16),1226 (BT32 CARRY:$ca, bb:$imm16)>;1227 1228multiclass BTF32Pat0<PatFrag cond0, PatFrag cond1, ImmLeaf imm_ty, Instruction inst> {1229 def : Pat<(brcond (i32 (cond0 GPR:$rs1, uimm16:$rs2)), bb:$imm16),1230 (BT32 (inst GPR:$rs1, imm_ty:$rs2), bb:$imm16)>;1231 def : Pat<(brcond (i32 (cond1 GPR:$rs1, uimm16:$rs2)), bb:$imm16),1232 (BF32 (inst GPR:$rs1, imm_ty:$rs2), bb:$imm16)>;1233}1234 1235defm : BTF32Pat0<setne, seteq, uimm16, CMPNEI32>;1236defm : BTF32Pat0<setuge, setult, oimm16, CMPHSI32>;1237defm : BTF32Pat0<setlt, setge, oimm16, CMPLTI32>;1238 1239def : Pat<(brcond (i32 (setne (and GPR:$rs, imm32_1_pop_bit:$im), 0)), bb:$imm16),1240 (BT32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),1241 bb:$imm16)>;1242def : Pat<(brcond (i32 (seteq (and GPR:$rs, imm32_1_pop_bit:$im), 0)), bb:$imm16),1243 (BF32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),1244 bb:$imm16)>;1245}1246 1247let Predicates = [iHas2E3] in {1248 1249def : Pat<(brcond (i32 (setne GPR:$rs1, GPR:$rs2)), bb:$imm16),1250 (BT32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;1251def : Pat<(brcond (i32 (seteq GPR:$rs1, GPR:$rs2)), bb:$imm16),1252 (BF32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;1253 1254multiclass BTF32Pat1<PatFrag cond0, PatFrag cond1, Instruction cmp,1255 Instruction br> {1256 def : Pat<(brcond (i32 (cond0 GPR:$rs1, GPR:$rs2)), bb:$imm16),1257 (br (cmp GPR:$rs1, GPR:$rs2), bb:$imm16)>;1258 def : Pat<(brcond (i32 (cond1 GPR:$rs1, GPR:$rs2)), bb:$imm16),1259 (br (cmp GPR:$rs2, GPR:$rs1), bb:$imm16)>;1260}1261 1262defm : BTF32Pat1<setuge, setule, CMPHS32, BT32>;1263defm : BTF32Pat1<setult, setugt, CMPHS32, BF32>;1264defm : BTF32Pat1<setlt, setgt, CMPLT32, BT32>;1265defm : BTF32Pat1<setge, setle, CMPLT32, BF32>;1266 1267def : Pat<(brcond (i32 (seteq GPR:$rs1, (i32 0))), bb:$imm16),1268 (BEZ32 GPR:$rs1, bb:$imm16)>;1269def : Pat<(brcond (i32 (setne GPR:$rs1, (i32 0))), bb:$imm16),1270 (BNEZ32 GPR:$rs1, bb:$imm16)>;1271def : Pat<(brcond (i32 (setlt GPR:$rs1, (i32 0))), bb:$imm16),1272 (BLZ32 GPR:$rs1, bb:$imm16)>;1273def : Pat<(brcond (i32 (setlt GPR:$rs1, (i32 1))), bb:$imm16),1274 (BLSZ32 GPR:$rs1, bb:$imm16)>;1275def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 0))), bb:$imm16),1276 (BHSZ32 GPR:$rs1, bb:$imm16)>;1277def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 1))), bb:$imm16),1278 (BHZ32 GPR:$rs1, bb:$imm16)>;1279def : Pat<(brcond (i32 (setgt GPR:$rs1, (i32 0))), bb:$imm16),1280 (BHZ32 GPR:$rs1, bb:$imm16)>;1281def : Pat<(brcond (i32 (setgt GPR:$rs1, (i32 -1))), bb:$imm16),1282 (BHSZ32 GPR:$rs1, bb:$imm16)>;1283def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 0))), bb:$imm16),1284 (BLSZ32 GPR:$rs1, bb:$imm16)>;1285def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 -1))), bb:$imm16),1286 (BLZ32 GPR:$rs1, bb:$imm16)>;1287}1288 1289// Compare Patterns.1290let Predicates = [iHas2E3] in {1291 def : Pat<(setne GPR:$rs1, GPR:$rs2),1292 (CMPNE32 GPR:$rs1, GPR:$rs2)>;1293 def : Pat<(setne (and GPR:$rs, imm32_1_pop_bit:$im), 0),1294 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im))>;1295 def : Pat<(i32 (seteq GPR:$rs1, GPR:$rs2)),1296 (MVCV32 (CMPNE32 GPR:$rs1, GPR:$rs2))>;1297 def : Pat<(setuge GPR:$rs1, GPR:$rs2),1298 (CMPHS32 GPR:$rs1, GPR:$rs2)>;1299 def : Pat<(setule GPR:$rs1, GPR:$rs2),1300 (CMPHS32 GPR:$rs2, GPR:$rs1)>;1301 def : Pat<(i32 (setult GPR:$rs1, GPR:$rs2)),1302 (MVCV32 (CMPHS32 GPR:$rs1, GPR:$rs2))>;1303 def : Pat<(i32 (setugt GPR:$rs1, GPR:$rs2)),1304 (MVCV32 (CMPHS32 GPR:$rs2, GPR:$rs1))>;1305 def : Pat<(setlt GPR:$rs1, GPR:$rs2),1306 (CMPLT32 GPR:$rs1, GPR:$rs2)>;1307 def : Pat<(setgt GPR:$rs1, GPR:$rs2),1308 (CMPLT32 GPR:$rs2, GPR:$rs1)>;1309 def : Pat<(i32 (setge GPR:$rs1, GPR:$rs2)),1310 (MVCV32 (CMPLT32 GPR:$rs1, GPR:$rs2))>;1311 def : Pat<(i32 (setle GPR:$rs1, GPR:$rs2)),1312 (MVCV32 (CMPLT32 GPR:$rs2, GPR:$rs1))>;1313}1314 1315let Predicates = [iHasE2] in {1316 def : Pat<(setne GPR:$rs1, uimm16:$rs2),1317 (CMPNEI32 GPR:$rs1, uimm16:$rs2)>;1318 let Predicates = [iHas2E3] in1319 def : Pat<(i32 (seteq GPR:$rs1, uimm16:$rs2)),1320 (MVCV32 (CMPNEI32 GPR:$rs1, uimm16:$rs2))>;1321 def : Pat<(setuge GPR:$rs1, oimm16:$rs2),1322 (CMPHSI32 GPR:$rs1, oimm16:$rs2)>;1323 let Predicates = [iHas2E3] in1324 def : Pat<(i32 (setult GPR:$rs1, oimm16:$rs2)),1325 (MVCV32 (CMPHSI32 GPR:$rs1, oimm16:$rs2))>;1326 def : Pat<(setlt GPR:$rs1, oimm16:$rs2),1327 (CMPLTI32 GPR:$rs1, oimm16:$rs2)>;1328 let Predicates = [iHas2E3] in1329 def : Pat<(i32 (setge GPR:$rs1, oimm16:$rs2)),1330 (MVCV32 (CMPLTI32 GPR:$rs1, oimm16:$rs2))>;1331}1332 1333// Select Patterns.1334let Predicates = [iHasE2] in {1335 1336def : Pat<(select (i32 (setne GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),1337 (INCT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;1338def : Pat<(select (i32 (seteq GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),1339 (INCF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;1340def : Pat<(select (i32 (setne GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false),1341 (DECT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx,1342 (imm_neg_XFORM uimm5_neg:$imm))>;1343def : Pat<(select (i32 (seteq GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false),1344 (DECF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx,1345 (imm_neg_XFORM uimm5:$imm))>;1346 1347multiclass INCDECPat<PatFrag cond0, PatFrag cond1, Instruction cmp> {1348 def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),1349 (INCT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;1350 def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),1351 (INCF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;1352 def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),1353 (INCF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;1354 def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),1355 (INCT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;1356 def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),1357 (DECT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx,1358 (imm_neg_XFORM uimm5_neg:$imm))>;1359 def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),1360 (DECF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx,1361 (imm_neg_XFORM uimm5_neg:$imm))>;1362 def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),1363 (DECF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx,1364 (imm_neg_XFORM uimm5_neg:$imm))>;1365 def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),1366 (DECT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx,1367 (imm_neg_XFORM uimm5_neg:$imm))>;1368}1369 1370defm : INCDECPat<setuge, setult, CMPHSI32>;1371defm : INCDECPat<setlt, setge, CMPLTI32>;1372 1373def : Pat<(select CARRY:$ca, (add GPR:$rx, uimm5:$imm), GPR:$other),1374 (INCT32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>;1375def : Pat<(select CARRY:$ca, GPR:$other, (add GPR:$rx, uimm5:$imm)),1376 (INCF32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>;1377def : Pat<(select (and CARRY:$ca, 1), (add GPR:$rx, uimm5:$imm), GPR:$other),1378 (INCT32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>;1379def : Pat<(select (and CARRY:$ca, 1), GPR:$other, (add GPR:$rx, uimm5:$imm)),1380 (INCF32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>;1381 1382def : Pat<(select CARRY:$ca, (add GPR:$rx, uimm5_neg:$imm), GPR:$other),1383 (DECT32 CARRY:$ca, GPR:$other, GPR:$rx, (imm_neg_XFORM uimm5_neg:$imm))>;1384def : Pat<(select CARRY:$ca, GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),1385 (DECF32 CARRY:$ca, GPR:$other, GPR:$rx, (imm_neg_XFORM uimm5_neg:$imm))>;1386def : Pat<(select (and CARRY:$ca, 1), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),1387 (DECT32 CARRY:$ca, GPR:$other, GPR:$rx, (imm_neg_XFORM uimm5_neg:$imm))>;1388def : Pat<(select (and CARRY:$ca, 1), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),1389 (DECF32 CARRY:$ca, GPR:$other, GPR:$rx, (imm_neg_XFORM uimm5_neg:$imm))>;1390 1391def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),1392 (MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>;1393def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),1394 (MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>;1395 1396multiclass MOVTF32Pat0<PatFrag cond0, PatFrag cond1, ImmLeaf imm_ty, Instruction inst> {1397 def : Pat<(select (i32 (cond0 GPR:$rs1, imm_ty:$rs2)), GPR:$rx, GPR:$false),1398 (MOVT32 (inst GPR:$rs1, imm_ty:$rs2), GPR:$rx, GPR:$false)>;1399 def : Pat<(select (i32 (cond1 GPR:$rs1, imm_ty:$rs2)), GPR:$rx, GPR:$false),1400 (MOVF32 (inst GPR:$rs1, imm_ty:$rs2), GPR:$rx, GPR:$false)>;1401}1402 1403defm : MOVTF32Pat0<setne, seteq, uimm16, CMPNEI32>;1404defm : MOVTF32Pat0<setuge, setult, oimm16, CMPHSI32>;1405defm : MOVTF32Pat0<setlt, setge, oimm16, CMPLTI32>;1406 1407def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),1408 (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;1409def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),1410 (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;1411 1412def : Pat<(select (i32 (setne (and GPR:$rs, imm32_1_pop_bit:$im), 0)),1413 GPR:$true, GPR:$false),1414 (MOVT32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),1415 GPR:$true, GPR:$false)>;1416def : Pat<(select (i32 (seteq (and GPR:$rs, imm32_1_pop_bit:$im), 0)),1417 GPR:$true, GPR:$false),1418 (MOVF32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),1419 GPR:$true, GPR:$false)>;1420}1421 1422let Predicates = [iHas2E3] in {1423def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),1424 (INCT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;1425def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),1426 (INCF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;1427def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false),1428 (DECT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx,1429 (imm_neg_XFORM uimm5_neg:$imm))>;1430def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false),1431 (DECF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx,1432 (imm_neg_XFORM uimm5_neg:$imm))>;1433 1434multiclass INCPat<PatFrag cond0, PatFrag cond1, Instruction cmp, Instruction inc0, Instruction inc1> {1435 def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),1436 (inc0 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;1437 def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),1438 (inc1 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;1439 def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),1440 (inc0 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>;1441 def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),1442 (inc1 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>;1443}1444 1445defm : INCPat<setuge, setule, CMPHS32, INCT32, INCF32>;1446defm : INCPat<setult, setugt, CMPHS32, INCF32, INCT32>;1447defm : INCPat<setlt, setgt, CMPLT32, INCT32, INCF32>;1448defm : INCPat<setge, setle, CMPLT32, INCF32, INCT32>;1449 1450multiclass DECPat<PatFrag cond0, PatFrag cond1, Instruction cmp, Instruction dec0, Instruction dec1> {1451 def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),1452 (dec0 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx,1453 (imm_neg_XFORM uimm5_neg:$imm))>;1454 def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),1455 (dec1 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx,1456 (imm_neg_XFORM uimm5_neg:$imm))>;1457 def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),1458 (dec0 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx,1459 (imm_neg_XFORM uimm5_neg:$imm))>;1460 def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),1461 (dec1 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx,1462 (imm_neg_XFORM uimm5_neg:$imm))>;1463}1464 1465defm : DECPat<setuge, setule, CMPHS32, DECT32, DECF32>;1466defm : DECPat<setult, setugt, CMPHS32, DECF32, DECT32>;1467defm : DECPat<setlt, setgt, CMPLT32, DECT32, DECF32>;1468defm : DECPat<setge, setle, CMPLT32, DECF32, DECT32>;1469 1470def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),1471 (MOVT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;1472def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),1473 (MOVF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;1474 1475multiclass MOVTF32Pat1<PatFrag cond0, PatFrag cond1, Instruction cmp_inst,1476 Instruction mov_inst> {1477 def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),1478 (mov_inst (cmp_inst GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;1479 def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),1480 (mov_inst (cmp_inst GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;1481}1482 1483defm : MOVTF32Pat1<setuge, setule, CMPHS32, MOVT32>;1484defm : MOVTF32Pat1<setult, setugt, CMPHS32, MOVF32>;1485defm : MOVTF32Pat1<setlt, setgt, CMPLT32, MOVT32>;1486defm : MOVTF32Pat1<setge, setle, CMPLT32, MOVF32>;1487 1488def : Pat<(select CARRY:$ca, (i32 0), GPR:$other),1489 (CLRT32 CARRY:$ca, GPR:$other)>;1490def : Pat<(select CARRY:$ca, GPR:$other, (i32 0)),1491 (CLRF32 CARRY:$ca, GPR:$other)>;1492}1493 1494// Constant materialize patterns.1495let Predicates = [iHasE2] in1496 def : Pat<(i32 imm:$imm),1497 (ORI32 (MOVIH32 (uimm32_hi16 imm:$imm)), (uimm32_lo16 imm:$imm))>;1498 1499// Bit operations.1500let Predicates = [iHasE2] in {1501 def : Pat<(or GPR:$rs, imm32_1_pop_bit:$imm),1502 (BSETI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$imm))>;1503 def : Pat<(and GPR:$rs, imm32_1_zero_bit:$imm),1504 (BCLRI32 GPR:$rs, (imm32_1_zero_bit_XFORM imm32_1_zero_bit:$imm))>;1505}1506 1507// Other operations.1508let Predicates = [iHasE2] in {1509 def : Pat<(rotl GPR:$rs1, GPR:$rs2),1510 (ROTL32 GPR:$rs1, (ANDI32 GPR:$rs2, 0x1f))>;1511 let Predicates = [iHas2E3] in {1512 def : Pat<(bitreverse GPR:$rx), (BREV32 GPR:$rx)>;1513 def : Pat<(bswap GPR:$rx), (REVB32 GPR:$rx)>;1514 def : Pat<(i32 (cttz GPR:$rx)), (FF1 (BREV32 GPR:$rx))>;1515 }1516 def : Pat<(i32 (ctlz GPR:$rx)), (FF1 GPR:$rx)>;1517}1518 1519//===----------------------------------------------------------------------===//1520// Pseudo for assembly1521//===----------------------------------------------------------------------===//1522 1523let isCall = 1, Defs = [ R15 ], mayLoad = 1, Size = 4, isCodeGenOnly = 0 in1524def JBSR32 : CSKYPseudo<(outs), (ins call_symbol:$src1), "jbsr32\t$src1", []>;1525 1526def JBR32 : CSKYPseudo<(outs), (ins br_symbol:$src1), "jbr32\t$src1", []> {1527 let isBranch = 1;1528 let isTerminator = 1;1529 let isBarrier = 1;1530 let isIndirectBranch = 1;1531 let mayLoad = 1;1532 let Size = 4;1533}1534 1535def JBT32 : CSKYPseudo<(outs), (ins CARRY:$ca, br_symbol:$src1), "jbt32\t$src1", []> {1536 let isBranch = 1;1537 let isTerminator = 1;1538 let isIndirectBranch = 1;1539 let mayLoad = 1;1540 let Size = 4;1541}1542 1543def JBF32 : CSKYPseudo<(outs), (ins CARRY:$ca, br_symbol:$src1), "jbf32\t$src1", []> {1544 let isBranch = 1;1545 let isTerminator = 1;1546 let isIndirectBranch = 1;1547 let mayLoad = 1;1548 let Size = 4;1549}1550 1551def JBT_E : CSKYPseudo<(outs), (ins CARRY:$ca, br_symbol:$src1), "!jbt_e\t$src1", []> {1552 let isBranch = 1;1553 let isTerminator = 1;1554 let isIndirectBranch = 1;1555 let mayLoad = 1;1556 let Size = 6;1557}1558 1559def JBF_E : CSKYPseudo<(outs), (ins CARRY:$ca, br_symbol:$src1), "!jbf_e\t$src1", []> {1560 let isBranch = 1;1561 let isTerminator = 1;1562 let isIndirectBranch = 1;1563 let mayLoad = 1;1564 let Size = 6;1565}1566 1567let mayLoad = 1, Size = 2, isCodeGenOnly = 0 in1568def PseudoLRW32 : CSKYPseudo<(outs GPR:$rz), (ins bare_symbol:$src), "lrw32 $rz, $src", []>;1569 1570let mayLoad = 1, Size = 4, isCodeGenOnly = 0 in1571def PseudoJSRI32 : CSKYPseudo<(outs), (ins call_symbol:$src), "jsri32 $src", []>;1572 1573let mayLoad = 1, Size = 4, isCodeGenOnly = 0 in1574def PseudoJMPI32 : CSKYPseudo<(outs), (ins br_symbol:$src), "jmpi32 $src", []>;1575 1576let isNotDuplicable = 1, mayLoad = 1, mayStore = 0, Size = 8 in1577def PseudoTLSLA32 : CSKYPseudo<(outs GPR:$dst1, GPR:$dst2),1578 (ins constpool_symbol:$src, i32imm:$label), "!tlslrw32\t$dst1, $dst2, $src, $label", []>;1579 1580let hasSideEffects = 0, isNotDuplicable = 1 in1581def CONSTPOOL_ENTRY : CSKYPseudo<(outs),1582 (ins i32imm:$instid, i32imm:$cpidx, i32imm:$size), "", []>;1583 1584include "CSKYInstrInfo16Instr.td"1585include "CSKYInstrInfoF1.td"1586include "CSKYInstrInfoF2.td"1587include "CSKYInstrAlias.td"1588