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1//===-- CSKYInstrInfo16Instr.td - CSKY 16-bit Instruction --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the CSKY 16-bit instructions in TableGen format.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// CSKY specific DAG Nodes.15//===----------------------------------------------------------------------===//16 17// Target-dependent nodes.18def CSKY_NIE : SDNode<"CSKYISD::NIE", SDTNone,19 [SDNPHasChain, SDNPOptInGlue]>;20def CSKY_NIR : SDNode<"CSKYISD::NIR", SDTNone,21 [SDNPHasChain, SDNPOptInGlue]>;22 23//===----------------------------------------------------------------------===//24// Operand and SDNode transformation definitions.25//===----------------------------------------------------------------------===//26 27def br_symbol_16bit : Operand<OtherVT> {28 let EncoderMethod =29 "getBranchSymbolOpValue<CSKY::fixup_csky_pcrel_imm10_scale2>";30 let ParserMatchClass = CSKYSymbol;31 let DecoderMethod = "decodeSImmOperand<10, 1>";32 let PrintMethod = "printCSKYSymbolOperand";33 let OperandType = "OPERAND_PCREL";34}35 36def constpool_symbol_16bit : Operand<iPTR> {37 let ParserMatchClass = Constpool;38 let EncoderMethod =39 "getConstpoolSymbolOpValue<CSKY::fixup_csky_pcrel_uimm7_scale4>";40 let DecoderMethod = "decodeLRW16Imm8";41 let PrintMethod = "printConstpool";42 let OperandType = "OPERAND_PCREL";43}44 45//===----------------------------------------------------------------------===//46// Instruction Formats47//===----------------------------------------------------------------------===//48 49include "CSKYInstrFormats16Instr.td"50 51//===----------------------------------------------------------------------===//52// Instruction definitions.53//===----------------------------------------------------------------------===//54 55//===----------------------------------------------------------------------===//56// Basic ALU instructions.57//===----------------------------------------------------------------------===//58 59let isCommutable = 1, isAdd = 1 in60 def ADDU16 : R16_XYZ<0, "addu16", add>;61let Pattern = [(set mGPR:$rz, (sub mGPR:$rx, mGPR:$ry))] in62 def SUBU16 : R16_XYZ<1, "subu16", sub>;63 64let isCommutable = 1, isAdd = 1 in65 def ADDC16 : R16_XZ_BINOP_C<0b1000, 0b01, "addc16">;66def SUBC16 : R16_XZ_BINOP_C<0b1000, 0b11, "subc16">;67 68let isCommutable = 1 in {69 let isAdd = 1 in70 def ADDU16XZ : R16_XZ_BINOP<0b1000, 0b00, "addu16", BinOpFrag<(add node:$LHS, node:$RHS)>>;71 def AND16 : R16_XZ_BINOP<0b1010, 0b00, "and16", BinOpFrag<(and node:$LHS, node:$RHS)>>;72 def OR16 : R16_XZ_BINOP<0b1011, 0b00, "or16", BinOpFrag<(or node:$LHS, node:$RHS)>>;73 def XOR16 : R16_XZ_BINOP<0b1011, 0b01, "xor16", BinOpFrag<(xor node:$LHS, node:$RHS)>>;74 def NOR16 : R16_XZ_BINOP<0b1011, 0b10, "nor16", BinOpFrag<(not (or node:$LHS, node:$RHS))>>;75 let isCodeGenOnly = 1 in76 def NOT16 : R16_Z_UNOP<0b1011, 0b10, "not16">;77 def MULT16 : R16_XZ_BINOP<0b1111, 0b00, "mult16", BinOpFrag<(mul node:$LHS, node:$RHS)>>;78}79def SUBU16XZ : R16_XZ_BINOP<0b1000, 0b10, "subu16", BinOpFrag<(sub node:$LHS, node:$RHS)>>;80def ANDN16 : R16_XZ_BINOP<0b1010, 0b01, "andn16", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;81def LSL16 : R16_XZ_BINOP<0b1100, 0b00, "lsl16", BinOpFrag<(shl node:$LHS, node:$RHS)>>;82def LSR16 : R16_XZ_BINOP<0b1100, 0b01, "lsr16", BinOpFrag<(srl node:$LHS, node:$RHS)>>;83def ASR16 : R16_XZ_BINOP<0b1100, 0b10, "asr16", BinOpFrag<(sra node:$LHS, node:$RHS)>>;84def ROTL16 : R16_XZ_BINOP<0b1100, 0b11, "rotl16", BinOpFrag<(rotl node:$LHS, (and node:$RHS, 0x1f))>>;85 86def MULSH16 : R16_XZ_BINOP_NOPat<0b1111, 0b01, "mulsh16">;87 88def ZEXTB16 : R16_XZ_UNOP<0b1101, 0b00, "zextb16">;89def ZEXTH16 : R16_XZ_UNOP<0b1101, 0b01, "zexth16">;90def SEXTB16 : R16_XZ_UNOP<0b1101, 0b10, "sextb16">;91def SEXTH16 : R16_XZ_UNOP<0b1101, 0b11, "sexth16">;92 93let Constraints = "$rZ = $rz", isReMaterializable = 1, isAsCheapAsAMove = 1 in {94 let isAdd = 1, Pattern = [(set mGPR:$rz, (add mGPR:$rZ, oimm8:$imm8))] in95 def ADDI16 : I16_Z_8<0b100, (ins mGPR:$rZ, oimm8:$imm8), "addi16\t$rz, $imm8">;96 let Pattern = [(set mGPR:$rz, (sub mGPR:$rZ, oimm8:$imm8))] in97 def SUBI16 : I16_Z_8<0b101, (ins mGPR:$rZ, oimm8:$imm8), "subi16\t$rz, $imm8">;98}99 100def : Pat<(add GPR:$rs1, (oimm8_neg:$im)),101 (SUBI16 GPR:$rs1, (imm_neg_XFORM oimm8_neg:$im))>;102 103let isAdd = 1 in104def ADDI16ZSP : I16_Z_8<0b011, (ins GPRSP:$sp, uimm8_2:$imm8),105 "addi16\t$rz, $sp, $imm8"> {106 bits<0> sp;107}108 109let isAdd = 1 in110def ADDI16SPSP : I16_SP_IMM7<0b000,"addi16">;111def SUBI16SPSP : I16_SP_IMM7<0b001,"subi16">;112 113let isReMaterializable = 1, isAsCheapAsAMove = 1 in {114 def LSLI16 : I16_XZ_IMM5<0, "lsli16", shl>;115 def LSRI16 : I16_XZ_IMM5<1, "lsri16", srl>;116 def ASRI16 : I16_XZ_IMM5<2, "asri16", sra>;117}118 119let isAdd = 1 in120def ADDI16XZ : I16_XZ_IMM3<0b10, "addi16", add>;121def SUBI16XZ : I16_XZ_IMM3<0b11, "subi16", sub>;122 123let Size = 4 in124def NEG16 : CSKYPseudo<(outs mGPR:$rd), (ins mGPR:$rx), "neg16 $rd, $rx", []>;125 126let Size = 4 in127def RSUBI16 : CSKYPseudo<(outs mGPR:$rd),128 (ins mGPR:$rx, uimm8:$imm8), "rsubi16 $rd, $rx, $imm8", []>;129 130//===----------------------------------------------------------------------===//131// Load & Store instructions.132//===----------------------------------------------------------------------===//133 134def LD16B : I16_XZ_LDST<AddrMode16B, 0b000, "ld16.b",135 (outs mGPR:$rz), (ins mGPR:$rx, uimm5:$imm)>;136def LD16H : I16_XZ_LDST<AddrMode16H, 0b001, "ld16.h",137 (outs mGPR:$rz), (ins mGPR:$rx, uimm5_1:$imm)>;138def LD16W : I16_XZ_LDST<AddrMode16W, 0b010, "ld16.w",139 (outs mGPR:$rz), (ins mGPR:$rx, uimm5_2:$imm)>;140def ST16B : I16_XZ_LDST<AddrMode16B, 0b100, "st16.b",141 (outs), (ins mGPR:$rz, mGPR:$rx, uimm5:$imm)>;142def ST16H : I16_XZ_LDST<AddrMode16H, 0b101, "st16.h",143 (outs), (ins mGPR:$rz, mGPR:$rx, uimm5_1:$imm)>;144def ST16W : I16_XZ_LDST<AddrMode16W, 0b110, "st16.w",145 (outs), (ins mGPR:$rz, mGPR:$rx, uimm5_2:$imm)>;146 147def LD16WSP : I16_ZSP_LDST<AddrMode16W, 0b011, "ld16.w", (outs mGPR:$rz),148 (ins GPRSP:$sp, uimm8_2:$addr)> {149 bits<0> sp;150}151def ST16WSP : I16_ZSP_LDST<AddrMode16W, 0b111, "st16.w", (outs),152 (ins mGPR:$rz, GPRSP:$sp, uimm8_2:$addr)> {153 bits<0> sp;154}155 156//===----------------------------------------------------------------------===//157// Compare instructions.158//===----------------------------------------------------------------------===//159 160def CMPHS16 : R16_XY_CMP<0, "cmphs16">;161def CMPLT16 : R16_XY_CMP<1, "cmplt16">;162let isCommutable = 1 in163def CMPNE16 : R16_XY_CMP<2, "cmpne16">;164 165 166def CMPHSI16 : I16_X_CMP<0, "cmphsi16", oimm5>;167def CMPLTI16 : I16_X_CMP<1, "cmplti16", oimm5>;168def CMPLEI16 : CSKYPseudo<(outs CARRY:$ca), (ins mGPR:$rx, uimm5:$imm5),169 "cmplei16\t$rx, $imm5", []>;170def CMPNEI16 : I16_X_CMP<2, "cmpnei16", uimm5>;171 172//===----------------------------------------------------------------------===//173// Data move instructions.174//===----------------------------------------------------------------------===//175 176 177def MOVI16 : I16_Z_8<0b110, (ins uimm8:$imm8), "movi16\t$rz, $imm8"> {178 let isReMaterializable = 1;179 let isAsCheapAsAMove = 1;180 let isMoveImm = 1;181 let Pattern = [(set mGPR:$rz, uimm8:$imm8)];182}183 184def MOV16 : CSKY16Inst<AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rx),185 "mov16\t$rz, $rx", []> {186 bits<4> rz;187 bits<4> rx;188 let Inst{15,14} = 0b01;189 let Inst{13 - 10} = 0b1011;190 let Inst{9 - 6} = rz;191 let Inst{5 - 2} = rx;192 let Inst{1,0} = 0b11;193}194 195// MVC16 is not in "cskyv2 instructions reference manul"196def MVCV16 : CSKY16Inst<AddrModeNone, (outs sGPR:$rz), (ins CARRY:$ca),197 "mvcv16\t$rz", []> {198 bits<0> ca;199 bits<4> rz;200 let Inst{15,14} = 0b01;201 let Inst{13 - 10} = 0b1001;202 let Inst{9 - 6} = rz;203 let Inst{5 - 2} = 0;204 let Inst{1,0} = 0b11;205}206 207 208//===----------------------------------------------------------------------===//209// Branch and call instructions.210//===----------------------------------------------------------------------===//211 212let isBranch = 1, isTerminator = 1 in {213 let isBarrier = 1, isPredicable = 1 in214 def BR16 : J16<1, "br16", (ins br_symbol_16bit:$offset)>;215 216 def BT16 : J16_B<2, "bt16">;217 def BF16 : J16_B<3, "bf16">;218}219 220def JMP16 : R16_X_J<0b11100000, 0b00, "jmp16"> {221 let isBranch = 1;222 let isTerminator = 1;223 let isBarrier = 1;224 let isIndirectBranch = 1;225 let Pattern = [(brind sGPR:$rx)];226}227 228def JSR16 : R16_X_J<0b11101111, 0b01, "jsr16"> {229 let isCall = 1;230 let Defs = [ R15 ];231}232 233def RTS16 : CSKY16Inst<AddrModeNone, (outs), (ins), "rts16", [(CSKY_RET)]> {234 let isTerminator = 1;235 let isReturn = 1;236 let isBarrier = 1;237 let Inst = 0b0111100000111100;238 let Uses = [R15];239 let isCodeGenOnly = 1;240}241 242def JMPIX16 : CSKY16Inst<AddrModeNone, (outs),243 (ins mGPR:$rx, uimm2_jmpix:$indeximm2), "jmpix16\t$rx, $indeximm2", []> {244 bits<3> rx;245 bits<2> indeximm2;246 let Inst{15,14} = 0b00;247 let Inst{13 - 11} = 0b111;248 let Inst{10 - 8} = rx;249 let Inst{7 - 2} = 0b111000;250 let Inst{1,0} = indeximm2;251 let Predicates = [HasJAVA];252 let Uses = [R30];253}254 255//===----------------------------------------------------------------------===//256// Symbol address instructions.257//===----------------------------------------------------------------------===//258 259def LRW16 : CSKY16Inst<AddrModeNone, (outs mGPR:$rz),260 (ins constpool_symbol_16bit:$label), "lrw16\t$rz, $label", []> {261 bits<3> rz;262 bits<8> label;263 let Inst{15 - 13} = 0b000;264 let Inst{12} = label{7};265 let Inst{11,10} = 0b00;266 let Inst{9,8} = label{6,5};267 let Inst{7 - 5} = rz;268 let Inst{4 - 0} = label{4-0};269 let mayLoad = 1;270 let mayStore = 0;271}272 273def LRW16_Gen : CSKY16Inst<AddrModeNone, (outs mGPR:$rz),274 (ins bare_symbol:$src, constpool_symbol_16bit:$label),275 "lrw16\t$rz, $label", []> {276 bits<3> rz;277 bits<8> label;278 let Inst{15 - 13} = 0b000;279 let Inst{12} = label{7};280 let Inst{11,10} = 0b00;281 let Inst{9,8} = label{6,5};282 let Inst{7 - 5} = rz;283 let Inst{4 - 0} = label{4-0};284 let mayLoad = 1;285 let mayStore = 0;286 let isCodeGenOnly = 1;287}288 289 290//===----------------------------------------------------------------------===//291// Other operation instructions.292//===----------------------------------------------------------------------===//293 294def REVB16 : R16_XZ_UNOP<0b1110, 0b10, "revb16">;295def REVH16 : R16_XZ_UNOP<0b1110, 0b11, "revh16">;296 297let isCodeGenOnly = 1 in298def SETC16 : CSKY16Inst<AddrModeNone,299 (outs CARRY:$ca), (ins), "setc16", []> {300 let Inst{15, 14} = 0b01;301 let Inst{13 - 10} = 0b1001;302 let Inst{9 - 6} = 0;303 let Inst{5 - 2} = 0;304 let Inst{1, 0} = 0;305 let isCompare = 1;306}307 308let isCodeGenOnly = 1 in309def CLRC16 : CSKY16Inst<AddrModeNone,310 (outs CARRY:$ca), (ins), "clrc16", []> {311 let Inst{15, 14} = 0b01;312 let Inst{13 - 10} = 0b1001;313 let Inst{9 - 6} = 0;314 let Inst{5 - 2} = 0;315 let Inst{1, 0} = 2;316 let isCompare = 1;317}318 319let Constraints = "$rZ = $rz" in {320 def BCLRI16 : I16_Z_5<0b100, (outs mGPR:$rz), (ins mGPR:$rZ, uimm5:$imm5),321 "bclri16">;322 def BSETI16 : I16_Z_5<0b101, (outs mGPR:$rz), (ins mGPR:$rZ, uimm5:$imm5),323 "bseti16">;324}325 326let Predicates = [HasBTST16] in327def BTSTI16 : I16_Z_5<0b110, (outs CARRY:$ca), (ins mGPR:$rz, uimm5:$imm5),328 "btsti16"> {329 bits<0> ca;330}331 332def TST16 : CSKY16Inst<AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry),333 "tst16\t$rx, $ry", []> {334 bits<0> ca;335 bits<4> ry;336 bits<4> rx;337 let Inst{15,14} = 0b01;338 let Inst{13 - 10} = 0b1010;339 let Inst{9 - 6} = ry;340 let Inst{5 - 2} = rx;341 let Inst{1,0} = 0b10;342 let isCompare = 1;343}344 345def TSTNBZ16 : CSKY16Inst<AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx),346 "tstnbz16\t$rx", []> {347 bits<0> ca;348 bits<4> rx;349 let Inst{15,14} = 0b01;350 let Inst{13 - 10} = 0b1010;351 let Inst{9 - 6} = 0b0000;352 let Inst{5 - 2} = rx;353 let Inst{1,0} = 0b11;354 let isCompare = 1;355}356 357//===----------------------------------------------------------------------===//358// Special instructions.359//===----------------------------------------------------------------------===//360 361def BKPT : CSKY16Inst<AddrModeNone, (outs), (ins), "bkpt", []> {362 let Inst = 0;363}364 365let mayStore = 1 in {366def BPUSHH : I16_BPushPop<0b00010100111, 0, (outs), (ins mGPR:$rz), "bpush.h $rz">;367def BPUSHW : I16_BPushPop<0b00010100111, 0b10, (outs), (ins mGPR:$rz), "bpush.w $rz">;368}369 370let mayLoad = 1 in {371def BPOPH : I16_BPushPop<0b00010100101, 0, (outs mGPR:$rz), (ins), "bpop.h $rz">;372def BPOPW : I16_BPushPop<0b00010100101, 0b10, (outs mGPR:$rz), (ins), "bpop.w $rz">;373}374 375def NIE : CSKY16Inst<AddrModeNone, (outs), (ins), "nie", [(CSKY_NIE)]> {376 let Inst = 0b0001010001100000;377}378 379let isBarrier = 1, isReturn = 1, isTerminator = 1 in380def NIR : CSKY16Inst<AddrModeNone, (outs), (ins), "nir", [(CSKY_NIR)]> {381 let Inst = 0b0001010001100001;382}383 384def IPUSH16 : CSKY16Inst<AddrModeNone, (outs), (ins), "ipush16", []> {385 let Inst{15- 5} = 0b00010100011;386 let Inst{4-0} = 0b00010;387 let Predicates = [iHasE1];388 let Defs = [R14];389 let Uses = [R14, R0, R1, R2, R3, R12, R13];390 let mayStore = 1;391}392 393def IPOP16 : CSKY16Inst<AddrModeNone, (outs), (ins), "ipop16", []> {394 let Inst{15- 5} = 0b00010100011;395 let Inst{4-0} = 0b00011;396 let Predicates = [iHasE1];397 let Defs = [R14, R0, R1, R2, R3, R12, R13];398 let Uses = [R14];399 let mayLoad = 1;400}401 402def PUSH16 : CSKY16Inst<AddrModeNone, (outs),403 (ins reglist:$regs, variable_ops), "push16 $regs", []> {404 bits<5> regs;405 406 let Inst{15- 5} = 0b00010100110;407 let Inst{4-0} = regs;408 let Predicates = [iHasE1];409 let Defs = [R14];410 let Uses = [R14];411 let mayStore = 1;412}413 414def POP16 : CSKY16Inst<AddrModeNone, (outs),415 (ins reglist:$regs, variable_ops), "pop16 $regs", []> {416 bits<5> regs;417 418 let Inst{15- 5} = 0b00010100100;419 let Inst{4-0} = regs;420 let Predicates = [iHasE1];421 let Defs = [R14];422 let Uses = [R14];423 let mayLoad = 1;424}425 426//===----------------------------------------------------------------------===//427// CSKYPseudo428//===----------------------------------------------------------------------===//429 430let usesCustomInserter = 1 in {431 def ISEL16 : CSKYPseudo<(outs sGPR:$dst),432 (ins CARRY:$cond, sGPR:$src1, sGPR:$src2),433 "!isel16\t$dst, $src1, src2",434 [(set sGPR:$dst, (select CARRY:$cond, sGPR:$src1, sGPR:$src2))]>;435}436 437class JBranchPseudo<dag out, dag ins, string opstr> :438 CSKYPseudo<out, ins, opstr, []> {439 let isBranch = 1;440 let isTerminator = 1;441 let isIndirectBranch = 1;442 let mayLoad = 1;443 let Size = 2;444}445 446let isBarrier = 1 in447def JBR16 : JBranchPseudo<(outs),448 (ins br_symbol_16bit:$src1), "jbr16\t$src1">;449def JBT16 : JBranchPseudo<(outs),450 (ins CARRY:$ca, br_symbol_16bit:$src1), "jbt16\t$src1">;451def JBF16 : JBranchPseudo<(outs),452 (ins CARRY:$ca, br_symbol_16bit:$src1), "jbf16\t$src1">;453 454let mayLoad = 1, Size = 2, isCodeGenOnly = 0 in455def PseudoLRW16 : CSKYPseudo<(outs mGPR:$rz),456 (ins bare_symbol:$src), "lrw16 $rz, $src", []>;457 458//===----------------------------------------------------------------------===//459// Instruction Patterns.460//===----------------------------------------------------------------------===//461 462def : Pat<(sext_inreg mGPR:$src, i1), (ASRI16 (LSLI16 mGPR:$src, 7), 7)>;463def : Pat<(sext_inreg sGPR:$src, i8), (SEXTB16 sGPR:$src)>;464def : Pat<(sext_inreg sGPR:$src, i16), (SEXTH16 sGPR:$src)>;465 466// Load & Store Patterns467 468defm : LdPat<extloadi8, uimm5, LD16B, i32>;469defm : LdPat<zextloadi8, uimm5, LD16B, i32>;470 471defm : LdPat<extloadi16, uimm5_1, LD16H, i32>;472defm : LdPat<zextloadi16, uimm5_1, LD16H, i32>;473 474defm : LdPat<load, uimm5_2, LD16W, i32>;475 476 477defm : StPat<truncstorei8, i32, uimm5, ST16B>;478defm : StPat<truncstorei16, i32, uimm5_1, ST16H>;479defm : StPat<store, i32, uimm5_2, ST16W>;480 481def : Pat<(CSKY_CALLReg sGPR:$src), (JSR16 sGPR:$src)>;482def : Pat<(CSKY_TAILReg sGPR:$src), (JMP16 sGPR:$src)>;483 484// Symbol address Patterns485def : Pat<(CSKY_LOAD_ADDR tglobaladdr, tconstpool:$src2), (LRW16 tconstpool:$src2)>;486def : Pat<(CSKY_LOAD_ADDR tblockaddress, tconstpool:$src2), (LRW16 tconstpool:$src2)>;487def : Pat<(CSKY_LOAD_ADDR tjumptable:$src1, tconstpool:$src2), (LRW16_Gen tjumptable:$src1, tconstpool:$src2)>;488def : Pat<(CSKY_LOAD_ADDR texternalsym, tconstpool:$src2), (LRW16 tconstpool:$src2)>;489def : Pat<(CSKY_LOAD_ADDR tconstpool:$src1, tconstpool:$src2), (LRW16_Gen tconstpool:$src1, tconstpool:$src2)>;490 491def : Pat<(i32 (load constpool:$src)), (LRW16 (to_tconstpool tconstpool:$src))>;492 493// Branch Patterns.494 495def : Pat<(brcond CARRY:$ca, bb:$offset),496 (BT16 CARRY:$ca, bb:$offset)>;497 498def : Pat<(br bb:$offset), (BR16 bb:$offset)>;499 500multiclass BTF16Pat0<PatFrag cond0, PatFrag cond1, ImmLeaf imm_ty, Instruction inst> {501 def : Pat<(brcond (i32 (cond0 mGPR:$rs1, imm_ty:$rs2)), bb:$offset),502 (BT16 (inst mGPR:$rs1, imm_ty:$rs2), bb:$offset)>;503 def : Pat<(brcond (i32 (cond1 mGPR:$rs1, imm_ty:$rs2)), bb:$offset),504 (BF16 (inst mGPR:$rs1, imm_ty:$rs2), bb:$offset)>;505}506 507defm : BTF16Pat0<setne, seteq, uimm5, CMPNEI16>;508defm : BTF16Pat0<setuge, setult, oimm5, CMPHSI16>;509defm : BTF16Pat0<setlt, setge, oimm5, CMPLTI16>;510 511def : Pat<(brcond (i32 (setne sGPR:$rs1, sGPR:$rs2)), bb:$offset),512 (BT16 (CMPNE16 sGPR:$rs1, sGPR:$rs2), bb:$offset)>;513def : Pat<(brcond (i32 (seteq sGPR:$rs1, sGPR:$rs2)), bb:$offset),514 (BF16 (CMPNE16 sGPR:$rs1, sGPR:$rs2), bb:$offset)>;515 516multiclass BTF16Pat1<PatFrag cond0, PatFrag cond1, Instruction cmp,517 Instruction br> {518 def : Pat<(brcond (i32 (cond0 sGPR:$rs1, sGPR:$rs2)), bb:$offset),519 (br (cmp sGPR:$rs1, sGPR:$rs2), bb:$offset)>;520 def : Pat<(brcond (i32 (cond1 sGPR:$rs1, sGPR:$rs2)), bb:$offset),521 (br (cmp sGPR:$rs2, sGPR:$rs1), bb:$offset)>;522}523 524defm : BTF16Pat1<setuge, setule, CMPHS16, BT16>;525defm : BTF16Pat1<setult, setugt, CMPHS16, BF16>;526defm : BTF16Pat1<setlt, setgt, CMPLT16, BT16>;527defm : BTF16Pat1<setge, setle, CMPLT16, BF16>;528 529// Compare Patterns.530def : Pat<(setne sGPR:$rs1, sGPR:$rs2),531 (SUBU16XZ (MOVI16 1), (MVCV16 (CMPNE16 sGPR:$rs1, sGPR:$rs2)))>;532def : Pat<(seteq sGPR:$rs1, sGPR:$rs2),533 (MVCV16 (CMPNE16 sGPR:$rs1, sGPR:$rs2))>;534def : Pat<(setuge sGPR:$rs1, sGPR:$rs2),535 (SUBU16XZ (MOVI16 1), (MVCV16 (CMPHS16 sGPR:$rs1, sGPR:$rs2)))>;536def : Pat<(setule sGPR:$rs1, sGPR:$rs2),537 (SUBU16XZ (MOVI16 1), (MVCV16 (CMPHS16 sGPR:$rs2, sGPR:$rs1)))>;538def : Pat<(setult sGPR:$rs1, sGPR:$rs2),539 (MVCV16 (CMPHS16 sGPR:$rs1, sGPR:$rs2))>;540def : Pat<(setugt sGPR:$rs1, sGPR:$rs2),541 (MVCV16 (CMPHS16 sGPR:$rs2, sGPR:$rs1))>;542def : Pat<(setlt sGPR:$rs1, sGPR:$rs2),543 (SUBU16XZ (MOVI16 1), (MVCV16 (CMPLT16 sGPR:$rs1, sGPR:$rs2)))>;544def : Pat<(setgt sGPR:$rs1, sGPR:$rs2),545 (SUBU16XZ (MOVI16 1), (MVCV16 (CMPLT16 sGPR:$rs2, sGPR:$rs1)))>;546def : Pat<(setge sGPR:$rs1, sGPR:$rs2),547 (MVCV16 (CMPLT16 sGPR:$rs1, sGPR:$rs2))>;548def : Pat<(setle sGPR:$rs1, sGPR:$rs2),549 (MVCV16 (CMPLT16 sGPR:$rs2, sGPR:$rs1))>;550 551 552def : Pat<(setne mGPR:$rs1, uimm5:$rs2),553 (SUBU16XZ (MOVI16 1), (MVCV16 (CMPNEI16 mGPR:$rs1, uimm5:$rs2)))>;554def : Pat<(seteq mGPR:$rs1, uimm5:$rs2),555 (MVCV16 (CMPNEI16 mGPR:$rs1, uimm5:$rs2))>;556def : Pat<(setuge mGPR:$rs1, oimm5:$rs2),557 (SUBU16XZ (MOVI16 1), (MVCV16 (CMPHSI16 mGPR:$rs1, oimm5:$rs2)))>;558def : Pat<(setult mGPR:$rs1, oimm5:$rs2),559 (MVCV16 (CMPHSI16 mGPR:$rs1, oimm5:$rs2))>;560def : Pat<(setlt mGPR:$rs1, oimm5:$rs2),561 (SUBU16XZ (MOVI16 1), (MVCV16 (CMPLTI16 mGPR:$rs1, oimm5:$rs2)))>;562def : Pat<(setge mGPR:$rs1, oimm5:$rs2),563 (MVCV16 (CMPLTI16 mGPR:$rs1, oimm5:$rs2))>;564 565def : Pat<(select CARRY:$ca, sGPR:$rx, sGPR:$false),566 (ISEL16 CARRY:$ca, sGPR:$rx, sGPR:$false)>;567def : Pat<(select (and CARRY:$ca, 1), sGPR:$rx, sGPR:$false),568 (ISEL16 CARRY:$ca, sGPR:$rx, sGPR:$false)>;569 570def : Pat<(rotl sGPR:$rs1, sGPR:$rs2),571 (ROTL16 sGPR:$rs1, (AND16 sGPR:$rs2, (MOVI16 0x1f)))>;572 573 574// FIXME: This is a temporary treatment for the e801.575def : Pat<(i32 imm:$imm),576 (OR16 (MOVI16 (uimm8SRL_0 imm:$imm)),577 (OR16 (LSLI16 (MOVI16 (uimm8SRL_8 imm:$imm)), 8),578 (OR16 (LSLI16 (MOVI16 (uimm8SRL_16 imm:$imm)), 16),579 (LSLI16 (MOVI16 (uimm8SRL_24 imm:$imm)), 24))))>;580 581// Other operations.582let Predicates = [iHasE2] in {583 def : Pat<(bswap sGPR:$rx), (REVB16 sGPR:$rx)>;584}585 586//===----------------------------------------------------------------------===//587// Compress Instruction tablegen backend.588//===----------------------------------------------------------------------===//589 590def : CompressPat<(ADDU32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),591 (ADDU16XZ sGPR:$rd, sGPR:$rs2)>;592def : CompressPat<(ADDU32 sGPR:$rd, sGPR:$rs1, sGPR:$rd),593 (ADDU16XZ sGPR:$rd, sGPR:$rs1)>;594def : CompressPat<(ADDU32 mGPR:$rd, mGPR:$rs1, mGPR:$rs2),595 (ADDU16 mGPR:$rd, mGPR:$rs1, mGPR:$rs2)>;596def : CompressPat<(SUBU32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),597 (SUBU16XZ sGPR:$rd, sGPR:$rs2)>;598def : CompressPat<(SUBU32 mGPR:$rd, mGPR:$rs1, mGPR:$rs2),599 (SUBU16 mGPR:$rd, mGPR:$rs1, mGPR:$rs2)>;600 601def : CompressPat<602 (ADDC32 sGPR:$rd, CARRY:$cout, sGPR:$rd, sGPR:$rs2, CARRY:$cout),603 (ADDC16 sGPR:$rd, CARRY:$cout, sGPR:$rs2, CARRY:$cout)604 >;605def : CompressPat<606 (SUBC32 sGPR:$rd, CARRY:$cout, sGPR:$rd, sGPR:$rs2, CARRY:$cout),607 (SUBC16 sGPR:$rd, CARRY:$cout, sGPR:$rs2, CARRY:$cout)608 >;609 610def : CompressPat<(ADDI32 mGPR:$rd, mGPR:$rs, oimm3:$imm),611 (ADDI16XZ mGPR:$rd, mGPR:$rs, oimm3:$imm)>;612def : CompressPat<(SUBI32 mGPR:$rd, mGPR:$rs, oimm3:$imm),613 (SUBI16XZ mGPR:$rd, mGPR:$rs, oimm3:$imm)>;614 615def : CompressPat<(ADDI32 mGPR:$rd, mGPR:$rd, oimm8:$imm),616 (ADDI16 mGPR:$rd, oimm8:$imm)>;617def : CompressPat<(SUBI32 mGPR:$rd, mGPR:$rd, oimm8:$imm),618 (SUBI16 mGPR:$rd, oimm8:$imm)>;619 620def : CompressPat<(ADDI32 GPRSP:$sp, GPRSP:$sp, uimm7_2:$imm),621 (ADDI16SPSP GPRSP:$sp, GPRSP:$sp, uimm7_2:$imm)>;622def : CompressPat<(SUBI32 GPRSP:$sp, GPRSP:$sp, uimm7_2:$imm),623 (SUBI16SPSP GPRSP:$sp, GPRSP:$sp, uimm7_2:$imm)>;624 625def : CompressPat<(ADDI32 mGPR:$rd, GPRSP:$sp, uimm8_2:$imm),626 (ADDI16ZSP mGPR:$rd, GPRSP:$sp, uimm8_2:$imm)>;627 628def : CompressPat<(MULT32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),629 (MULT16 sGPR:$rd, sGPR:$rs2)>;630def : CompressPat<(MULT32 sGPR:$rd, sGPR:$rs1, sGPR:$rd),631 (MULT16 sGPR:$rd, sGPR:$rs1)>;632def : CompressPat<(AND32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),633 (AND16 sGPR:$rd, sGPR:$rs2)>;634def : CompressPat<(AND32 sGPR:$rd, sGPR:$rs1, sGPR:$rd),635 (AND16 sGPR:$rd, sGPR:$rs1)>;636def : CompressPat<(OR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),637 (OR16 sGPR:$rd, sGPR:$rs2)>;638def : CompressPat<(OR32 sGPR:$rd, sGPR:$rs1, sGPR:$rd),639 (OR16 sGPR:$rd, sGPR:$rs1)>;640def : CompressPat<(XOR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),641 (XOR16 sGPR:$rd, sGPR:$rs2)>;642def : CompressPat<(XOR32 sGPR:$rd, sGPR:$rs1, sGPR:$rd),643 (XOR16 sGPR:$rd, sGPR:$rs1)>;644 645def : CompressPat<(ANDN32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),646 (ANDN16 sGPR:$rd, sGPR:$rs2)>;647def : CompressPat<(NOR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),648 (NOR16 sGPR:$rd, sGPR:$rs2)>;649def : CompressPat<(LSL32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),650 (LSL16 sGPR:$rd, sGPR:$rs2)>;651def : CompressPat<(LSR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),652 (LSR16 sGPR:$rd, sGPR:$rs2)>;653def : CompressPat<(ASR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),654 (ASR16 sGPR:$rd, sGPR:$rs2)>;655def : CompressPat<(ROTL32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),656 (ROTL16 sGPR:$rd, sGPR:$rs2)>;657 658def : CompressPat<(NOT32 sGPR:$rd, sGPR:$rd),659 (NOT16 sGPR:$rd)>;660 661let Predicates = [iHas2E3] in662def : CompressPat<(REVB32 sGPR:$rd, sGPR:$rs),663 (REVB16 sGPR:$rd, sGPR:$rs)>;664 665def : CompressPat<(LSLI32 mGPR:$rd, mGPR:$rs, uimm5:$imm),666 (LSLI16 mGPR:$rd, mGPR:$rs, uimm5:$imm)>;667def : CompressPat<(LSRI32 mGPR:$rd, mGPR:$rs, uimm5:$imm),668 (LSRI16 mGPR:$rd, mGPR:$rs, uimm5:$imm)>;669def : CompressPat<(ASRI32 mGPR:$rd, mGPR:$rs, uimm5:$imm),670 (ASRI16 mGPR:$rd, mGPR:$rs, uimm5:$imm)>;671 672def : CompressPat<(CMPHS32 CARRY:$ca, sGPR:$rs1, sGPR:$rs2),673 (CMPHS16 CARRY:$ca, sGPR:$rs1, sGPR:$rs2)>;674def : CompressPat<(CMPLT32 CARRY:$ca, sGPR:$rs1, sGPR:$rs2),675 (CMPLT16 CARRY:$ca, sGPR:$rs1, sGPR:$rs2)>;676def : CompressPat<(CMPNE32 CARRY:$ca, sGPR:$rs1, sGPR:$rs2),677 (CMPNE16 CARRY:$ca, sGPR:$rs1, sGPR:$rs2)>;678 679def : CompressPat<(CMPHSI32 CARRY:$ca, mGPR:$rs, oimm5:$imm),680 (CMPHSI16 CARRY:$ca, mGPR:$rs, oimm5:$imm)>;681def : CompressPat<(CMPLTI32 CARRY:$ca, mGPR:$rs, oimm5:$imm),682 (CMPLTI16 CARRY:$ca, mGPR:$rs, oimm5:$imm)>;683def : CompressPat<(CMPNEI32 CARRY:$ca, mGPR:$rs, uimm5:$imm),684 (CMPNEI16 CARRY:$ca, mGPR:$rs, uimm5:$imm)>;685 686def : CompressPat<(JSR32 sGPR:$rd),687 (JSR16 sGPR:$rd)>;688 689 690def : CompressPat<(MVCV32 sGPR:$rd, CARRY:$ca),691 (MVCV16 sGPR:$rd, CARRY:$ca)>;692def : CompressPat<(MOV32 sGPR:$rd, sGPR:$ca),693 (MOV16 sGPR:$rd, sGPR:$ca)>;694def : CompressPat<(MOVI32 mGPR:$rd, uimm8:$imm),695 (MOVI16 mGPR:$rd, uimm8:$imm)>;696 697def : CompressPat<(LD32B mGPR:$rd, mGPR:$rs, uimm5:$imm),698 (LD16B mGPR:$rd, mGPR:$rs, uimm5:$imm)>;699def : CompressPat<(LD32H mGPR:$rd, mGPR:$rs, uimm5_1:$imm),700 (LD16H mGPR:$rd, mGPR:$rs, uimm5_1:$imm)>;701def : CompressPat<(LD32W mGPR:$rd, mGPR:$rs, uimm5_2:$imm),702 (LD16W mGPR:$rd, mGPR:$rs, uimm5_2:$imm)>;703def : CompressPat<(LD32W mGPR:$rd, GPRSP:$sp, uimm8_2:$imm),704 (LD16WSP mGPR:$rd, GPRSP:$sp, uimm8_2:$imm)>;705 706def : CompressPat<(ST32B mGPR:$rd, mGPR:$rs, uimm5:$imm),707 (ST16B mGPR:$rd, mGPR:$rs, uimm5:$imm)>;708def : CompressPat<(ST32H mGPR:$rd, mGPR:$rs, uimm5_1:$imm),709 (ST16H mGPR:$rd, mGPR:$rs, uimm5_1:$imm)>;710def : CompressPat<(ST32W mGPR:$rd, mGPR:$rs, uimm5_2:$imm),711 (ST16W mGPR:$rd, mGPR:$rs, uimm5_2:$imm)>;712def : CompressPat<(ST32W mGPR:$rd, GPRSP:$sp, uimm8_2:$imm),713 (ST16WSP mGPR:$rd, GPRSP:$sp, uimm8_2:$imm)>;714 715let Predicates = [HasBTST16] in716def : CompressPat<(BTSTI32 CARRY:$ca, mGPR:$rs, uimm5:$imm),717 (BTSTI16 CARRY:$ca, mGPR:$rs, uimm5:$imm)>;718def : CompressPat<(BCLRI32 mGPR:$rd, mGPR:$rd, uimm5:$imm),719 (BCLRI16 mGPR:$rd, uimm5:$imm)>;720def : CompressPat<(BSETI32 mGPR:$rd, mGPR:$rd, uimm5:$imm),721 (BSETI16 mGPR:$rd, uimm5:$imm)>;722 723def : CompressPat<(ZEXTB32 sGPR:$rd, sGPR:$rs),724 (ZEXTB16 sGPR:$rd, sGPR:$rs)>;725def : CompressPat<(ZEXTH32 sGPR:$rd, sGPR:$rs),726 (ZEXTH16 sGPR:$rd, sGPR:$rs)>;727def : CompressPat<(SEXTB32 sGPR:$rd, sGPR:$rs),728 (SEXTB16 sGPR:$rd, sGPR:$rs)>;729def : CompressPat<(SEXTH32 sGPR:$rd, sGPR:$rs),730 (SEXTH16 sGPR:$rd, sGPR:$rs)>;731