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1//===- CSKYInstrInfoF1.td - CSKY Instruction Float1.0 ------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file describes the CSKY instructions in TableGen format.10//11//===----------------------------------------------------------------------===//12 13def regseq_f1 : Operand<iPTR> {14 let EncoderMethod = "getRegisterSeqOpValue";15 let ParserMatchClass = RegSeqAsmOperand<"V1">;16 let PrintMethod = "printRegisterSeq";17 let DecoderMethod = "DecodeRegSeqOperandF1";18 let MIOperandInfo = (ops sFPR32, uimm5);19}20 21def regseq_d1 : Operand<iPTR> {22 let EncoderMethod = "getRegisterSeqOpValue";23 let ParserMatchClass = RegSeqAsmOperand<"V1">;24 let PrintMethod = "printRegisterSeq";25 let DecoderMethod = "DecodeRegSeqOperandD1";26 let MIOperandInfo = (ops sFPR64, uimm5);27}28 29def sFPR32Op : RegisterOperand<sFPR32, "printFPR">;30def sFPR64Op : RegisterOperand<sFPR64, "printFPR">;31def sFPR64_V_OP : RegisterOperand<sFPR64_V, "printFPR">;32 33include "CSKYInstrFormatsF1.td"34 35//===----------------------------------------------------------------------===//36// CSKY specific DAG Nodes.37//===----------------------------------------------------------------------===//38 39def SDT_BITCAST_TO_LOHI : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;40def CSKY_BITCAST_TO_LOHI : SDNode<"CSKYISD::BITCAST_TO_LOHI", SDT_BITCAST_TO_LOHI>;41def SDT_BITCAST_FROM_LOHI : SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>]>;42def CSKY_BITCAST_FROM_LOHI : SDNode<"CSKYISD::BITCAST_FROM_LOHI", SDT_BITCAST_FROM_LOHI>;43//===----------------------------------------------------------------------===//44// Operand and SDNode transformation definitions.45//===----------------------------------------------------------------------===//46 47def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;48 49def fpimm32_hi16 : SDNodeXForm<fpimm, [{50 return CurDAG->getTargetConstant(51 (N->getValueAPF().bitcastToAPInt().getZExtValue() >> 16) & 0xFFFF,52 SDLoc(N), MVT::i32);53}]>;54 55def fpimm32_lo16 : SDNodeXForm<fpimm, [{56 return CurDAG->getTargetConstant(57 N->getValueAPF().bitcastToAPInt().getZExtValue() & 0xFFFF,58 SDLoc(N), MVT::i32);59}]>;60 61class fpimm_xform<int width, int shift = 0> : SDNodeXForm<fpimm,62 "return CurDAG->getTargetConstant(N->getValueAPF().bitcastToAPInt().lshr("#shift#").getLoBits("#width#"), SDLoc(N), MVT::i32);">;63 64class fpimm_xform_i16<int width, int shift = 0> : SDNodeXForm<fpimm,65 "return CurDAG->getTargetConstant(N->getValueAPF().bitcastToAPInt().lshr("#shift#").getLoBits("#width#"), SDLoc(N), MVT::i16);">;66 67class fpimm_t<int width, int shift = 0> : PatLeaf<(fpimm),68 "return isShiftedUInt<"#width#", "#shift#">(N->getValueAPF().bitcastToAPInt().getZExtValue());">;69 70def fpimm8 : fpimm_t<8>;71def fpimm8_8 : fpimm_t<8, 8>;72def fpimm8_16 : fpimm_t<8, 16>;73def fpimm8_24 : fpimm_t<8, 24>;74def fpimm16 : fpimm_t<16>;75def fpimm16_8 : fpimm_t<16, 8>;76def fpimm16_16 : fpimm_t<16, 16>;77def fpimm24 : fpimm_t<24>;78def fpimm24_8 : fpimm_t<24, 8>;79def fpimm32 : fpimm_t<32>;80 81def fpimm8_sr0_XFORM : fpimm_xform<8>;82def fpimm8_sr8_XFORM : fpimm_xform<8, 8>;83def fpimm8_sr16_XFORM : fpimm_xform<8, 16>;84def fpimm8_sr24_XFORM : fpimm_xform<8, 24>;85 86def fpimm8_sr0_i16_XFORM : fpimm_xform_i16<8>;87def fpimm8_sr8_i16_XFORM : fpimm_xform_i16<8, 8>;88 89def fconstpool_symbol : Operand<iPTR> {90 let ParserMatchClass = Constpool;91 let EncoderMethod =92 "getConstpoolSymbolOpValue<CSKY::fixup_csky_pcrel_uimm8_scale4>";93 let DecoderMethod = "decodeUImmOperand<8, 2>";94 let PrintMethod = "printConstpool";95 let OperandType = "OPERAND_PCREL";96}97 98 99 100//===----------------------------------------------------------------------===//101// Instructions102//===----------------------------------------------------------------------===//103 104//arithmetic105 106def FABSM : F_XZ<0x2, 0b000110, "fabsm", "", UnOpFrag<(fabs node:$Src)>, sFPR64_V_OP>;107def FNEGM : F_XZ<0x2, 0b000111, "fnegm", "", UnOpFrag<(fneg node:$Src)>, sFPR64_V_OP>;108def FADDM : F_XYZ<0x2, 0b000000, "faddm", "", BinOpFrag<(fadd node:$LHS, node:$RHS)>, sFPR64_V_OP>;109def FSUBM : F_XYZ<0x2, 0b000001, "fsubm", "", BinOpFrag<(fsub node:$LHS, node:$RHS)>, sFPR64_V_OP>;110def FMULM : F_XYZ<0x2, 0b010000, "fmulm", "", BinOpFrag<(fmul node:$LHS, node:$RHS)>, sFPR64_V_OP>;111def FNMULM : F_XYZ<0x2, 0b010001, "fnmulm", "", BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>, sFPR64_V_OP>;112def FMACM : F_ACCUM_XYZ<0x2, 0b010100, "fmacm", "", TriOpFrag<(fadd node:$LHS, (fmul node:$MHS, node:$RHS))>, sFPR64_V_OP>;113def FMSCM : F_ACCUM_XYZ<0x2, 0b010101, "fmscm", "", TriOpFrag<(fsub (fmul node:$MHS, node:$RHS), node:$LHS)>, sFPR64_V_OP>;114def FNMACM : F_ACCUM_XYZ<0x2, 0b010110, "fnmacm", "", TriOpFrag<(fsub node:$LHS, (fmul node:$MHS, node:$RHS))>, sFPR64_V_OP>;115def FNMSCM : F_ACCUM_XYZ<0x2, 0b010111, "fnmscm", "", TriOpFrag<(fneg (fadd node:$LHS, (fmul node:$MHS, node:$RHS)))>, sFPR64_V_OP>;116 117def FMOVM : F_MOV<0x2, 0b000100, "fmovm", "", sFPR64_V_OP>;118 119defm FABS : FT_XZ<0b000110, "fabs", UnOpFrag<(fabs node:$Src)>>;120defm FNEG : FT_XZ<0b000111, "fneg", UnOpFrag<(fneg node:$Src)>>;121defm FSQRT : FT_XZ<0b011010, "fsqrt", UnOpFrag<(fsqrt node:$Src)>>;122 123defm FADD : FT_XYZ<0b000000, "fadd", BinOpFrag<(fadd node:$LHS, node:$RHS)>>;124defm FSUB : FT_XYZ<0b000001, "fsub", BinOpFrag<(fsub node:$LHS, node:$RHS)>>;125defm FDIV : FT_XYZ<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;126defm FMUL : FT_XYZ<0b010000, "fmul", BinOpFrag<(fmul node:$LHS, node:$RHS)>>;127defm FNMUL : FT_XYZ<0b010001, "fnmul", BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>>;128defm FMAC : FT_ACCUM_XYZ<0b010100, "fmac", TriOpFrag<(fadd node:$LHS, (fmul node:$MHS, node:$RHS))>>;129defm FMSC : FT_ACCUM_XYZ<0b010101, "fmsc", TriOpFrag<(fsub (fmul node:$MHS, node:$RHS), node:$LHS)>>;130defm FNMAC : FT_ACCUM_XYZ<0b010110, "fnmac", TriOpFrag<(fsub node:$LHS, (fmul node:$MHS, node:$RHS))>>;131defm FNMSC : FT_ACCUM_XYZ<0b010111, "fnmsc", TriOpFrag<(fneg (fadd node:$LHS, (fmul node:$MHS, node:$RHS)))>>;132 133defm FCMPHS : FT_CMPXY<0b001100, "fcmphs">;134defm FCMPLT : FT_CMPXY<0b001101, "fcmplt">;135defm FCMPNE : FT_CMPXY<0b001110, "fcmpne">;136defm FCMPUO : FT_CMPXY<0b001111, "fcmpuo">;137defm FCMPZHS : FT_CMPZX<0b001000, "fcmpzhs">;138defm FCMPZLS : FT_CMPZX<0b001001, "fcmpzls">;139defm FCMPZNE : FT_CMPZX<0b001010, "fcmpzne">;140defm FCMPZUO : FT_CMPZX<0b001011, "fcmpzuo">;141 142defm FRECIP : FT_MOV<0b011001, "frecip">;143 144// multiplication145let Predicates = [HasFPUv2_SF] in {146 def : Pat<(f32 (fmul (fneg sFPR32Op:$vrx), sFPR32Op:$vry)),147 (FNMUL_S sFPR32Op:$vrx, sFPR32Op:$vry)>;148}149let Predicates = [HasFPUv2_DF] in {150 def : Pat<(f64 (fmul (fneg sFPR64Op:$vrx), sFPR64Op:$vry)),151 (FNMUL_D sFPR64Op:$vrx, sFPR64Op:$vry)>;152}153 154//fmov, fmtvr, fmfvr155defm FMOV : FT_MOV<0b000100, "fmov">;156def FMFVRL : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR32Op:$vrx),157 "fmfvrl\t$rz, $vrx", [(set GPR:$rz, (bitconvert sFPR32Op:$vrx))]>;158def FMTVRL : F_XZ_FG<3, 0b011011, (outs sFPR32Op:$vrz), (ins GPR:$rx),159 "fmtvrl\t$vrz, $rx", [(set sFPR32Op:$vrz, (bitconvert GPR:$rx))]>;160 161let Predicates = [HasFPUv2_DF] in {162 let isCodeGenOnly = 1 in163 def FMFVRL_D : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR64Op:$vrx),164 "fmfvrl\t$rz, $vrx", []>;165 def FMFVRH_D : F_XZ_GF<3, 0b011000, (outs GPR:$rz), (ins sFPR64Op:$vrx),166 "fmfvrh\t$rz, $vrx", []>;167 let isCodeGenOnly = 1 in168 def FMTVRL_D : F_XZ_FG<3, 0b011011, (outs sFPR64Op:$vrz), (ins GPR:$rx),169 "fmtvrl\t$vrz, $rx", []>;170let Constraints = "$vrZ = $vrz" in171 def FMTVRH_D : F_XZ_FG<3, 0b011010, (outs sFPR64Op:$vrz), (ins sFPR64Op:$vrZ, GPR:$rx),172 "fmtvrh\t$vrz, $rx", []>;173}174 175//fcvt176 177def FSITOS : F_XZ_TRANS<0b010000, "fsitos", sFPR32Op, sFPR32Op>;178def : Pat<(f32 (sint_to_fp GPR:$a)),179 (FSITOS (COPY_TO_REGCLASS GPR:$a, sFPR32))>,180 Requires<[HasFPUv2_SF]>;181 182def FUITOS : F_XZ_TRANS<0b010001, "fuitos", sFPR32Op, sFPR32Op>;183def : Pat<(f32 (uint_to_fp GPR:$a)),184 (FUITOS (COPY_TO_REGCLASS GPR:$a, sFPR32))>,185 Requires<[HasFPUv2_SF]>;186 187def FSITOD : F_XZ_TRANS<0b010100, "fsitod", sFPR64Op, sFPR64Op>;188def : Pat<(f64 (sint_to_fp GPR:$a)),189 (FSITOD (COPY_TO_REGCLASS GPR:$a, sFPR64))>,190 Requires<[HasFPUv2_DF]>;191 192def FUITOD : F_XZ_TRANS<0b010101, "fuitod", sFPR64Op, sFPR64Op>;193def : Pat<(f64 (uint_to_fp GPR:$a)),194 (FUITOD (COPY_TO_REGCLASS GPR:$a, sFPR64))>,195 Requires<[HasFPUv2_DF]>;196 197let Predicates = [HasFPUv2_DF] in {198def FDTOS : F_XZ_TRANS_DS<0b010110,"fdtos", UnOpFrag<(fpround node:$Src)>>;199def FSTOD : F_XZ_TRANS_SD<0b010111,"fstod", UnOpFrag<(fpextend node:$Src)>>;200}201 202def rpiFSTOSI : F_XZ_TRANS<0b000010, "fstosi.rpi", sFPR32Op, sFPR32Op>;203def rpiFSTOUI : F_XZ_TRANS<0b000110, "fstoui.rpi", sFPR32Op, sFPR32Op>;204def rzFSTOSI : F_XZ_TRANS<0b000001, "fstosi.rz", sFPR32Op, sFPR32Op>;205def rzFSTOUI : F_XZ_TRANS<0b000101, "fstoui.rz", sFPR32Op, sFPR32Op>;206def rnFSTOSI : F_XZ_TRANS<0b000000, "fstosi.rn", sFPR32Op, sFPR32Op>;207def rnFSTOUI : F_XZ_TRANS<0b000100, "fstoui.rn", sFPR32Op, sFPR32Op>;208def rniFSTOSI : F_XZ_TRANS<0b000011, "fstosi.rni", sFPR32Op, sFPR32Op>;209def rniFSTOUI : F_XZ_TRANS<0b000111, "fstoui.rni", sFPR32Op, sFPR32Op>;210 211let Predicates = [HasFPUv2_DF] in {212def rpiFDTOSI : F_XZ_TRANS<0b001010, "fdtosi.rpi", sFPR64Op, sFPR64Op>;213def rpiFDTOUI : F_XZ_TRANS<0b001110, "fdtoui.rpi", sFPR64Op, sFPR64Op>;214def rzFDTOSI : F_XZ_TRANS<0b001001, "fdtosi.rz", sFPR64Op, sFPR64Op>;215def rzFDTOUI : F_XZ_TRANS<0b001101, "fdtoui.rz", sFPR64Op, sFPR64Op>;216def rnFDTOSI : F_XZ_TRANS<0b001000, "fdtosi.rn", sFPR64Op, sFPR64Op>;217def rnFDTOUI : F_XZ_TRANS<0b001100, "fdtoui.rn", sFPR64Op, sFPR64Op>;218def rniFDTOSI : F_XZ_TRANS<0b001011, "fdtosi.rni", sFPR64Op, sFPR64Op>;219def rniFDTOUI : F_XZ_TRANS<0b001111, "fdtoui.rni", sFPR64Op, sFPR64Op>;220}221 222multiclass FPToIntegerPats<SDNode round, string SUFFIX> {223 def : Pat<(i32 (fp_to_sint (round sFPR32Op:$Rn))),224 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GPR)>,225 Requires<[HasFPUv2_SF]>;226 def : Pat<(i32 (fp_to_uint (round sFPR32Op:$Rn))),227 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32Op:$Rn), GPR)>,228 Requires<[HasFPUv2_SF]>;229 def : Pat<(i32 (fp_to_sint (round sFPR64Op:$Rn))),230 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64Op:$Rn), GPR)>,231 Requires<[HasFPUv2_DF]>;232 def : Pat<(i32 (fp_to_uint (round sFPR64Op:$Rn))),233 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOUI) sFPR64Op:$Rn), GPR)>,234 Requires<[HasFPUv2_DF]>;235}236 237defm: FPToIntegerPats<fceil, "rpi">;238defm: FPToIntegerPats<fround, "rn">;239defm: FPToIntegerPats<ffloor, "rni">;240 241multiclass FPToIntegerTowardszeroPats<string SUFFIX> {242 def : Pat<(i32 (fp_to_sint sFPR32Op:$Rn)),243 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GPR)>,244 Requires<[HasFPUv2_SF]>;245 def : Pat<(i32 (fp_to_uint sFPR32Op:$Rn)),246 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32Op:$Rn), GPR)>,247 Requires<[HasFPUv2_SF]>;248 def : Pat<(i32 (fp_to_sint sFPR64Op:$Rn)),249 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64Op:$Rn), GPR)>,250 Requires<[HasFPUv2_DF]>;251 def : Pat<(i32 (fp_to_uint sFPR64Op:$Rn)),252 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOUI) sFPR64Op:$Rn), GPR)>,253 Requires<[HasFPUv2_DF]>;254}255 256defm: FPToIntegerTowardszeroPats<"rz">;257 258 259//fld, fst260let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {261 defm FLD : FT_XYAI_LD<0b0010000, "fld">;262 defm FLDR : FT_XYAR_LD<0b0010100, "fldr">;263 defm FLDM : FT_XYAR_LDM<0b0011000, "fldm">;264 265 let Predicates = [HasFPUv2_DF] in266 def FLDRM : F_XYAR_LD<0b0010101, 0, "fldrm", "", sFPR64Op>;267 let Predicates = [HasFPUv2_DF] in268 def FLDMM : F_I4_XY_MEM<0b0011001, 0,269 (outs), (ins GPR:$rx, regseq_d1:$regs, variable_ops), "fldmm\t$regs, (${rx})", []>;270 let Predicates = [HasFPUv2_DF] in271 def FLDM : F_XYAI_LD<0b0010001, 0, "fldm", "", sFPR64Op, uimm8_3>;272}273 274 275 276let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {277 defm FST : FT_XYAI_ST<0b0010010, "fst">;278 defm FSTR : FT_XYAR_ST<0b0010110, "fstr">;279 defm FSTM : FT_XYAR_STM<0b0011010, "fstm">;280 281 let Predicates = [HasFPUv2_DF] in282 def FSTRM : F_XYAR_ST<0b0010111, 0, "fstrm", "", sFPR64Op>;283 let Predicates = [HasFPUv2_DF] in284 def FSTMM : F_I4_XY_MEM<0b0011011, 0,285 (outs), (ins GPR:$rx, regseq_d1:$regs, variable_ops), "fstmm\t$regs, (${rx})", []>;286 let Predicates = [HasFPUv2_DF] in287 def FSTM : F_XYAI_ST<0b0010011, 0, "fstm", "", sFPR64Op, uimm8_3>;288}289 290defm : LdPat<load, uimm8_2, FLD_S, f32>, Requires<[HasFPUv2_SF]>;291defm : LdPat<load, uimm8_2, FLD_D, f64>, Requires<[HasFPUv2_DF]>;292defm : LdrPat<load, FLDR_S, f32>, Requires<[HasFPUv2_SF]>;293defm : LdrPat<load, FLDR_D, f64>, Requires<[HasFPUv2_DF]>;294 295defm : StPat<store, f32, uimm8_2, FST_S>, Requires<[HasFPUv2_SF]>;296defm : StPat<store, f64, uimm8_2, FST_D>, Requires<[HasFPUv2_DF]>;297defm : StrPat<store, f32, FSTR_S>, Requires<[HasFPUv2_SF]>;298defm : StrPat<store, f64, FSTR_D>, Requires<[HasFPUv2_DF]>;299 300 301def : Pat<(f32 fpimm16:$imm), (COPY_TO_REGCLASS (MOVI32 (fpimm32_lo16 fpimm16:$imm)), sFPR32)>,302 Requires<[HasFPUv2_SF]>;303def : Pat<(f32 fpimm16_16:$imm), (f32 (COPY_TO_REGCLASS (MOVIH32 (fpimm32_hi16 fpimm16_16:$imm)), sFPR32))>,304 Requires<[HasFPUv2_SF]>;305def : Pat<(f32 fpimm:$imm), (COPY_TO_REGCLASS (ORI32 (MOVIH32 (fpimm32_hi16 fpimm:$imm)), (fpimm32_lo16 fpimm:$imm)), sFPR32)>,306 Requires<[HasFPUv2_SF]>;307 308def : Pat<(f64(CSKY_BITCAST_FROM_LOHI GPR:$rs1, GPR:$rs2)), (FMTVRH_D(FMTVRL_D GPR:$rs1), GPR:$rs2)>,309 Requires<[HasFPUv2_DF]>;310 311multiclass BRCond_Bin<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV> {312 let Predicates = [HasFPUv2_SF] in313 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),314 (Br0 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;315 let Predicates = [HasFPUv2_SF] in316 def : Pat<(brcond (xor (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), 1), bb:$imm16),317 (Br1 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;318 let Predicates = [HasFPUv2_DF] in319 def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),320 (Br0 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;321 let Predicates = [HasFPUv2_DF] in322 def : Pat<(brcond (xor (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), 1), bb:$imm16),323 (Br1 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;324 325 let Predicates = [HasFPUv2_SF] in326 def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),327 (MV (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2))>;328 let Predicates = [HasFPUv2_DF] in329 def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),330 (MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2))>;331}332 333multiclass BRCond_Bin_SWAP<CondCode CC, string Instr, Instruction Br0, Instruction Br1, Instruction MV> {334 let Predicates = [HasFPUv2_SF] in335 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),336 (Br0 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;337 let Predicates = [HasFPUv2_SF] in338 def : Pat<(brcond (xor (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), 1), bb:$imm16),339 (Br1 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;340 let Predicates = [HasFPUv2_DF] in341 def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),342 (Br0 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;343 let Predicates = [HasFPUv2_DF] in344 def : Pat<(brcond (xor (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), 1), bb:$imm16),345 (Br1 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;346 347 let Predicates = [HasFPUv2_SF] in348 def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),349 (MV (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1))>;350 let Predicates = [HasFPUv2_DF] in351 def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),352 (MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1))>;353}354 355// inverse (order && compare) to (unorder || inverse(compare))356 357defm : BRCond_Bin<SETUNE, "FCMPNE", BT32, BF32, MVC32>;358defm : BRCond_Bin<SETOEQ, "FCMPNE", BF32, BT32, MVCV32>;359defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, BF32, MVC32>;360defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, BF32, MVC32>;361defm : BRCond_Bin<SETUO, "FCMPUO", BT32, BF32, MVC32>;362defm : BRCond_Bin<SETO, "FCMPUO", BF32, BT32, MVCV32>;363defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, BF32, MVC32>;364defm : BRCond_Bin_SWAP<SETOLE, "FCMPHS", BT32, BF32, MVC32>;365 366defm : BRCond_Bin<SETNE, "FCMPNE", BT32, BF32, MVC32>;367defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, BT32, MVCV32>;368defm : BRCond_Bin<SETGE, "FCMPHS", BT32, BF32, MVC32>;369defm : BRCond_Bin<SETLT, "FCMPLT", BT32, BF32, MVC32>;370defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, BF32, MVC32>;371defm : BRCond_Bin_SWAP<SETLE, "FCMPHS", BT32, BF32, MVC32>;372 373// -----------374 375let Predicates = [HasFPUv2_SF] in {376 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),377 (BT32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;378 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)),379 (MVC32 (FCMPZHS_S sFPR32Op:$rs1))>;380 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),381 (BF32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;382 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)),383 (MVCV32 (FCMPZHS_S sFPR32Op:$rs1))>;384 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLE)), bb:$imm16),385 (BT32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;386 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLE)),387 (MVC32 (FCMPZLS_S sFPR32Op:$rs1))>;388 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)), bb:$imm16),389 (BF32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;390 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)),391 (MVCV32 (FCMPZLS_S sFPR32Op:$rs1))>;392 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETUNE)), bb:$imm16),393 (BT32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;394 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETUNE)),395 (MVC32 (FCMPZNE_S sFPR32Op:$rs1))>;396 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOEQ)), bb:$imm16),397 (BF32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;398 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOEQ)),399 (MVCV32 (FCMPZNE_S sFPR32Op:$rs1))>;400 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm, SETUO)), bb:$imm16),401 (BT32 (FCMPZUO_S sFPR32Op:$rs1), bb:$imm16)>;402 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm, SETUO)),403 (MVC32 (FCMPZUO_S sFPR32Op:$rs1))>;404 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm, SETO)), bb:$imm16),405 (BF32 (FCMPZUO_S sFPR32Op:$rs1), bb:$imm16)>;406 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm, SETO)),407 (MVCV32 (FCMPZUO_S sFPR32Op:$rs1))>;408 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)), bb:$imm16),409 (BT32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;410 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)),411 (MVC32 (FCMPZHS_S sFPR32Op:$rs1))>;412 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),413 (BF32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;414 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)),415 (MVCV32 (FCMPZHS_S sFPR32Op:$rs1))>;416 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLE)), bb:$imm16),417 (BT32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;418 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLE)),419 (MVC32 (FCMPZLS_S sFPR32Op:$rs1))>;420 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)), bb:$imm16),421 (BF32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;422 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)),423 (MVCV32 (FCMPZLS_S sFPR32Op:$rs1))>;424 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)), bb:$imm16),425 (BT32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;426 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)),427 (MVC32 (FCMPZNE_S sFPR32Op:$rs1))>;428 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),429 (BF32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;430 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)),431 (MVCV32 (FCMPZNE_S sFPR32Op:$rs1))>;432}433 434let usesCustomInserter = 1 in {435 let Predicates = [HasFPUv2_SF] in436 def FSELS : CSKYPseudo<(outs sFPR32Op:$dst), (ins CARRY:$cond, sFPR32Op:$src1, sFPR32Op:$src2),437 "!fsels\t$dst, $src1, src2", [(set sFPR32Op:$dst, (select CARRY:$cond, sFPR32Op:$src1, sFPR32Op:$src2))]>;438 439 let Predicates = [HasFPUv2_DF] in440 def FSELD : CSKYPseudo<(outs sFPR64Op:$dst), (ins CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2),441 "!fseld\t$dst, $src1, src2", [(set sFPR64Op:$dst, (select CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2))]>;442}443