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1//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This is the top level entry point for the Hexagon target.10//11//===----------------------------------------------------------------------===//12 13//===----------------------------------------------------------------------===//14// Target-independent interfaces which we are implementing15//===----------------------------------------------------------------------===//16 17include "llvm/Target/Target.td"18 19//===----------------------------------------------------------------------===//20// Hexagon Subtarget features.21//===----------------------------------------------------------------------===//22 23// Hexagon Architectures24include "HexagonDepArch.td"25 26def ProcTinyCore: SubtargetFeature<"tinycore", "HexagonProcFamily",27 "TinyCore", "Hexagon Tiny Core">;28 29// Hexagon ISA Extensions30def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true",31 "Hexagon ZReg extension instructions">;32def ExtensionHVXQFloat: SubtargetFeature<"hvx-qfloat", "UseHVXQFloatOps",33 "true", "Hexagon HVX QFloating point instructions">;34 35def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",36 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;37def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",38 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",39 [ExtensionHVX]>;40def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",41 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",42 [ExtensionHVX, ExtensionHVXV60]>;43def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",44 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",45 [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62]>;46def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion",47 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions",48 [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,49 ExtensionZReg]>;50def ExtensionHVXV67: SubtargetFeature<"hvxv67", "HexagonHVXVersion",51 "Hexagon::ArchEnum::V67", "Hexagon HVX instructions",52 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66]>;53def ExtensionHVXV68: SubtargetFeature<"hvxv68", "HexagonHVXVersion",54 "Hexagon::ArchEnum::V68", "Hexagon HVX instructions",55 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,56 ExtensionHVXV67]>;57def ExtensionHVXV69: SubtargetFeature<"hvxv69", "HexagonHVXVersion",58 "Hexagon::ArchEnum::V69", "Hexagon HVX instructions",59 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,60 ExtensionHVXV67, ExtensionHVXV68]>;61def ExtensionHVXV71: SubtargetFeature<"hvxv71", "HexagonHVXVersion",62 "Hexagon::ArchEnum::V71", "Hexagon HVX instructions",63 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,64 ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69]>;65def ExtensionHVXV73: SubtargetFeature<"hvxv73", "HexagonHVXVersion",66 "Hexagon::ArchEnum::V73", "Hexagon HVX instructions",67 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,68 ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71]>;69 70def ExtensionHVXV75: SubtargetFeature<"hvxv75", "HexagonHVXVersion",71 "Hexagon::ArchEnum::V75", "Hexagon HVX instructions",72 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,73 ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,74 ExtensionHVXV73]>;75 76def ExtensionHVXV79: SubtargetFeature<"hvxv79", "HexagonHVXVersion",77 "Hexagon::ArchEnum::V79", "Hexagon HVX instructions",78 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,79 ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,80 ExtensionHVXV73, ExtensionHVXV75]>;81 82def ExtensionHVXV81: SubtargetFeature<"hvxv81", "HexagonHVXVersion",83 "Hexagon::ArchEnum::V81", "Hexagon HVX instructions",84 [ExtensionHVXV65, ExtensionHVXV66, ExtensionHVXV67,85 ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,86 ExtensionHVXV73, ExtensionHVXV75, ExtensionHVXV79]>;87 88def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",89 "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;90def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",91 "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;92 93def ExtensionAudio: SubtargetFeature<"audio", "UseAudioOps", "true",94 "Hexagon Audio extension instructions">;95 96def ExtensionHVXIEEEFP: SubtargetFeature<"hvx-ieee-fp", "UseHVXIEEEFPOps",97 "true", "Hexagon HVX IEEE floating point instructions">;98 99def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true",100 "Use compound instructions">;101def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",102 "Support for instruction packets">;103def FeaturePreV65: SubtargetFeature<"prev65", "HasPreV65", "true",104 "Support features deprecated in v65">;105def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",106 "Use constant-extended calls">;107def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",108 "Supports mem_noshuf feature">;109def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true",110 "Use memop instructions">;111def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true",112 "Support for new-value jumps", [FeaturePackets]>;113def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true",114 "Support for new-value stores", [FeaturePackets]>;115def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true",116 "Allow GP-relative addressing of global variables">;117def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",118 "Enable generation of duplex instruction">;119def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",120 "true", "Reserve register R19">;121def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim",122 "NoreturnStackElim", "true",123 "Eliminate stack allocation in a noreturn function when possible">;124def FeatureCabac: SubtargetFeature<"cabac", "UseCabac", "false",125 "Emit the CABAC instruction">;126 127//===----------------------------------------------------------------------===//128// Hexagon Instruction Predicate Definitions.129//===----------------------------------------------------------------------===//130 131def UseMEMOPS : Predicate<"HST->useMemops()">;132def UseHVX64B : Predicate<"HST->useHVX64BOps()">,133 AssemblerPredicate<(all_of ExtensionHVX64B)>;134def UseHVX128B : Predicate<"HST->useHVX128BOps()">,135 AssemblerPredicate<(all_of ExtensionHVX128B)>;136def UseHVX : Predicate<"HST->useHVXOps()">,137 AssemblerPredicate<(all_of ExtensionHVXV60)>;138def UseHVXV60 : Predicate<"HST->useHVXV60Ops()">,139 AssemblerPredicate<(all_of ExtensionHVXV60)>;140def UseHVXV62 : Predicate<"HST->useHVXV62Ops()">,141 AssemblerPredicate<(all_of ExtensionHVXV62)>;142def UseHVXV65 : Predicate<"HST->useHVXV65Ops()">,143 AssemblerPredicate<(all_of ExtensionHVXV65)>;144def UseHVXV66 : Predicate<"HST->useHVXV66Ops()">,145 AssemblerPredicate<(all_of ExtensionHVXV66)>;146def UseHVXV67 : Predicate<"HST->useHVXV67Ops()">,147 AssemblerPredicate<(all_of ExtensionHVXV67)>;148def UseHVXV68 : Predicate<"HST->useHVXV68Ops()">,149 AssemblerPredicate<(all_of ExtensionHVXV68)>;150def UseHVXV69 : Predicate<"HST->useHVXV69Ops()">,151 AssemblerPredicate<(all_of ExtensionHVXV69)>;152def UseHVXV71 : Predicate<"HST->useHVXV71Ops()">,153 AssemblerPredicate<(all_of ExtensionHVXV71)>;154def UseHVXV73 : Predicate<"HST->useHVXV73Ops()">,155 AssemblerPredicate<(all_of ExtensionHVXV73)>;156def UseHVXV75 : Predicate<"HST->useHVXV75Ops()">,157 AssemblerPredicate<(all_of ExtensionHVXV75)>;158def UseHVXV79 : Predicate<"HST->useHVXV79Ops()">,159 AssemblerPredicate<(all_of ExtensionHVXV79)>;160def UseHVXV81 : Predicate<"HST->useHVXV81Ops()">,161 AssemblerPredicate<(all_of ExtensionHVXV81)>;162def UseAudio : Predicate<"HST->useAudioOps()">,163 AssemblerPredicate<(all_of ExtensionAudio)>;164def UseZReg : Predicate<"HST->useZRegOps()">,165 AssemblerPredicate<(all_of ExtensionZReg)>;166def UseCompound : Predicate<"HST->useCompound()">;167def HasPreV65 : Predicate<"HST->hasPreV65()">,168 AssemblerPredicate<(all_of FeaturePreV65)>;169def UseHVXIEEEFP : Predicate<"HST->useHVXIEEEFPOps()">,170 AssemblerPredicate<(all_of ExtensionHVXIEEEFP)>;171def UseHVXQFloat : Predicate<"HST->useHVXQFloatOps()">,172 AssemblerPredicate<(all_of ExtensionHVXQFloat)>;173def UseHVXFloatingPoint: Predicate<"HST->useHVXFloatingPoint()">;174def HasMemNoShuf : Predicate<"HST->hasMemNoShuf()">,175 AssemblerPredicate<(all_of FeatureMemNoShuf)>;176def NotOptTinyCore : Predicate<"!HST->isTinyCore() ||"177 "MF->getFunction().hasOptSize()"> {178 let RecomputePerFunction = 1;179}180def UseSmallData : Predicate<"HST->useSmallData()">;181def UseCabac : Predicate<"HST->useCabac()">,182 AssemblerPredicate<(any_of FeatureCabac)>;183 184def : HwModePredicateProlog<[{185 const auto *HST = static_cast<const HexagonSubtarget *>(this);186}]>;187def Hvx64: HwMode<[UseHVX64B]>;188def Hvx128: HwMode<[UseHVX128B]>;189 190//===----------------------------------------------------------------------===//191// Classes used for relation maps.192//===----------------------------------------------------------------------===//193 194// The classes below should remain in hierarchical order...195class ImmRegShl;196// ImmRegRel - Filter class used to relate instructions having reg-reg form197// with their reg-imm counterparts.198class ImmRegRel;199// PredRel - Filter class used to relate non-predicated instructions with their200// predicated forms.201class PredRel;202class PredNewRel: PredRel;203// NewValueRel - Filter class used to relate regular store instructions with204// their new-value store form.205class NewValueRel: PredNewRel;206class AddrModeRel: NewValueRel;207class PostInc_BaseImm;208class IntrinsicsRel;209// ... through here.210 211//===----------------------------------------------------------------------===//212// Generate mapping table to relate non-predicate instructions with their213// predicated formats - true and false.214//215 216def getPredOpcode : InstrMapping {217 let FilterClass = "PredRel";218 // Instructions with the same BaseOpcode and isNVStore values form a row.219 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];220 // Instructions with the same predicate sense form a column.221 let ColFields = ["PredSense"];222 // The key column is the unpredicated instructions.223 let KeyCol = [""];224 // Value columns are PredSense=true and PredSense=false225 let ValueCols = [["true"], ["false"]];226}227 228//===----------------------------------------------------------------------===//229// Generate mapping table to relate predicate-true instructions with their230// predicate-false forms231//232def getFalsePredOpcode : InstrMapping {233 let FilterClass = "PredRel";234 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];235 let ColFields = ["PredSense"];236 let KeyCol = ["true"];237 let ValueCols = [["false"]];238}239 240//===----------------------------------------------------------------------===//241// Generate mapping table to relate predicate-false instructions with their242// predicate-true forms243//244def getTruePredOpcode : InstrMapping {245 let FilterClass = "PredRel";246 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];247 let ColFields = ["PredSense"];248 let KeyCol = ["false"];249 let ValueCols = [["true"]];250}251 252//===----------------------------------------------------------------------===//253// Generate mapping table to relate predicated instructions with their .new254// format.255//256def getPredNewOpcode : InstrMapping {257 let FilterClass = "PredNewRel";258 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];259 let ColFields = ["PNewValue"];260 let KeyCol = [""];261 let ValueCols = [["new"]];262}263 264//===----------------------------------------------------------------------===//265// Generate mapping table to relate .new predicated instructions with their old266// format.267//268def getPredOldOpcode : InstrMapping {269 let FilterClass = "PredNewRel";270 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];271 let ColFields = ["PNewValue"];272 let KeyCol = ["new"];273 let ValueCols = [[""]];274}275 276//===----------------------------------------------------------------------===//277// Generate mapping table to relate store instructions with their new-value278// format.279//280def getNewValueOpcode : InstrMapping {281 let FilterClass = "NewValueRel";282 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];283 let ColFields = ["NValueST"];284 let KeyCol = ["false"];285 let ValueCols = [["true"]];286}287 288//===----------------------------------------------------------------------===//289// Generate mapping table to relate new-value store instructions with their old290// format.291//292def getNonNVStore : InstrMapping {293 let FilterClass = "NewValueRel";294 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];295 let ColFields = ["NValueST"];296 let KeyCol = ["true"];297 let ValueCols = [["false"]];298}299 300def changeAddrMode_abs_io: InstrMapping {301 let FilterClass = "AddrModeRel";302 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",303 "isFloat"];304 let ColFields = ["addrMode"];305 let KeyCol = ["Absolute"];306 let ValueCols = [["BaseImmOffset"]];307}308 309def changeAddrMode_io_abs: InstrMapping {310 let FilterClass = "AddrModeRel";311 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",312 "isFloat"];313 let ColFields = ["addrMode"];314 let KeyCol = ["BaseImmOffset"];315 let ValueCols = [["Absolute"]];316}317 318def changeAddrMode_io_rr: InstrMapping {319 let FilterClass = "AddrModeRel";320 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];321 let ColFields = ["addrMode"];322 let KeyCol = ["BaseImmOffset"];323 let ValueCols = [["BaseRegOffset"]];324}325 326def changeAddrMode_rr_io: InstrMapping {327 let FilterClass = "AddrModeRel";328 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];329 let ColFields = ["addrMode"];330 let KeyCol = ["BaseRegOffset"];331 let ValueCols = [["BaseImmOffset"]];332}333 334def changeAddrMode_pi_io: InstrMapping {335 let FilterClass = "PostInc_BaseImm";336 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];337 let ColFields = ["addrMode"];338 let KeyCol = ["PostInc"];339 let ValueCols = [["BaseImmOffset"]];340}341 342def changeAddrMode_io_pi: InstrMapping {343 let FilterClass = "PostInc_BaseImm";344 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];345 let ColFields = ["addrMode"];346 let KeyCol = ["BaseImmOffset"];347 let ValueCols = [["PostInc"]];348}349 350def changeAddrMode_rr_ur: InstrMapping {351 let FilterClass = "ImmRegShl";352 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];353 let ColFields = ["addrMode"];354 let KeyCol = ["BaseRegOffset"];355 let ValueCols = [["BaseLongOffset"]];356}357 358def changeAddrMode_ur_rr: InstrMapping {359 let FilterClass = "ImmRegShl";360 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];361 let ColFields = ["addrMode"];362 let KeyCol = ["BaseLongOffset"];363 let ValueCols = [["BaseRegOffset"]];364}365 366def getRegForm : InstrMapping {367 let FilterClass = "ImmRegRel";368 let RowFields = ["CextOpcode", "PredSense", "PNewValue"];369 let ColFields = ["InputType"];370 let KeyCol = ["imm"];371 let ValueCols = [["reg"]];372}373 374def notTakenBranchPrediction : InstrMapping {375 let FilterClass = "PredRel";376 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];377 let ColFields = ["isBrTaken"];378 let KeyCol = ["true"];379 let ValueCols = [["false"]];380}381 382def takenBranchPrediction : InstrMapping {383 let FilterClass = "PredRel";384 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];385 let ColFields = ["isBrTaken"];386 let KeyCol = ["false"];387 let ValueCols = [["true"]];388}389 390def getRealHWInstr : InstrMapping {391 let FilterClass = "IntrinsicsRel";392 let RowFields = ["BaseOpcode"];393 let ColFields = ["InstrType"];394 let KeyCol = ["Pseudo"];395 let ValueCols = [["Pseudo"], ["Real"]];396}397//===----------------------------------------------------------------------===//398// Register File, Instruction Descriptions399//===----------------------------------------------------------------------===//400include "HexagonSchedule.td"401include "HexagonRegisterInfo.td"402include "HexagonOperands.td"403include "HexagonDepOperands.td"404include "HexagonDepITypes.td"405include "HexagonInstrFormats.td"406include "HexagonDepInstrFormats.td"407include "HexagonDepInstrInfo.td"408include "HexagonCallingConv.td"409include "HexagonPseudo.td"410include "HexagonPatterns.td"411include "HexagonPatternsHVX.td"412include "HexagonPatternsV65.td"413include "HexagonDepMappings.td"414include "HexagonIntrinsics.td"415 416defm : RemapAllTargetPseudoPointerOperands<IntRegs>;417 418def HexagonInstrInfo : InstrInfo;419 420//===----------------------------------------------------------------------===//421// Hexagon processors supported.422//===----------------------------------------------------------------------===//423 424class Proc<string Name, SchedMachineModel Model,425 list<SubtargetFeature> Features>426 : ProcessorModel<Name, Model, Features>;427 428def : Proc<"generic", HexagonModelV60,429 [ArchV5, ArchV55, ArchV60,430 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,431 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,432 FeatureCabac]>;433def : Proc<"hexagonv5", HexagonModelV5,434 [ArchV5,435 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,436 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,437 FeatureCabac]>;438def : Proc<"hexagonv55", HexagonModelV55,439 [ArchV5, ArchV55,440 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,441 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,442 FeatureCabac]>;443def : Proc<"hexagonv60", HexagonModelV60,444 [ArchV5, ArchV55, ArchV60,445 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,446 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,447 FeatureCabac]>;448def : Proc<"hexagonv62", HexagonModelV62,449 [ArchV5, ArchV55, ArchV60, ArchV62,450 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,451 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,452 FeatureCabac]>;453def : Proc<"hexagonv65", HexagonModelV65,454 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,455 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,456 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,457 FeatureCabac]>;458def : Proc<"hexagonv66", HexagonModelV66,459 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66,460 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,461 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,462 FeatureCabac]>;463def : Proc<"hexagonv67", HexagonModelV67,464 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,465 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,466 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,467 FeatureCabac]>;468def : Proc<"hexagonv68", HexagonModelV68,469 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,470 ArchV68,471 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,472 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,473 FeatureCabac]>;474def : Proc<"hexagonv69", HexagonModelV69,475 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,476 ArchV68, ArchV69,477 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,478 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,479 FeatureCabac]>;480def : Proc<"hexagonv71", HexagonModelV71,481 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,482 ArchV68, ArchV69, ArchV71,483 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,484 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,485 FeatureCabac]>;486def : Proc<"hexagonv73", HexagonModelV73,487 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,488 ArchV68, ArchV69, ArchV71, ArchV73,489 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,490 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;491def : Proc<"hexagonv75", HexagonModelV75,492 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,493 ArchV68, ArchV69, ArchV71, ArchV73, ArchV75, FeatureCompound,494 FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,495 FeatureNVS, FeaturePackets, FeatureSmallData]>;496def : Proc<"hexagonv79", HexagonModelV79,497 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,498 ArchV68, ArchV69, ArchV71, ArchV73, ArchV75, ArchV79,499 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,500 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;501def : Proc<"hexagonv81", HexagonModelV81,502 [ArchV65, ArchV66, ArchV67, ArchV68, ArchV69, ArchV71, ArchV73,503 ArchV75, ArchV79, ArchV81,504 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,505 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;506 507// Need to update the correct features for tiny core.508// Disable NewValueJumps since the packetizer is unable to handle a packet with509// a new value jump and another SLOT0 instruction.510def : Proc<"hexagonv67t", HexagonModelV67T,511 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,512 ProcTinyCore, ExtensionAudio,513 FeatureCompound, FeatureMemNoShuf, FeatureMemops,514 FeatureNVS, FeaturePackets, FeatureSmallData]>;515 516def : Proc<"hexagonv71t", HexagonModelV71T,517 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,518 ArchV68, ArchV69, ArchV71,519 ProcTinyCore, ExtensionAudio,520 FeatureCompound, FeatureMemNoShuf, FeatureMemops,521 FeatureNVS, FeaturePackets, FeatureSmallData]>;522 523//===----------------------------------------------------------------------===//524// Declare the target which we are implementing525//===----------------------------------------------------------------------===//526 527def HexagonAsmParser : AsmParser {528 let ShouldEmitMatchRegisterAltName = 1;529 bit HasMnemonicFirst = 0;530}531 532def HexagonAsmParserVariant : AsmParserVariant {533 int Variant = 0;534 string TokenizingCharacters = "#()=:.<>!+*-|^&";535 string BreakCharacters = "";536}537 538def HexagonAsmWriter : AsmWriter {539 string AsmWriterClassName = "InstPrinter";540 bit isMCAsmWriter = 1;541}542 543def Hexagon : Target {544 let InstructionSet = HexagonInstrInfo;545 let AssemblyParsers = [HexagonAsmParser];546 let AssemblyParserVariants = [HexagonAsmParserVariant];547 let AssemblyWriters = [HexagonAsmWriter];548 let AllowRegisterRenaming = 1;549}550