2737 lines · cpp
1//===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//8//===----------------------------------------------------------------------===//9 10#include "HexagonFrameLowering.h"11#include "HexagonBlockRanges.h"12#include "HexagonInstrInfo.h"13#include "HexagonMachineFunctionInfo.h"14#include "HexagonRegisterInfo.h"15#include "HexagonSubtarget.h"16#include "HexagonTargetMachine.h"17#include "MCTargetDesc/HexagonBaseInfo.h"18#include "llvm/ADT/BitVector.h"19#include "llvm/ADT/DenseMap.h"20#include "llvm/ADT/PostOrderIterator.h"21#include "llvm/ADT/SetVector.h"22#include "llvm/ADT/SmallSet.h"23#include "llvm/ADT/SmallVector.h"24#include "llvm/CodeGen/LivePhysRegs.h"25#include "llvm/CodeGen/MachineBasicBlock.h"26#include "llvm/CodeGen/MachineDominators.h"27#include "llvm/CodeGen/MachineFrameInfo.h"28#include "llvm/CodeGen/MachineFunction.h"29#include "llvm/CodeGen/MachineFunctionPass.h"30#include "llvm/CodeGen/MachineInstr.h"31#include "llvm/CodeGen/MachineInstrBuilder.h"32#include "llvm/CodeGen/MachineMemOperand.h"33#include "llvm/CodeGen/MachineModuleInfo.h"34#include "llvm/CodeGen/MachineOperand.h"35#include "llvm/CodeGen/MachinePostDominators.h"36#include "llvm/CodeGen/MachineRegisterInfo.h"37#include "llvm/CodeGen/PseudoSourceValue.h"38#include "llvm/CodeGen/RegisterScavenging.h"39#include "llvm/CodeGen/TargetRegisterInfo.h"40#include "llvm/IR/Attributes.h"41#include "llvm/IR/DebugLoc.h"42#include "llvm/IR/Function.h"43#include "llvm/MC/MCDwarf.h"44#include "llvm/MC/MCRegisterInfo.h"45#include "llvm/Pass.h"46#include "llvm/Support/CodeGen.h"47#include "llvm/Support/CommandLine.h"48#include "llvm/Support/Compiler.h"49#include "llvm/Support/Debug.h"50#include "llvm/Support/ErrorHandling.h"51#include "llvm/Support/MathExtras.h"52#include "llvm/Support/raw_ostream.h"53#include "llvm/Target/TargetMachine.h"54#include "llvm/Target/TargetOptions.h"55#include <algorithm>56#include <cassert>57#include <cstdint>58#include <iterator>59#include <limits>60#include <map>61#include <optional>62#include <utility>63#include <vector>64 65#define DEBUG_TYPE "hexagon-pei"66 67// Hexagon stack frame layout as defined by the ABI:68//69// Incoming arguments70// passed via stack71// |72// |73// SP during function's FP during function's |74// +-- runtime (top of stack) runtime (bottom) --+ |75// | | |76// --++---------------------+------------------+-----------------++-+-------77// | parameter area for | variable-size | fixed-size |LR| arg78// | called functions | local objects | local objects |FP|79// --+----------------------+------------------+-----------------+--+-------80// <- size known -> <- size unknown -> <- size known ->81//82// Low address High address83//84// <--- stack growth85//86//87// - In any circumstances, the outgoing function arguments are always accessi-88// ble using the SP, and the incoming arguments are accessible using the FP.89// - If the local objects are not aligned, they can always be accessed using90// the FP.91// - If there are no variable-sized objects, the local objects can always be92// accessed using the SP, regardless whether they are aligned or not. (The93// alignment padding will be at the bottom of the stack (highest address),94// and so the offset with respect to the SP will be known at the compile-95// -time.)96//97// The only complication occurs if there are both, local aligned objects, and98// dynamically allocated (variable-sized) objects. The alignment pad will be99// placed between the FP and the local objects, thus preventing the use of the100// FP to access the local objects. At the same time, the variable-sized objects101// will be between the SP and the local objects, thus introducing an unknown102// distance from the SP to the locals.103//104// To avoid this problem, a new register is created that holds the aligned105// address of the bottom of the stack, referred in the sources as AP (aligned106// pointer). The AP will be equal to "FP-p", where "p" is the smallest pad107// that aligns AP to the required boundary (a maximum of the alignments of108// all stack objects, fixed- and variable-sized). All local objects[1] will109// then use AP as the base pointer.110// [1] The exception is with "fixed" stack objects. "Fixed" stack objects get111// their name from being allocated at fixed locations on the stack, relative112// to the FP. In the presence of dynamic allocation and local alignment, such113// objects can only be accessed through the FP.114//115// Illustration of the AP:116// FP --+117// |118// ---------------+---------------------+-----+-----------------------++-+--119// Rest of the | Local stack objects | Pad | Fixed stack objects |LR|120// stack frame | (aligned) | | (CSR, spills, etc.) |FP|121// ---------------+---------------------+-----+-----------------+-----+--+--122// |<-- Multiple of the -->|123// stack alignment +-- AP124//125// The AP is set up at the beginning of the function. Since it is not a dedi-126// cated (reserved) register, it needs to be kept live throughout the function127// to be available as the base register for local object accesses.128// Normally, an address of a stack objects is obtained by a pseudo-instruction129// PS_fi. To access local objects with the AP register present, a different130// pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra131// argument compared to PS_fi: the first input register is the AP register.132// This keeps the register live between its definition and its uses.133 134// The AP register is originally set up using pseudo-instruction PS_aligna:135// AP = PS_aligna A136// where137// A - required stack alignment138// The alignment value must be the maximum of all alignments required by139// any stack object.140 141// The dynamic allocation uses a pseudo-instruction PS_alloca:142// Rd = PS_alloca Rs, A143// where144// Rd - address of the allocated space145// Rs - minimum size (the actual allocated can be larger to accommodate146// alignment)147// A - required alignment148 149using namespace llvm;150 151static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",152 cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));153 154static cl::opt<unsigned>155 NumberScavengerSlots("number-scavenger-slots", cl::Hidden,156 cl::desc("Set the number of scavenger slots"),157 cl::init(2));158 159static cl::opt<int>160 SpillFuncThreshold("spill-func-threshold", cl::Hidden,161 cl::desc("Specify O2(not Os) spill func threshold"),162 cl::init(6));163 164static cl::opt<int>165 SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden,166 cl::desc("Specify Os spill func threshold"),167 cl::init(1));168 169static cl::opt<bool> EnableStackOVFSanitizer(170 "enable-stackovf-sanitizer", cl::Hidden,171 cl::desc("Enable runtime checks for stack overflow."), cl::init(false));172 173static cl::opt<bool>174 EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden,175 cl::desc("Enable stack frame shrink wrapping"));176 177static cl::opt<unsigned>178 ShrinkLimit("shrink-frame-limit",179 cl::init(std::numeric_limits<unsigned>::max()), cl::Hidden,180 cl::desc("Max count of stack frame shrink-wraps"));181 182static cl::opt<bool>183 EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden,184 cl::desc("Enable long calls for save-restore stubs."),185 cl::init(false));186 187static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),188 cl::Hidden, cl::desc("Refrain from using FP whenever possible"));189 190static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,191 cl::init(true), cl::desc("Optimize spill slots"));192 193#ifndef NDEBUG194static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,195 cl::init(std::numeric_limits<unsigned>::max()));196static unsigned SpillOptCount = 0;197#endif198 199namespace {200 201 class HexagonCallFrameInformation : public MachineFunctionPass {202 public:203 static char ID;204 205 HexagonCallFrameInformation() : MachineFunctionPass(ID) {}206 207 bool runOnMachineFunction(MachineFunction &MF) override;208 209 MachineFunctionProperties getRequiredProperties() const override {210 return MachineFunctionProperties().setNoVRegs();211 }212 };213 214 char HexagonCallFrameInformation::ID = 0;215 216} // end anonymous namespace217 218bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {219 auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();220 bool NeedCFI = MF.needsFrameMoves();221 222 if (!NeedCFI)223 return false;224 HFI.insertCFIInstructions(MF);225 return true;226}227 228INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",229 "Hexagon call frame information", false, false)230 231FunctionPass *llvm::createHexagonCallFrameInformation() {232 return new HexagonCallFrameInformation();233}234 235/// Map a register pair Reg to the subregister that has the greater "number",236/// i.e. D3 (aka R7:6) will be mapped to R7, etc.237static Register getMax32BitSubRegister(Register Reg,238 const TargetRegisterInfo &TRI,239 bool hireg = true) {240 if (Reg < Hexagon::D0 || Reg > Hexagon::D15)241 return Reg;242 243 Register RegNo = 0;244 for (MCPhysReg SubReg : TRI.subregs(Reg)) {245 if (hireg) {246 if (SubReg > RegNo)247 RegNo = SubReg;248 } else {249 if (!RegNo || SubReg < RegNo)250 RegNo = SubReg;251 }252 }253 return RegNo;254}255 256/// Returns the callee saved register with the largest id in the vector.257static Register getMaxCalleeSavedReg(ArrayRef<CalleeSavedInfo> CSI,258 const TargetRegisterInfo &TRI) {259 static_assert(Hexagon::R1 > 0,260 "Assume physical registers are encoded as positive integers");261 if (CSI.empty())262 return 0;263 264 Register Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);265 for (unsigned I = 1, E = CSI.size(); I < E; ++I) {266 Register Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);267 if (Reg > Max)268 Max = Reg;269 }270 return Max;271}272 273/// Checks if the basic block contains any instruction that needs a stack274/// frame to be already in place.275static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,276 const HexagonRegisterInfo &HRI) {277 for (const MachineInstr &MI : MBB) {278 if (MI.isCall())279 return true;280 unsigned Opc = MI.getOpcode();281 switch (Opc) {282 case Hexagon::PS_alloca:283 case Hexagon::PS_aligna:284 return true;285 default:286 break;287 }288 // Check individual operands.289 for (const MachineOperand &MO : MI.operands()) {290 // While the presence of a frame index does not prove that a stack291 // frame will be required, all frame indexes should be within alloc-292 // frame/deallocframe. Otherwise, the code that translates a frame293 // index into an offset would have to be aware of the placement of294 // the frame creation/destruction instructions.295 if (MO.isFI())296 return true;297 if (MO.isReg()) {298 Register R = MO.getReg();299 // Debug instructions may refer to $noreg.300 if (!R)301 continue;302 // Virtual registers will need scavenging, which then may require303 // a stack slot.304 if (R.isVirtual())305 return true;306 for (MCPhysReg S : HRI.subregs_inclusive(R))307 if (CSR[S])308 return true;309 continue;310 }311 if (MO.isRegMask()) {312 // A regmask would normally have all callee-saved registers marked313 // as preserved, so this check would not be needed, but in case of314 // ever having other regmasks (for other calling conventions),315 // make sure they would be processed correctly.316 const uint32_t *BM = MO.getRegMask();317 for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {318 unsigned R = x;319 // If this regmask does not preserve a CSR, a frame will be needed.320 if (!(BM[R/32] & (1u << (R%32))))321 return true;322 }323 }324 }325 }326 return false;327}328 329 /// Returns true if MBB has a machine instructions that indicates a tail call330 /// in the block.331static bool hasTailCall(const MachineBasicBlock &MBB) {332 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();333 if (I == MBB.end())334 return false;335 unsigned RetOpc = I->getOpcode();336 return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;337}338 339/// Returns true if MBB contains an instruction that returns.340static bool hasReturn(const MachineBasicBlock &MBB) {341 for (const MachineInstr &MI : MBB.terminators())342 if (MI.isReturn())343 return true;344 return false;345}346 347/// Returns the "return" instruction from this block, or nullptr if there348/// isn't any.349static MachineInstr *getReturn(MachineBasicBlock &MBB) {350 for (auto &I : MBB)351 if (I.isReturn())352 return &I;353 return nullptr;354}355 356static bool isRestoreCall(unsigned Opc) {357 switch (Opc) {358 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:359 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:360 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:361 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:362 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:363 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:364 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:365 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:366 return true;367 }368 return false;369}370 371static inline bool isOptNone(const MachineFunction &MF) {372 return MF.getFunction().hasOptNone() ||373 MF.getTarget().getOptLevel() == CodeGenOptLevel::None;374}375 376static inline bool isOptSize(const MachineFunction &MF) {377 const Function &F = MF.getFunction();378 return F.hasOptSize() && !F.hasMinSize();379}380 381static inline bool isMinSize(const MachineFunction &MF) {382 return MF.getFunction().hasMinSize();383}384 385/// Implements shrink-wrapping of the stack frame. By default, stack frame386/// is created in the function entry block, and is cleaned up in every block387/// that returns. This function finds alternate blocks: one for the frame388/// setup (prolog) and one for the cleanup (epilog).389void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,390 MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {391 static unsigned ShrinkCounter = 0;392 393 if (MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl() &&394 MF.getFunction().isVarArg())395 return;396 if (ShrinkLimit.getPosition()) {397 if (ShrinkCounter >= ShrinkLimit)398 return;399 ShrinkCounter++;400 }401 402 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();403 404 MachineDominatorTree MDT;405 MDT.recalculate(MF);406 MachinePostDominatorTree MPT;407 MPT.recalculate(MF);408 409 using UnsignedMap = DenseMap<unsigned, unsigned>;410 using RPOTType = ReversePostOrderTraversal<const MachineFunction *>;411 412 UnsignedMap RPO;413 RPOTType RPOT(&MF);414 unsigned RPON = 0;415 for (auto &I : RPOT)416 RPO[I->getNumber()] = RPON++;417 418 // Don't process functions that have loops, at least for now. Placement419 // of prolog and epilog must take loop structure into account. For simpli-420 // city don't do it right now.421 for (auto &I : MF) {422 unsigned BN = RPO[I.getNumber()];423 for (MachineBasicBlock *Succ : I.successors())424 // If found a back-edge, return.425 if (RPO[Succ->getNumber()] <= BN)426 return;427 }428 429 // Collect the set of blocks that need a stack frame to execute. Scan430 // each block for uses/defs of callee-saved registers, calls, etc.431 SmallVector<MachineBasicBlock*,16> SFBlocks;432 BitVector CSR(Hexagon::NUM_TARGET_REGS);433 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)434 for (MCPhysReg S : HRI.subregs_inclusive(*P))435 CSR[S] = true;436 437 for (auto &I : MF)438 if (needsStackFrame(I, CSR, HRI))439 SFBlocks.push_back(&I);440 441 LLVM_DEBUG({442 dbgs() << "Blocks needing SF: {";443 for (auto &B : SFBlocks)444 dbgs() << " " << printMBBReference(*B);445 dbgs() << " }\n";446 });447 // No frame needed?448 if (SFBlocks.empty())449 return;450 451 // Pick a common dominator and a common post-dominator.452 MachineBasicBlock *DomB = SFBlocks[0];453 for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {454 DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);455 if (!DomB)456 break;457 }458 MachineBasicBlock *PDomB = SFBlocks[0];459 for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {460 PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);461 if (!PDomB)462 break;463 }464 LLVM_DEBUG({465 dbgs() << "Computed dom block: ";466 if (DomB)467 dbgs() << printMBBReference(*DomB);468 else469 dbgs() << "<null>";470 dbgs() << ", computed pdom block: ";471 if (PDomB)472 dbgs() << printMBBReference(*PDomB);473 else474 dbgs() << "<null>";475 dbgs() << "\n";476 });477 if (!DomB || !PDomB)478 return;479 480 // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.481 if (!MDT.dominates(DomB, PDomB)) {482 LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n");483 return;484 }485 if (!MPT.dominates(PDomB, DomB)) {486 LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");487 return;488 }489 490 // Finally, everything seems right.491 PrologB = DomB;492 EpilogB = PDomB;493}494 495/// Perform most of the PEI work here:496/// - saving/restoring of the callee-saved registers,497/// - stack frame creation and destruction.498/// Normally, this work is distributed among various functions, but doing it499/// in one place allows shrink-wrapping of the stack frame.500void HexagonFrameLowering::emitPrologue(MachineFunction &MF,501 MachineBasicBlock &MBB) const {502 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();503 504 MachineFrameInfo &MFI = MF.getFrameInfo();505 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();506 507 MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;508 if (EnableShrinkWrapping)509 findShrunkPrologEpilog(MF, PrologB, EpilogB);510 511 bool PrologueStubs = false;512 insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);513 insertPrologueInBlock(*PrologB, PrologueStubs);514 updateEntryPaths(MF, *PrologB);515 516 if (EpilogB) {517 insertCSRRestoresInBlock(*EpilogB, CSI, HRI);518 insertEpilogueInBlock(*EpilogB);519 } else {520 for (auto &B : MF)521 if (B.isReturnBlock())522 insertCSRRestoresInBlock(B, CSI, HRI);523 524 for (auto &B : MF)525 if (B.isReturnBlock())526 insertEpilogueInBlock(B);527 528 for (auto &B : MF) {529 if (B.empty())530 continue;531 MachineInstr *RetI = getReturn(B);532 if (!RetI || isRestoreCall(RetI->getOpcode()))533 continue;534 for (auto &R : CSI)535 RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));536 }537 }538 539 if (EpilogB) {540 // If there is an epilog block, it may not have a return instruction.541 // In such case, we need to add the callee-saved registers as live-ins542 // in all blocks on all paths from the epilog to any return block.543 unsigned MaxBN = MF.getNumBlockIDs();544 BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);545 updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);546 }547}548 549/// Returns true if the target can safely skip saving callee-saved registers550/// for noreturn nounwind functions.551bool HexagonFrameLowering::enableCalleeSaveSkip(552 const MachineFunction &MF) const {553 const auto &F = MF.getFunction();554 assert(F.hasFnAttribute(Attribute::NoReturn) &&555 F.getFunction().hasFnAttribute(Attribute::NoUnwind) &&556 !F.getFunction().hasFnAttribute(Attribute::UWTable));557 (void)F;558 559 // No need to save callee saved registers if the function does not return.560 return MF.getSubtarget<HexagonSubtarget>().noreturnStackElim();561}562 563// Helper function used to determine when to eliminate the stack frame for564// functions marked as noreturn and when the noreturn-stack-elim options are565// specified. When both these conditions are true, then a FP may not be needed566// if the function makes a call. It is very similar to enableCalleeSaveSkip,567// but it used to check if the allocframe can be eliminated as well.568static bool enableAllocFrameElim(const MachineFunction &MF) {569 const auto &F = MF.getFunction();570 const auto &MFI = MF.getFrameInfo();571 const auto &HST = MF.getSubtarget<HexagonSubtarget>();572 assert(!MFI.hasVarSizedObjects() &&573 !HST.getRegisterInfo()->hasStackRealignment(MF));574 return F.hasFnAttribute(Attribute::NoReturn) &&575 F.hasFnAttribute(Attribute::NoUnwind) &&576 !F.hasFnAttribute(Attribute::UWTable) && HST.noreturnStackElim() &&577 MFI.getStackSize() == 0;578}579 580void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,581 bool PrologueStubs) const {582 MachineFunction &MF = *MBB.getParent();583 MachineFrameInfo &MFI = MF.getFrameInfo();584 auto &HST = MF.getSubtarget<HexagonSubtarget>();585 auto &HII = *HST.getInstrInfo();586 auto &HRI = *HST.getRegisterInfo();587 588 Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign());589 590 // Calculate the total stack frame size.591 // Get the number of bytes to allocate from the FrameInfo.592 unsigned FrameSize = MFI.getStackSize();593 // Round up the max call frame size to the max alignment on the stack.594 unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);595 MFI.setMaxCallFrameSize(MaxCFA);596 597 FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);598 MFI.setStackSize(FrameSize);599 600 bool AlignStack = (MaxAlign > getStackAlign());601 602 // Get the number of bytes to allocate from the FrameInfo.603 unsigned NumBytes = MFI.getStackSize();604 Register SP = HRI.getStackRegister();605 unsigned MaxCF = MFI.getMaxCallFrameSize();606 MachineBasicBlock::iterator InsertPt = MBB.begin();607 608 SmallVector<MachineInstr *, 4> AdjustRegs;609 for (auto &MBB : MF)610 for (auto &MI : MBB)611 if (MI.getOpcode() == Hexagon::PS_alloca)612 AdjustRegs.push_back(&MI);613 614 for (auto *MI : AdjustRegs) {615 assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");616 expandAlloca(MI, HII, SP, MaxCF);617 MI->eraseFromParent();618 }619 620 DebugLoc dl = MBB.findDebugLoc(InsertPt);621 622 if (MF.getFunction().isVarArg() &&623 MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {624 // Calculate the size of register saved area.625 int NumVarArgRegs = 6 - FirstVarArgSavedReg;626 int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0)627 ? NumVarArgRegs * 4628 : NumVarArgRegs * 4 + 4;629 if (RegisterSavedAreaSizePlusPadding > 0) {630 // Decrement the stack pointer by size of register saved area plus631 // padding if any.632 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)633 .addReg(SP)634 .addImm(-RegisterSavedAreaSizePlusPadding)635 .setMIFlag(MachineInstr::FrameSetup);636 637 int NumBytes = 0;638 // Copy all the named arguments below register saved area.639 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();640 for (int i = HMFI.getFirstNamedArgFrameIndex(),641 e = HMFI.getLastNamedArgFrameIndex(); i >= e; --i) {642 uint64_t ObjSize = MFI.getObjectSize(i);643 Align ObjAlign = MFI.getObjectAlign(i);644 645 // Determine the kind of load/store that should be used.646 unsigned LDOpc, STOpc;647 uint64_t OpcodeChecker = ObjAlign.value();648 649 // Handle cases where alignment of an object is > its size.650 if (ObjAlign > ObjSize) {651 if (ObjSize <= 1)652 OpcodeChecker = 1;653 else if (ObjSize <= 2)654 OpcodeChecker = 2;655 else if (ObjSize <= 4)656 OpcodeChecker = 4;657 else if (ObjSize > 4)658 OpcodeChecker = 8;659 }660 661 switch (OpcodeChecker) {662 case 1:663 LDOpc = Hexagon::L2_loadrb_io;664 STOpc = Hexagon::S2_storerb_io;665 break;666 case 2:667 LDOpc = Hexagon::L2_loadrh_io;668 STOpc = Hexagon::S2_storerh_io;669 break;670 case 4:671 LDOpc = Hexagon::L2_loadri_io;672 STOpc = Hexagon::S2_storeri_io;673 break;674 case 8:675 default:676 LDOpc = Hexagon::L2_loadrd_io;677 STOpc = Hexagon::S2_storerd_io;678 break;679 }680 681 Register RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3682 : Hexagon::R6;683 int LoadStoreCount = ObjSize / OpcodeChecker;684 685 if (ObjSize % OpcodeChecker)686 ++LoadStoreCount;687 688 // Get the start location of the load. NumBytes is basically the689 // offset from the stack pointer of previous function, which would be690 // the caller in this case, as this function has variable argument691 // list.692 if (NumBytes != 0)693 NumBytes = alignTo(NumBytes, ObjAlign);694 695 int Count = 0;696 while (Count < LoadStoreCount) {697 // Load the value of the named argument on stack.698 BuildMI(MBB, InsertPt, dl, HII.get(LDOpc), RegUsed)699 .addReg(SP)700 .addImm(RegisterSavedAreaSizePlusPadding +701 ObjAlign.value() * Count + NumBytes)702 .setMIFlag(MachineInstr::FrameSetup);703 704 // Store it below the register saved area plus padding.705 BuildMI(MBB, InsertPt, dl, HII.get(STOpc))706 .addReg(SP)707 .addImm(ObjAlign.value() * Count + NumBytes)708 .addReg(RegUsed)709 .setMIFlag(MachineInstr::FrameSetup);710 711 Count++;712 }713 NumBytes += MFI.getObjectSize(i);714 }715 716 // Make NumBytes 8 byte aligned717 NumBytes = alignTo(NumBytes, 8);718 719 // If the number of registers having variable arguments is odd,720 // leave 4 bytes of padding to get to the location where first721 // variable argument which was passed through register was copied.722 NumBytes = (NumVarArgRegs % 2 == 0) ? NumBytes : NumBytes + 4;723 724 for (int j = FirstVarArgSavedReg, i = 0; j < 6; ++j, ++i) {725 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io))726 .addReg(SP)727 .addImm(NumBytes + 4 * i)728 .addReg(Hexagon::R0 + j)729 .setMIFlag(MachineInstr::FrameSetup);730 }731 }732 }733 734 if (hasFP(MF)) {735 insertAllocframe(MBB, InsertPt, NumBytes);736 if (AlignStack) {737 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)738 .addReg(SP)739 .addImm(-int64_t(MaxAlign.value()));740 }741 // If the stack-checking is enabled, and we spilled the callee-saved742 // registers inline (i.e. did not use a spill function), then call743 // the stack checker directly.744 if (EnableStackOVFSanitizer && !PrologueStubs)745 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))746 .addExternalSymbol("__runtime_stack_check");747 } else if (NumBytes > 0) {748 assert(alignTo(NumBytes, 8) == NumBytes);749 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)750 .addReg(SP)751 .addImm(-int(NumBytes));752 }753}754 755void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {756 MachineFunction &MF = *MBB.getParent();757 auto &HST = MF.getSubtarget<HexagonSubtarget>();758 auto &HII = *HST.getInstrInfo();759 auto &HRI = *HST.getRegisterInfo();760 Register SP = HRI.getStackRegister();761 762 MachineBasicBlock::iterator InsertPt = MBB.getFirstTerminator();763 DebugLoc dl = MBB.findDebugLoc(InsertPt);764 765 if (!hasFP(MF)) {766 MachineFrameInfo &MFI = MF.getFrameInfo();767 unsigned NumBytes = MFI.getStackSize();768 if (MF.getFunction().isVarArg() &&769 MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {770 // On Hexagon Linux, deallocate the stack for the register saved area.771 int NumVarArgRegs = 6 - FirstVarArgSavedReg;772 int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?773 (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);774 NumBytes += RegisterSavedAreaSizePlusPadding;775 }776 if (NumBytes) {777 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)778 .addReg(SP)779 .addImm(NumBytes);780 }781 return;782 }783 784 MachineInstr *RetI = getReturn(MBB);785 unsigned RetOpc = RetI ? RetI->getOpcode() : 0;786 787 // Handle EH_RETURN.788 if (RetOpc == Hexagon::EH_RETURN_JMPR) {789 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))790 .addDef(Hexagon::D15)791 .addReg(Hexagon::R30);792 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)793 .addReg(SP)794 .addReg(Hexagon::R28);795 return;796 }797 798 // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-799 // frame instruction if we encounter it.800 if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||801 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||802 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||803 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {804 MachineBasicBlock::iterator It = RetI;805 ++It;806 // Delete all instructions after the RESTORE (except labels).807 while (It != MBB.end()) {808 if (!It->isLabel())809 It = MBB.erase(It);810 else811 ++It;812 }813 return;814 }815 816 // It is possible that the restoring code is a call to a library function.817 // All of the restore* functions include "deallocframe", so we need to make818 // sure that we don't add an extra one.819 bool NeedsDeallocframe = true;820 if (!MBB.empty() && InsertPt != MBB.begin()) {821 MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);822 unsigned COpc = PrevIt->getOpcode();823 if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||824 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||825 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||826 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||827 COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)828 NeedsDeallocframe = false;829 }830 831 if (!MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl() ||832 !MF.getFunction().isVarArg()) {833 if (!NeedsDeallocframe)834 return;835 // If the returning instruction is PS_jmpret, replace it with836 // dealloc_return, otherwise just add deallocframe. The function837 // could be returning via a tail call.838 if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {839 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))840 .addDef(Hexagon::D15)841 .addReg(Hexagon::R30);842 return;843 }844 unsigned NewOpc = Hexagon::L4_return;845 MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))846 .addDef(Hexagon::D15)847 .addReg(Hexagon::R30);848 // Transfer the function live-out registers.849 NewI->copyImplicitOps(MF, *RetI);850 MBB.erase(RetI);851 } else {852 // L2_deallocframe instruction after it.853 // Calculate the size of register saved area.854 int NumVarArgRegs = 6 - FirstVarArgSavedReg;855 int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?856 (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);857 858 MachineBasicBlock::iterator Term = MBB.getFirstTerminator();859 MachineBasicBlock::iterator I = (Term == MBB.begin()) ? MBB.end()860 : std::prev(Term);861 if (I == MBB.end() ||862 (I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT &&863 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC &&864 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 &&865 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC))866 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))867 .addDef(Hexagon::D15)868 .addReg(Hexagon::R30);869 if (RegisterSavedAreaSizePlusPadding != 0)870 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)871 .addReg(SP)872 .addImm(RegisterSavedAreaSizePlusPadding);873 }874}875 876void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,877 MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {878 MachineFunction &MF = *MBB.getParent();879 auto &HST = MF.getSubtarget<HexagonSubtarget>();880 auto &HII = *HST.getInstrInfo();881 auto &HRI = *HST.getRegisterInfo();882 883 // Check for overflow.884 // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?885 const unsigned int ALLOCFRAME_MAX = 16384;886 887 // Create a dummy memory operand to avoid allocframe from being treated as888 // a volatile memory reference.889 auto *MMO = MF.getMachineMemOperand(MachinePointerInfo::getStack(MF, 0),890 MachineMemOperand::MOStore, 4, Align(4));891 892 DebugLoc dl = MBB.findDebugLoc(InsertPt);893 Register SP = HRI.getStackRegister();894 895 if (NumBytes >= ALLOCFRAME_MAX) {896 // Emit allocframe(#0).897 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))898 .addDef(SP)899 .addReg(SP)900 .addImm(0)901 .addMemOperand(MMO)902 .setMIFlag(MachineInstr::FrameSetup);903 904 // Subtract the size from the stack pointer.905 Register SP = HRI.getStackRegister();906 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)907 .addReg(SP)908 .addImm(-int(NumBytes))909 .setMIFlag(MachineInstr::FrameSetup);910 } else {911 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))912 .addDef(SP)913 .addReg(SP)914 .addImm(NumBytes)915 .addMemOperand(MMO)916 .setMIFlag(MachineInstr::FrameSetup);917 }918}919 920void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,921 MachineBasicBlock &SaveB) const {922 SetVector<unsigned> Worklist;923 924 MachineBasicBlock &EntryB = MF.front();925 Worklist.insert(EntryB.getNumber());926 927 unsigned SaveN = SaveB.getNumber();928 auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();929 930 for (unsigned i = 0; i < Worklist.size(); ++i) {931 unsigned BN = Worklist[i];932 MachineBasicBlock &MBB = *MF.getBlockNumbered(BN);933 for (auto &R : CSI)934 if (!MBB.isLiveIn(R.getReg()))935 MBB.addLiveIn(R.getReg());936 if (BN != SaveN)937 for (auto &SB : MBB.successors())938 Worklist.insert(SB->getNumber());939 }940}941 942bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,943 MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,944 BitVector &Path) const {945 assert(MBB.getNumber() >= 0);946 unsigned BN = MBB.getNumber();947 if (Path[BN] || DoneF[BN])948 return false;949 if (DoneT[BN])950 return true;951 952 auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();953 954 Path[BN] = true;955 bool ReachedExit = false;956 for (auto &SB : MBB.successors())957 ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);958 959 if (!MBB.empty() && MBB.back().isReturn()) {960 // Add implicit uses of all callee-saved registers to the reached961 // return instructions. This is to prevent the anti-dependency breaker962 // from renaming these registers.963 MachineInstr &RetI = MBB.back();964 if (!isRestoreCall(RetI.getOpcode()))965 for (auto &R : CSI)966 RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));967 ReachedExit = true;968 }969 970 // We don't want to add unnecessary live-ins to the restore block: since971 // the callee-saved registers are being defined in it, the entry of the972 // restore block cannot be on the path from the definitions to any exit.973 if (ReachedExit && &MBB != &RestoreB) {974 for (auto &R : CSI)975 if (!MBB.isLiveIn(R.getReg()))976 MBB.addLiveIn(R.getReg());977 DoneT[BN] = true;978 }979 if (!ReachedExit)980 DoneF[BN] = true;981 982 Path[BN] = false;983 return ReachedExit;984}985 986static std::optional<MachineBasicBlock::iterator>987findCFILocation(MachineBasicBlock &B) {988 // The CFI instructions need to be inserted right after allocframe.989 // An exception to this is a situation where allocframe is bundled990 // with a call: then the CFI instructions need to be inserted before991 // the packet with the allocframe+call (in case the call throws an992 // exception).993 auto End = B.instr_end();994 995 for (MachineInstr &I : B) {996 MachineBasicBlock::iterator It = I.getIterator();997 if (!I.isBundle()) {998 if (I.getOpcode() == Hexagon::S2_allocframe)999 return std::next(It);1000 continue;1001 }1002 // I is a bundle.1003 bool HasCall = false, HasAllocFrame = false;1004 auto T = It.getInstrIterator();1005 while (++T != End && T->isBundled()) {1006 if (T->getOpcode() == Hexagon::S2_allocframe)1007 HasAllocFrame = true;1008 else if (T->isCall())1009 HasCall = true;1010 }1011 if (HasAllocFrame)1012 return HasCall ? It : std::next(It);1013 }1014 return std::nullopt;1015}1016 1017void HexagonFrameLowering::insertCFIInstructions(MachineFunction &MF) const {1018 for (auto &B : MF)1019 if (auto At = findCFILocation(B))1020 insertCFIInstructionsAt(B, *At);1021}1022 1023void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,1024 MachineBasicBlock::iterator At) const {1025 MachineFunction &MF = *MBB.getParent();1026 MachineFrameInfo &MFI = MF.getFrameInfo();1027 auto &HST = MF.getSubtarget<HexagonSubtarget>();1028 auto &HII = *HST.getInstrInfo();1029 auto &HRI = *HST.getRegisterInfo();1030 1031 // If CFI instructions have debug information attached, something goes1032 // wrong with the final assembly generation: the prolog_end is placed1033 // in a wrong location.1034 DebugLoc DL;1035 const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);1036 1037 MCSymbol *FrameLabel = MF.getContext().createTempSymbol();1038 bool HasFP = hasFP(MF);1039 1040 if (HasFP) {1041 unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);1042 unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);1043 1044 // Define CFA via an offset from the value of FP.1045 //1046 // -8 -4 0 (SP)1047 // --+----+----+---------------------1048 // | FP | LR | increasing addresses -->1049 // --+----+----+---------------------1050 // | +-- Old SP (before allocframe)1051 // +-- New FP (after allocframe)1052 //1053 // MCCFIInstruction::cfiDefCfa adds the offset from the register.1054 // MCCFIInstruction::createOffset takes the offset without sign change.1055 auto DefCfa = MCCFIInstruction::cfiDefCfa(FrameLabel, DwFPReg, 8);1056 BuildMI(MBB, At, DL, CFID)1057 .addCFIIndex(MF.addFrameInst(DefCfa));1058 // R31 (return addr) = CFA - 41059 auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);1060 BuildMI(MBB, At, DL, CFID)1061 .addCFIIndex(MF.addFrameInst(OffR31));1062 // R30 (frame ptr) = CFA - 81063 auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);1064 BuildMI(MBB, At, DL, CFID)1065 .addCFIIndex(MF.addFrameInst(OffR30));1066 }1067 1068 static const MCPhysReg RegsToMove[] = {1069 Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,1070 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,1071 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,1072 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,1073 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,1074 Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D131075 };1076 1077 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();1078 1079 for (MCPhysReg Reg : RegsToMove) {1080 auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {1081 return C.getReg() == Reg;1082 };1083 auto F = find_if(CSI, IfR);1084 if (F == CSI.end())1085 continue;1086 1087 int64_t Offset;1088 if (HasFP) {1089 // If the function has a frame pointer (i.e. has an allocframe),1090 // then the CFA has been defined in terms of FP. Any offsets in1091 // the following CFI instructions have to be defined relative1092 // to FP, which points to the bottom of the stack frame.1093 // The function getFrameIndexReference can still choose to use SP1094 // for the offset calculation, so we cannot simply call it here.1095 // Instead, get the offset (relative to the FP) directly.1096 Offset = MFI.getObjectOffset(F->getFrameIdx());1097 } else {1098 Register FrameReg;1099 Offset =1100 getFrameIndexReference(MF, F->getFrameIdx(), FrameReg).getFixed();1101 }1102 // Subtract 8 to make room for R30 and R31, which are added above.1103 Offset -= 8;1104 1105 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {1106 unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);1107 auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,1108 Offset);1109 BuildMI(MBB, At, DL, CFID)1110 .addCFIIndex(MF.addFrameInst(OffReg));1111 } else {1112 // Split the double regs into subregs, and generate appropriate1113 // cfi_offsets.1114 // The only reason, we are split double regs is, llvm-mc does not1115 // understand paired registers for cfi_offset.1116 // Eg .cfi_offset r1:0, -641117 1118 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);1119 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);1120 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);1121 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);1122 auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,1123 Offset+4);1124 BuildMI(MBB, At, DL, CFID)1125 .addCFIIndex(MF.addFrameInst(OffHi));1126 auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,1127 Offset);1128 BuildMI(MBB, At, DL, CFID)1129 .addCFIIndex(MF.addFrameInst(OffLo));1130 }1131 }1132}1133 1134bool HexagonFrameLowering::hasFPImpl(const MachineFunction &MF) const {1135 auto &MFI = MF.getFrameInfo();1136 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();1137 bool HasExtraAlign = HRI.hasStackRealignment(MF);1138 bool HasAlloca = MFI.hasVarSizedObjects();1139 1140 // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think1141 // that this shouldn't be required, but doing so now because gcc does and1142 // gdb can't break at the start of the function without it. Will remove if1143 // this turns out to be a gdb bug.1144 //1145 if (MF.getTarget().getOptLevel() == CodeGenOptLevel::None)1146 return true;1147 1148 // By default we want to use SP (since it's always there). FP requires1149 // some setup (i.e. ALLOCFRAME).1150 // Both, alloca and stack alignment modify the stack pointer by an1151 // undetermined value, so we need to save it at the entry to the function1152 // (i.e. use allocframe).1153 if (HasAlloca || HasExtraAlign)1154 return true;1155 1156 if (MFI.getStackSize() > 0) {1157 // If FP-elimination is disabled, we have to use FP at this point.1158 const TargetMachine &TM = MF.getTarget();1159 if (TM.Options.DisableFramePointerElim(MF) || !EliminateFramePointer)1160 return true;1161 if (EnableStackOVFSanitizer)1162 return true;1163 }1164 1165 const auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();1166 if ((MFI.hasCalls() && !enableAllocFrameElim(MF)) || HMFI.hasClobberLR())1167 return true;1168 1169 return false;1170}1171 1172enum SpillKind {1173 SK_ToMem,1174 SK_FromMem,1175 SK_FromMemTailcall1176};1177 1178static const char *getSpillFunctionFor(Register MaxReg, SpillKind SpillType,1179 bool Stkchk = false) {1180 const char * V4SpillToMemoryFunctions[] = {1181 "__save_r16_through_r17",1182 "__save_r16_through_r19",1183 "__save_r16_through_r21",1184 "__save_r16_through_r23",1185 "__save_r16_through_r25",1186 "__save_r16_through_r27" };1187 1188 const char * V4SpillToMemoryStkchkFunctions[] = {1189 "__save_r16_through_r17_stkchk",1190 "__save_r16_through_r19_stkchk",1191 "__save_r16_through_r21_stkchk",1192 "__save_r16_through_r23_stkchk",1193 "__save_r16_through_r25_stkchk",1194 "__save_r16_through_r27_stkchk" };1195 1196 const char * V4SpillFromMemoryFunctions[] = {1197 "__restore_r16_through_r17_and_deallocframe",1198 "__restore_r16_through_r19_and_deallocframe",1199 "__restore_r16_through_r21_and_deallocframe",1200 "__restore_r16_through_r23_and_deallocframe",1201 "__restore_r16_through_r25_and_deallocframe",1202 "__restore_r16_through_r27_and_deallocframe" };1203 1204 const char * V4SpillFromMemoryTailcallFunctions[] = {1205 "__restore_r16_through_r17_and_deallocframe_before_tailcall",1206 "__restore_r16_through_r19_and_deallocframe_before_tailcall",1207 "__restore_r16_through_r21_and_deallocframe_before_tailcall",1208 "__restore_r16_through_r23_and_deallocframe_before_tailcall",1209 "__restore_r16_through_r25_and_deallocframe_before_tailcall",1210 "__restore_r16_through_r27_and_deallocframe_before_tailcall"1211 };1212 1213 const char **SpillFunc = nullptr;1214 1215 switch(SpillType) {1216 case SK_ToMem:1217 SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions1218 : V4SpillToMemoryFunctions;1219 break;1220 case SK_FromMem:1221 SpillFunc = V4SpillFromMemoryFunctions;1222 break;1223 case SK_FromMemTailcall:1224 SpillFunc = V4SpillFromMemoryTailcallFunctions;1225 break;1226 }1227 assert(SpillFunc && "Unknown spill kind");1228 1229 // Spill all callee-saved registers up to the highest register used.1230 switch (MaxReg) {1231 case Hexagon::R17:1232 return SpillFunc[0];1233 case Hexagon::R19:1234 return SpillFunc[1];1235 case Hexagon::R21:1236 return SpillFunc[2];1237 case Hexagon::R23:1238 return SpillFunc[3];1239 case Hexagon::R25:1240 return SpillFunc[4];1241 case Hexagon::R27:1242 return SpillFunc[5];1243 default:1244 llvm_unreachable("Unhandled maximum callee save register");1245 }1246 return nullptr;1247}1248 1249StackOffset1250HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,1251 Register &FrameReg) const {1252 auto &MFI = MF.getFrameInfo();1253 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();1254 1255 int Offset = MFI.getObjectOffset(FI);1256 bool HasAlloca = MFI.hasVarSizedObjects();1257 bool HasExtraAlign = HRI.hasStackRealignment(MF);1258 bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOptLevel::None;1259 1260 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();1261 unsigned FrameSize = MFI.getStackSize();1262 Register SP = HRI.getStackRegister();1263 Register FP = HRI.getFrameRegister();1264 Register AP = HMFI.getStackAlignBaseReg();1265 // It may happen that AP will be absent even HasAlloca && HasExtraAlign1266 // is true. HasExtraAlign may be set because of vector spills, without1267 // aligned locals or aligned outgoing function arguments. Since vector1268 // spills will ultimately be "unaligned", it is safe to use FP as the1269 // base register.1270 // In fact, in such a scenario the stack is actually not required to be1271 // aligned, although it may end up being aligned anyway, since this1272 // particular case is not easily detectable. The alignment will be1273 // unnecessary, but not incorrect.1274 // Unfortunately there is no quick way to verify that the above is1275 // indeed the case (and that it's not a result of an error), so just1276 // assume that missing AP will be replaced by FP.1277 // (A better fix would be to rematerialize AP from FP and always align1278 // vector spills.)1279 bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).1280 // Use FP at -O0, except when there are objects with extra alignment.1281 // That additional alignment requirement may cause a pad to be inserted,1282 // which will make it impossible to use FP to access objects located1283 // past the pad.1284 if (NoOpt && !HasExtraAlign)1285 UseFP = true;1286 if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {1287 // Fixed and preallocated objects will be located before any padding1288 // so FP must be used to access them.1289 UseFP |= (HasAlloca || HasExtraAlign);1290 } else {1291 if (HasAlloca) {1292 if (HasExtraAlign)1293 UseAP = true;1294 else1295 UseFP = true;1296 }1297 }1298 1299 // If FP was picked, then there had better be FP.1300 bool HasFP = hasFP(MF);1301 assert((HasFP || !UseFP) && "This function must have frame pointer");1302 1303 // Having FP implies allocframe. Allocframe will store extra 8 bytes:1304 // FP/LR. If the base register is used to access an object across these1305 // 8 bytes, then the offset will need to be adjusted by 8.1306 //1307 // After allocframe:1308 // HexagonISelLowering adds 8 to ---+1309 // the offsets of all stack-based |1310 // arguments (*) |1311 // |1312 // getObjectOffset < 0 0 8 getObjectOffset >= 81313 // ------------------------+-----+------------------------> increasing1314 // <local objects> |FP/LR| <input arguments> addresses1315 // -----------------+------+-----+------------------------>1316 // | |1317 // SP/AP point --+ +-- FP points here (**)1318 // somewhere on1319 // this side of FP/LR1320 //1321 // (*) See LowerFormalArguments. The FP/LR is assumed to be present.1322 // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.1323 1324 // The lowering assumes that FP/LR is present, and so the offsets of1325 // the formal arguments start at 8. If FP/LR is not there we need to1326 // reduce the offset by 8.1327 if (Offset > 0 && !HasFP)1328 Offset -= 8;1329 1330 if (UseFP)1331 FrameReg = FP;1332 else if (UseAP)1333 FrameReg = AP;1334 else1335 FrameReg = SP;1336 1337 // Calculate the actual offset in the instruction. If there is no FP1338 // (in other words, no allocframe), then SP will not be adjusted (i.e.1339 // there will be no SP -= FrameSize), so the frame size should not be1340 // added to the calculated offset.1341 int RealOffset = Offset;1342 if (!UseFP && !UseAP)1343 RealOffset = FrameSize+Offset;1344 return StackOffset::getFixed(RealOffset);1345}1346 1347bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,1348 const CSIVect &CSI, const HexagonRegisterInfo &HRI,1349 bool &PrologueStubs) const {1350 if (CSI.empty())1351 return true;1352 1353 MachineBasicBlock::iterator MI = MBB.begin();1354 PrologueStubs = false;1355 MachineFunction &MF = *MBB.getParent();1356 auto &HST = MF.getSubtarget<HexagonSubtarget>();1357 auto &HII = *HST.getInstrInfo();1358 1359 if (useSpillFunction(MF, CSI)) {1360 PrologueStubs = true;1361 Register MaxReg = getMaxCalleeSavedReg(CSI, HRI);1362 bool StkOvrFlowEnabled = EnableStackOVFSanitizer;1363 const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,1364 StkOvrFlowEnabled);1365 auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());1366 bool IsPIC = HTM.isPositionIndependent();1367 bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;1368 1369 // Call spill function.1370 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();1371 unsigned SpillOpc;1372 if (StkOvrFlowEnabled) {1373 if (LongCalls)1374 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC1375 : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;1376 else1377 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC1378 : Hexagon::SAVE_REGISTERS_CALL_V4STK;1379 } else {1380 if (LongCalls)1381 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC1382 : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;1383 else1384 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC1385 : Hexagon::SAVE_REGISTERS_CALL_V4;1386 }1387 1388 MachineInstr *SaveRegsCall =1389 BuildMI(MBB, MI, DL, HII.get(SpillOpc))1390 .addExternalSymbol(SpillFun);1391 1392 // Add callee-saved registers as use.1393 addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);1394 // Add live in registers.1395 for (const CalleeSavedInfo &I : CSI)1396 MBB.addLiveIn(I.getReg());1397 return true;1398 }1399 1400 for (const CalleeSavedInfo &I : CSI) {1401 MCRegister Reg = I.getReg();1402 // Add live in registers. We treat eh_return callee saved register r0 - r31403 // specially. They are not really callee saved registers as they are not1404 // supposed to be killed.1405 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);1406 int FI = I.getFrameIdx();1407 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);1408 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, Register());1409 if (IsKill)1410 MBB.addLiveIn(Reg);1411 }1412 return true;1413}1414 1415bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,1416 const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {1417 if (CSI.empty())1418 return false;1419 1420 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();1421 MachineFunction &MF = *MBB.getParent();1422 auto &HST = MF.getSubtarget<HexagonSubtarget>();1423 auto &HII = *HST.getInstrInfo();1424 1425 if (useRestoreFunction(MF, CSI)) {1426 bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);1427 Register MaxR = getMaxCalleeSavedReg(CSI, HRI);1428 SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem;1429 const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);1430 auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());1431 bool IsPIC = HTM.isPositionIndependent();1432 bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;1433 1434 // Call spill function.1435 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()1436 : MBB.findDebugLoc(MBB.end());1437 MachineInstr *DeallocCall = nullptr;1438 1439 if (HasTC) {1440 unsigned RetOpc;1441 if (LongCalls)1442 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC1443 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;1444 else1445 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC1446 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;1447 DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))1448 .addExternalSymbol(RestoreFn);1449 } else {1450 // The block has a return.1451 MachineBasicBlock::iterator It = MBB.getFirstTerminator();1452 assert(It->isReturn() && std::next(It) == MBB.end());1453 unsigned RetOpc;1454 if (LongCalls)1455 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC1456 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;1457 else1458 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC1459 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;1460 DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))1461 .addExternalSymbol(RestoreFn);1462 // Transfer the function live-out registers.1463 DeallocCall->copyImplicitOps(MF, *It);1464 }1465 addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);1466 return true;1467 }1468 1469 for (const CalleeSavedInfo &I : CSI) {1470 MCRegister Reg = I.getReg();1471 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);1472 int FI = I.getFrameIdx();1473 HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, Register());1474 }1475 1476 return true;1477}1478 1479MachineBasicBlock::iterator HexagonFrameLowering::eliminateCallFramePseudoInstr(1480 MachineFunction &MF, MachineBasicBlock &MBB,1481 MachineBasicBlock::iterator I) const {1482 MachineInstr &MI = *I;1483 unsigned Opc = MI.getOpcode();1484 (void)Opc; // Silence compiler warning.1485 assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&1486 "Cannot handle this call frame pseudo instruction");1487 return MBB.erase(I);1488}1489 1490void HexagonFrameLowering::processFunctionBeforeFrameFinalized(1491 MachineFunction &MF, RegScavenger *RS) const {1492 // If this function has uses aligned stack and also has variable sized stack1493 // objects, then we need to map all spill slots to fixed positions, so that1494 // they can be accessed through FP. Otherwise they would have to be accessed1495 // via AP, which may not be available at the particular place in the program.1496 MachineFrameInfo &MFI = MF.getFrameInfo();1497 bool HasAlloca = MFI.hasVarSizedObjects();1498 bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign());1499 1500 if (!HasAlloca || !NeedsAlign)1501 return;1502 1503 // Set the physical aligned-stack base address register.1504 MCRegister AP;1505 if (const MachineInstr *AI = getAlignaInstr(MF))1506 AP = AI->getOperand(0).getReg();1507 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();1508 assert(!AP.isValid() || AP.isPhysical());1509 HMFI.setStackAlignBaseReg(AP);1510}1511 1512/// Returns true if there are no caller-saved registers available in class RC.1513static bool needToReserveScavengingSpillSlots(MachineFunction &MF,1514 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {1515 MachineRegisterInfo &MRI = MF.getRegInfo();1516 1517 auto IsUsed = [&HRI,&MRI] (Register Reg) -> bool {1518 for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)1519 if (MRI.isPhysRegUsed(*AI))1520 return true;1521 return false;1522 };1523 1524 // Check for an unused caller-saved register. Callee-saved registers1525 // have become pristine by now.1526 for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)1527 if (!IsUsed(*P))1528 return false;1529 1530 // All caller-saved registers are used.1531 return true;1532}1533 1534#ifndef NDEBUG1535static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {1536 dbgs() << '{';1537 for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {1538 Register R = x;1539 dbgs() << ' ' << printReg(R, &TRI);1540 }1541 dbgs() << " }";1542}1543#endif1544 1545bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,1546 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {1547 LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n');1548 MachineFrameInfo &MFI = MF.getFrameInfo();1549 BitVector SRegs(Hexagon::NUM_TARGET_REGS);1550 1551 // Generate a set of unique, callee-saved registers (SRegs), where each1552 // register in the set is maximal in terms of sub-/super-register relation,1553 // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.1554 1555 // (1) For each callee-saved register, add that register and all of its1556 // sub-registers to SRegs.1557 LLVM_DEBUG(dbgs() << "Initial CS registers: {");1558 for (const CalleeSavedInfo &I : CSI) {1559 Register R = I.getReg();1560 LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));1561 for (MCPhysReg SR : TRI->subregs_inclusive(R))1562 SRegs[SR] = true;1563 }1564 LLVM_DEBUG(dbgs() << " }\n");1565 LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);1566 dbgs() << "\n");1567 1568 // (2) For each reserved register, remove that register and all of its1569 // sub- and super-registers from SRegs.1570 BitVector Reserved = TRI->getReservedRegs(MF);1571 // Unreserve the stack align register: it is reserved for this function1572 // only, it still needs to be saved/restored.1573 Register AP =1574 MF.getInfo<HexagonMachineFunctionInfo>()->getStackAlignBaseReg();1575 if (AP.isValid()) {1576 Reserved[AP] = false;1577 // Unreserve super-regs if no other subregisters are reserved.1578 for (MCPhysReg SP : TRI->superregs(AP)) {1579 bool HasResSub = false;1580 for (MCPhysReg SB : TRI->subregs(SP)) {1581 if (!Reserved[SB])1582 continue;1583 HasResSub = true;1584 break;1585 }1586 if (!HasResSub)1587 Reserved[SP] = false;1588 }1589 }1590 1591 for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {1592 Register R = x;1593 for (MCPhysReg SR : TRI->superregs_inclusive(R))1594 SRegs[SR] = false;1595 }1596 LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);1597 dbgs() << "\n");1598 LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);1599 dbgs() << "\n");1600 1601 // (3) Collect all registers that have at least one sub-register in SRegs,1602 // and also have no sub-registers that are reserved. These will be the can-1603 // didates for saving as a whole instead of their individual sub-registers.1604 // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)1605 BitVector TmpSup(Hexagon::NUM_TARGET_REGS);1606 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {1607 Register R = x;1608 for (MCPhysReg SR : TRI->superregs(R))1609 TmpSup[SR] = true;1610 }1611 for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {1612 Register R = x;1613 for (MCPhysReg SR : TRI->subregs_inclusive(R)) {1614 if (!Reserved[SR])1615 continue;1616 TmpSup[R] = false;1617 break;1618 }1619 }1620 LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);1621 dbgs() << "\n");1622 1623 // (4) Include all super-registers found in (3) into SRegs.1624 SRegs |= TmpSup;1625 LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);1626 dbgs() << "\n");1627 1628 // (5) For each register R in SRegs, if any super-register of R is in SRegs,1629 // remove R from SRegs.1630 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {1631 Register R = x;1632 for (MCPhysReg SR : TRI->superregs(R)) {1633 if (!SRegs[SR])1634 continue;1635 SRegs[R] = false;1636 break;1637 }1638 }1639 LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);1640 dbgs() << "\n");1641 1642 // Now, for each register that has a fixed stack slot, create the stack1643 // object for it.1644 CSI.clear();1645 1646 using SpillSlot = TargetFrameLowering::SpillSlot;1647 1648 unsigned NumFixed;1649 int64_t MinOffset = 0; // CS offsets are negative.1650 const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);1651 for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {1652 if (!SRegs[S->Reg])1653 continue;1654 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);1655 int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);1656 MinOffset = std::min(MinOffset, S->Offset);1657 CSI.push_back(CalleeSavedInfo(S->Reg, FI));1658 SRegs[S->Reg] = false;1659 }1660 1661 // There can be some registers that don't have fixed slots. For example,1662 // we need to store R0-R3 in functions with exception handling. For each1663 // such register, create a non-fixed stack object.1664 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {1665 Register R = x;1666 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);1667 unsigned Size = TRI->getSpillSize(*RC);1668 int64_t Off = MinOffset - Size;1669 Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign());1670 Off &= -Alignment.value();1671 int FI = MFI.CreateFixedSpillStackObject(Size, Off);1672 MinOffset = std::min(MinOffset, Off);1673 CSI.push_back(CalleeSavedInfo(R, FI));1674 SRegs[R] = false;1675 }1676 1677 LLVM_DEBUG({1678 dbgs() << "CS information: {";1679 for (const CalleeSavedInfo &I : CSI) {1680 int FI = I.getFrameIdx();1681 int Off = MFI.getObjectOffset(FI);1682 dbgs() << ' ' << printReg(I.getReg(), TRI) << ":fi#" << FI << ":sp";1683 if (Off >= 0)1684 dbgs() << '+';1685 dbgs() << Off;1686 }1687 dbgs() << " }\n";1688 });1689 1690#ifndef NDEBUG1691 // Verify that all registers were handled.1692 bool MissedReg = false;1693 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {1694 Register R = x;1695 dbgs() << printReg(R, TRI) << ' ';1696 MissedReg = true;1697 }1698 if (MissedReg)1699 llvm_unreachable("...there are unhandled callee-saved registers!");1700#endif1701 1702 return true;1703}1704 1705bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,1706 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,1707 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {1708 MachineInstr *MI = &*It;1709 DebugLoc DL = MI->getDebugLoc();1710 Register DstR = MI->getOperand(0).getReg();1711 Register SrcR = MI->getOperand(1).getReg();1712 if (!Hexagon::ModRegsRegClass.contains(DstR) ||1713 !Hexagon::ModRegsRegClass.contains(SrcR))1714 return false;1715 1716 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);1717 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));1718 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)1719 .addReg(TmpR, RegState::Kill);1720 1721 NewRegs.push_back(TmpR);1722 B.erase(It);1723 return true;1724}1725 1726bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,1727 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,1728 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {1729 MachineInstr *MI = &*It;1730 if (!MI->getOperand(0).isFI())1731 return false;1732 1733 DebugLoc DL = MI->getDebugLoc();1734 unsigned Opc = MI->getOpcode();1735 Register SrcR = MI->getOperand(2).getReg();1736 bool IsKill = MI->getOperand(2).isKill();1737 int FI = MI->getOperand(0).getIndex();1738 1739 // TmpR = C2_tfrpr SrcR if SrcR is a predicate register1740 // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register1741 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);1742 unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr1743 : Hexagon::A2_tfrcrr;1744 BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)1745 .addReg(SrcR, getKillRegState(IsKill));1746 1747 // S2_storeri_io FI, 0, TmpR1748 BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))1749 .addFrameIndex(FI)1750 .addImm(0)1751 .addReg(TmpR, RegState::Kill)1752 .cloneMemRefs(*MI);1753 1754 NewRegs.push_back(TmpR);1755 B.erase(It);1756 return true;1757}1758 1759bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,1760 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,1761 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {1762 MachineInstr *MI = &*It;1763 if (!MI->getOperand(1).isFI())1764 return false;1765 1766 DebugLoc DL = MI->getDebugLoc();1767 unsigned Opc = MI->getOpcode();1768 Register DstR = MI->getOperand(0).getReg();1769 int FI = MI->getOperand(1).getIndex();1770 1771 // TmpR = L2_loadri_io FI, 01772 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);1773 BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)1774 .addFrameIndex(FI)1775 .addImm(0)1776 .cloneMemRefs(*MI);1777 1778 // DstR = C2_tfrrp TmpR if DstR is a predicate register1779 // DstR = A2_tfrrcr TmpR if DstR is a modifier register1780 unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp1781 : Hexagon::A2_tfrrcr;1782 BuildMI(B, It, DL, HII.get(TfrOpc), DstR)1783 .addReg(TmpR, RegState::Kill);1784 1785 NewRegs.push_back(TmpR);1786 B.erase(It);1787 return true;1788}1789 1790bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,1791 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,1792 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {1793 MachineInstr *MI = &*It;1794 if (!MI->getOperand(0).isFI())1795 return false;1796 1797 DebugLoc DL = MI->getDebugLoc();1798 Register SrcR = MI->getOperand(2).getReg();1799 bool IsKill = MI->getOperand(2).isKill();1800 int FI = MI->getOperand(0).getIndex();1801 auto *RC = &Hexagon::HvxVRRegClass;1802 1803 // Insert transfer to general vector register.1804 // TmpR0 = A2_tfrsi 0x010101011805 // TmpR1 = V6_vandqrt Qx, TmpR01806 // store FI, 0, TmpR11807 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);1808 Register TmpR1 = MRI.createVirtualRegister(RC);1809 1810 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)1811 .addImm(0x01010101);1812 1813 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)1814 .addReg(SrcR, getKillRegState(IsKill))1815 .addReg(TmpR0, RegState::Kill);1816 1817 HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, Register());1818 expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);1819 1820 NewRegs.push_back(TmpR0);1821 NewRegs.push_back(TmpR1);1822 B.erase(It);1823 return true;1824}1825 1826bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,1827 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,1828 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {1829 MachineInstr *MI = &*It;1830 if (!MI->getOperand(1).isFI())1831 return false;1832 1833 DebugLoc DL = MI->getDebugLoc();1834 Register DstR = MI->getOperand(0).getReg();1835 int FI = MI->getOperand(1).getIndex();1836 auto *RC = &Hexagon::HvxVRRegClass;1837 1838 // TmpR0 = A2_tfrsi 0x010101011839 // TmpR1 = load FI, 01840 // DstR = V6_vandvrt TmpR1, TmpR01841 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);1842 Register TmpR1 = MRI.createVirtualRegister(RC);1843 1844 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)1845 .addImm(0x01010101);1846 HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, Register());1847 expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);1848 1849 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)1850 .addReg(TmpR1, RegState::Kill)1851 .addReg(TmpR0, RegState::Kill);1852 1853 NewRegs.push_back(TmpR0);1854 NewRegs.push_back(TmpR1);1855 B.erase(It);1856 return true;1857}1858 1859bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,1860 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,1861 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {1862 MachineFunction &MF = *B.getParent();1863 auto &MFI = MF.getFrameInfo();1864 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();1865 MachineInstr *MI = &*It;1866 if (!MI->getOperand(0).isFI())1867 return false;1868 1869 // It is possible that the double vector being stored is only partially1870 // defined. From the point of view of the liveness tracking, it is ok to1871 // store it as a whole, but if we break it up we may end up storing a1872 // register that is entirely undefined.1873 LivePhysRegs LPR(HRI);1874 LPR.addLiveIns(B);1875 SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers;1876 for (auto R = B.begin(); R != It; ++R) {1877 Clobbers.clear();1878 LPR.stepForward(*R, Clobbers);1879 }1880 1881 DebugLoc DL = MI->getDebugLoc();1882 Register SrcR = MI->getOperand(2).getReg();1883 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);1884 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);1885 bool IsKill = MI->getOperand(2).isKill();1886 int FI = MI->getOperand(0).getIndex();1887 1888 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);1889 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);1890 Align HasAlign = MFI.getObjectAlign(FI);1891 unsigned StoreOpc;1892 1893 // Store low part.1894 if (LPR.contains(SrcLo)) {1895 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai1896 : Hexagon::V6_vS32Ub_ai;1897 BuildMI(B, It, DL, HII.get(StoreOpc))1898 .addFrameIndex(FI)1899 .addImm(0)1900 .addReg(SrcLo, getKillRegState(IsKill))1901 .cloneMemRefs(*MI);1902 }1903 1904 // Store high part.1905 if (LPR.contains(SrcHi)) {1906 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai1907 : Hexagon::V6_vS32Ub_ai;1908 BuildMI(B, It, DL, HII.get(StoreOpc))1909 .addFrameIndex(FI)1910 .addImm(Size)1911 .addReg(SrcHi, getKillRegState(IsKill))1912 .cloneMemRefs(*MI);1913 }1914 1915 B.erase(It);1916 return true;1917}1918 1919bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,1920 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,1921 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {1922 MachineFunction &MF = *B.getParent();1923 auto &MFI = MF.getFrameInfo();1924 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();1925 MachineInstr *MI = &*It;1926 if (!MI->getOperand(1).isFI())1927 return false;1928 1929 DebugLoc DL = MI->getDebugLoc();1930 Register DstR = MI->getOperand(0).getReg();1931 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);1932 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);1933 int FI = MI->getOperand(1).getIndex();1934 1935 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);1936 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);1937 Align HasAlign = MFI.getObjectAlign(FI);1938 unsigned LoadOpc;1939 1940 // Load low part.1941 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai1942 : Hexagon::V6_vL32Ub_ai;1943 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)1944 .addFrameIndex(FI)1945 .addImm(0)1946 .cloneMemRefs(*MI);1947 1948 // Load high part.1949 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai1950 : Hexagon::V6_vL32Ub_ai;1951 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)1952 .addFrameIndex(FI)1953 .addImm(Size)1954 .cloneMemRefs(*MI);1955 1956 B.erase(It);1957 return true;1958}1959 1960bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,1961 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,1962 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {1963 MachineFunction &MF = *B.getParent();1964 auto &MFI = MF.getFrameInfo();1965 MachineInstr *MI = &*It;1966 if (!MI->getOperand(0).isFI())1967 return false;1968 1969 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();1970 DebugLoc DL = MI->getDebugLoc();1971 Register SrcR = MI->getOperand(2).getReg();1972 bool IsKill = MI->getOperand(2).isKill();1973 int FI = MI->getOperand(0).getIndex();1974 1975 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);1976 Align HasAlign = MFI.getObjectAlign(FI);1977 unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai1978 : Hexagon::V6_vS32Ub_ai;1979 BuildMI(B, It, DL, HII.get(StoreOpc))1980 .addFrameIndex(FI)1981 .addImm(0)1982 .addReg(SrcR, getKillRegState(IsKill))1983 .cloneMemRefs(*MI);1984 1985 B.erase(It);1986 return true;1987}1988 1989bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,1990 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,1991 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {1992 MachineFunction &MF = *B.getParent();1993 auto &MFI = MF.getFrameInfo();1994 MachineInstr *MI = &*It;1995 if (!MI->getOperand(1).isFI())1996 return false;1997 1998 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();1999 DebugLoc DL = MI->getDebugLoc();2000 Register DstR = MI->getOperand(0).getReg();2001 int FI = MI->getOperand(1).getIndex();2002 2003 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);2004 Align HasAlign = MFI.getObjectAlign(FI);2005 unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai2006 : Hexagon::V6_vL32Ub_ai;2007 BuildMI(B, It, DL, HII.get(LoadOpc), DstR)2008 .addFrameIndex(FI)2009 .addImm(0)2010 .cloneMemRefs(*MI);2011 2012 B.erase(It);2013 return true;2014}2015 2016bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,2017 SmallVectorImpl<Register> &NewRegs) const {2018 auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();2019 MachineRegisterInfo &MRI = MF.getRegInfo();2020 bool Changed = false;2021 2022 for (auto &B : MF) {2023 // Traverse the basic block.2024 MachineBasicBlock::iterator NextI;2025 for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {2026 MachineInstr *MI = &*I;2027 NextI = std::next(I);2028 unsigned Opc = MI->getOpcode();2029 2030 switch (Opc) {2031 case TargetOpcode::COPY:2032 Changed |= expandCopy(B, I, MRI, HII, NewRegs);2033 break;2034 case Hexagon::STriw_pred:2035 case Hexagon::STriw_ctr:2036 Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);2037 break;2038 case Hexagon::LDriw_pred:2039 case Hexagon::LDriw_ctr:2040 Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);2041 break;2042 case Hexagon::PS_vstorerq_ai:2043 Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);2044 break;2045 case Hexagon::PS_vloadrq_ai:2046 Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);2047 break;2048 case Hexagon::PS_vloadrw_ai:2049 Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);2050 break;2051 case Hexagon::PS_vstorerw_ai:2052 Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);2053 break;2054 }2055 }2056 }2057 2058 return Changed;2059}2060 2061void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,2062 BitVector &SavedRegs,2063 RegScavenger *RS) const {2064 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();2065 2066 SavedRegs.resize(HRI.getNumRegs());2067 2068 // If we have a function containing __builtin_eh_return we want to spill and2069 // restore all callee saved registers. Pretend that they are used.2070 if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())2071 for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)2072 SavedRegs.set(*R);2073 2074 // Replace predicate register pseudo spill code.2075 SmallVector<Register,8> NewRegs;2076 expandSpillMacros(MF, NewRegs);2077 if (OptimizeSpillSlots && !isOptNone(MF))2078 optimizeSpillSlots(MF, NewRegs);2079 2080 // We need to reserve a spill slot if scavenging could potentially require2081 // spilling a scavenged register.2082 if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {2083 MachineFrameInfo &MFI = MF.getFrameInfo();2084 MachineRegisterInfo &MRI = MF.getRegInfo();2085 SetVector<const TargetRegisterClass*> SpillRCs;2086 // Reserve an int register in any case, because it could be used to hold2087 // the stack offset in case it does not fit into a spill instruction.2088 SpillRCs.insert(&Hexagon::IntRegsRegClass);2089 2090 for (Register VR : NewRegs)2091 SpillRCs.insert(MRI.getRegClass(VR));2092 2093 for (const auto *RC : SpillRCs) {2094 if (!needToReserveScavengingSpillSlots(MF, HRI, RC))2095 continue;2096 unsigned Num = 1;2097 switch (RC->getID()) {2098 case Hexagon::IntRegsRegClassID:2099 Num = NumberScavengerSlots;2100 break;2101 case Hexagon::HvxQRRegClassID:2102 Num = 2; // Vector predicate spills also need a vector register.2103 break;2104 }2105 unsigned S = HRI.getSpillSize(*RC);2106 Align A = HRI.getSpillAlign(*RC);2107 for (unsigned i = 0; i < Num; i++) {2108 int NewFI = MFI.CreateSpillStackObject(S, A);2109 RS->addScavengingFrameIndex(NewFI);2110 }2111 }2112 }2113 2114 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);2115}2116 2117Register HexagonFrameLowering::findPhysReg(MachineFunction &MF,2118 HexagonBlockRanges::IndexRange &FIR,2119 HexagonBlockRanges::InstrIndexMap &IndexMap,2120 HexagonBlockRanges::RegToRangeMap &DeadMap,2121 const TargetRegisterClass *RC) const {2122 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();2123 auto &MRI = MF.getRegInfo();2124 2125 auto isDead = [&FIR,&DeadMap] (Register Reg) -> bool {2126 auto F = DeadMap.find({Reg,0});2127 if (F == DeadMap.end())2128 return false;2129 for (auto &DR : F->second)2130 if (DR.contains(FIR))2131 return true;2132 return false;2133 };2134 2135 for (Register Reg : RC->getRawAllocationOrder(MF)) {2136 bool Dead = true;2137 for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {2138 if (isDead(R.Reg))2139 continue;2140 Dead = false;2141 break;2142 }2143 if (Dead)2144 return Reg;2145 }2146 return 0;2147}2148 2149void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,2150 SmallVectorImpl<Register> &VRegs) const {2151 auto &HST = MF.getSubtarget<HexagonSubtarget>();2152 auto &HII = *HST.getInstrInfo();2153 auto &HRI = *HST.getRegisterInfo();2154 auto &MRI = MF.getRegInfo();2155 HexagonBlockRanges HBR(MF);2156 2157 using BlockIndexMap =2158 std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;2159 using BlockRangeMap =2160 std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;2161 using IndexType = HexagonBlockRanges::IndexType;2162 2163 struct SlotInfo {2164 BlockRangeMap Map;2165 unsigned Size = 0;2166 const TargetRegisterClass *RC = nullptr;2167 2168 SlotInfo() = default;2169 };2170 2171 BlockIndexMap BlockIndexes;2172 SmallSet<int,4> BadFIs;2173 std::map<int,SlotInfo> FIRangeMap;2174 2175 // Accumulate register classes: get a common class for a pre-existing2176 // class HaveRC and a new class NewRC. Return nullptr if a common class2177 // cannot be found, otherwise return the resulting class. If HaveRC is2178 // nullptr, assume that it is still unset.2179 auto getCommonRC =2180 [](const TargetRegisterClass *HaveRC,2181 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * {2182 if (HaveRC == nullptr || HaveRC == NewRC)2183 return NewRC;2184 // Different classes, both non-null. Pick the more general one.2185 if (HaveRC->hasSubClassEq(NewRC))2186 return HaveRC;2187 if (NewRC->hasSubClassEq(HaveRC))2188 return NewRC;2189 return nullptr;2190 };2191 2192 // Scan all blocks in the function. Check all occurrences of frame indexes,2193 // and collect relevant information.2194 for (auto &B : MF) {2195 std::map<int,IndexType> LastStore, LastLoad;2196 auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));2197 auto &IndexMap = P.first->second;2198 LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"2199 << IndexMap << '\n');2200 2201 for (auto &In : B) {2202 int LFI, SFI;2203 bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);2204 bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);2205 if (Load && Store) {2206 // If it's both a load and a store, then we won't handle it.2207 BadFIs.insert(LFI);2208 BadFIs.insert(SFI);2209 continue;2210 }2211 // Check for register classes of the register used as the source for2212 // the store, and the register used as the destination for the load.2213 // Also, only accept base+imm_offset addressing modes. Other addressing2214 // modes can have side-effects (post-increments, etc.). For stack2215 // slots they are very unlikely, so there is not much loss due to2216 // this restriction.2217 if (Load || Store) {2218 int TFI = Load ? LFI : SFI;2219 unsigned AM = HII.getAddrMode(In);2220 SlotInfo &SI = FIRangeMap[TFI];2221 bool Bad = (AM != HexagonII::BaseImmOffset);2222 if (!Bad) {2223 // If the addressing mode is ok, check the register class.2224 unsigned OpNum = Load ? 0 : 2;2225 auto *RC = HII.getRegClass(In.getDesc(), OpNum);2226 RC = getCommonRC(SI.RC, RC);2227 if (RC == nullptr)2228 Bad = true;2229 else2230 SI.RC = RC;2231 }2232 if (!Bad) {2233 // Check sizes.2234 unsigned S = HII.getMemAccessSize(In);2235 if (SI.Size != 0 && SI.Size != S)2236 Bad = true;2237 else2238 SI.Size = S;2239 }2240 if (!Bad) {2241 for (auto *Mo : In.memoperands()) {2242 if (!Mo->isVolatile() && !Mo->isAtomic())2243 continue;2244 Bad = true;2245 break;2246 }2247 }2248 if (Bad)2249 BadFIs.insert(TFI);2250 }2251 2252 // Locate uses of frame indices.2253 for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {2254 const MachineOperand &Op = In.getOperand(i);2255 if (!Op.isFI())2256 continue;2257 int FI = Op.getIndex();2258 // Make sure that the following operand is an immediate and that2259 // it is 0. This is the offset in the stack object.2260 if (i+1 >= n || !In.getOperand(i+1).isImm() ||2261 In.getOperand(i+1).getImm() != 0)2262 BadFIs.insert(FI);2263 if (BadFIs.count(FI))2264 continue;2265 2266 IndexType Index = IndexMap.getIndex(&In);2267 auto &LS = LastStore[FI];2268 auto &LL = LastLoad[FI];2269 if (Load) {2270 if (LS == IndexType::None)2271 LS = IndexType::Entry;2272 LL = Index;2273 } else if (Store) {2274 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];2275 if (LS != IndexType::None)2276 RL.add(LS, LL, false, false);2277 else if (LL != IndexType::None)2278 RL.add(IndexType::Entry, LL, false, false);2279 LL = IndexType::None;2280 LS = Index;2281 } else {2282 BadFIs.insert(FI);2283 }2284 }2285 }2286 2287 for (auto &I : LastLoad) {2288 IndexType LL = I.second;2289 if (LL == IndexType::None)2290 continue;2291 auto &RL = FIRangeMap[I.first].Map[&B];2292 IndexType &LS = LastStore[I.first];2293 if (LS != IndexType::None)2294 RL.add(LS, LL, false, false);2295 else2296 RL.add(IndexType::Entry, LL, false, false);2297 LS = IndexType::None;2298 }2299 for (auto &I : LastStore) {2300 IndexType LS = I.second;2301 if (LS == IndexType::None)2302 continue;2303 auto &RL = FIRangeMap[I.first].Map[&B];2304 RL.add(LS, IndexType::None, false, false);2305 }2306 }2307 2308 LLVM_DEBUG({2309 for (auto &P : FIRangeMap) {2310 dbgs() << "fi#" << P.first;2311 if (BadFIs.count(P.first))2312 dbgs() << " (bad)";2313 dbgs() << " RC: ";2314 if (P.second.RC != nullptr)2315 dbgs() << HRI.getRegClassName(P.second.RC) << '\n';2316 else2317 dbgs() << "<null>\n";2318 for (auto &R : P.second.Map)2319 dbgs() << " " << printMBBReference(*R.first) << " { " << R.second2320 << "}\n";2321 }2322 });2323 2324 // When a slot is loaded from in a block without being stored to in the2325 // same block, it is live-on-entry to this block. To avoid CFG analysis,2326 // consider this slot to be live-on-exit from all blocks.2327 SmallSet<int,4> LoxFIs;2328 2329 std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;2330 2331 for (auto &P : FIRangeMap) {2332 // P = pair(FI, map: BB->RangeList)2333 if (BadFIs.count(P.first))2334 continue;2335 for (auto &B : MF) {2336 auto F = P.second.Map.find(&B);2337 // F = pair(BB, RangeList)2338 if (F == P.second.Map.end() || F->second.empty())2339 continue;2340 HexagonBlockRanges::IndexRange &IR = F->second.front();2341 if (IR.start() == IndexType::Entry)2342 LoxFIs.insert(P.first);2343 BlockFIMap[&B].push_back(P.first);2344 }2345 }2346 2347 LLVM_DEBUG({2348 dbgs() << "Block-to-FI map (* -- live-on-exit):\n";2349 for (auto &P : BlockFIMap) {2350 auto &FIs = P.second;2351 if (FIs.empty())2352 continue;2353 dbgs() << " " << printMBBReference(*P.first) << ": {";2354 for (auto I : FIs) {2355 dbgs() << " fi#" << I;2356 if (LoxFIs.count(I))2357 dbgs() << '*';2358 }2359 dbgs() << " }\n";2360 }2361 });2362 2363#ifndef NDEBUG2364 bool HasOptLimit = SpillOptMax.getPosition();2365#endif2366 2367 // eliminate loads, when all loads eliminated, eliminate all stores.2368 for (auto &B : MF) {2369 auto F = BlockIndexes.find(&B);2370 assert(F != BlockIndexes.end());2371 HexagonBlockRanges::InstrIndexMap &IM = F->second;2372 HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);2373 HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);2374 LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n"2375 << HexagonBlockRanges::PrintRangeMap(DM, HRI));2376 2377 for (auto FI : BlockFIMap[&B]) {2378 if (BadFIs.count(FI))2379 continue;2380 LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n');2381 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];2382 for (auto &Range : RL) {2383 LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n');2384 if (!IndexType::isInstr(Range.start()) ||2385 !IndexType::isInstr(Range.end()))2386 continue;2387 MachineInstr &SI = *IM.getInstr(Range.start());2388 MachineInstr &EI = *IM.getInstr(Range.end());2389 assert(SI.mayStore() && "Unexpected start instruction");2390 assert(EI.mayLoad() && "Unexpected end instruction");2391 MachineOperand &SrcOp = SI.getOperand(2);2392 2393 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),2394 SrcOp.getSubReg() };2395 auto *RC = HII.getRegClass(SI.getDesc(), 2);2396 // The this-> is needed to unconfuse MSVC.2397 Register FoundR = this->findPhysReg(MF, Range, IM, DM, RC);2398 LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)2399 << '\n');2400 if (FoundR == 0)2401 continue;2402#ifndef NDEBUG2403 if (HasOptLimit) {2404 if (SpillOptCount >= SpillOptMax)2405 return;2406 SpillOptCount++;2407 }2408#endif2409 2410 // Generate the copy-in: "FoundR = COPY SrcR" at the store location.2411 MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;2412 MachineInstr *CopyIn = nullptr;2413 if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {2414 const DebugLoc &DL = SI.getDebugLoc();2415 CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)2416 .add(SrcOp);2417 }2418 2419 ++StartIt;2420 // Check if this is a last store and the FI is live-on-exit.2421 if (LoxFIs.count(FI) && (&Range == &RL.back())) {2422 // Update store's source register.2423 if (unsigned SR = SrcOp.getSubReg())2424 SrcOp.setReg(HRI.getSubReg(FoundR, SR));2425 else2426 SrcOp.setReg(FoundR);2427 SrcOp.setSubReg(0);2428 // We are keeping this register live.2429 SrcOp.setIsKill(false);2430 } else {2431 B.erase(&SI);2432 IM.replaceInstr(&SI, CopyIn);2433 }2434 2435 auto EndIt = std::next(EI.getIterator());2436 for (auto It = StartIt; It != EndIt; It = NextIt) {2437 MachineInstr &MI = *It;2438 NextIt = std::next(It);2439 int TFI;2440 if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)2441 continue;2442 Register DstR = MI.getOperand(0).getReg();2443 assert(MI.getOperand(0).getSubReg() == 0);2444 MachineInstr *CopyOut = nullptr;2445 if (DstR != FoundR) {2446 DebugLoc DL = MI.getDebugLoc();2447 unsigned MemSize = HII.getMemAccessSize(MI);2448 assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);2449 unsigned CopyOpc = TargetOpcode::COPY;2450 if (HII.isSignExtendingLoad(MI))2451 CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;2452 else if (HII.isZeroExtendingLoad(MI))2453 CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;2454 CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)2455 .addReg(FoundR, getKillRegState(&MI == &EI));2456 }2457 IM.replaceInstr(&MI, CopyOut);2458 B.erase(It);2459 }2460 2461 // Update the dead map.2462 HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };2463 for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))2464 DM[RR].subtract(Range);2465 } // for Range in range list2466 }2467 }2468}2469 2470void HexagonFrameLowering::expandAlloca(MachineInstr *AI,2471 const HexagonInstrInfo &HII, Register SP, unsigned CF) const {2472 MachineBasicBlock &MB = *AI->getParent();2473 DebugLoc DL = AI->getDebugLoc();2474 unsigned A = AI->getOperand(2).getImm();2475 2476 // Have2477 // Rd = alloca Rs, #A2478 //2479 // If Rs and Rd are different registers, use this sequence:2480 // Rd = sub(r29, Rs)2481 // r29 = sub(r29, Rs)2482 // Rd = and(Rd, #-A) ; if necessary2483 // r29 = and(r29, #-A) ; if necessary2484 // Rd = add(Rd, #CF) ; CF size aligned to at most A2485 // otherwise, do2486 // Rd = sub(r29, Rs)2487 // Rd = and(Rd, #-A) ; if necessary2488 // r29 = Rd2489 // Rd = add(Rd, #CF) ; CF size aligned to at most A2490 2491 MachineOperand &RdOp = AI->getOperand(0);2492 MachineOperand &RsOp = AI->getOperand(1);2493 Register Rd = RdOp.getReg(), Rs = RsOp.getReg();2494 2495 // Rd = sub(r29, Rs)2496 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)2497 .addReg(SP)2498 .addReg(Rs);2499 if (Rs != Rd) {2500 // r29 = sub(r29, Rs)2501 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)2502 .addReg(SP)2503 .addReg(Rs);2504 }2505 if (A > 8) {2506 // Rd = and(Rd, #-A)2507 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)2508 .addReg(Rd)2509 .addImm(-int64_t(A));2510 if (Rs != Rd)2511 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)2512 .addReg(SP)2513 .addImm(-int64_t(A));2514 }2515 if (Rs == Rd) {2516 // r29 = Rd2517 BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)2518 .addReg(Rd);2519 }2520 if (CF > 0) {2521 // Rd = add(Rd, #CF)2522 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)2523 .addReg(Rd)2524 .addImm(CF);2525 }2526}2527 2528bool HexagonFrameLowering::needsAligna(const MachineFunction &MF) const {2529 const MachineFrameInfo &MFI = MF.getFrameInfo();2530 if (!MFI.hasVarSizedObjects())2531 return false;2532 // Do not check for max stack object alignment here, because the stack2533 // may not be complete yet. Assume that we will need PS_aligna if there2534 // are variable-sized objects.2535 return true;2536}2537 2538const MachineInstr *HexagonFrameLowering::getAlignaInstr(2539 const MachineFunction &MF) const {2540 for (auto &B : MF)2541 for (auto &I : B)2542 if (I.getOpcode() == Hexagon::PS_aligna)2543 return &I;2544 return nullptr;2545}2546 2547/// Adds all callee-saved registers as implicit uses or defs to the2548/// instruction.2549void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,2550 const CSIVect &CSI, bool IsDef, bool IsKill) const {2551 // Add the callee-saved registers as implicit uses.2552 for (auto &R : CSI)2553 MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));2554}2555 2556/// Determine whether the callee-saved register saves and restores should2557/// be generated via inline code. If this function returns "true", inline2558/// code will be generated. If this function returns "false", additional2559/// checks are performed, which may still lead to the inline code.2560bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,2561 const CSIVect &CSI) const {2562 if (MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl())2563 return true;2564 if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())2565 return true;2566 if (!hasFP(MF))2567 return true;2568 if (!isOptSize(MF) && !isMinSize(MF))2569 if (MF.getTarget().getOptLevel() > CodeGenOptLevel::Default)2570 return true;2571 2572 // Check if CSI only has double registers, and if the registers form2573 // a contiguous block starting from D8.2574 BitVector Regs(Hexagon::NUM_TARGET_REGS);2575 for (const CalleeSavedInfo &I : CSI) {2576 MCRegister R = I.getReg();2577 if (!Hexagon::DoubleRegsRegClass.contains(R))2578 return true;2579 Regs[R] = true;2580 }2581 int F = Regs.find_first();2582 if (F != Hexagon::D8)2583 return true;2584 while (F >= 0) {2585 int N = Regs.find_next(F);2586 if (N >= 0 && N != F+1)2587 return true;2588 F = N;2589 }2590 2591 return false;2592}2593 2594bool HexagonFrameLowering::useSpillFunction(const MachineFunction &MF,2595 const CSIVect &CSI) const {2596 if (shouldInlineCSR(MF, CSI))2597 return false;2598 unsigned NumCSI = CSI.size();2599 if (NumCSI <= 1)2600 return false;2601 2602 unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs2603 : SpillFuncThreshold;2604 return Threshold < NumCSI;2605}2606 2607bool HexagonFrameLowering::useRestoreFunction(const MachineFunction &MF,2608 const CSIVect &CSI) const {2609 if (shouldInlineCSR(MF, CSI))2610 return false;2611 // The restore functions do a bit more than just restoring registers.2612 // The non-returning versions will go back directly to the caller's2613 // caller, others will clean up the stack frame in preparation for2614 // a tail call. Using them can still save code size even if only one2615 // register is getting restores. Make the decision based on -Oz:2616 // using -Os will use inline restore for a single register.2617 if (isMinSize(MF))2618 return true;2619 unsigned NumCSI = CSI.size();2620 if (NumCSI <= 1)2621 return false;2622 2623 unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-12624 : SpillFuncThreshold;2625 return Threshold < NumCSI;2626}2627 2628bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {2629 unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);2630 auto &HST = MF.getSubtarget<HexagonSubtarget>();2631 // A fairly simplistic guess as to whether a potential load/store to a2632 // stack location could require an extra register.2633 if (HST.useHVXOps() && StackSize > 256)2634 return true;2635 2636 // Check if the function has store-immediate instructions that access2637 // the stack. Since the offset field is not extendable, if the stack2638 // size exceeds the offset limit (6 bits, shifted), the stores will2639 // require a new base register.2640 bool HasImmStack = false;2641 unsigned MinLS = ~0u; // Log_2 of the memory access size.2642 2643 for (const MachineBasicBlock &B : MF) {2644 for (const MachineInstr &MI : B) {2645 unsigned LS = 0;2646 switch (MI.getOpcode()) {2647 case Hexagon::S4_storeirit_io:2648 case Hexagon::S4_storeirif_io:2649 case Hexagon::S4_storeiri_io:2650 ++LS;2651 [[fallthrough]];2652 case Hexagon::S4_storeirht_io:2653 case Hexagon::S4_storeirhf_io:2654 case Hexagon::S4_storeirh_io:2655 ++LS;2656 [[fallthrough]];2657 case Hexagon::S4_storeirbt_io:2658 case Hexagon::S4_storeirbf_io:2659 case Hexagon::S4_storeirb_io:2660 if (MI.getOperand(0).isFI())2661 HasImmStack = true;2662 MinLS = std::min(MinLS, LS);2663 break;2664 }2665 }2666 }2667 2668 if (HasImmStack)2669 return !isUInt<6>(StackSize >> MinLS);2670 2671 return false;2672}2673 2674namespace {2675// Struct used by orderFrameObjects to help sort the stack objects.2676struct HexagonFrameSortingObject {2677 bool IsValid = false;2678 unsigned Index = 0; // Index of Object into MFI list.2679 unsigned Size = 0;2680 Align ObjectAlignment = Align(1); // Alignment of Object in bytes.2681};2682 2683struct HexagonFrameSortingComparator {2684 inline bool operator()(const HexagonFrameSortingObject &A,2685 const HexagonFrameSortingObject &B) const {2686 return std::make_tuple(!A.IsValid, A.ObjectAlignment, A.Size) <2687 std::make_tuple(!B.IsValid, B.ObjectAlignment, B.Size);2688 }2689};2690} // namespace2691 2692// Sort objects on the stack by alignment value and then by size to minimize2693// padding.2694void HexagonFrameLowering::orderFrameObjects(2695 const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {2696 2697 if (ObjectsToAllocate.empty())2698 return;2699 2700 const MachineFrameInfo &MFI = MF.getFrameInfo();2701 int NObjects = ObjectsToAllocate.size();2702 2703 // Create an array of all MFI objects.2704 SmallVector<HexagonFrameSortingObject> SortingObjects(2705 MFI.getObjectIndexEnd());2706 2707 for (int i = 0, j = 0, e = MFI.getObjectIndexEnd(); i < e && j != NObjects;2708 ++i) {2709 if (i != ObjectsToAllocate[j])2710 continue;2711 j++;2712 2713 // A variable size object has size equal to 0. Since Hexagon sets2714 // getUseLocalStackAllocationBlock() to true, a local block is allocated2715 // earlier. This case is not handled here for now.2716 int Size = MFI.getObjectSize(i);2717 if (Size == 0)2718 return;2719 2720 SortingObjects[i].IsValid = true;2721 SortingObjects[i].Index = i;2722 SortingObjects[i].Size = Size;2723 SortingObjects[i].ObjectAlignment = MFI.getObjectAlign(i);2724 }2725 2726 // Sort objects by alignment and then by size.2727 llvm::stable_sort(SortingObjects, HexagonFrameSortingComparator());2728 2729 // Modify the original list to represent the final order.2730 int i = NObjects;2731 for (auto &Obj : SortingObjects) {2732 if (i == 0)2733 break;2734 ObjectsToAllocate[--i] = Obj.Index;2735 }2736}2737