171 lines · cpp
1//===-- HexagonHazardRecognizer.cpp - Hexagon Post RA Hazard Recognizer ---===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines the hazard recognizer for scheduling on Hexagon.10// Use a DFA based hazard recognizer.11//12//===----------------------------------------------------------------------===//13 14#include "HexagonHazardRecognizer.h"15#include "llvm/CodeGen/MachineFunction.h"16#include "llvm/CodeGen/MachineInstr.h"17#include "llvm/CodeGen/MachineOperand.h"18#include "llvm/CodeGen/ScheduleDAG.h"19#include "llvm/Support/Debug.h"20#include "llvm/Support/raw_ostream.h"21#include <cassert>22 23using namespace llvm;24 25#define DEBUG_TYPE "post-RA-sched"26 27void HexagonHazardRecognizer::Reset() {28 LLVM_DEBUG(dbgs() << "Reset hazard recognizer\n");29 Resources->clearResources();30 PacketNum = 0;31 UsesDotCur = nullptr;32 DotCurPNum = -1;33 UsesLoad = false;34 PrefVectorStoreNew = nullptr;35 RegDefs.clear();36}37 38ScheduleHazardRecognizer::HazardType39HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) {40 MachineInstr *MI = SU->getInstr();41 if (!MI || TII->isZeroCost(MI->getOpcode()))42 return NoHazard;43 44 if (!Resources->canReserveResources(*MI)) {45 LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);46 HazardType RetVal = Hazard;47 if (isNewStore(*MI)) {48 // The .new store version uses different resources so check if it49 // causes a hazard.50 MachineFunction *MF = MI->getParent()->getParent();51 MachineInstr *NewMI =52 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),53 MI->getDebugLoc());54 if (Resources->canReserveResources(*NewMI))55 RetVal = NoHazard;56 LLVM_DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard)57 << "\n");58 MF->deleteMachineInstr(NewMI);59 }60 return RetVal;61 }62 63 if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) {64 LLVM_DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", "65 << *MI);66 return Hazard;67 }68 69 return NoHazard;70}71 72void HexagonHazardRecognizer::AdvanceCycle() {73 LLVM_DEBUG(dbgs() << "Advance cycle, clear state\n");74 Resources->clearResources();75 if (DotCurPNum != -1 && DotCurPNum != (int)PacketNum) {76 UsesDotCur = nullptr;77 DotCurPNum = -1;78 }79 UsesLoad = false;80 PrefVectorStoreNew = nullptr;81 PacketNum++;82 RegDefs.clear();83}84 85/// Handle the cases when we prefer one instruction over another. Case 1 - we86/// prefer not to generate multiple loads in the packet to avoid a potential87/// bank conflict. Case 2 - if a packet contains a dot cur instruction, then we88/// prefer the instruction that can use the dot cur result. However, if the use89/// is not scheduled in the same packet, then prefer other instructions in the90/// subsequent packet. Case 3 - we prefer a vector store that can be converted91/// to a .new store. The packetizer will not generate the .new store if the92/// store doesn't have resources to fit in the packet (but the .new store may93/// have resources). We attempt to schedule the store as soon as possible to94/// help packetize the two instructions together.95bool HexagonHazardRecognizer::ShouldPreferAnother(SUnit *SU) {96 if (PrefVectorStoreNew != nullptr && PrefVectorStoreNew != SU)97 return true;98 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad())99 return true;100 return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (int)PacketNum));101}102 103/// Return true if the instruction would be converted to a new value store when104/// packetized.105bool HexagonHazardRecognizer::isNewStore(MachineInstr &MI) {106 if (!TII->mayBeNewStore(MI))107 return false;108 MachineOperand &MO = MI.getOperand(MI.getNumOperands() - 1);109 return MO.isReg() && RegDefs.contains(MO.getReg());110}111 112void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) {113 MachineInstr *MI = SU->getInstr();114 if (!MI)115 return;116 117 // Keep the set of definitions for each packet, which is used to determine118 // if a .new can be used.119 for (const MachineOperand &MO : MI->operands())120 if (MO.isReg() && MO.isDef() && !MO.isImplicit())121 RegDefs.insert(MO.getReg());122 123 if (TII->isZeroCost(MI->getOpcode()))124 return;125 126 if (!Resources->canReserveResources(*MI) || isNewStore(*MI)) {127 // It must be a .new store since other instructions must be able to be128 // reserved at this point.129 assert(TII->mayBeNewStore(*MI) && "Expecting .new store");130 MachineFunction *MF = MI->getParent()->getParent();131 MachineInstr *NewMI =132 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),133 MI->getDebugLoc());134 if (Resources->canReserveResources(*NewMI))135 Resources->reserveResources(*NewMI);136 else137 Resources->reserveResources(*MI);138 MF->deleteMachineInstr(NewMI);139 } else140 Resources->reserveResources(*MI);141 LLVM_DEBUG(dbgs() << " Add instruction " << *MI);142 143 // When scheduling a dot cur instruction, check if there is an instruction144 // that can use the dot cur in the same packet. If so, we'll attempt to145 // schedule it before other instructions. We only do this if the load has a146 // single zero-latency use.147 if (TII->mayBeCurLoad(*MI))148 for (auto &S : SU->Succs)149 if (S.isAssignedRegDep() && S.getLatency() == 0 &&150 S.getSUnit()->NumPredsLeft == 1) {151 UsesDotCur = S.getSUnit();152 DotCurPNum = PacketNum;153 break;154 }155 if (SU == UsesDotCur) {156 UsesDotCur = nullptr;157 DotCurPNum = -1;158 }159 160 UsesLoad = MI->mayLoad();161 162 if (TII->isHVXVec(*MI) && !MI->mayLoad() && !MI->mayStore())163 for (auto &S : SU->Succs)164 if (S.isAssignedRegDep() && S.getLatency() == 0 &&165 TII->mayBeNewStore(*S.getSUnit()->getInstr()) &&166 Resources->canReserveResources(*S.getSUnit()->getInstr())) {167 PrefVectorStoreNew = S.getSUnit();168 break;169 }170}171