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1//===--- HexagonOperands.td -----------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9def f32ImmOperand : AsmOperandClass { let Name = "f32Imm"; }10def f32Imm : Operand<f32> { let ParserMatchClass = f32ImmOperand; }11def f64ImmOperand : AsmOperandClass { let Name = "f64Imm"; }12def f64Imm : Operand<f64> { let ParserMatchClass = f64ImmOperand; }13def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ return isInt<8>(N->getSExtValue()); }]>;14def s9_0ImmOperand : AsmOperandClass { let Name = "s9_0Imm"; }15def s9_0Imm : Operand<i32> { let ParserMatchClass = s9_0ImmOperand; }16def s27_2ImmOperand : AsmOperandClass { let Name = "s27_2Imm"; let RenderMethod = "addSignedImmOperands"; }17def s27_2Imm : Operand<i32> { let ParserMatchClass = s27_2ImmOperand; }18def r32_0ImmPred : PatLeaf<(i32 imm), [{19 int64_t v = (int64_t)N->getSExtValue();20 return isInt<32>(v);21}]>;22def u9_0ImmPred : PatLeaf<(i32 imm), [{23 int64_t v = (int64_t)N->getSExtValue();24 return isUInt<9>(v);25}]>;26 27def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; let RenderMethod = "addImmOperands"; }28def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; }29def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; }30def n1Const : Operand<i32> {31 let ParserMatchClass = n1ConstOperand;32 let DecoderMethod = "n1ConstDecoder";33}34def sgp10ConstOperand : AsmOperandClass { let Name = "sgp10Const"; }35def sgp10Const : Operand<i32> {36 let ParserMatchClass = sgp10ConstOperand;37 let DecoderMethod = "sgp10ConstDecoder";38}39 40def bblabel : Operand<i32>;41def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">;42