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1//===- HexagonPatternsHVX.td - Selection Patterns for HVX --*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9def HQ8: PatLeaf<(VecQ8 HvxQR:$R)>;10def HQ16: PatLeaf<(VecQ16 HvxQR:$R)>;11def HQ32: PatLeaf<(VecQ32 HvxQR:$R)>;12 13def HVI8: PatLeaf<(VecI8 HvxVR:$R)>;14def HVI16: PatLeaf<(VecI16 HvxVR:$R)>;15def HVI32: PatLeaf<(VecI32 HvxVR:$R)>;16def HVF16: PatLeaf<(VecF16 HvxVR:$R)>;17def HVF32: PatLeaf<(VecF32 HvxVR:$R)>;18def HVBF16: PatLeaf<(VecBF16 HvxVR:$R)>;19 20def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>;21def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>;22def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>;23def HWF16: PatLeaf<(VecPF16 HvxWR:$R)>;24def HWF32: PatLeaf<(VecPF32 HvxWR:$R)>;25def HWBF16: PatLeaf<(VecBF16 HvxWR:$R)>;26 27def SDTVecUnaryOp:28 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;29 30def SDTVecBinOp:31 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>]>;32 33def SDTHexagonVEXTRACTW: SDTypeProfile<1, 2,34 [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisVT<2, i32>]>;35def HexagonVEXTRACTW : SDNode<"HexagonISD::VEXTRACTW", SDTHexagonVEXTRACTW>;36 37def SDTHexagonVINSERTW0: SDTypeProfile<1, 2,38 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;39def HexagonVINSERTW0: SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;40 41def HwLen2: SDNodeXForm<imm, [{42 const auto &ST = CurDAG->getSubtarget<HexagonSubtarget>();43 return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32);44}]>;45 46def Q2V: OutPatFrag<(ops node:$Qs), (V6_vandqrt $Qs, (ToI32 -1))>;47 48def Combinev: OutPatFrag<(ops node:$Vs, node:$Vt),49 (REG_SEQUENCE HvxWR, $Vs, vsub_hi, $Vt, vsub_lo)>;50 51def Combineq: OutPatFrag<(ops node:$Qs, node:$Qt),52 (V6_vandvrt53 (V6_vor54 (V6_vror (V6_vpackeb (V6_vd0), (Q2V $Qs)),55 (ToI32 (HwLen2 (i32 0)))), // Half the vector length56 (V6_vpackeb (V6_vd0), (Q2V $Qt))),57 (ToI32 -1))>;58 59def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;60def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;61 62def HexagonQCAT: SDNode<"HexagonISD::QCAT", SDTVecBinOp>;63def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>;64def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>;65 66def vzero: PatFrags<(ops), [(splat_vector (i32 0)), (splat_vector (f32zero))]>;67def qtrue: PatFrag<(ops), (HexagonQTRUE)>;68def qfalse: PatFrag<(ops), (HexagonQFALSE)>;69def qcat: PatFrag<(ops node:$Qs, node:$Qt),70 (HexagonQCAT node:$Qs, node:$Qt)>;71 72def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>;73 74def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>;75def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>;76def VZxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackub $Vs)>;77def VZxth: OutPatFrag<(ops node:$Vs), (V6_vunpackuh $Vs)>;78 79class VSubi<InstHexagon VSub, InstHexagon VSplati>:80 OutPatFrag<(ops node:$Imm, node:$Vs), (VSub (VSplati (i32 $Imm)), $Vs)>;81 82def VSubib: VSubi<V6_vsubb, PS_vsplatib>;83def VSubih: VSubi<V6_vsubh, PS_vsplatih>;84def VSubiw: VSubi<V6_vsubw, PS_vsplatiw>;85 86def VNegb: OutPatFrag<(ops node:$Vs), (VSubib 0, $Vs)>;87def VNegh: OutPatFrag<(ops node:$Vs), (VSubih 0, $Vs)>;88def VNegw: OutPatFrag<(ops node:$Vs), (VSubiw 0, $Vs)>;89 90class pf3<SDNode Op>: PatFrag<(ops node:$a, node:$b, node:$c),91 (Op node:$a, node:$b, node:$c)>;92 93def Mfshl: pf3<HexagonMFSHL>;94def Mfshr: pf3<HexagonMFSHR>;95 96def IsVecOff : PatLeaf<(i32 imm), [{97 int32_t V = N->getSExtValue();98 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);99 assert(isPowerOf2_32(VecSize));100 if ((uint32_t(V) & (uint32_t(VecSize)-1)) != 0)101 return false;102 int32_t L = Log2_32(VecSize);103 return isInt<4>(V >> L);104}]>;105 106 107def alignedload: PatFrag<(ops node:$a), (load $a), [{108 return isAlignedMemNode(cast<MemSDNode>(N));109}]>;110 111def unalignedload: PatFrag<(ops node:$a), (load $a), [{112 return !isAlignedMemNode(cast<MemSDNode>(N));113}]>;114 115def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{116 return isAlignedMemNode(cast<MemSDNode>(N));117}]>;118 119def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{120 return !isAlignedMemNode(cast<MemSDNode>(N));121}]>;122 123 124// HVX loads125 126multiclass HvxLdfi_pat<InstHexagon MI, PatFrag Load, ValueType ResType,127 PatFrag ImmPred> {128 def: Pat<(ResType (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),129 (MI AddrFI:$fi, imm:$Off)>;130 def: Pat<(ResType (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))),131 (MI AddrFI:$fi, imm:$Off)>;132 def: Pat<(ResType (Load AddrFI:$fi)), (ResType (MI AddrFI:$fi, 0))>;133}134 135multiclass HvxLdgi_pat<InstHexagon MI, PatFrag Load, ValueType ResType,136 PatFrag ImmPred> {137 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$Off))),138 (MI I32:$Rt, imm:$Off)>;139 def: Pat<(ResType (Load I32:$Rt)),140 (MI I32:$Rt, 0)>;141}142 143multiclass HvxLdc_pat<InstHexagon MI, PatFrag Load, ValueType ResType> {144 // The HVX selection code for shuffles can generate vector constants.145 // Calling "Select" on the resulting loads from CP fails without these146 // patterns.147 def: Pat<(ResType (Load (HexagonCP tconstpool:$Addr))),148 (MI (ToI32 imm:$Addr), 0)>;149 def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$Addr))),150 (MI (C4_addipc imm:$Addr), 0)>;151}152 153multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType ResType,154 PatFrag ImmPred> {155 defm: HvxLdfi_pat<MI, Load, ResType, ImmPred>;156 defm: HvxLdgi_pat<MI, Load, ResType, ImmPred>;157 defm: HvxLdc_pat <MI, Load, ResType>;158}159 160// Aligned loads: everything, plus loads with valignaddr node.161multiclass HvxLda_pat<InstHexagon MI, PatFrag Load, ValueType ResType,162 PatFrag ImmPred> {163 let AddedComplexity = 50 in {164 def: Pat<(ResType (Load (valignaddr I32:$Rt))),165 (MI I32:$Rt, 0)>;166 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),167 (MI I32:$Rt, imm:$Off)>;168 }169 defm: HvxLd_pat<MI, Load, ResType, ImmPred>;170}171 172let Predicates = [UseHVX] in {173 // alignedload will match a non-temporal load as well, so try non-temporal174 // first.175 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI8, IsVecOff>;176 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI16, IsVecOff>;177 defm: HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecI32, IsVecOff>;178 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI8, IsVecOff>;179 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI16, IsVecOff>;180 defm: HvxLda_pat<V6_vL32b_ai, alignedload, VecI32, IsVecOff>;181 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI8, IsVecOff>;182 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI16, IsVecOff>;183 defm: HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecI32, IsVecOff>;184}185 186let Predicates = [UseHVXV68] in {187 defm : HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecBF16, IsVecOff>;188 defm : HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecF16, IsVecOff>;189 defm : HvxLda_pat<V6_vL32b_nt_ai, alignednontemporalload, VecF32, IsVecOff>;190 defm : HvxLda_pat<V6_vL32b_ai, alignedload, VecBF16, IsVecOff>;191 defm : HvxLda_pat<V6_vL32b_ai, alignedload, VecF16, IsVecOff>;192 defm : HvxLda_pat<V6_vL32b_ai, alignedload, VecF32, IsVecOff>;193 defm : HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecBF16, IsVecOff>;194 defm : HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecF16, IsVecOff>;195 defm : HvxLd_pat<V6_vL32Ub_ai, unalignedload, VecF32, IsVecOff>;196}197 198// HVX stores199 200multiclass HvxStfi_pat<InstHexagon MI, PatFrag Store, PatFrag Value,201 PatFrag ImmPred> {202 def: Pat<(Store Value:$Vs, (add (i32 AddrFI:$fi), ImmPred:$Off)),203 (MI AddrFI:$fi, imm:$Off, Value:$Vs)>;204 def: Pat<(Store Value:$Vs, (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off)),205 (MI AddrFI:$fi, imm:$Off, Value:$Vs)>;206 def: Pat<(Store Value:$Vs, AddrFI:$fi),207 (MI AddrFI:$fi, 0, Value:$Vs)>;208}209 210multiclass HvxStgi_pat<InstHexagon MI, PatFrag Store, PatFrag Value,211 PatFrag ImmPred> {212 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$Off)),213 (MI I32:$Rt, imm:$Off, Value:$Vs)>;214 def: Pat<(Store Value:$Vs, (IsOrAdd I32:$Rt, ImmPred:$Off)),215 (MI I32:$Rt, imm:$Off, Value:$Vs)>;216 def: Pat<(Store Value:$Vs, I32:$Rt),217 (MI I32:$Rt, 0, Value:$Vs)>;218}219 220multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag Value,221 PatFrag ImmPred> {222 defm: HvxStfi_pat<MI, Store, Value, ImmPred>;223 defm: HvxStgi_pat<MI, Store, Value, ImmPred>;224}225 226let Predicates = [UseHVX] in {227 // alignedstore will match a non-temporal store as well, so try non-temporal228 // first.229 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVI8, IsVecOff>;230 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVI16, IsVecOff>;231 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVI32, IsVecOff>;232 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVI8, IsVecOff>;233 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVI16, IsVecOff>;234 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVI32, IsVecOff>;235 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVI8, IsVecOff>;236 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVI16, IsVecOff>;237 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVI32, IsVecOff>;238}239 240let Predicates = [UseHVXV68] in {241 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVBF16, IsVecOff>;242 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVF16, IsVecOff>;243 defm: HvxSt_pat<V6_vS32b_nt_ai, alignednontemporalstore, HVF32, IsVecOff>;244 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVBF16, IsVecOff>;245 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVF16, IsVecOff>;246 defm: HvxSt_pat<V6_vS32b_ai, alignedstore, HVF32, IsVecOff>;247 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVBF16, IsVecOff>;248 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVF16, IsVecOff>;249 defm: HvxSt_pat<V6_vS32Ub_ai, unalignedstore, HVF32, IsVecOff>;250}251 252// Bitcasts between same-size vector types are no-ops, except for the253// actual type change.254let Predicates = [UseHVX] in {255 defm: NopCast_pat<VecI8, VecI16, HvxVR>;256 defm: NopCast_pat<VecI8, VecI32, HvxVR>;257 defm: NopCast_pat<VecI16, VecI32, HvxVR>;258 259 defm: NopCast_pat<VecPI8, VecPI16, HvxWR>;260 defm: NopCast_pat<VecPI8, VecPI32, HvxWR>;261 defm: NopCast_pat<VecPI16, VecPI32, HvxWR>;262}263 264let Predicates = [UseHVX, UseHVXFloatingPoint] in {265 defm: NopCast_pat<VecI8, VecF16, HvxVR>;266 defm: NopCast_pat<VecI8, VecBF16, HvxVR>;267 defm: NopCast_pat<VecI8, VecF32, HvxVR>;268 defm: NopCast_pat<VecI16, VecF16, HvxVR>;269 defm: NopCast_pat<VecI16, VecBF16, HvxVR>;270 defm: NopCast_pat<VecI16, VecF32, HvxVR>;271 defm: NopCast_pat<VecI32, VecF16, HvxVR>;272 defm: NopCast_pat<VecI32, VecBF16, HvxVR>;273 defm: NopCast_pat<VecI32, VecF32, HvxVR>;274 defm: NopCast_pat<VecF16, VecF32, HvxVR>;275 276 defm: NopCast_pat<VecPI8, VecPF16, HvxWR>;277 defm: NopCast_pat<VecPI8, VecPBF16, HvxWR>;278 defm: NopCast_pat<VecPI8, VecPF32, HvxWR>;279 defm: NopCast_pat<VecPI16, VecPF16, HvxWR>;280 defm: NopCast_pat<VecPI16, VecPBF16, HvxWR>;281 defm: NopCast_pat<VecPI16, VecPF32, HvxWR>;282 defm: NopCast_pat<VecPI32, VecPF16, HvxWR>;283 defm: NopCast_pat<VecPI32, VecPBF16, HvxWR>;284 defm: NopCast_pat<VecPI32, VecPF32, HvxWR>;285 defm: NopCast_pat<VecPF16, VecPF32, HvxWR>;286}287 288let Predicates = [UseHVX] in {289 let AddedComplexity = 100 in {290 // These should be preferred over a vsplat of 0.291 def: Pat<(VecI8 vzero), (V6_vd0)>;292 def: Pat<(VecI16 vzero), (V6_vd0)>;293 def: Pat<(VecI32 vzero), (V6_vd0)>;294 def: Pat<(VecPI8 vzero), (PS_vdd0)>;295 def: Pat<(VecPI16 vzero), (PS_vdd0)>;296 def: Pat<(VecPI32 vzero), (PS_vdd0)>;297 def: Pat<(VecPF32 vzero), (PS_vdd0)>;298 299 def: Pat<(concat_vectors (VecI8 vzero), (VecI8 vzero)), (PS_vdd0)>;300 def: Pat<(concat_vectors (VecI16 vzero), (VecI16 vzero)), (PS_vdd0)>;301 def: Pat<(concat_vectors (VecI32 vzero), (VecI32 vzero)), (PS_vdd0)>;302 }303 304 def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),305 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;306 def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),307 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;308 def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)),309 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;310 311 def: Pat<(VecQ8 (qcat HQ16:$Qs, HQ16:$Qt)), (Combineq $Qt, $Qs)>;312 def: Pat<(VecQ16 (qcat HQ32:$Qs, HQ32:$Qt)), (Combineq $Qt, $Qs)>;313 314 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),315 (V6_extractw HvxVR:$Vu, I32:$Rs)>;316 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),317 (V6_extractw HvxVR:$Vu, I32:$Rs)>;318 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),319 (V6_extractw HvxVR:$Vu, I32:$Rs)>;320 321 def: Pat<(HexagonVINSERTW0 HVI8:$Vu, I32:$Rt),322 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;323 def: Pat<(HexagonVINSERTW0 HVI16:$Vu, I32:$Rt),324 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;325 def: Pat<(HexagonVINSERTW0 HVI32:$Vu, I32:$Rt),326 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;327}328 329let Predicates = [UseHVX, UseHVXFloatingPoint] in {330 let AddedComplexity = 100 in {331 def: Pat<(VecF16 vzero), (V6_vd0)>;332 def: Pat<(VecBF16 vzero), (V6_vd0)>;333 def: Pat<(VecF32 vzero), (V6_vd0)>;334 def: Pat<(VecPF16 vzero), (PS_vdd0)>;335 def: Pat<(VecPBF16 vzero), (PS_vdd0)>;336 def: Pat<(VecPF32 vzero), (PS_vdd0)>;337 338 def: Pat<(concat_vectors (VecF16 vzero), (VecF16 vzero)), (PS_vdd0)>;339 def : Pat<(concat_vectors (VecBF16 vzero), (VecBF16 vzero)), (PS_vdd0)>;340 def: Pat<(concat_vectors (VecF32 vzero), (VecF32 vzero)), (PS_vdd0)>;341 }342 343 def: Pat<(VecPF16 (concat_vectors HVF16:$Vs, HVF16:$Vt)),344 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;345 def: Pat<(VecPF32 (concat_vectors HVF32:$Vs, HVF32:$Vt)),346 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;347 348 def: Pat<(HexagonVINSERTW0 HVF16:$Vu, I32:$Rt),349 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;350 def: Pat<(HexagonVINSERTW0 HVF32:$Vu, I32:$Rt),351 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;352}353 354def Rep: OutPatFrag<(ops node:$N), (Combinev $N, $N)>;355 356let Predicates = [UseHVX] in {357 let AddedComplexity = 10 in {358 def: Pat<(VecI8 (splat_vector u8_0ImmPred:$V)), (PS_vsplatib imm:$V)>;359 def: Pat<(VecI16 (splat_vector u16_0ImmPred:$V)), (PS_vsplatih imm:$V)>;360 def: Pat<(VecI32 (splat_vector anyimm:$V)), (PS_vsplatiw imm:$V)>;361 def: Pat<(VecPI8 (splat_vector u8_0ImmPred:$V)), (Rep (PS_vsplatib imm:$V))>;362 def: Pat<(VecPI16 (splat_vector u16_0ImmPred:$V)), (Rep (PS_vsplatih imm:$V))>;363 def: Pat<(VecPI32 (splat_vector anyimm:$V)), (Rep (PS_vsplatiw imm:$V))>;364 }365 def: Pat<(VecI8 (splat_vector I32:$Rs)), (PS_vsplatrb $Rs)>;366 def: Pat<(VecI16 (splat_vector I32:$Rs)), (PS_vsplatrh $Rs)>;367 def: Pat<(VecI32 (splat_vector I32:$Rs)), (PS_vsplatrw $Rs)>;368 def: Pat<(VecPI8 (splat_vector I32:$Rs)), (Rep (PS_vsplatrb $Rs))>;369 def: Pat<(VecPI16 (splat_vector I32:$Rs)), (Rep (PS_vsplatrh $Rs))>;370 def: Pat<(VecPI32 (splat_vector I32:$Rs)), (Rep (PS_vsplatrw $Rs))>;371}372let Predicates = [UseHVXV68, UseHVXFloatingPoint] in {373 let AddedComplexity = 30 in {374 def: Pat<(VecF16 (splat_vector u16_0ImmPred:$V)), (PS_vsplatih imm:$V)>;375 def: Pat<(VecBF16 (splat_vector u16_0ImmPred:$V)), (PS_vsplatih imm:$V)>;376 def: Pat<(VecF32 (splat_vector anyint:$V)), (PS_vsplatiw imm:$V)>;377 def: Pat<(VecF32 (splat_vector f32ImmPred:$V)), (PS_vsplatiw (ftoi $V))>;378 }379 let AddedComplexity = 20 in {380 def: Pat<(VecF16 (splat_vector I32:$Rs)), (PS_vsplatrh $Rs)>;381 def: Pat<(VecBF16 (splat_vector I32:$Rs)), (PS_vsplatrh $Rs)>;382 def: Pat<(VecF32 (splat_vector I32:$Rs)), (PS_vsplatrw $Rs)>;383 def: Pat<(VecF32 (splat_vector F32:$Rs)), (PS_vsplatrw $Rs)>;384 }385}386 387class Vneg1<ValueType VecTy>388 : PatFrag<(ops), (VecTy (splat_vector (i32 -1)))>;389 390class Vnot<ValueType VecTy>391 : PatFrag<(ops node:$Vs), (xor $Vs, Vneg1<VecTy>)>;392 393let Predicates = [UseHVX] in {394 let AddedComplexity = 200 in {395 def: Pat<(Vnot<VecI8> HVI8:$Vs), (V6_vnot HvxVR:$Vs)>;396 def: Pat<(Vnot<VecI16> HVI16:$Vs), (V6_vnot HvxVR:$Vs)>;397 def: Pat<(Vnot<VecI32> HVI32:$Vs), (V6_vnot HvxVR:$Vs)>;398 }399 400 def: OpR_RR_pat<V6_vaddb, Add, VecI8, HVI8>;401 def: OpR_RR_pat<V6_vaddh, Add, VecI16, HVI16>;402 def: OpR_RR_pat<V6_vaddw, Add, VecI32, HVI32>;403 def: OpR_RR_pat<V6_vaddb_dv, Add, VecPI8, HWI8>;404 def: OpR_RR_pat<V6_vaddh_dv, Add, VecPI16, HWI16>;405 def: OpR_RR_pat<V6_vaddw_dv, Add, VecPI32, HWI32>;406 def: OpR_RR_pat<V6_vsubb, Sub, VecI8, HVI8>;407 def: OpR_RR_pat<V6_vsubh, Sub, VecI16, HVI16>;408 def: OpR_RR_pat<V6_vsubw, Sub, VecI32, HVI32>;409 def: OpR_RR_pat<V6_vsubb_dv, Sub, VecPI8, HWI8>;410 def: OpR_RR_pat<V6_vsubh_dv, Sub, VecPI16, HWI16>;411 def: OpR_RR_pat<V6_vsubw_dv, Sub, VecPI32, HWI32>;412 def: OpR_RR_pat<V6_vand, And, VecI8, HVI8>;413 def: OpR_RR_pat<V6_vand, And, VecI16, HVI16>;414 def: OpR_RR_pat<V6_vand, And, VecI32, HVI32>;415 def: OpR_RR_pat<V6_vor, Or, VecI8, HVI8>;416 def: OpR_RR_pat<V6_vor, Or, VecI16, HVI16>;417 def: OpR_RR_pat<V6_vor, Or, VecI32, HVI32>;418 def: OpR_RR_pat<V6_vxor, Xor, VecI8, HVI8>;419 def: OpR_RR_pat<V6_vxor, Xor, VecI16, HVI16>;420 def: OpR_RR_pat<V6_vxor, Xor, VecI32, HVI32>;421 422 def: OpR_RR_pat<V6_vminb, Smin, VecI8, HVI8>;423 def: OpR_RR_pat<V6_vmaxb, Smax, VecI8, HVI8>;424 def: OpR_RR_pat<V6_vminub, Umin, VecI8, HVI8>;425 def: OpR_RR_pat<V6_vmaxub, Umax, VecI8, HVI8>;426 def: OpR_RR_pat<V6_vminh, Smin, VecI16, HVI16>;427 def: OpR_RR_pat<V6_vmaxh, Smax, VecI16, HVI16>;428 def: OpR_RR_pat<V6_vminuh, Umin, VecI16, HVI16>;429 def: OpR_RR_pat<V6_vmaxuh, Umax, VecI16, HVI16>;430 def: OpR_RR_pat<V6_vminw, Smin, VecI32, HVI32>;431 def: OpR_RR_pat<V6_vmaxw, Smax, VecI32, HVI32>;432 433 def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),434 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;435 def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),436 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;437 def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),438 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;439 440 def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt),441 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;442 def: Pat<(vselect (qnot HQ16:$Qu), HVI16:$Vs, HVI16:$Vt),443 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;444 def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt),445 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;446}447 448let Predicates = [UseHVX] in {449 def: OpR_RR_pat_sat<V6_vaddubsat, uaddsat, VecI8, HVI8>;450 def: OpR_RR_pat_sat<V6_vadduhsat, uaddsat, VecI16, HVI16>;451 def: OpR_RR_pat_sat<V6_vadduwsat, uaddsat, VecI32, HVI32>;452 def: OpR_RR_pat_sat<V6_vaddbsat, saddsat, VecI8, HVI8>;453 def: OpR_RR_pat_sat<V6_vaddhsat, saddsat, VecI16, HVI16>;454 def: OpR_RR_pat_sat<V6_vaddwsat, saddsat, VecI32, HVI32>;455 def: OpR_RR_pat_sat<V6_vaddubsat_dv, uaddsat, VecPI8, HWI8>;456 def: OpR_RR_pat_sat<V6_vadduhsat_dv, uaddsat, VecPI16, HWI16>;457 def: OpR_RR_pat_sat<V6_vadduwsat_dv, uaddsat, VecPI32, HWI32>;458 def: OpR_RR_pat_sat<V6_vaddbsat_dv, saddsat, VecPI8, HWI8>;459 def: OpR_RR_pat_sat<V6_vaddhsat_dv, saddsat, VecPI16, HWI16>;460 def: OpR_RR_pat_sat<V6_vaddwsat_dv, saddsat, VecPI32, HWI32>;461}462 463let Predicates = [UseHVX] in {464 def: OpR_RR_pat_sat<V6_vsububsat, usubsat, VecI8, HVI8>;465 def: OpR_RR_pat_sat<V6_vsubuhsat, usubsat, VecI16, HVI16>;466 def: OpR_RR_pat_sat<V6_vsubuwsat, usubsat, VecI32, HVI32>;467 def: OpR_RR_pat_sat<V6_vsubbsat, ssubsat, VecI8, HVI8>;468 def: OpR_RR_pat_sat<V6_vsubhsat, ssubsat, VecI16, HVI16>;469 def: OpR_RR_pat_sat<V6_vsubwsat, ssubsat, VecI32, HVI32>;470 def: OpR_RR_pat_sat<V6_vsububsat_dv, usubsat, VecPI8, HWI8>;471 def: OpR_RR_pat_sat<V6_vsubuhsat_dv, usubsat, VecPI16, HWI16>;472 def: OpR_RR_pat_sat<V6_vsubuwsat_dv, usubsat, VecPI32, HWI32>;473 def: OpR_RR_pat_sat<V6_vsubbsat_dv, ssubsat, VecPI8, HWI8>;474 def: OpR_RR_pat_sat<V6_vsubhsat_dv, ssubsat, VecPI16, HWI16>;475 def: OpR_RR_pat_sat<V6_vsubwsat_dv, ssubsat, VecPI32, HWI32>;476}477 478// For now, we always deal with vector floating point in SF mode.479class OpR_RR_pat_conv<InstHexagon MI, PatFrag Op, ValueType ResType,480 PatFrag RsPred, PatFrag RtPred = RsPred>481 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),482 (V6_vconv_sf_qf32 (VecF32 (MI RsPred:$Rs, RtPred:$Rt)))>;483 484class OpR_RR_pat_conv_hf<InstHexagon MI, PatFrag Op, ValueType ResType,485 PatFrag RsPred, PatFrag RtPred = RsPred>486 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),487 (V6_vconv_hf_qf16 (VecF16 (MI RsPred:$Rs, RtPred:$Rt)))>;488 489let Predicates = [UseHVXV68, UseHVXQFloat] in {490 def: OpR_RR_pat_conv_hf<V6_vsub_hf, pf2<fsub>, VecF16, HVF16>;491 def: OpR_RR_pat_conv_hf<V6_vadd_hf, pf2<fadd>, VecF16, HVF16>;492 def: OpR_RR_pat_conv_hf<V6_vmpy_qf16_hf, pf2<fmul>, VecF16, HVF16>;493 def: OpR_RR_pat_conv<V6_vsub_sf, pf2<fsub>, VecF32, HVF32>;494 def: OpR_RR_pat_conv<V6_vadd_sf, pf2<fadd>, VecF32, HVF32>;495 def: OpR_RR_pat_conv<V6_vmpy_qf32_sf, pf2<fmul>, VecF32, HVF32>;496 497 // For now we assume that the fp32 register is always coming in as IEEE float498 // since the qfloat arithmetic instructions above always generate the499 // accompanying conversions as part of their pattern500 def: Pat<(VecF16 (pf1<fpround> HWF32:$Vuu)),501 (V6_vdealh (V6_vconv_hf_qf32502 (VecPF32 (Combinev (V6_vadd_sf (HiVec HvxWR:$Vuu), (V6_vd0)),503 (V6_vadd_sf (LoVec HvxWR:$Vuu), (V6_vd0))504 ))))>;505 // fpextend for QFloat is handled manually in HexagonISelLoweringHVX.cpp.506}507 508// HVX IEEE arithmetic Instructions509let Predicates = [UseHVXV68, UseHVXIEEEFP] in {510 def: Pat<(fadd HVF16:$Rs, HVF16:$Rt),511 (V6_vadd_hf_hf HVF16:$Rs, HVF16:$Rt)>;512 def: Pat<(fadd HVF32:$Rs, HVF32:$Rt),513 (V6_vadd_sf_sf HVF32:$Rs, HVF32:$Rt)>;514 def: Pat<(fsub HVF16:$Rs, HVF16:$Rt),515 (V6_vsub_hf_hf HVF16:$Rs, HVF16:$Rt)>;516 def: Pat<(fsub HVF32:$Rs, HVF32:$Rt),517 (V6_vsub_sf_sf HVF32:$Rs, HVF32:$Rt)>;518 def: Pat<(fmul HVF16:$Rs, HVF16:$Rt),519 (V6_vmpy_hf_hf HVF16:$Rs, HVF16:$Rt)>;520 def: Pat<(fmul HVF32:$Rs, HVF32:$Rt),521 (V6_vmpy_sf_sf HVF32:$Rs, HVF32:$Rt)>;522 523 def: Pat<(VecF16 (pf1<fpround> HWF32:$Vuu)),524 (V6_vdealh (V6_vcvt_hf_sf (HiVec HvxWR:$Vuu), (LoVec HvxWR:$Vuu)))>;525 def: Pat<(VecPF32 (pf1<fpextend> HVF16:$Vu)),526 (V6_vcvt_sf_hf (V6_vshuffh HvxVR:$Vu))>;527 528 def: OpR_R_pat<V6_vcvt_h_hf, Fptosi, VecI16, HVF16>;529 def: OpR_R_pat<V6_vcvt_uh_hf, Fptoui, VecI16, HVF16>;530 def: OpR_R_pat<V6_vcvt_hf_h, Sitofp, VecF16, HVI16>;531 def: OpR_R_pat<V6_vcvt_hf_uh, Uitofp, VecF16, HVI16>;532 533 def: Pat<(VecI8 (Fptosi HWF16:$Vu)),534 (V6_vcvt_b_hf (HiVec $Vu), (LoVec $Vu))>;535 def: Pat<(VecI8 (Fptoui HWF16:$Vu)),536 (V6_vcvt_ub_hf (HiVec $Vu), (LoVec $Vu))>;537 def: Pat<(VecPF16 (Sitofp HVI8:$Vu)), (V6_vcvt_hf_b HvxVR:$Vu)>;538 def: Pat<(VecPF16 (Uitofp HVI8:$Vu)), (V6_vcvt_hf_ub HvxVR:$Vu)>;539}540 541let Predicates = [UseHVXV81] in {542 def : Pat<(VecBF16 (pf1<fpround> HWF32:$Vuu)),543 (V6_vpackwuh_sat (V6_vmux544 (V6_veqsf (HiVec HvxWR:$Vuu), (HiVec HvxWR:$Vuu)),545 (V6_vlsrw (V6_vmux (V6_veqw (V6_vand (HiVec HvxWR:$Vuu),546 (PS_vsplatiw (i32 0x1FFFF))),547 (PS_vsplatiw (i32 0x08000))),548 (HiVec HvxWR:$Vuu),549 (V6_vaddw (HiVec HvxWR:$Vuu),550 (V6_vand (HiVec HvxWR:$Vuu),551 (PS_vsplatiw (i32 0x8000))))),552 (A2_tfrsi 16)),553 (PS_vsplatih (i32 0x7fff))),554 (V6_vmux (V6_veqsf (LoVec HvxWR:$Vuu), (LoVec HvxWR:$Vuu)),555 (V6_vlsrw (V6_vmux (V6_veqw (V6_vand (LoVec HvxWR:$Vuu),556 (PS_vsplatiw (i32 0x1FFFF))),557 (PS_vsplatiw (i32 0x08000))),558 (LoVec HvxWR:$Vuu),559 (V6_vaddw (LoVec HvxWR:$Vuu),560 (V6_vand (LoVec HvxWR:$Vuu),561 (PS_vsplatiw (i32 0x8000))))),562 (A2_tfrsi 16)),563 (PS_vsplatih (i32 0x7fff))))>;564}565 566let Predicates = [UseHVXV73, UseHVXQFloat] in {567 def : Pat<(VecF32 (Sitofp HVI32:$Vu)), (V6_vconv_sf_w HvxVR:$Vu)>;568}569 570let Predicates = [UseHVXV68, UseHVXFloatingPoint] in {571 def: Pat<(vselect HQ16:$Qu, HVF16:$Vs, HVF16:$Vt),572 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;573 def: Pat<(vselect (qnot HQ16:$Qu), HVF16:$Vs, HVF16:$Vt),574 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;575 576 def: Pat<(vselect HQ32:$Qu, HVF32:$Vs, HVF32:$Vt),577 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;578 def: Pat<(vselect (qnot HQ32:$Qu), HVF32:$Vs, HVF32:$Vt),579 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;580}581 582let Predicates = [UseHVXV81, UseHVXFloatingPoint] in {583 def : Pat<(vselect HQ16:$Qu, HVBF16:$Vs, HVBF16:$Vt),584 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;585 def : Pat<(vselect (qnot HQ16:$Qu), HVBF16:$Vs, HVBF16:$Vt),586 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;587}588 589let Predicates = [UseHVXV68, UseHVX128B, UseHVXQFloat] in {590 let AddedComplexity = 220 in {591 defm: MinMax_pats<V6_vmin_hf, V6_vmax_hf, vselect, setgt, VecQ16, HVF16>;592 defm: MinMax_pats<V6_vmin_hf, V6_vmax_hf, vselect, setogt, VecQ16, HVF16>;593 defm: MinMax_pats<V6_vmin_sf, V6_vmax_sf, vselect, setgt, VecQ32, HVF32>;594 defm: MinMax_pats<V6_vmin_sf, V6_vmax_sf, vselect, setogt, VecQ32, HVF32>;595 }596 def: OpR_RR_pat<V6_vmin_hf, pf2<fminimumnum>, VecF16, HVF16>;597 def: OpR_RR_pat<V6_vmax_hf, pf2<fmaximumnum>, VecF16, HVF16>;598 def: OpR_RR_pat<V6_vmin_sf, pf2<fminimumnum>, VecF32, HVF32>;599 def: OpR_RR_pat<V6_vmax_sf, pf2<fmaximumnum>, VecF32, HVF32>;600}601 602let Predicates = [UseHVXV68, UseHVX128B, UseHVXIEEEFP] in {603 let AddedComplexity = 220 in {604 defm: MinMax_pats<V6_vfmin_hf, V6_vfmax_hf, vselect, setgt, VecQ16, HVF16>;605 defm: MinMax_pats<V6_vfmin_hf, V6_vfmax_hf, vselect, setogt, VecQ16, HVF16>;606 defm: MinMax_pats<V6_vfmin_sf, V6_vfmax_sf, vselect, setgt, VecQ32, HVF32>;607 defm: MinMax_pats<V6_vfmin_sf, V6_vfmax_sf, vselect, setogt, VecQ32, HVF32>;608 }609 def: OpR_RR_pat<V6_vfmin_hf, pf2<fminimumnum>, VecF16, HVF16>;610 def: OpR_RR_pat<V6_vfmax_hf, pf2<fmaximumnum>, VecF16, HVF16>;611 def: OpR_RR_pat<V6_vfmin_sf, pf2<fminimumnum>, VecF32, HVF32>;612 def: OpR_RR_pat<V6_vfmax_sf, pf2<fmaximumnum>, VecF32, HVF32>;613}614 615let Predicates = [UseHVX] in {616 // For i8 vectors Vs = (a0, a1, ...), Vt = (b0, b1, ...),617 // V6_vmpybv Vs, Vt produces a pair of i16 vectors Hi:Lo,618 // where Lo = (a0*b0, a2*b2, ...), Hi = (a1*b1, a3*b3, ...).619 def: Pat<(mul HVI8:$Vs, HVI8:$Vt),620 (V6_vshuffeb (HiVec (V6_vmpybv HvxVR:$Vs, HvxVR:$Vt)),621 (LoVec (V6_vmpybv HvxVR:$Vs, HvxVR:$Vt)))>;622 def: Pat<(mul HVI16:$Vs, HVI16:$Vt),623 (V6_vmpyih HvxVR:$Vs, HvxVR:$Vt)>;624 def: Pat<(mul HVI32:$Vs, HVI32:$Vt),625 (V6_vmpyiewuh_acc (V6_vmpyieoh HvxVR:$Vs, HvxVR:$Vt),626 HvxVR:$Vs, HvxVR:$Vt)>;627}628 629let Predicates = [UseHVX] in {630 def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>;631 def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>;632 def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>;633 def: Pat<(VecPI32 (zext HVI16:$Vs)), (VZxth $Vs)>;634 635 def: Pat<(VecI16 (sext_invec HVI8:$Vs)), (LoVec (VSxtb $Vs))>;636 def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (VSxth $Vs))>;637 def: Pat<(VecI32 (sext_invec HVI8:$Vs)),638 (LoVec (VSxth (LoVec (VSxtb $Vs))))>;639 def: Pat<(VecPI16 (sext_invec HWI8:$Vss)), (VSxtb (LoVec $Vss))>;640 def: Pat<(VecPI32 (sext_invec HWI16:$Vss)), (VSxth (LoVec $Vss))>;641 def: Pat<(VecPI32 (sext_invec HWI8:$Vss)),642 (VSxth (LoVec (VSxtb (LoVec $Vss))))>;643 644 def: Pat<(VecI16 (zext_invec HVI8:$Vs)), (LoVec (VZxtb $Vs))>;645 def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (VZxth $Vs))>;646 def: Pat<(VecI32 (zext_invec HVI8:$Vs)),647 (LoVec (VZxth (LoVec (VZxtb $Vs))))>;648 def: Pat<(VecPI16 (zext_invec HWI8:$Vss)), (VZxtb (LoVec $Vss))>;649 def: Pat<(VecPI32 (zext_invec HWI16:$Vss)), (VZxth (LoVec $Vss))>;650 def: Pat<(VecPI32 (zext_invec HWI8:$Vss)),651 (VZxth (LoVec (VZxtb (LoVec $Vss))))>;652 653 def: Pat<(VecI8 (trunc HWI16:$Vss)),654 (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;655 def: Pat<(VecI16 (trunc HWI32:$Vss)),656 (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;657 // Pattern for (v32i8 (trunc v32i32:$Vs)) after widening:658 def: Pat<(VecI8 (trunc659 (concat_vectors660 (VecI16 (trunc (concat_vectors HVI32:$Vs, undef))),661 undef))),662 (V6_vdealb4w (IMPLICIT_DEF), HvxVR:$Vs)>;663 664 def: Pat<(VecQ8 (trunc HVI8:$Vs)),665 (V6_vandvrt HvxVR:$Vs, (ToI32 0x01010101))>;666 def: Pat<(VecQ16 (trunc HVI16:$Vs)),667 (V6_vandvrt HvxVR:$Vs, (ToI32 0x01010101))>;668 def: Pat<(VecQ32 (trunc HVI32:$Vs)),669 (V6_vandvrt HvxVR:$Vs, (ToI32 0x01010101))>;670 def: Pat<(VecQ16 (trunc HWI32:$Vss)),671 (Combineq(VecQ32(V6_vandvrt (HiVec $Vss), (ToI32 0x01010101))),672 (VecQ32 (V6_vandvrt (LoVec $Vss), (ToI32 0x01010101))))>;673}674 675let Predicates = [UseHVX] in {676 // The "source" types are not legal, and there are no parameterized677 // definitions for them, but they are length-specific.678 let Predicates = [UseHVX,UseHVX64B] in {679 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v32i8)),680 (V6_vasrh (V6_vaslh HVI16:$Vs, (ToI32 8)), (ToI32 8))>;681 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i8)),682 (V6_vasrw (V6_vaslw HVI32:$Vs, (ToI32 24)), (ToI32 24))>;683 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)),684 (V6_vasrw (V6_vaslw HVI32:$Vs, (ToI32 16)), (ToI32 16))>;685 }686 let Predicates = [UseHVX,UseHVX128B] in {687 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)),688 (V6_vasrh (V6_vaslh HVI16:$Vs, (ToI32 8)), (ToI32 8))>;689 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i8)),690 (V6_vasrw (V6_vaslw HVI32:$Vs, (ToI32 24)), (ToI32 24))>;691 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)),692 (V6_vasrw (V6_vaslw HVI32:$Vs, (ToI32 16)), (ToI32 16))>;693 }694 695 // Take a pair of vectors Vt:Vs and shift them towards LSB by (Rt & HwLen).696 def: Pat<(VecI8 (valign HVI8:$Vt, HVI8:$Vs, I32:$Rt)),697 (LoVec (V6_valignb HvxVR:$Vt, HvxVR:$Vs, I32:$Rt))>;698 def: Pat<(VecI16 (valign HVI16:$Vt, HVI16:$Vs, I32:$Rt)),699 (LoVec (V6_valignb HvxVR:$Vt, HvxVR:$Vs, I32:$Rt))>;700 def: Pat<(VecI32 (valign HVI32:$Vt, HVI32:$Vs, I32:$Rt)),701 (LoVec (V6_valignb HvxVR:$Vt, HvxVR:$Vs, I32:$Rt))>;702 703 def: Pat<(HexagonVASL HVI8:$Vs, I32:$Rt),704 (V6_vshuffeb (V6_vaslh (HiVec (V6_vzb HvxVR:$Vs)), I32:$Rt),705 (V6_vaslh (LoVec (V6_vzb HvxVR:$Vs)), I32:$Rt))>;706 def: Pat<(HexagonVASR HVI8:$Vs, I32:$Rt),707 (V6_vshuffeb (V6_vasrh (HiVec (V6_vsb HvxVR:$Vs)), I32:$Rt),708 (V6_vasrh (LoVec (V6_vsb HvxVR:$Vs)), I32:$Rt))>;709 def: Pat<(HexagonVLSR HVI8:$Vs, I32:$Rt),710 (V6_vshuffeb (V6_vlsrh (HiVec (V6_vzb HvxVR:$Vs)), I32:$Rt),711 (V6_vlsrh (LoVec (V6_vzb HvxVR:$Vs)), I32:$Rt))>;712 713 def: Pat<(HexagonVASL HVI16:$Vs, I32:$Rt), (V6_vaslh HvxVR:$Vs, I32:$Rt)>;714 def: Pat<(HexagonVASL HVI32:$Vs, I32:$Rt), (V6_vaslw HvxVR:$Vs, I32:$Rt)>;715 def: Pat<(HexagonVASR HVI16:$Vs, I32:$Rt), (V6_vasrh HvxVR:$Vs, I32:$Rt)>;716 def: Pat<(HexagonVASR HVI32:$Vs, I32:$Rt), (V6_vasrw HvxVR:$Vs, I32:$Rt)>;717 def: Pat<(HexagonVLSR HVI16:$Vs, I32:$Rt), (V6_vlsrh HvxVR:$Vs, I32:$Rt)>;718 def: Pat<(HexagonVLSR HVI32:$Vs, I32:$Rt), (V6_vlsrw HvxVR:$Vs, I32:$Rt)>;719 720 def: Pat<(add HVI32:$Vx, (HexagonVASL HVI32:$Vu, I32:$Rt)),721 (V6_vaslw_acc HvxVR:$Vx, HvxVR:$Vu, I32:$Rt)>;722 def: Pat<(add HVI32:$Vx, (HexagonVASR HVI32:$Vu, I32:$Rt)),723 (V6_vasrw_acc HvxVR:$Vx, HvxVR:$Vu, I32:$Rt)>;724 725 def: Pat<(shl HVI8:$Vs, HVI8:$Vt),726 (V6_vshuffeb (V6_vaslhv (HiVec (V6_vzb $Vs)), (HiVec (V6_vzb $Vt))),727 (V6_vaslhv (LoVec (V6_vzb $Vs)), (LoVec (V6_vzb $Vt))))>;728 def: Pat<(sra HVI8:$Vs, HVI8:$Vt),729 (V6_vshuffeb (V6_vasrhv (HiVec (V6_vsb $Vs)), (HiVec (V6_vzb $Vt))),730 (V6_vasrhv (LoVec (V6_vsb $Vs)), (LoVec (V6_vzb $Vt))))>;731 def: Pat<(srl HVI8:$Vs, HVI8:$Vt),732 (V6_vshuffeb (V6_vlsrhv (HiVec (V6_vzb $Vs)), (HiVec (V6_vzb $Vt))),733 (V6_vlsrhv (LoVec (V6_vzb $Vs)), (LoVec (V6_vzb $Vt))))>;734 735 def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>;736 def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>;737 def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;738 def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>;739 def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;740 def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;741 742 // Mfshl hi, lo, amt743 def: Pat<(Mfshl HVI8:$Vu, HVI8:$Vv, HVI8:$Vs),744 (V6_vshuffob (V6_vaslhv (HiVec (V6_vshufoeb $Vu, $Vv)),745 (HiVec (V6_vzb $Vs))),746 (V6_vaslhv (LoVec (V6_vshufoeb $Vu, $Vv)),747 (LoVec (V6_vzb $Vs))))>;748 let Predicates = [UseHVX,UseHVXV60] in {749 // V60 doesn't produce 0 on shifts by bitwidth, e.g. Vv.h << 16-0750 def: Pat<(Mfshl HVI16:$Vu, HVI16:$Vv, HVI16:$Vs),751 (V6_vmux (V6_veqh $Vs, (V6_vd0)),752 $Vu,753 (V6_vor (V6_vaslhv $Vu, $Vs),754 (V6_vlsrhv $Vv, (VSubih 16, $Vs))))>;755 def: Pat<(Mfshl HVI32:$Vu, HVI32:$Vv, HVI32:$Vs),756 (V6_vmux (V6_veqw (V6_vand $Vs, (PS_vsplatiw (i32 31))), (V6_vd0)),757 $Vu,758 (V6_vor (V6_vaslwv $Vu, $Vs),759 (V6_vlsrwv $Vv, (VSubiw 32, $Vs))))>;760 }761 let Predicates = [UseHVX,UseHVXV62], AddedComplexity = 10 in {762 // Do it as (Vu << Vs) | (Vv >> (BW-Vs)).763 // For Vs == 0 becomes Vu | (Vv >> -BW), since the shift amount is764 // sign-extended. Then this becomes Vu | (Vv << BW) == Vu.765 def: Pat<(Mfshl HVI16:$Vu, HVI16:$Vv, HVI16:$Vs),766 (V6_vor (V6_vaslhv $Vu, $Vs),767 (V6_vlsrhv $Vv, (VSubih 16, $Vs)))>;768 def: Pat<(Mfshl HVI32:$Vu, HVI32:$Vv, HVI32:$Vs),769 (V6_vor (V6_vaslwv $Vu, $Vs),770 (V6_vlsrwv $Vv, (VSubiw 32, $Vs)))>;771 }772 let Predicates = [UseHVX,UseHVXV66], AddedComplexity = 20 in {773 // Assume Vs > 0 (and within bit width)774 // Vx[1]:Vx[0] = V6_vasr_into Vx[0], Vv, Vs775 // --> (Vx[0]:Vx[0] & (ffffffff << -Vs)) | (Vv:00000000 << -Vs)776 // i.e. Vx[1] = insert ((Vv << -Vs) -> Vx[0])777 def: Pat<(Mfshl HVI32:$Vu, HVI32:$Vv, HVI32:$Vs),778 (HiVec (V6_vasr_into (Combinev (VecI32 (IMPLICIT_DEF)),779 (V6_vlsrwv $Vv, (VSubiw 32, $Vs))),780 $Vu,781 (V6_vsubw (V6_vd0), $Vs)))>;782 }783 784 // Mfshr hi, lo, amt785 def: Pat<(Mfshr HVI8:$Vu, HVI8:$Vv, HVI8:$Vs),786 (V6_vshuffeb (V6_vlsrhv (HiVec (V6_vshufoeb $Vu, $Vv)),787 (HiVec (V6_vzb $Vs))),788 (V6_vlsrhv (LoVec (V6_vshufoeb $Vu, $Vv)),789 (LoVec (V6_vzb $Vs))))>;790 let Predicates = [UseHVX,UseHVXV60] in {791 def: Pat<(Mfshr HVI16:$Vu, HVI16:$Vv, HVI16:$Vs),792 (V6_vmux (V6_veqh $Vs, (V6_vd0)),793 $Vv,794 (V6_vor (V6_vaslhv $Vu, (VSubih 16, $Vs)),795 (V6_vlsrhv $Vv, $Vs)))>;796 def: Pat<(Mfshr HVI32:$Vu, HVI32:$Vv, HVI32:$Vs),797 (V6_vmux (V6_veqw $Vs, (V6_vd0)),798 $Vv,799 (V6_vor (V6_vaslwv $Vu, (VSubiw 32, $Vs)),800 (V6_vlsrwv $Vv, $Vs)))>;801 }802 let Predicates = [UseHVX,UseHVXV62], AddedComplexity = 10 in {803 // Do it as (Vu >> -(BW-Vs)) | (Vv >> Vs).804 // For Vs == 0 becomes (Vu << BW) | Vs == 0 | Vv805 def: Pat<(Mfshr HVI16:$Vu, HVI16:$Vv, HVI16:$Vs),806 (V6_vor (V6_vlsrhv $Vu, (V6_vsubh $Vs, (PS_vsplatih (i32 16)))),807 (V6_vlsrhv $Vv, $Vs))>;808 def: Pat<(Mfshr HVI32:$Vu, HVI32:$Vv, HVI32:$Vs),809 (V6_vor (V6_vlsrwv $Vu, (V6_vsubw $Vs, (PS_vsplatiw (i32 32)))),810 (V6_vlsrwv $Vv, $Vs))>;811 }812 let Predicates = [UseHVX,UseHVXV66], AddedComplexity = 20 in {813 // Assume Vs > 0 (and within bit width)814 // Vx[1]:Vx[0] = V6_vasr_into Vx[0], Vv, Vs815 // --> (Vx[0]:Vx[0] & (ffffffff >> Vs)) | (Vv:00000000 >> Vs)816 // i.e. Vx[0] = insert ((Vv >> Vs) -> Vx[0])817 def: Pat<(Mfshr HVI32:$Vu, HVI32:$Vv, HVI32:$Vs),818 (LoVec (V6_vasr_into (Combinev (VecI32 (IMPLICIT_DEF)),819 (V6_vlsrwv $Vv, $Vs)),820 $Vu,821 $Vs))>;822 }823 824 def: Pat<(VecI16 (bswap HVI16:$Vs)),825 (V6_vdelta HvxVR:$Vs, (PS_vsplatib (i32 0x01)))>;826 def: Pat<(VecI32 (bswap HVI32:$Vs)),827 (V6_vdelta HvxVR:$Vs, (PS_vsplatib (i32 0x03)))>;828 829 def: Pat<(VecI8 (ctpop HVI8:$Vs)),830 (V6_vshuffeb (V6_vpopcounth (HiVec (V6_vzb HvxVR:$Vs))),831 (V6_vpopcounth (LoVec (V6_vzb HvxVR:$Vs))))>;832 def: Pat<(VecI16 (ctpop HVI16:$Vs)), (V6_vpopcounth HvxVR:$Vs)>;833 def: Pat<(VecI32 (ctpop HVI32:$Vs)),834 (V6_vaddw (LoVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))),835 (HiVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))))>;836 837 def: Pat<(VecI8 (ctlz HVI8:$Vs)),838 (V6_vsubb (V6_vshuffeb (V6_vcl0h (HiVec (V6_vzb HvxVR:$Vs))),839 (V6_vcl0h (LoVec (V6_vzb HvxVR:$Vs)))),840 (PS_vsplatib (i32 0x08)))>;841 842 def: Pat<(VecI16 (ctlz HVI16:$Vs)), (V6_vcl0h HvxVR:$Vs)>;843 def: Pat<(VecI32 (ctlz HVI32:$Vs)), (V6_vcl0w HvxVR:$Vs)>;844}845 846class HvxSel_pat<InstHexagon MI, PatFrag RegPred>847 : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),848 (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;849 850let Predicates = [UseHVX] in {851 def: HvxSel_pat<PS_vselect, HVI8>;852 def: HvxSel_pat<PS_vselect, HVI16>;853 def: HvxSel_pat<PS_vselect, HVI32>;854 def: HvxSel_pat<PS_wselect, HWI8>;855 def: HvxSel_pat<PS_wselect, HWI16>;856 def: HvxSel_pat<PS_wselect, HWI32>;857}858 859def V2Q: OutPatFrag<(ops node:$Vs), (V6_vandvrt $Vs, (ToI32 -1))>;860 861let Predicates = [UseHVX] in {862 def: Pat<(select I1:$Pu, VecQ8:$Qs, VecQ8:$Qt),863 (V2Q (PS_vselect $Pu, (Q2V $Qs), (Q2V $Qt)))>;864 def: Pat<(select I1:$Pu, VecQ16:$Qs, VecQ16:$Qt),865 (V2Q (PS_vselect $Pu, (Q2V $Qs), (Q2V $Qt)))>;866 def: Pat<(select I1:$Pu, VecQ32:$Qs, VecQ32:$Qt),867 (V2Q (PS_vselect $Pu, (Q2V $Qs), (Q2V $Qt)))>;868}869 870let Predicates = [UseHVX] in {871 def: Pat<(VecQ8 (qtrue)), (PS_qtrue)>;872 def: Pat<(VecQ16 (qtrue)), (PS_qtrue)>;873 def: Pat<(VecQ32 (qtrue)), (PS_qtrue)>;874 def: Pat<(VecQ8 (qfalse)), (PS_qfalse)>;875 def: Pat<(VecQ16 (qfalse)), (PS_qfalse)>;876 def: Pat<(VecQ32 (qfalse)), (PS_qfalse)>;877 878 def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;879 def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;880 def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;881 def: Pat<(qnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;882 def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;883 def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;884 885 def: OpR_RR_pat<V6_pred_and, And, VecQ8, HQ8>;886 def: OpR_RR_pat<V6_pred_and, And, VecQ16, HQ16>;887 def: OpR_RR_pat<V6_pred_and, And, VecQ32, HQ32>;888 def: OpR_RR_pat<V6_pred_or, Or, VecQ8, HQ8>;889 def: OpR_RR_pat<V6_pred_or, Or, VecQ16, HQ16>;890 def: OpR_RR_pat<V6_pred_or, Or, VecQ32, HQ32>;891 def: OpR_RR_pat<V6_pred_xor, Xor, VecQ8, HQ8>;892 def: OpR_RR_pat<V6_pred_xor, Xor, VecQ16, HQ16>;893 def: OpR_RR_pat<V6_pred_xor, Xor, VecQ32, HQ32>;894 895 def: OpR_RR_pat<V6_pred_and_n, VNot2<And, qnot>, VecQ8, HQ8>;896 def: OpR_RR_pat<V6_pred_and_n, VNot2<And, qnot>, VecQ16, HQ16>;897 def: OpR_RR_pat<V6_pred_and_n, VNot2<And, qnot>, VecQ32, HQ32>;898 def: OpR_RR_pat<V6_pred_or_n, VNot2<Or, qnot>, VecQ8, HQ8>;899 def: OpR_RR_pat<V6_pred_or_n, VNot2<Or, qnot>, VecQ16, HQ16>;900 def: OpR_RR_pat<V6_pred_or_n, VNot2<Or, qnot>, VecQ32, HQ32>;901 902 def: OpR_RR_pat<V6_veqb, seteq, VecQ8, HVI8>;903 def: OpR_RR_pat<V6_veqh, seteq, VecQ16, HVI16>;904 def: OpR_RR_pat<V6_veqw, seteq, VecQ32, HVI32>;905 def: OpR_RR_pat<V6_vgtb, setgt, VecQ8, HVI8>;906 def: OpR_RR_pat<V6_vgth, setgt, VecQ16, HVI16>;907 def: OpR_RR_pat<V6_vgtw, setgt, VecQ32, HVI32>;908 def: OpR_RR_pat<V6_vgtub, setugt, VecQ8, HVI8>;909 def: OpR_RR_pat<V6_vgtuh, setugt, VecQ16, HVI16>;910 def: OpR_RR_pat<V6_vgtuw, setugt, VecQ32, HVI32>;911 912 def: AccRRR_pat<V6_veqb_and, And, seteq, HQ8, HVI8, HVI8>;913 def: AccRRR_pat<V6_veqb_or, Or, seteq, HQ8, HVI8, HVI8>;914 def: AccRRR_pat<V6_veqb_xor, Xor, seteq, HQ8, HVI8, HVI8>;915 def: AccRRR_pat<V6_veqh_and, And, seteq, HQ16, HVI16, HVI16>;916 def: AccRRR_pat<V6_veqh_or, Or, seteq, HQ16, HVI16, HVI16>;917 def: AccRRR_pat<V6_veqh_xor, Xor, seteq, HQ16, HVI16, HVI16>;918 def: AccRRR_pat<V6_veqw_and, And, seteq, HQ32, HVI32, HVI32>;919 def: AccRRR_pat<V6_veqw_or, Or, seteq, HQ32, HVI32, HVI32>;920 def: AccRRR_pat<V6_veqw_xor, Xor, seteq, HQ32, HVI32, HVI32>;921 922 def: AccRRR_pat<V6_vgtb_and, And, setgt, HQ8, HVI8, HVI8>;923 def: AccRRR_pat<V6_vgtb_or, Or, setgt, HQ8, HVI8, HVI8>;924 def: AccRRR_pat<V6_vgtb_xor, Xor, setgt, HQ8, HVI8, HVI8>;925 def: AccRRR_pat<V6_vgth_and, And, setgt, HQ16, HVI16, HVI16>;926 def: AccRRR_pat<V6_vgth_or, Or, setgt, HQ16, HVI16, HVI16>;927 def: AccRRR_pat<V6_vgth_xor, Xor, setgt, HQ16, HVI16, HVI16>;928 def: AccRRR_pat<V6_vgtw_and, And, setgt, HQ32, HVI32, HVI32>;929 def: AccRRR_pat<V6_vgtw_or, Or, setgt, HQ32, HVI32, HVI32>;930 def: AccRRR_pat<V6_vgtw_xor, Xor, setgt, HQ32, HVI32, HVI32>;931 932 def: AccRRR_pat<V6_vgtub_and, And, setugt, HQ8, HVI8, HVI8>;933 def: AccRRR_pat<V6_vgtub_or, Or, setugt, HQ8, HVI8, HVI8>;934 def: AccRRR_pat<V6_vgtub_xor, Xor, setugt, HQ8, HVI8, HVI8>;935 def: AccRRR_pat<V6_vgtuh_and, And, setugt, HQ16, HVI16, HVI16>;936 def: AccRRR_pat<V6_vgtuh_or, Or, setugt, HQ16, HVI16, HVI16>;937 def: AccRRR_pat<V6_vgtuh_xor, Xor, setugt, HQ16, HVI16, HVI16>;938 def: AccRRR_pat<V6_vgtuw_and, And, setugt, HQ32, HVI32, HVI32>;939 def: AccRRR_pat<V6_vgtuw_or, Or, setugt, HQ32, HVI32, HVI32>;940 def: AccRRR_pat<V6_vgtuw_xor, Xor, setugt, HQ32, HVI32, HVI32>;941}942 943let Predicates = [UseHVXV68, UseHVXFloatingPoint] in {944 def: OpR_RR_pat<V6_veqh, seteq, VecQ16, HVF16>;945 def: OpR_RR_pat<V6_veqh, setoeq, VecQ16, HVF16>;946 def: OpR_RR_pat<V6_veqh, setueq, VecQ16, HVF16>;947 def: OpR_RR_pat<V6_vgthf, setgt, VecQ16, HVF16>;948 def: OpR_RR_pat<V6_vgthf, setogt, VecQ16, HVF16>;949 def: OpR_RR_pat<V6_vgthf, setugt, VecQ16, HVF16>;950 951 def: OpR_RR_pat<V6_veqw, seteq, VecQ32, HVF32>;952 def: OpR_RR_pat<V6_veqw, setoeq, VecQ32, HVF32>;953 def: OpR_RR_pat<V6_veqw, setueq, VecQ32, HVF32>;954 def: OpR_RR_pat<V6_vgtsf, setgt, VecQ32, HVF32>;955 def: OpR_RR_pat<V6_vgtsf, setogt, VecQ32, HVF32>;956 def: OpR_RR_pat<V6_vgtsf, setugt, VecQ32, HVF32>;957 958 def: AccRRR_pat<V6_veqh_and, And, seteq, HQ16, HVF16, HVF16>;959 def: AccRRR_pat<V6_veqh_or, Or, seteq, HQ16, HVF16, HVF16>;960 def: AccRRR_pat<V6_veqh_xor, Xor, seteq, HQ16, HVF16, HVF16>;961 def: AccRRR_pat<V6_veqh_and, And, setoeq, HQ16, HVF16, HVF16>;962 def: AccRRR_pat<V6_veqh_or, Or, setoeq, HQ16, HVF16, HVF16>;963 def: AccRRR_pat<V6_veqh_xor, Xor, setoeq, HQ16, HVF16, HVF16>;964 def: AccRRR_pat<V6_veqh_and, And, setueq, HQ16, HVF16, HVF16>;965 def: AccRRR_pat<V6_veqh_or, Or, setueq, HQ16, HVF16, HVF16>;966 def: AccRRR_pat<V6_veqh_xor, Xor, setueq, HQ16, HVF16, HVF16>;967 def: AccRRR_pat<V6_vgthf_and, And, setgt, HQ16, HVF16, HVF16>;968 def: AccRRR_pat<V6_vgthf_or, Or, setgt, HQ16, HVF16, HVF16>;969 def: AccRRR_pat<V6_vgthf_xor, Xor, setgt, HQ16, HVF16, HVF16>;970 def: AccRRR_pat<V6_vgthf_and, And, setogt, HQ16, HVF16, HVF16>;971 def: AccRRR_pat<V6_vgthf_or, Or, setogt, HQ16, HVF16, HVF16>;972 def: AccRRR_pat<V6_vgthf_xor, Xor, setogt, HQ16, HVF16, HVF16>;973 def: AccRRR_pat<V6_vgthf_and, And, setugt, HQ16, HVF16, HVF16>;974 def: AccRRR_pat<V6_vgthf_or, Or, setugt, HQ16, HVF16, HVF16>;975 def: AccRRR_pat<V6_vgthf_xor, Xor, setugt, HQ16, HVF16, HVF16>;976 977 def: AccRRR_pat<V6_veqw_and, And, seteq, HQ32, HVF32, HVF32>;978 def: AccRRR_pat<V6_veqw_or, Or, seteq, HQ32, HVF32, HVF32>;979 def: AccRRR_pat<V6_veqw_xor, Xor, seteq, HQ32, HVF32, HVF32>;980 def: AccRRR_pat<V6_veqw_and, And, setoeq, HQ32, HVF32, HVF32>;981 def: AccRRR_pat<V6_veqw_or, Or, setoeq, HQ32, HVF32, HVF32>;982 def: AccRRR_pat<V6_veqw_xor, Xor, setoeq, HQ32, HVF32, HVF32>;983 def: AccRRR_pat<V6_veqw_and, And, setueq, HQ32, HVF32, HVF32>;984 def: AccRRR_pat<V6_veqw_or, Or, setueq, HQ32, HVF32, HVF32>;985 def: AccRRR_pat<V6_veqw_xor, Xor, setueq, HQ32, HVF32, HVF32>;986 def: AccRRR_pat<V6_vgtsf_and, And, setgt, HQ32, HVF32, HVF32>;987 def: AccRRR_pat<V6_vgtsf_or, Or, setgt, HQ32, HVF32, HVF32>;988 def: AccRRR_pat<V6_vgtsf_xor, Xor, setgt, HQ32, HVF32, HVF32>;989 def: AccRRR_pat<V6_vgtsf_and, And, setogt, HQ32, HVF32, HVF32>;990 def: AccRRR_pat<V6_vgtsf_or, Or, setogt, HQ32, HVF32, HVF32>;991 def: AccRRR_pat<V6_vgtsf_xor, Xor, setogt, HQ32, HVF32, HVF32>;992 def: AccRRR_pat<V6_vgtsf_and, And, setugt, HQ32, HVF32, HVF32>;993 def: AccRRR_pat<V6_vgtsf_or, Or, setugt, HQ32, HVF32, HVF32>;994 def: AccRRR_pat<V6_vgtsf_xor, Xor, setugt, HQ32, HVF32, HVF32>;995 996 def: Pat<(VecQ16 (setone HVF16:$Vt, HVF16:$Vu)),997 (V6_pred_not (V6_veqh HvxVR:$Vt, HvxVR:$Vu))>;998 999 def: Pat<(VecQ32 (setone HVF32:$Vt, HVF32:$Vu)),1000 (V6_pred_not (V6_veqw HvxVR:$Vt, HvxVR:$Vu))>;1001}1002 1003// Multiply high for non-i32 types1004def: Pat<(VecI8 (mulhs HVI8:$Vu, HVI8:$Vv)),1005 (V6_vshuffob (HiVec (V6_vmpybv $Vu, $Vv)),1006 (LoVec (V6_vmpybv $Vu, $Vv)))>;1007def: Pat<(VecI16 (mulhs HVI16:$Vu, HVI16:$Vv)),1008 (V6_vshufoh (HiVec (V6_vmpyhv $Vu, $Vv)),1009 (LoVec (V6_vmpyhv $Vu, $Vv)))>;1010def: Pat<(VecI8 (mulhu HVI8:$Vu, HVI8:$Vv)),1011 (V6_vshuffob (HiVec (V6_vmpyubv $Vu, $Vv)),1012 (LoVec (V6_vmpyubv $Vu, $Vv)))>;1013def: Pat<(VecI16 (mulhu HVI16:$Vu, HVI16:$Vv)),1014 (V6_vshufoh (HiVec (V6_vmpyuhv $Vu, $Vv)),1015 (LoVec (V6_vmpyuhv $Vu, $Vv)))>;1016let Predicates = [UseHVXV69], AddedComplexity = 20 in {1017 def: Pat<(VecI16 (mulhu HVI16:$Vu, HVI16:$Vv)),1018 (V6_vmpyuhvs $Vu, $Vv)>;1019}1020 1021let Predicates = [UseHVXV60] in {1022 // V60 doesn't have vabsb or byte shifts.1023 // Do the "mask = x >> width-1; abs = (x + mask) ^ mask" trick.1024 // v31:30.h = vsxt(Inp.b) ; generate masks in odd bytes in1025 // ; interleaved half-words1026 // v29:28.b = vshuffoe(v31.b,v30.b) ; collect odd/even bytes, masks = v291027 // v27.b = vadd(Inp.b,v29.b) ; x + masks1028 // Abs = vxor(v27,v29) ; ^ masks1029 def: Pat<(VecI8 (abs HVI8:$Vs)),1030 (V6_vxor HvxVR:$Vs,1031 (V6_vaddb HvxVR:$Vs,1032 (HiVec1033 (V6_vshufoeb1034 (HiVec (V6_vsb HvxVR:$Vs)),1035 (LoVec (V6_vsb HvxVR:$Vs))))))>;1036}1037 1038let Predicates = [UseHVXV62], AddedComplexity = 20 in {1039 def: Pat<(VecI8 (abs HVI8:$Vs)), (V6_vabsb HvxVR:$Vs)>;1040}1041 1042def: Pat<(VecI16 (abs HVI16:$Vs)), (V6_vabsh HvxVR:$Vs)>;1043def: Pat<(VecI32 (abs HVI32:$Vs)), (V6_vabsw HvxVR:$Vs)>;1044 1045// If a node takes an MVT type as a parameter, the argument must be1046// a name of a member of MVT.1047multiclass Saturates<ValueType HvxTy_i8, ValueType HvxTy_i16> {1048 def: Pat<(VecI8 (ssat HWI16:$Vss, HvxTy_i8)),1049 (V6_vpackhb_sat (HiVec $Vss), (LoVec $Vss))>;1050 def: Pat<(VecI8 (ssat (concat_vectors HWI32:$Vss, HWI32:$Vtt), HvxTy_i8)),1051 (V6_vpackhb_sat (V6_vpackwh_sat (HiVec $Vtt), (LoVec $Vtt)),1052 (V6_vpackwh_sat (HiVec $Vss), (LoVec $Vss)))>;1053 def: Pat<(VecI16 (ssat HWI32:$Vss, HvxTy_i16)),1054 (V6_vpackwh_sat (HiVec $Vss), (LoVec $Vss))>;1055 1056 def: Pat<(VecI8 (usat HWI16:$Vss, HvxTy_i8)),1057 (V6_vpackhub_sat (HiVec $Vss), (LoVec $Vss))>;1058 def: Pat<(VecI8 (usat (concat_vectors HWI32:$Vss, HWI32:$Vtt), HvxTy_i8)),1059 (V6_vpackhub_sat (V6_vpackwuh_sat (HiVec $Vtt), (LoVec $Vtt)),1060 (V6_vpackwuh_sat (HiVec $Vss), (LoVec $Vss)))>;1061 def: Pat<(VecI16 (usat HWI32:$Vss, HvxTy_i16)),1062 (V6_vpackwuh_sat (HiVec $Vss), (LoVec $Vss))>;1063}1064let Predicates = [UseHVX64B] in {1065 defm: Saturates<v64i8, v32i16>;1066}1067let Predicates = [UseHVX128B] in {1068 defm: Saturates<v128i8, v64i16>;1069}1070