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1//=-HexagonScheduleV55.td - HexagonV55 Scheduling Definitions -*- tablegen -*=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9 10class HexagonV55PseudoItin {11 list<InstrItinData> V55PseudoItin_list = [12 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],13 [1, 1, 1]>,14 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,15 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,16 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,17 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>18 ];19}20 21def HexagonV55ItinList : DepScalarItinV55,22 HexagonV55PseudoItin {23 list<InstrItinData> V55Itin_list = [24 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>,25 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],26 [1, 1, 1]>27 ];28 list<InstrItinData> ItinList =29 !listconcat(V55Itin_list, DepScalarItinV55_list,30 V55PseudoItin_list);31}32 33def HexagonItinerariesV55 :34 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],35 [Hex_FWD], HexagonV55ItinList.ItinList>;36 37def HexagonModelV55 : SchedMachineModel {38 // Max issue per cycle == bundle width.39 let IssueWidth = 4;40 let Itineraries = HexagonItinerariesV55;41 let LoadLatency = 1;42 let CompleteModel = 0;43}44 45//===----------------------------------------------------------------------===//46// Hexagon V55 Resource Definitions -47//===----------------------------------------------------------------------===//48