32 lines · plain
1//=-HexagonScheduleV81.td - HexagonV81 Scheduling Definitions *- tablegen -*-=//2//3// The LLVM Compiler Infrastructure4//5// This file is distributed under the University of Illinois Open Source6// License. See LICENSE.TXT for details.7//8//===----------------------------------------------------------------------===//9 10def HexagonV81ItinList : DepScalarItinV81, ScalarItin,11 DepHVXItinV81, HVXItin, PseudoItin {12 list<InstrItinData> ItinList =13 !listconcat(DepScalarItinV81_list, ScalarItin_list,14 DepHVXItinV81_list, HVXItin_list, PseudoItin_list);15}16 17def HexagonItinerariesV81 :18 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,19 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,20 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,21 CVI_ALL_NOMEM, CVI_ZW],22 [Hex_FWD, HVX_FWD],23 HexagonV81ItinList.ItinList>;24 25def HexagonModelV81 : SchedMachineModel {26 // Max issue per cycle == bundle width.27 let IssueWidth = 4;28 let Itineraries = HexagonItinerariesV81;29 let LoadLatency = 1;30 let CompleteModel = 0;31}32