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1//===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains small standalone helper functions and enum definitions for10// the Hexagon target useful for the compiler back-end and the MC libraries.11// As such, it deliberately does not include references to LLVM core12// code gen types, passes, etc..13//14//===----------------------------------------------------------------------===//15 16#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H17#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H18 19#include "HexagonDepITypes.h"20#include "MCTargetDesc/HexagonMCTargetDesc.h"21 22namespace llvm {23 24/// HexagonII - This namespace holds all of the target specific flags that25/// instruction info tracks.26namespace HexagonII {27 unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY;28 unsigned const TypeCVI_LAST = TypeCVI_ZW;29 30 enum AddrMode {31 NoAddrMode = 0, // No addressing mode32 Absolute = 1, // Absolute addressing mode33 AbsoluteSet = 2, // Absolute set addressing mode34 BaseImmOffset = 3, // Indirect with offset35 BaseLongOffset = 4, // Indirect with long offset36 BaseRegOffset = 5, // Indirect with register offset37 PostInc = 6 // Post increment addressing mode38 };39 40 enum MemAccessSize {41 NoMemAccess = 0,42 ByteAccess,43 HalfWordAccess,44 WordAccess,45 DoubleWordAccess,46 HVXVectorAccess47 };48 49 // MCInstrDesc TSFlags50 // *** Must match HexagonInstrFormat*.td ***51 enum {52 // This 7-bit field describes the insn type.53 TypePos = 0,54 TypeMask = 0x7f,55 56 // Solo instructions.57 SoloPos = 7,58 SoloMask = 0x1,59 // Packed only with A or X-type instructions.60 SoloAXPos = 8,61 SoloAXMask = 0x1,62 // Only A-type instruction in first slot or nothing.63 RestrictSlot1AOKPos = 9,64 RestrictSlot1AOKMask = 0x1,65 66 // Predicated instructions.67 PredicatedPos = 10,68 PredicatedMask = 0x1,69 PredicatedFalsePos = 11,70 PredicatedFalseMask = 0x1,71 PredicatedNewPos = 12,72 PredicatedNewMask = 0x1,73 PredicateLatePos = 13,74 PredicateLateMask = 0x1,75 76 // New-Value consumer instructions.77 NewValuePos = 14,78 NewValueMask = 0x1,79 // New-Value producer instructions.80 hasNewValuePos = 15,81 hasNewValueMask = 0x1,82 // Which operand consumes or produces a new value.83 NewValueOpPos = 16,84 NewValueOpMask = 0x7,85 // Stores that can become new-value stores.86 mayNVStorePos = 19,87 mayNVStoreMask = 0x1,88 // New-value store instructions.89 NVStorePos = 20,90 NVStoreMask = 0x1,91 // Loads that can become current-value loads.92 mayCVLoadPos = 21,93 mayCVLoadMask = 0x1,94 // Current-value load instructions.95 CVLoadPos = 22,96 CVLoadMask = 0x1,97 98 // Extendable insns.99 ExtendablePos = 23,100 ExtendableMask = 0x1,101 // Insns must be extended.102 ExtendedPos = 24,103 ExtendedMask = 0x1,104 // Which operand may be extended.105 ExtendableOpPos = 25,106 ExtendableOpMask = 0x7,107 // Signed or unsigned range.108 ExtentSignedPos = 28,109 ExtentSignedMask = 0x1,110 // Number of bits of range before extending operand.111 ExtentBitsPos = 29,112 ExtentBitsMask = 0x1f,113 // Alignment power-of-two before extending operand.114 ExtentAlignPos = 34,115 ExtentAlignMask = 0x3,116 117 CofMax1Pos = 36,118 CofMax1Mask = 0x1,119 CofRelax1Pos = 37,120 CofRelax1Mask = 0x1,121 CofRelax2Pos = 38,122 CofRelax2Mask = 0x1,123 124 RestrictNoSlot1StorePos = 39,125 RestrictNoSlot1StoreMask = 0x1,126 127 // Addressing mode for load/store instructions.128 AddrModePos = 40,129 AddrModeMask = 0x7,130 // Access size for load/store instructions.131 MemAccessSizePos = 43,132 MemAccesSizeMask = 0xf,133 134 // Branch predicted taken.135 TakenPos = 47,136 TakenMask = 0x1,137 138 // Floating-point instructions.139 FPPos = 48,140 FPMask = 0x1,141 142 // New-Value producer-2 instructions.143 hasNewValuePos2 = 50,144 hasNewValueMask2 = 0x1,145 // Which operand consumes or produces a new value.146 NewValueOpPos2 = 51,147 NewValueOpMask2 = 0x7,148 149 // Accumulator instructions.150 AccumulatorPos = 54,151 AccumulatorMask = 0x1,152 153 // Complex XU, prevent xu competition by preferring slot3154 PrefersSlot3Pos = 55,155 PrefersSlot3Mask = 0x1,156 157 HasHvxTmpPos = 56,158 HasHvxTmpMask = 0x1,159 160 CVINewPos = 58,161 CVINewMask = 0x1,162 163 isCVIPos = 59,164 isCVIMask = 0x1,165 166 isHVXALUPos = 60,167 isHVXALUMask = 0x1,168 169 isHVXALU2SRCPos = 61,170 isHVXALU2SRCMask = 0x1,171 172 hasUnaryRestrictionPos = 62,173 hasUnaryRestrictionMask = 0x1,174 };175 176 // *** The code above must match HexagonInstrFormat*.td *** //177 178 // Hexagon specific MO operand flag mask.179 enum HexagonMOTargetFlagVal {180 // Hexagon-specific MachineOperand target flags.181 //182 // When changing these, make sure to update183 // getSerializableDirectMachineOperandTargetFlags and184 // getSerializableBitmaskMachineOperandTargetFlags if needed.185 MO_NO_FLAG,186 187 /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation188 /// Used for computing a global address for PIC compilations189 MO_PCREL,190 191 /// MO_GOT - Indicates a GOT-relative relocation192 MO_GOT,193 194 // Low or high part of a symbol.195 MO_LO16,196 MO_HI16,197 198 // Offset from the base of the SDA.199 MO_GPREL,200 201 // MO_GDGOT - indicates GOT relative relocation for TLS202 // GeneralDynamic method203 MO_GDGOT,204 205 // MO_GDPLT - indicates PLT relative relocation for TLS206 // GeneralDynamic method207 MO_GDPLT,208 209 // MO_IE - indicates non PIC relocation for TLS210 // Initial Executable method211 MO_IE,212 213 // MO_IEGOT - indicates PIC relocation for TLS214 // Initial Executable method215 MO_IEGOT,216 217 // MO_TPREL - indicates relocation for TLS218 // local Executable method219 MO_TPREL,220 221 // HMOTF_ConstExtended222 // Addendum to above, indicates a const extended op223 // Can be used as a mask.224 HMOTF_ConstExtended = 0x80,225 226 // Union of all bitmasks (currently only HMOTF_ConstExtended).227 MO_Bitmasks = HMOTF_ConstExtended228 };229 230 // Hexagon Sub-instruction classes.231 enum SubInstructionGroup {232 HSIG_None = 0,233 HSIG_L1,234 HSIG_L2,235 HSIG_S1,236 HSIG_S2,237 HSIG_A,238 HSIG_Compound239 };240 241 // Hexagon Compound classes.242 enum CompoundGroup {243 HCG_None = 0,244 HCG_A,245 HCG_B,246 HCG_C247 };248 249 enum InstParseBits {250 INST_PARSE_MASK = 0x0000c000,251 INST_PARSE_PACKET_END = 0x0000c000,252 INST_PARSE_LOOP_END = 0x00008000,253 INST_PARSE_NOT_END = 0x00004000,254 INST_PARSE_DUPLEX = 0x00000000,255 INST_PARSE_EXTENDER = 0x00000000256 };257 258 enum InstIClassBits : unsigned {259 INST_ICLASS_MASK = 0xf0000000,260 INST_ICLASS_EXTENDER = 0x00000000,261 INST_ICLASS_J_1 = 0x10000000,262 INST_ICLASS_J_2 = 0x20000000,263 INST_ICLASS_LD_ST_1 = 0x30000000,264 INST_ICLASS_LD_ST_2 = 0x40000000,265 INST_ICLASS_J_3 = 0x50000000,266 INST_ICLASS_CR = 0x60000000,267 INST_ICLASS_ALU32_1 = 0x70000000,268 INST_ICLASS_XTYPE_1 = 0x80000000,269 INST_ICLASS_LD = 0x90000000,270 INST_ICLASS_ST = 0xa0000000,271 INST_ICLASS_ALU32_2 = 0xb0000000,272 INST_ICLASS_XTYPE_2 = 0xc0000000,273 INST_ICLASS_XTYPE_3 = 0xd0000000,274 INST_ICLASS_XTYPE_4 = 0xe0000000,275 INST_ICLASS_ALU32_3 = 0xf0000000276 };277 278 [[maybe_unused]]279 static unsigned getMemAccessSizeInBytes(MemAccessSize S) {280 switch (S) {281 case ByteAccess: return 1;282 case HalfWordAccess: return 2;283 case WordAccess: return 4;284 case DoubleWordAccess: return 8;285 default: return 0;286 }287 }288} // end namespace HexagonII289 290} // end namespace llvm291 292#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H293