123 lines · c
1//===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file provides Hexagon specific target descriptions.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H14#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H15 16#include "llvm/MC/MCRegisterInfo.h"17#include "llvm/Support/CommandLine.h"18#include <cstdint>19 20#define Hexagon_POINTER_SIZE 421 22#define Hexagon_PointerSize (Hexagon_POINTER_SIZE)23#define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8)24#define Hexagon_WordSize Hexagon_PointerSize25#define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits26 27// allocframe saves LR and FP on stack before allocating28// a new stack frame. This takes 8 bytes.29#define HEXAGON_LRFP_SIZE 830 31// Normal instruction size (in bytes).32#define HEXAGON_INSTR_SIZE 433 34// Maximum number of words and instructions in a packet.35#define HEXAGON_PACKET_SIZE 436#define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE)37// Minimum number of instructions in an end-loop packet.38#define HEXAGON_PACKET_INNER_SIZE 239#define HEXAGON_PACKET_OUTER_SIZE 340// Maximum number of instructions in a packet before shuffling,41// including a compound one or a duplex or an extender.42#define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3)43 44// Name of the global offset table as defined by the Hexagon ABI45#define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"46 47namespace llvm {48 49struct InstrStage;50class FeatureBitset;51class MCAsmBackend;52class MCCodeEmitter;53class MCContext;54class MCInstrInfo;55class MCObjectTargetWriter;56class MCRegisterInfo;57class MCSubtargetInfo;58class MCTargetOptions;59class Target;60class Triple;61class StringRef;62 63extern cl::opt<bool> HexagonDisableCompound;64extern cl::opt<bool> HexagonDisableDuplex;65extern const InstrStage HexagonStages[];66 67MCInstrInfo *createHexagonMCInstrInfo();68MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);69 70namespace Hexagon_MC {71 StringRef selectHexagonCPU(StringRef CPU);72 73 FeatureBitset completeHVXFeatures(const FeatureBitset &FB);74 /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,75 /// etc. do not need to go through TargetRegistry.76 MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU,77 StringRef FS);78 MCSubtargetInfo const *getArchSubtarget(MCSubtargetInfo const *STI);79 void addArchSubtarget(MCSubtargetInfo const *STI,80 StringRef FS);81 unsigned GetELFFlags(const MCSubtargetInfo &STI);82 83 llvm::ArrayRef<MCPhysReg> GetVectRegRev();84 85 std::optional<unsigned> getHVXVersion(const FeatureBitset &Features);86 87 unsigned getArchVersion(const FeatureBitset &Features);88 } // namespace Hexagon_MC89 90MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,91 MCContext &MCT);92 93MCAsmBackend *createHexagonAsmBackend(const Target &T,94 const MCSubtargetInfo &STI,95 const MCRegisterInfo &MRI,96 const MCTargetOptions &Options);97 98std::unique_ptr<MCObjectTargetWriter>99createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU);100 101unsigned HexagonGetLastSlot();102unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);103 104} // End llvm namespace105 106// Define symbolic names for Hexagon registers. This defines a mapping from107// register name to register number.108//109#define GET_REGINFO_ENUM110#include "HexagonGenRegisterInfo.inc"111 112// Defines symbolic names for the Hexagon instructions.113//114#define GET_INSTRINFO_ENUM115#define GET_INSTRINFO_SCHED_ENUM116#define GET_INSTRINFO_MC_HELPER_DECLS117#include "HexagonGenInstrInfo.inc"118 119#define GET_SUBTARGETINFO_ENUM120#include "HexagonGenSubtargetInfo.inc"121 122#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H123