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1//===-- LoongArch.td - Describe the LoongArch Target -------*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9include "llvm/Target/Target.td"10 11//===----------------------------------------------------------------------===//12// LoongArch subtarget features and instruction predicates.13//===----------------------------------------------------------------------===//14 15// LoongArch is divided into two versions, the 32-bit version (LA32) and the16// 64-bit version (LA64).17 18// LoongArch 32-bit is divided into two variants, the reduced 32-bit variant19// (LA32R) and the standard 32-bit variant (LA32S).20def Feature32S21 : SubtargetFeature<"32s", "Has32S", "true",22 "LA32 Standard Basic Instruction Extension">;23def Has32S : Predicate<"Subtarget->has32S()">;24 25def Feature64Bit26 : SubtargetFeature<"64bit", "HasLA64", "true",27 "LA64 Basic Integer and Privilege Instruction Set",28 [Feature32S]>;29def Feature32Bit30 : SubtargetFeature<"32bit", "HasLA32", "true",31 "LA32 Basic Integer and Privilege Instruction Set">;32def IsLA6433 : Predicate<"Subtarget->is64Bit()">,34 AssemblerPredicate<(all_of Feature64Bit),35 "LA64 Basic Integer and Privilege Instruction Set">;36def IsLA3237 : Predicate<"!Subtarget->is64Bit()">,38 AssemblerPredicate<(all_of(not Feature64Bit)),39 "LA32 Basic Integer and Privilege Instruction Set">;40 41defvar LA32 = DefaultMode;42def LA64 : HwMode<[IsLA64]>;43 44// Single Precision floating point45def FeatureBasicF46 : SubtargetFeature<"f", "HasBasicF", "true",47 "'F' (Single-Precision Floating-Point)">;48def HasBasicF : Predicate<"Subtarget->hasBasicF()">;49 50// Double Precision floating point51def FeatureBasicD52 : SubtargetFeature<"d", "HasBasicD", "true",53 "'D' (Double-Precision Floating-Point)",54 [FeatureBasicF]>;55def HasBasicD : Predicate<"Subtarget->hasBasicD()">;56 57// Loongson SIMD eXtension (LSX)58def FeatureExtLSX59 : SubtargetFeature<"lsx", "HasExtLSX", "true",60 "'LSX' (Loongson SIMD Extension)", [FeatureBasicD]>;61def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">;62 63// Loongson Advanced SIMD eXtension (LASX)64def FeatureExtLASX65 : SubtargetFeature<"lasx", "HasExtLASX", "true",66 "'LASX' (Loongson Advanced SIMD Extension)",67 [FeatureExtLSX]>;68def HasExtLASX : Predicate<"Subtarget->hasExtLASX()">;69 70// Loongson VirtualiZation (LVZ)71def FeatureExtLVZ72 : SubtargetFeature<"lvz", "HasExtLVZ", "true",73 "'LVZ' (Loongson Virtualization Extension)">;74def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">;75 76// Loongson Binary Translation (LBT)77def FeatureExtLBT78 : SubtargetFeature<"lbt", "HasExtLBT", "true",79 "'LBT' (Loongson Binary Translation Extension)">;80def HasExtLBT : Predicate<"Subtarget->hasExtLBT()">;81 82// Expand la.global as la.pcrel83def LaGlobalWithPcrel84 : SubtargetFeature<"la-global-with-pcrel", "HasLaGlobalWithPcrel", "true",85 "Expand la.global as la.pcrel">;86def HasLaGlobalWithPcrel87 : Predicate<"Subtarget->hasLaGlobalWithPcrel()">,88 AssemblerPredicate<(all_of LaGlobalWithPcrel),89 "Expand la.global as la.pcrel">;90 91// Expand la.global as la.abs92def LaGlobalWithAbs93 : SubtargetFeature<"la-global-with-abs", "HasLaGlobalWithAbs", "true",94 "Expand la.global as la.abs">;95def HasLaGlobalWithAbs96 : Predicate<"Subtarget->hasLaGlobalWithAbs()">,97 AssemblerPredicate<(all_of LaGlobalWithAbs),98 "Expand la.global as la.abs">;99 100// Expand la.local as la.abs101def LaLocalWithAbs102 : SubtargetFeature<"la-local-with-abs", "HasLaLocalWithAbs", "true",103 "Expand la.local as la.abs">;104def HasLaLocalWithAbs105 : Predicate<"Subtarget->hasLaLocalWithAbs()">,106 AssemblerPredicate<(all_of LaLocalWithAbs),107 "Expand la.local as la.abs">;108 109// Unaligned memory access110def FeatureUAL111 : SubtargetFeature<"ual", "HasUAL", "true",112 "Allow memory accesses to be unaligned">;113 114def FeatureRelax115 : SubtargetFeature<"relax", "HasLinkerRelax", "true",116 "Enable Linker relaxation">;117 118// Floating point approximation operation119def FeatureFrecipe120 : SubtargetFeature<"frecipe", "HasFrecipe", "true",121 "Support frecipe.{s/d} and frsqrte.{s/d} instructions">;122def HasFrecipe : Predicate<"Subtarget->hasFrecipe()">;123 124// Atomic memory swap and add instructions for byte and half word125def FeatureLAM_BH126 : SubtargetFeature<"lam-bh", "HasLAM_BH", "true",127 "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions">;128def HasLAM_BH : Predicate<"Subtarget->hasLAM_BH()">;129 130// Atomic memory compare and swap instructions for byte, half word, word and double word131def FeatureLAMCAS132 : SubtargetFeature<"lamcas", "HasLAMCAS", "true",133 "Support amcas[_db].{b/h/w/d}">;134def HasLAMCAS : Predicate<"Subtarget->hasLAMCAS()">;135 136def FeatureLD_SEQ_SA137 : SubtargetFeature<"ld-seq-sa", "HasLD_SEQ_SA", "true",138 "Don't use a same-address load-load barrier (dbar 0x700)">;139def HasLD_SEQ_SA : Predicate<"Subtarget->hasLD_SEQ_SA()">;140 141// Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended.142def FeatureDiv32143 : SubtargetFeature<"div32", "HasDiv32", "true",144 "Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended">;145def HasDiv32 : Predicate<"Subtarget->hasDiv32()">;146 147// Support SC.Q instruction148def FeatureSCQ149 : SubtargetFeature<"scq", "HasSCQ", "true",150 "Support sc.q instruction">;151def HasSCQ : Predicate<"Subtarget->hasSCQ()">;152 153def TunePreferWInst154 : SubtargetFeature<"prefer-w-inst", "PreferWInst", "true",155 "Prefer instructions with W suffix">;156 157//===----------------------------------------------------------------------===//158// Registers, instruction descriptions ...159//===----------------------------------------------------------------------===//160 161include "LoongArchRegisterInfo.td"162include "LoongArchCallingConv.td"163include "LoongArchInstrInfo.td"164 165//===----------------------------------------------------------------------===//166// LoongArch processors supported.167//===----------------------------------------------------------------------===//168 169def : ProcessorModel<"generic-la32", NoSchedModel, [Feature32Bit]>;170def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit,171 FeatureUAL,172 FeatureExtLSX]>;173 174// Generic 64-bit processor with double-precision floating-point support.175def : ProcessorModel<"loongarch64", NoSchedModel, [Feature64Bit,176 FeatureUAL,177 FeatureBasicD]>;178 179// Support generic for compatibility with other targets. The triple will be used180// to change to the appropriate la32/la64 version.181def : ProcessorModel<"generic", NoSchedModel, []>;182 183def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit,184 FeatureUAL,185 FeatureExtLASX,186 FeatureExtLVZ,187 FeatureExtLBT]>;188 189def : ProcessorModel<"la664", NoSchedModel, [Feature64Bit,190 FeatureUAL,191 FeatureExtLASX,192 FeatureExtLVZ,193 FeatureExtLBT,194 FeatureFrecipe,195 FeatureLAM_BH,196 FeatureLAMCAS,197 FeatureLD_SEQ_SA,198 FeatureDiv32,199 FeatureSCQ]>;200 201//===----------------------------------------------------------------------===//202// Define the LoongArch target.203//===----------------------------------------------------------------------===//204 205defm : RemapAllTargetPseudoPointerOperands<GPR>;206 207def LoongArchInstrInfo : InstrInfo {208 let guessInstructionProperties = 0;209}210 211def LoongArchAsmParser : AsmParser {212 let ShouldEmitMatchRegisterAltName = 1;213 let AllowDuplicateRegisterNames = 1;214}215 216def LoongArchAsmParserVariant : AsmParserVariant {217 int Variant = 0;218 // Recognize hard coded registers.219 string RegisterPrefix = "$";220}221 222def LoongArchAsmWriter : AsmWriter {223 int PassSubtarget = 1;224}225 226def LoongArch : Target {227 let InstructionSet = LoongArchInstrInfo;228 let AssemblyParsers = [LoongArchAsmParser];229 let AssemblyParserVariants = [LoongArchAsmParserVariant];230 let AssemblyWriters = [LoongArchAsmWriter];231 let AllowRegisterRenaming = 1;232}233