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1//=- LoongArchISelDAGToDAG.h - A dag to dag inst selector for LoongArch ---===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file defines an instruction selector for the LoongArch target.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H14#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H15 16#include "LoongArch.h"17#include "LoongArchSelectionDAGInfo.h"18#include "LoongArchTargetMachine.h"19#include "llvm/CodeGen/SelectionDAGISel.h"20 21// LoongArch-specific code to select LoongArch machine instructions for22// SelectionDAG operations.23namespace llvm {24class LoongArchDAGToDAGISel : public SelectionDAGISel {25 const LoongArchSubtarget *Subtarget = nullptr;26 27public:28 LoongArchDAGToDAGISel() = delete;29 30 explicit LoongArchDAGToDAGISel(LoongArchTargetMachine &TM,31 CodeGenOptLevel OptLevel)32 : SelectionDAGISel(TM, OptLevel) {}33 34 bool runOnMachineFunction(MachineFunction &MF) override {35 Subtarget = &MF.getSubtarget<LoongArchSubtarget>();36 return SelectionDAGISel::runOnMachineFunction(MF);37 }38 39 void Select(SDNode *Node) override;40 41 bool SelectInlineAsmMemoryOperand(const SDValue &Op,42 InlineAsm::ConstraintCode ConstraintID,43 std::vector<SDValue> &OutOps) override;44 45 bool SelectBaseAddr(SDValue Addr, SDValue &Base);46 bool SelectAddrConstant(SDValue Addr, SDValue &Base, SDValue &Offset);47 bool selectNonFIBaseAddr(SDValue Addr, SDValue &Base);48 bool SelectAddrRegImm12(SDValue Addr, SDValue &Base, SDValue &Offset);49 50 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);51 bool selectShiftMaskGRLen(SDValue N, SDValue &ShAmt) {52 return selectShiftMask(N, Subtarget->getGRLen(), ShAmt);53 }54 bool selectShiftMask32(SDValue N, SDValue &ShAmt) {55 return selectShiftMask(N, 32, ShAmt);56 }57 58 bool selectSExti32(SDValue N, SDValue &Val);59 bool selectZExti32(SDValue N, SDValue &Val);60 61 bool selectVSplat(SDNode *N, APInt &Imm, unsigned MinSizeInBits) const;62 63 template <unsigned ImmSize, bool IsSigned = false>64 bool selectVSplatImm(SDValue N, SDValue &SplatVal);65 66 bool selectVSplatUimmInvPow2(SDValue N, SDValue &SplatImm) const;67 bool selectVSplatUimmPow2(SDValue N, SDValue &SplatImm) const;68 69 // Return the LoongArch branch opcode that matches the given DAG integer70 // condition code. The CondCode must be one of those supported by the71 // LoongArch ISA (see translateSetCCForBranch).72 static unsigned getBranchOpcForIntCC(ISD::CondCode CC) {73 switch (CC) {74 default:75 llvm_unreachable("Unsupported CondCode");76 case ISD::SETEQ:77 return LoongArch::BEQ;78 case ISD::SETNE:79 return LoongArch::BNE;80 case ISD::SETLT:81 return LoongArch::BLT;82 case ISD::SETGE:83 return LoongArch::BGE;84 case ISD::SETULT:85 return LoongArch::BLTU;86 case ISD::SETUGE:87 return LoongArch::BGEU;88 }89 }90 91// Include the pieces autogenerated from the target description.92#include "LoongArchGenDAGISel.inc"93};94 95class LoongArchDAGToDAGISelLegacy : public SelectionDAGISelLegacy {96public:97 static char ID;98 explicit LoongArchDAGToDAGISelLegacy(LoongArchTargetMachine &TM,99 CodeGenOptLevel OptLevel);100};101 102} // end namespace llvm103 104#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELDAGTODAG_H105