404 lines · plain
1//===- LoongArchInstrFormats.td - LoongArch Instr. Formats -*- tablegen -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Describe LoongArch instructions format11//12// opcode - operation code.13// rd - destination register operand.14// r{j/k} - source register operand.15// immN - immediate data operand.16//17//===----------------------------------------------------------------------===//18 19class LAInst<dag outs, dag ins, string opcstr, string opnstr,20 list<dag> pattern = []>21 : Instruction {22 field bits<32> Inst;23 24 let Namespace = "LoongArch";25 let Size = 4;26 let OutOperandList = outs;27 let InOperandList = ins;28 let AsmString = opcstr # "\t" # opnstr;29 let Pattern = pattern;30 31 // Target-specific instruction info and defaults32 33 bit IsSubjectToAMORdConstraint = 0;34 let TSFlags{0} = IsSubjectToAMORdConstraint;35 36 bit IsAMCAS = 0;37 let TSFlags{1} = IsAMCAS;38}39 40// Pseudo instructions41class Pseudo<dag outs, dag ins, list<dag> pattern = [], string opcstr = "",42 string opnstr = "">43 : LAInst<outs, ins, opcstr, opnstr, pattern> {44 let isPseudo = 1;45 let isCodeGenOnly = 1;46}47 48class deriveInsnMnemonic<string name> {49 string ret = !tolower(!subst("@", "_", !subst("_", ".", !subst("__", "@", name))));50}51 52// 2R-type53// <opcode | rj | rd>54class Fmt2R<bits<32> op, dag outs, dag ins, string opnstr,55 list<dag> pattern = []>56 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {57 bits<5> rj;58 bits<5> rd;59 60 let Inst{31-0} = op;61 let Inst{9-5} = rj;62 let Inst{4-0} = rd;63}64 65// 3R-type66// <opcode | rk | rj | rd>67class Fmt3R<bits<32> op, dag outs, dag ins, string opnstr,68 list<dag> pattern = []>69 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {70 bits<5> rk;71 bits<5> rj;72 bits<5> rd;73 74 let Inst{31-0} = op;75 let Inst{14-10} = rk;76 let Inst{9-5} = rj;77 let Inst{4-0} = rd;78}79 80// 3RI2-type81// <opcode | I2 | rk | rj | rd>82class Fmt3RI2<bits<32> op, dag outs, dag ins, string opnstr,83 list<dag> pattern = []>84 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {85 bits<2> imm2;86 bits<5> rk;87 bits<5> rj;88 bits<5> rd;89 90 let Inst{31-0} = op;91 let Inst{16-15} = imm2;92 let Inst{14-10} = rk;93 let Inst{9-5} = rj;94 let Inst{4-0} = rd;95}96 97// 3RI3-type98// <opcode | I3 | rk | rj | rd>99class Fmt3RI3<bits<32> op, dag outs, dag ins, string opnstr,100 list<dag> pattern = []>101 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {102 bits<3> imm3;103 bits<5> rk;104 bits<5> rj;105 bits<5> rd;106 107 let Inst{31-0} = op;108 let Inst{17-15} = imm3;109 let Inst{14-10} = rk;110 let Inst{9-5} = rj;111 let Inst{4-0} = rd;112}113 114// 2RI5-type115// <opcode | I5 | rj | rd>116class Fmt2RI5<bits<32> op, dag outs, dag ins, string opnstr,117 list<dag> pattern = []>118 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {119 bits<5> imm5;120 bits<5> rj;121 bits<5> rd;122 123 let Inst{31-0} = op;124 let Inst{14-10} = imm5;125 let Inst{9-5} = rj;126 let Inst{4-0} = rd;127}128 129// 2RI6-type130// <opcode | I6 | rj | rd>131class Fmt2RI6<bits<32> op, dag outs, dag ins, string opnstr,132 list<dag> pattern = []>133 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {134 bits<6> imm6;135 bits<5> rj;136 bits<5> rd;137 138 let Inst{31-0} = op;139 let Inst{15-10} = imm6;140 let Inst{9-5} = rj;141 let Inst{4-0} = rd;142}143 144// 2RI8-type145// <opcode | I8 | rj | rd>146class Fmt2RI8<bits<32> op, dag outs, dag ins, string opnstr,147 list<dag> pattern = []>148 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {149 bits<8> imm8;150 bits<5> rj;151 bits<5> rd;152 153 let Inst{31-0} = op;154 let Inst{17-10} = imm8;155 let Inst{9-5} = rj;156 let Inst{4-0} = rd;157}158 159// 2RI12-type160// <opcode | I12 | rj | rd>161class Fmt2RI12<bits<32> op, dag outs, dag ins, string opnstr,162 list<dag> pattern = []>163 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {164 bits<12> imm12;165 bits<5> rj;166 bits<5> rd;167 168 let Inst{31-0} = op;169 let Inst{21-10} = imm12;170 let Inst{9-5} = rj;171 let Inst{4-0} = rd;172}173 174// 2RI14-type175// <opcode | I14 | rj | rd>176class Fmt2RI14<bits<32> op, dag outs, dag ins, string opnstr,177 list<dag> pattern = []>178 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {179 bits<14> imm14;180 bits<5> rj;181 bits<5> rd;182 183 let Inst{31-0} = op;184 let Inst{23-10} = imm14;185 let Inst{9-5} = rj;186 let Inst{4-0} = rd;187}188 189// 2RI16-type190// <opcode | I16 | rj | rd>191class Fmt2RI16<bits<32> op, dag outs, dag ins, string opnstr,192 list<dag> pattern = []>193 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {194 bits<16> imm16;195 bits<5> rj;196 bits<5> rd;197 198 let Inst{31-0} = op;199 let Inst{25-10} = imm16;200 let Inst{9-5} = rj;201 let Inst{4-0} = rd;202}203 204// 1RI20-type205// <opcode | I20 | rd>206class Fmt1RI20<bits<32> op, dag outs, dag ins, string opnstr,207 list<dag> pattern = []>208 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {209 bits<20> imm20;210 bits<5> rd;211 212 let Inst{31-0} = op;213 let Inst{24-5} = imm20;214 let Inst{4-0} = rd;215}216 217// 1RI21-type218// <opcode | I21[15:0] | rj | I21[20:16]>219class Fmt1RI21<bits<32> op, dag outs, dag ins, string opnstr,220 list<dag> pattern = []>221 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {222 bits<21> imm21;223 bits<5> rj;224 225 let Inst{31-0} = op;226 let Inst{25-10} = imm21{15-0};227 let Inst{9-5} = rj;228 let Inst{4-0} = imm21{20-16};229}230 231// I15-type232// <opcode | I15>233class FmtI15<bits<32> op, dag outs, dag ins, string opnstr,234 list<dag> pattern = []>235 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {236 bits<15> imm15;237 238 let Inst{31-0} = op;239 let Inst{14-0} = imm15;240}241 242// I26-type243// <opcode | I26[15:0] | I26[25:16]>244class FmtI26<bits<32> op, dag outs, dag ins, string opnstr,245 list<dag> pattern = []>246 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {247 bits<26> imm26;248 249 let Inst{31-0} = op;250 let Inst{25-10} = imm26{15-0};251 let Inst{9-0} = imm26{25-16};252}253 254// FmtBSTR_W255// <opcode | msbw | lsbw | rj | rd>256class FmtBSTR_W<bits<32> op, dag outs, dag ins, string opnstr,257 list<dag> pattern = []>258 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {259 bits<5> msbw;260 bits<5> lsbw;261 bits<5> rj;262 bits<5> rd;263 264 let Inst{31-0} = op;265 let Inst{20-16} = msbw;266 let Inst{14-10} = lsbw;267 let Inst{9-5} = rj;268 let Inst{4-0} = rd;269}270 271// FmtBSTR_D272// <opcode | msbd | lsbd | rj | rd>273class FmtBSTR_D<bits<32> op, dag outs, dag ins, string opnstr,274 list<dag> pattern = []>275 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {276 bits<6> msbd;277 bits<6> lsbd;278 bits<5> rj;279 bits<5> rd;280 281 let Inst{31-0} = op;282 let Inst{21-16} = msbd;283 let Inst{15-10} = lsbd;284 let Inst{9-5} = rj;285 let Inst{4-0} = rd;286}287 288// FmtASRT289// <opcode | rk | rj>290class FmtASRT<bits<32> op, dag outs, dag ins, string opnstr,291 list<dag> pattern = []>292 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {293 bits<5> rk;294 bits<5> rj;295 296 let Inst{31-0} = op;297 let Inst{14-10} = rk;298 let Inst{9-5} = rj;299}300 301// FmtPRELD302// < 0b0010101011 | I12 | rj | I5>303class FmtPRELD<dag outs, dag ins, string opnstr, list<dag> pattern = []>304 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {305 bits<12> imm12;306 bits<5> rj;307 bits<5> imm5;308 309 let Inst{31-22} = 0b0010101011;310 let Inst{21-10} = imm12;311 let Inst{9-5} = rj;312 let Inst{4-0} = imm5;313}314 315// FmtPRELDX316// < 0b00111000001011000 | rk | rj | I5>317class FmtPRELDX<dag outs, dag ins, string opnstr, list<dag> pattern = []>318 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {319 bits<5> rk;320 bits<5> rj;321 bits<5> imm5;322 323 let Inst{31-15} = 0b00111000001011000;324 let Inst{14-10} = rk;325 let Inst{9-5} = rj;326 let Inst{4-0} = imm5;327}328 329// FmtCSR330// <opcode | csr_num | rd>331class FmtCSR<bits<32> op, dag outs, dag ins, string opnstr,332 list<dag> pattern = []>333 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {334 bits<14> csr_num;335 bits<5> rd;336 337 let Inst{31-0} = op;338 let Inst{23-10} = csr_num;339 let Inst{4-0} = rd;340}341 342// FmtCSRXCHG343// <opcode | csr_num | rj | rd>344class FmtCSRXCHG<bits<32> op, dag outs, dag ins, string opnstr,345 list<dag> pattern = []>346 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {347 bits<14> csr_num;348 bits<5> rj;349 bits<5> rd;350 351 let Inst{31-0} = op;352 let Inst{23-10} = csr_num;353 let Inst{9-5} = rj;354 let Inst{4-0} = rd;355}356 357// FmtCACOP358// <0b0000011000 | I12 | rj | I5>359class FmtCACOP<dag outs, dag ins, string opnstr, list<dag> pattern = []>360 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {361 bits<12> imm12;362 bits<5> rj;363 bits<5> op;364 365 let Inst{31-22} = 0b0000011000;366 let Inst{21-10} = imm12;367 let Inst{9-5} = rj;368 let Inst{4-0} = op;369}370 371// FmtIMM32372// <I32>373class FmtI32<bits<32> op, list<dag> pattern = []>374 : LAInst<(outs), (ins), deriveInsnMnemonic<NAME>.ret, "", pattern> {375 let Inst{31-0} = op;376}377 378// FmtINVTLB379// <0b00000110010010011 | rk | rj | I5>380class FmtINVTLB<dag outs, dag ins, string opnstr, list<dag> pattern = []>381 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {382 bits<5> rk;383 bits<5> rj;384 bits<5> op;385 386 let Inst{31-15} = 0b00000110010010011;387 let Inst{14-10} = rk;388 let Inst{9-5} = rj;389 let Inst{4-0} = op;390}391 392// FmtLDPTE393// <0b00000110010001 | seq | rj | 00000>394class FmtLDPTE<dag outs, dag ins, string opnstr, list<dag> pattern = []>395 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {396 bits<8> seq;397 bits<5> rj;398 399 let Inst{31-18} = 0b00000110010001;400 let Inst{17-10} = seq;401 let Inst{9-5} = rj;402 let Inst{4-0} = 0b00000;403}404