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1//=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file contains the LoongArch implementation of the TargetInstrInfo class.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H14#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H15 16#include "LoongArchRegisterInfo.h"17#include "llvm/CodeGen/TargetInstrInfo.h"18 19#define GET_INSTRINFO_HEADER20#include "LoongArchGenInstrInfo.inc"21 22namespace llvm {23 24class LoongArchSubtarget;25 26class LoongArchInstrInfo : public LoongArchGenInstrInfo {27 const LoongArchRegisterInfo RegInfo;28 29public:30 explicit LoongArchInstrInfo(const LoongArchSubtarget &STI);31 32 const LoongArchRegisterInfo &getRegisterInfo() const { return RegInfo; }33 34 MCInst getNop() const override;35 36 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,37 const DebugLoc &DL, Register DstReg, Register SrcReg,38 bool KillSrc, bool RenamableDest = false,39 bool RenamableSrc = false) const override;40 41 void storeRegToStackSlot(42 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,43 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,44 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;45 void loadRegFromStackSlot(46 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg,47 int FrameIndex, const TargetRegisterClass *RC, Register VReg,48 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;49 50 // Materializes the given integer Val into DstReg.51 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,52 const DebugLoc &DL, Register DstReg, uint64_t Val,53 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;54 55 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;56 57 bool isAsCheapAsAMove(const MachineInstr &MI) const override;58 59 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;60 61 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,62 MachineBasicBlock *&FBB,63 SmallVectorImpl<MachineOperand> &Cond,64 bool AllowModify) const override;65 66 bool isBranchOffsetInRange(unsigned BranchOpc,67 int64_t BrOffset) const override;68 69 bool isSafeToMove(const MachineInstr &MI, const MachineBasicBlock *MBB,70 const MachineFunction &MF) const override;71 72 bool isSchedulingBoundary(const MachineInstr &MI,73 const MachineBasicBlock *MBB,74 const MachineFunction &MF) const override;75 76 unsigned removeBranch(MachineBasicBlock &MBB,77 int *BytesRemoved = nullptr) const override;78 79 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,80 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,81 const DebugLoc &dl,82 int *BytesAdded = nullptr) const override;83 84 void insertIndirectBranch(MachineBasicBlock &MBB,85 MachineBasicBlock &NewDestBB,86 MachineBasicBlock &RestoreBB, const DebugLoc &DL,87 int64_t BrOffset, RegScavenger *RS) const override;88 89 bool90 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;91 92 std::pair<unsigned, unsigned>93 decomposeMachineOperandsTargetFlags(unsigned TF) const override;94 95 ArrayRef<std::pair<unsigned, const char *>>96 getSerializableDirectMachineOperandTargetFlags() const override;97 98 ArrayRef<std::pair<unsigned, const char *>>99 getSerializableBitmaskMachineOperandTargetFlags() const override;100 101 bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,102 const MachineInstr &AddrI,103 ExtAddrMode &AM) const override;104 MachineInstr *emitLdStWithAddr(MachineInstr &MemI,105 const ExtAddrMode &AM) const override;106 107protected:108 const LoongArchSubtarget &STI;109};110 111namespace LoongArch {112 113// Returns true if this is the sext.w pattern, addi.w rd, rs, 0.114bool isSEXT_W(const MachineInstr &MI);115 116// Mask assignments for floating-point.117static constexpr unsigned FClassMaskSignalingNaN = 0x001;118static constexpr unsigned FClassMaskQuietNaN = 0x002;119static constexpr unsigned FClassMaskNegativeInfinity = 0x004;120static constexpr unsigned FClassMaskNegativeNormal = 0x008;121static constexpr unsigned FClassMaskNegativeSubnormal = 0x010;122static constexpr unsigned FClassMaskNegativeZero = 0x020;123static constexpr unsigned FClassMaskPositiveInfinity = 0x040;124static constexpr unsigned FClassMaskPositiveNormal = 0x080;125static constexpr unsigned FClassMaskPositiveSubnormal = 0x100;126static constexpr unsigned FClassMaskPositiveZero = 0x200;127} // namespace LoongArch128 129} // end namespace llvm130#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H131