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1// LoongArchLBTInstrFormats.td - LoongArch LBT Instr Formats -*- tablegen -*-=//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9//===----------------------------------------------------------------------===//10// Describe LoongArch LBT instructions format11//12// opcode - operation code.13// rd/sd - destination register operand.14// rj/rk/sj - source register operand.15// immN/ptr - immediate data operand.16//17// Note: The definition of "NoDstFmt..." conveys the meaning of no explicit18// output operand. In other words, there will be no output operand in the19// assembly notation of these instructions. In fact, they always manipulate20// the "EFLAGS" register.21// Since these instructions are currently not used for code generation,22// we do not need to add `let Defs/Uses = [EFLAGS]`.23//===----------------------------------------------------------------------===//24 25// 1R-type (no outs)26// <opcode | rj>27class NoDstFmt1R<bits<32> op>28 : LAInst<(outs), (ins GPR:$rj),29 deriveInsnMnemonic<NAME>.ret, "$rj"> {30 bits<5> rj;31 32 let Inst{31-0} = op;33 let Inst{9-5} = rj;34}35 36// 1RI3-type (no outs)37// <opcode | I3 | rj>38class NoDstFmt1RI3<bits<32> op>39 : LAInst<(outs), (ins GPR:$rj, uimm3:$imm3),40 deriveInsnMnemonic<NAME>.ret, "$rj, $imm3"> {41 bits<3> imm3;42 bits<5> rj;43 44 let Inst{31-0} = op;45 let Inst{12-10} = imm3;46 let Inst{9-5} = rj;47}48 49// 1RI4-type (no outs)50// <opcode | I4 | rj>51class NoDstFmt1RI4<bits<32> op>52 : LAInst<(outs), (ins GPR:$rj, uimm4:$imm4),53 deriveInsnMnemonic<NAME>.ret, "$rj, $imm4"> {54 bits<4> imm4;55 bits<5> rj;56 57 let Inst{31-0} = op;58 let Inst{13-10} = imm4;59 let Inst{9-5} = rj;60}61 62// 1RI4-type63// <opcode | I4 | rd>64class Fmt1RI4<bits<32> op>65 : LAInst<(outs GPR:$rd), (ins uimm4:$imm4),66 deriveInsnMnemonic<NAME>.ret, "$rd, $imm4"> {67 bits<4> imm4;68 bits<5> rd;69 70 let Inst{31-0} = op;71 let Inst{13-10} = imm4;72 let Inst{4-0} = rd;73}74 75// 1RI5-type (no outs)76// <opcode | I5 | rj>77class NoDstFmt1RI5<bits<32> op>78 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5),79 deriveInsnMnemonic<NAME>.ret, "$rj, $imm5"> {80 bits<5> imm5;81 bits<5> rj;82 83 let Inst{31-0} = op;84 let Inst{14-10} = imm5;85 let Inst{9-5} = rj;86}87 88// 1RI5I4-type (no outs)89// <opcode | rd | I5 | I4>90class NoDstFmt1RI5I4<bits<32> op>91 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5, uimm4:$imm4),92 deriveInsnMnemonic<NAME>.ret, "$rj, $imm5, $imm4"> {93 bits<5> imm5;94 bits<5> rj;95 bits<4> imm4;96 97 let Inst{31-0} = op;98 let Inst{14-10} = imm5;99 let Inst{9-5} = rj;100 let Inst{3-0} = imm4;101}102 103// 1RI5I8-type104// <opcode | rd | I5 | I8>105class Fmt1RI5I8<bits<32> op>106 : LAInst<(outs GPR:$rd), (ins uimm5:$imm5, uimm8:$imm8),107 deriveInsnMnemonic<NAME>.ret, "$rd, $imm5, $imm8"> {108 bits<8> imm8;109 bits<5> imm5;110 bits<5> rd;111 112 let Inst{31-0} = op;113 let Inst{17-10} = imm8;114 let Inst{9-5} = imm5;115 let Inst{4-0} = rd;116}117 118// 1RI6-type (no outs)119// <opcode | I6 | rj>120class NoDstFmt1RI6<bits<32> op>121 : LAInst<(outs), (ins GPR:$rj, uimm6:$imm6),122 deriveInsnMnemonic<NAME>.ret, "$rj, $imm6"> {123 bits<6> imm6;124 bits<5> rj;125 126 let Inst{31-0} = op;127 let Inst{15-10} = imm6;128 let Inst{9-5} = rj;129}130 131// 1RI8-type132// <opcode | I8 | rd>133class Fmt1RI8<bits<32> op>134 : LAInst<(outs GPR:$rd), (ins uimm8:$imm8),135 deriveInsnMnemonic<NAME>.ret, "$rd, $imm8"> {136 bits<8> imm8;137 bits<5> rd;138 139 let Inst{31-0} = op;140 let Inst{17-10} = imm8;141 let Inst{4-0} = rd;142}143 144// 2R-type (no outs)145// <opcode | rk | rj>146class NoDstFmt2R<bits<32> op>147 : LAInst<(outs), (ins GPR:$rj, GPR:$rk),148 deriveInsnMnemonic<NAME>.ret, "$rj, $rk"> {149 bits<5> rk;150 bits<5> rj;151 152 let Inst{31-0} = op;153 let Inst{14-10} = rk;154 let Inst{9-5} = rj;155}156 157// 2RI4-type (no outs)158// <opcode | rk | rj | imm4>159class NoDstFmt2RI4<bits<32> op>160 : LAInst<(outs), (ins GPR:$rj, GPR:$rk, uimm4:$imm4),161 deriveInsnMnemonic<NAME>.ret, "$rj, $rk, $imm4"> {162 bits<4> imm4;163 bits<5> rk;164 bits<5> rj;165 166 let Inst{31-0} = op;167 let Inst{14-10} = rk;168 let Inst{9-5} = rj;169 let Inst{3-0} = imm4;170}171 172// 2RI3-type173// <opcode | I3 | rj | rd>174class Fmt2RI3<bits<32> op>175 : LAInst<(outs GPR:$rd), (ins GPR:$rj, uimm3:$imm3),176 deriveInsnMnemonic<NAME>.ret, "$rd, $rj, $imm3"> {177 bits<3> imm3;178 bits<5> rj;179 bits<5> rd;180 181 let Inst{31-0} = op;182 let Inst{12-10} = imm3;183 let Inst{9-5} = rj;184 let Inst{4-0} = rd;185}186 187// 2RI4-type188// <opcode | I4 | rj | rd>189class Fmt2RI4<bits<32> op>190 : LAInst<(outs GPR:$rd), (ins GPR:$rj, uimm4:$imm4),191 deriveInsnMnemonic<NAME>.ret, "$rd, $rj, $imm4"> {192 bits<4> imm4;193 bits<5> rj;194 bits<5> rd;195 196 let Inst{31-0} = op;197 let Inst{13-10} = imm4;198 let Inst{9-5} = rj;199 let Inst{4-0} = rd;200}201 202// <opcode | rj | sd>203class FmtGR2SCR<bits<32> op>204 : LAInst<(outs SCR:$sd), (ins GPR:$rj), deriveInsnMnemonic<NAME>.ret,205 "$sd, $rj"> {206 bits<5> rj;207 bits<2> sd;208 209 let Inst{31-0} = op;210 let Inst{9-5} = rj;211 let Inst{1-0} = sd;212}213 214// <opcode | sj | rd>215class FmtSCR2GR<bits<32> op>216 : LAInst<(outs GPR:$rd), (ins SCR:$sj), deriveInsnMnemonic<NAME>.ret,217 "$rd, $sj"> {218 bits<2> sj;219 bits<5> rd;220 221 let Inst{31-0} = op;222 let Inst{6-5} = sj;223 let Inst{4-0} = rd;224}225 226// <opcode | I21[15:0] | I21[20:16]>227class FmtJISCR<bits<32> op>228 : LAInst<(outs), (ins simm21_lsl2:$imm21), deriveInsnMnemonic<NAME>.ret,229 "$imm21"> {230 bits<21> imm21;231 bits<5> rj;232 233 let Inst{31-0} = op;234 let Inst{25-10} = imm21{15-0};235 let Inst{4-0} = imm21{20-16};236}237 238// <opcode | rd>239class FmtMFTOP<bits<32> op>240 : LAInst<(outs GPR:$rd), (ins), deriveInsnMnemonic<NAME>.ret,241 "$rd"> {242 bits<5> rd;243 244 let Inst{31-0} = op;245 let Inst{4-0} = rd;246}247 248// <opcode | ptr>249class FmtMTTOP<bits<32> op>250 : LAInst<(outs), (ins uimm3:$ptr), deriveInsnMnemonic<NAME>.ret,251 "$ptr"> {252 bits<3> ptr;253 254 let Inst{31-0} = op;255 let Inst{7-5} = ptr;256}257